1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Russell King
5 * This assembly is required to safely remap the physical address space
8 #include <linux/linkage.h>
9 #include <asm/asm-offsets.h>
11 #include <asm/memory.h>
12 #include <asm/pgtable.h>
14 .section ".idmap.text", "ax"
19 ENTRY(lpae_pgtables_remap_asm)
20 stmfd sp!, {r4-r8, lr}
22 mrc p15, 0, r8, c1, c0, 0 @ read control reg
23 bic ip, r8, #CR_M @ disable caches and MMU
24 mcr p15, 0, ip, c1, c0, 0
28 /* Update level 2 entries covering the kernel */
31 add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
32 add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
36 strd r4, r5, [r7], #1 << L2_ORDER
40 /* Update level 2 entries for the boot data */
42 add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER
43 bic r7, r7, #(1 << L2_ORDER) - 1
47 strd r4, r5, [r7], #1 << L2_ORDER
53 /* Update level 1 entries */
59 strd r4, r5, [r7], #1 << L1_ORDER
63 mrrc p15, 0, r4, r5, c2 @ read TTBR0
64 adds r4, r4, r0 @ update physical address
66 mcrr p15, 0, r4, r5, c2 @ write back TTBR0
67 mrrc p15, 1, r4, r5, c2 @ read TTBR1
68 adds r4, r4, r0 @ update physical address
70 mcrr p15, 1, r4, r5, c2 @ write back TTBR1
75 mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
76 mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
80 mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
84 ldmfd sp!, {r4-r8, pc}
85 ENDPROC(lpae_pgtables_remap_asm)