1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
8 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
11 model = "Khadas VIM3";
13 vddcpu_a: regulator-vddcpu-a {
17 compatible = "pwm-regulator";
19 regulator-name = "VDDCPU_A";
20 regulator-min-microvolt = <690000>;
21 regulator-max-microvolt = <1050000>;
23 vin-supply = <&dc_in>;
25 pwms = <&pwm_ab 0 1250 0>;
26 pwm-dutycycle-range = <100 0>;
32 vddcpu_b: regulator-vddcpu-b {
34 * Silergy SY8030DEC Regulator.
36 compatible = "pwm-regulator";
38 regulator-name = "VDDCPU_B";
39 regulator-min-microvolt = <690000>;
40 regulator-max-microvolt = <1050000>;
42 vin-supply = <&vsys_3v3>;
44 pwms = <&pwm_AO_cd 1 1250 0>;
45 pwm-dutycycle-range = <100 0>;
52 compatible = "amlogic,axg-sound-card";
53 model = "G12B-KHADAS-VIM3";
54 audio-aux-devs = <&tdmout_b>;
55 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
56 "TDMOUT_B IN 1", "FRDDR_B OUT 1",
57 "TDMOUT_B IN 2", "FRDDR_C OUT 1",
58 "TDM_B Playback", "TDMOUT_B OUT";
60 assigned-clocks = <&clkc CLKID_MPLL2>,
63 assigned-clock-parents = <0>, <0>, <0>;
64 assigned-clock-rates = <294912000>,
70 sound-dai = <&frddr_a>;
74 sound-dai = <&frddr_b>;
78 sound-dai = <&frddr_c>;
81 /* 8ch hdmi interface */
83 sound-dai = <&tdmif_b>;
85 dai-tdm-slot-tx-mask-0 = <1 1>;
86 dai-tdm-slot-tx-mask-1 = <1 1>;
87 dai-tdm-slot-tx-mask-2 = <1 1>;
88 dai-tdm-slot-tx-mask-3 = <1 1>;
92 sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
98 sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
101 sound-dai = <&hdmi_tx>;
116 cpu-supply = <&vddcpu_b>;
117 operating-points-v2 = <&cpu_opp_table_0>;
118 clocks = <&clkc CLKID_CPU_CLK>;
119 clock-latency = <50000>;
123 cpu-supply = <&vddcpu_b>;
124 operating-points-v2 = <&cpu_opp_table_0>;
125 clocks = <&clkc CLKID_CPU_CLK>;
126 clock-latency = <50000>;
130 cpu-supply = <&vddcpu_a>;
131 operating-points-v2 = <&cpub_opp_table_1>;
132 clocks = <&clkc CLKID_CPUB_CLK>;
133 clock-latency = <50000>;
137 cpu-supply = <&vddcpu_a>;
138 operating-points-v2 = <&cpub_opp_table_1>;
139 clocks = <&clkc CLKID_CPUB_CLK>;
140 clock-latency = <50000>;
144 cpu-supply = <&vddcpu_a>;
145 operating-points-v2 = <&cpub_opp_table_1>;
146 clocks = <&clkc CLKID_CPUB_CLK>;
147 clock-latency = <50000>;
151 cpu-supply = <&vddcpu_a>;
152 operating-points-v2 = <&cpub_opp_table_1>;
153 clocks = <&clkc CLKID_CPUB_CLK>;
154 clock-latency = <50000>;
166 pinctrl-0 = <&pwm_a_e_pins>;
167 pinctrl-names = "default";
169 clock-names = "clkin0";
174 pinctrl-0 = <&pwm_ao_d_e_pins>;
175 pinctrl-names = "default";
177 clock-names = "clkin1";