arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include "meson-gx.dtsi"
   8 #include <dt-bindings/clock/gxbb-clkc.h>
   9 #include <dt-bindings/clock/gxbb-aoclkc.h>
  10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxl";
  15
  16         soc {
  17                 usb0: usb@c9000000 {
  18                         status = "disabled";
  19                         compatible = "amlogic,meson-gxl-dwc3";
  20                         #address-cells = <2>;
  21                         #size-cells = <2>;
  22                         ranges;
  23
  24                         clocks = <&clkc CLKID_USB>;
  25                         clock-names = "usb_general";
  26                         resets = <&reset RESET_USB_OTG>;
  27                         reset-names = "usb_otg";
  28
  29                         dwc3: dwc3@c9000000 {
  30                                 compatible = "snps,dwc3";
  31                                 reg = <0x0 0xc9000000 0x0 0x100000>;
  32                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  33                                 dr_mode = "host";
  34                                 maximum-speed = "high-speed";
  35                                 snps,dis_u2_susphy_quirk;
  36                                 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
  37                         };
  38                 };
  39
  40                 crypto: crypto@c883e000 {
  41                         compatible = "amlogic,gxl-crypto";
  42                         reg = <0x0 0xc883e000 0x0 0x36>;
  43                         interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
  44                                      <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  45                         clocks = <&clkc CLKID_BLKMV>;
  46                         clock-names = "blkmv";
  47                         status = "okay";
  48                 };
  49         };
  50 };
  51
  52 &apb {
  53         usb2_phy0: phy@78000 {
  54                 compatible = "amlogic,meson-gxl-usb2-phy";
  55                 #phy-cells = <0>;
  56                 reg = <0x0 0x78000 0x0 0x20>;
  57                 clocks = <&clkc CLKID_USB>;
  58                 clock-names = "phy";
  59                 resets = <&reset RESET_USB_OTG>;
  60                 reset-names = "phy";
  61                 status = "okay";
  62         };
  63
  64         usb2_phy1: phy@78020 {
  65                 compatible = "amlogic,meson-gxl-usb2-phy";
  66                 #phy-cells = <0>;
  67                 reg = <0x0 0x78020 0x0 0x20>;
  68                 clocks = <&clkc CLKID_USB>;
  69                 clock-names = "phy";
  70                 resets = <&reset RESET_USB_OTG>;
  71                 reset-names = "phy";
  72                 status = "okay";
  73         };
  74
  75         usb3_phy: phy@78080 {
  76                 compatible = "amlogic,meson-gxl-usb3-phy";
  77                 #phy-cells = <0>;
  78                 reg = <0x0 0x78080 0x0 0x20>;
  79                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  80                 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
  81                 clock-names = "phy", "peripheral";
  82                 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
  83                 reset-names = "phy", "peripheral";
  84                 status = "okay";
  85         };
  86 };
  87
  88 &efuse {
  89         clocks = <&clkc CLKID_EFUSE>;
  90 };
  91
  92 &ethmac {
  93         clocks = <&clkc CLKID_ETH>,
  94                  <&clkc CLKID_FCLK_DIV2>,
  95                  <&clkc CLKID_MPLL2>;
  96         clock-names = "stmmaceth", "clkin0", "clkin1";
  97
  98         mdio0: mdio {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 compatible = "snps,dwmac-mdio";
 102         };
 103 };
 104
 105 &aobus {
 106         pinctrl_aobus: pinctrl@14 {
 107                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
 108                 #address-cells = <2>;
 109                 #size-cells = <2>;
 110                 ranges;
 111
 112                 gpio_ao: bank@14 {
 113                         reg = <0x0 0x00014 0x0 0x8>,
 114                               <0x0 0x0002c 0x0 0x4>,
 115                               <0x0 0x00024 0x0 0x8>;
 116                         reg-names = "mux", "pull", "gpio";
 117                         gpio-controller;
 118                         #gpio-cells = <2>;
 119                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 120                 };
 121
 122                 uart_ao_a_pins: uart_ao_a {
 123                         mux {
 124                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 125                                 function = "uart_ao";
 126                                 bias-disable;
 127                         };
 128                 };
 129
 130                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 131                         mux {
 132                                 groups = "uart_cts_ao_a",
 133                                        "uart_rts_ao_a";
 134                                 function = "uart_ao";
 135                                 bias-disable;
 136                         };
 137                 };
 138
 139                 uart_ao_b_pins: uart_ao_b {
 140                         mux {
 141                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 142                                 function = "uart_ao_b";
 143                                 bias-disable;
 144                         };
 145                 };
 146
 147                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 148                         mux {
 149                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 150                                 function = "uart_ao_b";
 151                                 bias-disable;
 152                         };
 153                 };
 154
 155                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 156                         mux {
 157                                 groups = "uart_cts_ao_b",
 158                                        "uart_rts_ao_b";
 159                                 function = "uart_ao_b";
 160                                 bias-disable;
 161                         };
 162                 };
 163
 164                 remote_input_ao_pins: remote_input_ao {
 165                         mux {
 166                                 groups = "remote_input_ao";
 167                                 function = "remote_input_ao";
 168                                 bias-disable;
 169                         };
 170                 };
 171
 172                 i2c_ao_pins: i2c_ao {
 173                         mux {
 174                                 groups = "i2c_sck_ao",
 175                                        "i2c_sda_ao";
 176                                 function = "i2c_ao";
 177                                 bias-disable;
 178                         };
 179                 };
 180
 181                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 182                         mux {
 183                                 groups = "pwm_ao_a_3";
 184                                 function = "pwm_ao_a";
 185                                 bias-disable;
 186                         };
 187                 };
 188
 189                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 190                         mux {
 191                                 groups = "pwm_ao_a_8";
 192                                 function = "pwm_ao_a";
 193                                 bias-disable;
 194                         };
 195                 };
 196
 197                 pwm_ao_b_pins: pwm_ao_b {
 198                         mux {
 199                                 groups = "pwm_ao_b";
 200                                 function = "pwm_ao_b";
 201                                 bias-disable;
 202                         };
 203                 };
 204
 205                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 206                         mux {
 207                                 groups = "pwm_ao_b_6";
 208                                 function = "pwm_ao_b";
 209                                 bias-disable;
 210                         };
 211                 };
 212
 213                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 214                         mux {
 215                                 groups = "i2s_out_ch23_ao";
 216                                 function = "i2s_out_ao";
 217                                 bias-disable;
 218                         };
 219                 };
 220
 221                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 222                         mux {
 223                                 groups = "i2s_out_ch45_ao";
 224                                 function = "i2s_out_ao";
 225                                 bias-disable;
 226                         };
 227                 };
 228
 229                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 230                         mux {
 231                                 groups = "spdif_out_ao_6";
 232                                 function = "spdif_out_ao";
 233                                 bias-disable;
 234                         };
 235                 };
 236
 237                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 238                         mux {
 239                                 groups = "spdif_out_ao_9";
 240                                 function = "spdif_out_ao";
 241                                 bias-disable;
 242                         };
 243                 };
 244
 245                 ao_cec_pins: ao_cec {
 246                         mux {
 247                                 groups = "ao_cec";
 248                                 function = "cec_ao";
 249                                 bias-disable;
 250                         };
 251                 };
 252
 253                 ee_cec_pins: ee_cec {
 254                         mux {
 255                                 groups = "ee_cec";
 256                                 function = "cec_ao";
 257                                 bias-disable;
 258                         };
 259                 };
 260         };
 261 };
 262
 263 &cec_AO {
 264         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 265         clock-names = "core";
 266 };
 267
 268 &clkc_AO {
 269         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 270         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 271         clock-names = "xtal", "mpeg-clk";
 272 };
 273
 274 &gpio_intc {
 275         compatible = "amlogic,meson-gpio-intc",
 276                      "amlogic,meson-gxl-gpio-intc";
 277         status = "okay";
 278 };
 279
 280 &hdmi_tx {
 281         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 282         resets = <&reset RESET_HDMITX_CAPB3>,
 283                  <&reset RESET_HDMI_SYSTEM_RESET>,
 284                  <&reset RESET_HDMI_TX>;
 285         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 286         clocks = <&clkc CLKID_HDMI_PCLK>,
 287                  <&clkc CLKID_CLK81>,
 288                  <&clkc CLKID_GCLK_VENCI_INT0>;
 289         clock-names = "isfr", "iahb", "venci";
 290 };
 291
 292 &sysctrl {
 293         clkc: clock-controller {
 294                 compatible = "amlogic,gxl-clkc";
 295                 #clock-cells = <1>;
 296                 clocks = <&xtal>;
 297                 clock-names = "xtal";
 298         };
 299 };
 300
 301 &i2c_A {
 302         clocks = <&clkc CLKID_I2C>;
 303 };
 304
 305 &i2c_AO {
 306         clocks = <&clkc CLKID_AO_I2C>;
 307 };
 308
 309 &i2c_B {
 310         clocks = <&clkc CLKID_I2C>;
 311 };
 312
 313 &i2c_C {
 314         clocks = <&clkc CLKID_I2C>;
 315 };
 316
 317 &periphs {
 318         pinctrl_periphs: pinctrl@4b0 {
 319                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 320                 #address-cells = <2>;
 321                 #size-cells = <2>;
 322                 ranges;
 323
 324                 gpio: bank@4b0 {
 325                         reg = <0x0 0x004b0 0x0 0x28>,
 326                               <0x0 0x004e8 0x0 0x14>,
 327                               <0x0 0x00520 0x0 0x14>,
 328                               <0x0 0x00430 0x0 0x40>;
 329                         reg-names = "mux", "pull", "pull-enable", "gpio";
 330                         gpio-controller;
 331                         #gpio-cells = <2>;
 332                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
 333                 };
 334
 335                 emmc_pins: emmc {
 336                         mux-0 {
 337                                 groups = "emmc_nand_d07",
 338                                        "emmc_cmd";
 339                                 function = "emmc";
 340                                 bias-pull-up;
 341                         };
 342
 343                         mux-1 {
 344                                 groups = "emmc_clk";
 345                                 function = "emmc";
 346                                 bias-disable;
 347                         };
 348                 };
 349
 350                 emmc_ds_pins: emmc-ds {
 351                         mux {
 352                                 groups = "emmc_ds";
 353                                 function = "emmc";
 354                                 bias-pull-down;
 355                         };
 356                 };
 357
 358                 emmc_clk_gate_pins: emmc_clk_gate {
 359                         mux {
 360                                 groups = "BOOT_8";
 361                                 function = "gpio_periphs";
 362                                 bias-pull-down;
 363                         };
 364                 };
 365
 366                 nor_pins: nor {
 367                         mux {
 368                                 groups = "nor_d",
 369                                        "nor_q",
 370                                        "nor_c",
 371                                        "nor_cs";
 372                                 function = "nor";
 373                                 bias-disable;
 374                         };
 375                 };
 376
 377                 spi_pins: spi-pins {
 378                         mux {
 379                                 groups = "spi_miso",
 380                                         "spi_mosi",
 381                                         "spi_sclk";
 382                                 function = "spi";
 383                                 bias-disable;
 384                         };
 385                 };
 386
 387                 spi_ss0_pins: spi-ss0 {
 388                         mux {
 389                                 groups = "spi_ss0";
 390                                 function = "spi";
 391                                 bias-disable;
 392                         };
 393                 };
 394
 395                 sdcard_pins: sdcard {
 396                         mux-0 {
 397                                 groups = "sdcard_d0",
 398                                        "sdcard_d1",
 399                                        "sdcard_d2",
 400                                        "sdcard_d3",
 401                                        "sdcard_cmd";
 402                                 function = "sdcard";
 403                                 bias-pull-up;
 404                         };
 405
 406                         mux-1 {
 407                                 groups = "sdcard_clk";
 408                                 function = "sdcard";
 409                                 bias-disable;
 410                         };
 411                 };
 412
 413                 sdcard_clk_gate_pins: sdcard_clk_gate {
 414                         mux {
 415                                 groups = "CARD_2";
 416                                 function = "gpio_periphs";
 417                                 bias-pull-down;
 418                         };
 419                 };
 420
 421                 sdio_pins: sdio {
 422                         mux-0 {
 423                                 groups = "sdio_d0",
 424                                        "sdio_d1",
 425                                        "sdio_d2",
 426                                        "sdio_d3",
 427                                        "sdio_cmd";
 428                                 function = "sdio";
 429                                 bias-pull-up;
 430                         };
 431
 432                         mux-1 {
 433                                 groups = "sdio_clk";
 434                                 function = "sdio";
 435                                 bias-disable;
 436                         };
 437                 };
 438
 439                 sdio_clk_gate_pins: sdio_clk_gate {
 440                         mux {
 441                                 groups = "GPIOX_4";
 442                                 function = "gpio_periphs";
 443                                 bias-pull-down;
 444                         };
 445                 };
 446
 447                 sdio_irq_pins: sdio_irq {
 448                         mux {
 449                                 groups = "sdio_irq";
 450                                 function = "sdio";
 451                                 bias-disable;
 452                         };
 453                 };
 454
 455                 uart_a_pins: uart_a {
 456                         mux {
 457                                 groups = "uart_tx_a",
 458                                        "uart_rx_a";
 459                                 function = "uart_a";
 460                                 bias-disable;
 461                         };
 462                 };
 463
 464                 uart_a_cts_rts_pins: uart_a_cts_rts {
 465                         mux {
 466                                 groups = "uart_cts_a",
 467                                        "uart_rts_a";
 468                                 function = "uart_a";
 469                                 bias-disable;
 470                         };
 471                 };
 472
 473                 uart_b_pins: uart_b {
 474                         mux {
 475                                 groups = "uart_tx_b",
 476                                        "uart_rx_b";
 477                                 function = "uart_b";
 478                                 bias-disable;
 479                         };
 480                 };
 481
 482                 uart_b_cts_rts_pins: uart_b_cts_rts {
 483                         mux {
 484                                 groups = "uart_cts_b",
 485                                        "uart_rts_b";
 486                                 function = "uart_b";
 487                                 bias-disable;
 488                         };
 489                 };
 490
 491                 uart_c_pins: uart_c {
 492                         mux {
 493                                 groups = "uart_tx_c",
 494                                        "uart_rx_c";
 495                                 function = "uart_c";
 496                                 bias-disable;
 497                         };
 498                 };
 499
 500                 uart_c_cts_rts_pins: uart_c_cts_rts {
 501                         mux {
 502                                 groups = "uart_cts_c",
 503                                        "uart_rts_c";
 504                                 function = "uart_c";
 505                                 bias-disable;
 506                         };
 507                 };
 508
 509                 i2c_a_pins: i2c_a {
 510                         mux {
 511                                 groups = "i2c_sck_a",
 512                                      "i2c_sda_a";
 513                                 function = "i2c_a";
 514                                 bias-disable;
 515                         };
 516                 };
 517
 518                 i2c_b_pins: i2c_b {
 519                         mux {
 520                                 groups = "i2c_sck_b",
 521                                       "i2c_sda_b";
 522                                 function = "i2c_b";
 523                                 bias-disable;
 524                         };
 525                 };
 526
 527                 i2c_c_pins: i2c_c {
 528                         mux {
 529                                 groups = "i2c_sck_c",
 530                                       "i2c_sda_c";
 531                                 function = "i2c_c";
 532                                 bias-disable;
 533                         };
 534                 };
 535
 536                 i2c_c_dv18_pins: i2c_c_dv18 {
 537                         mux {
 538                                 groups = "i2c_sck_c_dv19",
 539                                       "i2c_sda_c_dv18";
 540                                 function = "i2c_c";
 541                                 bias-disable;
 542                         };
 543                 };
 544
 545                 eth_pins: eth_c {
 546                         mux {
 547                                 groups = "eth_mdio",
 548                                        "eth_mdc",
 549                                        "eth_clk_rx_clk",
 550                                        "eth_rx_dv",
 551                                        "eth_rxd0",
 552                                        "eth_rxd1",
 553                                        "eth_rxd2",
 554                                        "eth_rxd3",
 555                                        "eth_rgmii_tx_clk",
 556                                        "eth_tx_en",
 557                                        "eth_txd0",
 558                                        "eth_txd1",
 559                                        "eth_txd2",
 560                                        "eth_txd3";
 561                                 function = "eth";
 562                                 bias-disable;
 563                         };
 564                 };
 565
 566                 eth_link_led_pins: eth_link_led {
 567                         mux {
 568                                 groups = "eth_link_led";
 569                                 function = "eth_led";
 570                                 bias-disable;
 571                         };
 572                 };
 573
 574                 eth_act_led_pins: eth_act_led {
 575                         mux {
 576                                 groups = "eth_act_led";
 577                                 function = "eth_led";
 578                         };
 579                 };
 580
 581                 pwm_a_pins: pwm_a {
 582                         mux {
 583                                 groups = "pwm_a";
 584                                 function = "pwm_a";
 585                                 bias-disable;
 586                         };
 587                 };
 588
 589                 pwm_b_pins: pwm_b {
 590                         mux {
 591                                 groups = "pwm_b";
 592                                 function = "pwm_b";
 593                                 bias-disable;
 594                         };
 595                 };
 596
 597                 pwm_c_pins: pwm_c {
 598                         mux {
 599                                 groups = "pwm_c";
 600                                 function = "pwm_c";
 601                                 bias-disable;
 602                         };
 603                 };
 604
 605                 pwm_d_pins: pwm_d {
 606                         mux {
 607                                 groups = "pwm_d";
 608                                 function = "pwm_d";
 609                                 bias-disable;
 610                         };
 611                 };
 612
 613                 pwm_e_pins: pwm_e {
 614                         mux {
 615                                 groups = "pwm_e";
 616                                 function = "pwm_e";
 617                                 bias-disable;
 618                         };
 619                 };
 620
 621                 pwm_f_clk_pins: pwm_f_clk {
 622                         mux {
 623                                 groups = "pwm_f_clk";
 624                                 function = "pwm_f";
 625                                 bias-disable;
 626                         };
 627                 };
 628
 629                 pwm_f_x_pins: pwm_f_x {
 630                         mux {
 631                                 groups = "pwm_f_x";
 632                                 function = "pwm_f";
 633                                 bias-disable;
 634                         };
 635                 };
 636
 637                 hdmi_hpd_pins: hdmi_hpd {
 638                         mux {
 639                                 groups = "hdmi_hpd";
 640                                 function = "hdmi_hpd";
 641                                 bias-disable;
 642                         };
 643                 };
 644
 645                 hdmi_i2c_pins: hdmi_i2c {
 646                         mux {
 647                                 groups = "hdmi_sda", "hdmi_scl";
 648                                 function = "hdmi_i2c";
 649                                 bias-disable;
 650                         };
 651                 };
 652
 653                 i2s_am_clk_pins: i2s_am_clk {
 654                         mux {
 655                                 groups = "i2s_am_clk";
 656                                 function = "i2s_out";
 657                                 bias-disable;
 658                         };
 659                 };
 660
 661                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 662                         mux {
 663                                 groups = "i2s_out_ao_clk";
 664                                 function = "i2s_out";
 665                                 bias-disable;
 666                         };
 667                 };
 668
 669                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 670                         mux {
 671                                 groups = "i2s_out_lr_clk";
 672                                 function = "i2s_out";
 673                                 bias-disable;
 674                         };
 675                 };
 676
 677                 i2s_out_ch01_pins: i2s_out_ch01 {
 678                         mux {
 679                                 groups = "i2s_out_ch01";
 680                                 function = "i2s_out";
 681                                 bias-disable;
 682                         };
 683                 };
 684                 i2sout_ch23_z_pins: i2sout_ch23_z {
 685                         mux {
 686                                 groups = "i2sout_ch23_z";
 687                                 function = "i2s_out";
 688                                 bias-disable;
 689                         };
 690                 };
 691
 692                 i2sout_ch45_z_pins: i2sout_ch45_z {
 693                         mux {
 694                                 groups = "i2sout_ch45_z";
 695                                 function = "i2s_out";
 696                                 bias-disable;
 697                         };
 698                 };
 699
 700                 i2sout_ch67_z_pins: i2sout_ch67_z {
 701                         mux {
 702                                 groups = "i2sout_ch67_z";
 703                                 function = "i2s_out";
 704                                 bias-disable;
 705                         };
 706                 };
 707
 708                 spdif_out_h_pins: spdif_out_ao_h {
 709                         mux {
 710                                 groups = "spdif_out_h";
 711                                 function = "spdif_out";
 712                                 bias-disable;
 713                         };
 714                 };
 715         };
 716
 717         eth-phy-mux {
 718                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 719                 #address-cells = <1>;
 720                 #size-cells = <0>;
 721                 reg = <0x0 0x55c 0x0 0x4>;
 722                 mux-mask = <0xffffffff>;
 723                 mdio-parent-bus = <&mdio0>;
 724
 725                 internal_mdio: mdio@e40908ff {
 726                         reg = <0xe40908ff>;
 727                         #address-cells = <1>;
 728                         #size-cells = <0>;
 729
 730                         internal_phy: ethernet-phy@8 {
 731                                 compatible = "ethernet-phy-id0181.4400";
 732                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 733                                 reg = <8>;
 734                                 max-speed = <100>;
 735                         };
 736                 };
 737
 738                 external_mdio: mdio@2009087f {
 739                         reg = <0x2009087f>;
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                 };
 743         };
 744 };
 745
 746 &pwrc_vpu {
 747         resets = <&reset RESET_VIU>,
 748                  <&reset RESET_VENC>,
 749                  <&reset RESET_VCBUS>,
 750                  <&reset RESET_BT656>,
 751                  <&reset RESET_DVIN_RESET>,
 752                  <&reset RESET_RDMA>,
 753                  <&reset RESET_VENCI>,
 754                  <&reset RESET_VENCP>,
 755                  <&reset RESET_VDAC>,
 756                  <&reset RESET_VDI6>,
 757                  <&reset RESET_VENCL>,
 758                  <&reset RESET_VID_LOCK>;
 759         clocks = <&clkc CLKID_VPU>,
 760                  <&clkc CLKID_VAPB>;
 761         clock-names = "vpu", "vapb";
 762         /*
 763          * VPU clocking is provided by two identical clock paths
 764          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 765          * free mux to safely change frequency while running.
 766          * Same for VAPB but with a final gate after the glitch free mux.
 767          */
 768         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 769                           <&clkc CLKID_VPU_0>,
 770                           <&clkc CLKID_VPU>, /* Glitch free mux */
 771                           <&clkc CLKID_VAPB_0_SEL>,
 772                           <&clkc CLKID_VAPB_0>,
 773                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 774         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 775                                  <0>, /* Do Nothing */
 776                                  <&clkc CLKID_VPU_0>,
 777                                  <&clkc CLKID_FCLK_DIV4>,
 778                                  <0>, /* Do Nothing */
 779                                  <&clkc CLKID_VAPB_0>;
 780         assigned-clock-rates = <0>, /* Do Nothing */
 781                                <666666666>,
 782                                <0>, /* Do Nothing */
 783                                <0>, /* Do Nothing */
 784                                <250000000>,
 785                                <0>; /* Do Nothing */
 786 };
 787
 788 &saradc {
 789         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 790         clocks = <&xtal>,
 791                  <&clkc CLKID_SAR_ADC>,
 792                  <&clkc CLKID_SAR_ADC_CLK>,
 793                  <&clkc CLKID_SAR_ADC_SEL>;
 794         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 795 };
 796
 797 &sd_emmc_a {
 798         clocks = <&clkc CLKID_SD_EMMC_A>,
 799                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 800                  <&clkc CLKID_FCLK_DIV2>;
 801         clock-names = "core", "clkin0", "clkin1";
 802         resets = <&reset RESET_SD_EMMC_A>;
 803 };
 804
 805 &sd_emmc_b {
 806         clocks = <&clkc CLKID_SD_EMMC_B>,
 807                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 808                  <&clkc CLKID_FCLK_DIV2>;
 809         clock-names = "core", "clkin0", "clkin1";
 810         resets = <&reset RESET_SD_EMMC_B>;
 811 };
 812
 813 &sd_emmc_c {
 814         clocks = <&clkc CLKID_SD_EMMC_C>,
 815                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 816                  <&clkc CLKID_FCLK_DIV2>;
 817         clock-names = "core", "clkin0", "clkin1";
 818         resets = <&reset RESET_SD_EMMC_C>;
 819 };
 820
 821 &simplefb_hdmi {
 822         clocks = <&clkc CLKID_HDMI_PCLK>,
 823                  <&clkc CLKID_CLK81>,
 824                  <&clkc CLKID_GCLK_VENCI_INT0>;
 825 };
 826
 827 &spicc {
 828         clocks = <&clkc CLKID_SPICC>;
 829         clock-names = "core";
 830         resets = <&reset RESET_PERIPHS_SPICC>;
 831         num-cs = <1>;
 832 };
 833
 834 &spifc {
 835         clocks = <&clkc CLKID_SPI>;
 836 };
 837
 838 &uart_A {
 839         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 840         clock-names = "xtal", "pclk", "baud";
 841 };
 842
 843 &uart_AO {
 844         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 845         clock-names = "xtal", "pclk", "baud";
 846 };
 847
 848 &uart_AO_B {
 849         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 850         clock-names = "xtal", "pclk", "baud";
 851 };
 852
 853 &uart_B {
 854         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 855         clock-names = "xtal", "pclk", "baud";
 856 };
 857
 858 &uart_C {
 859         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 860         clock-names = "xtal", "pclk", "baud";
 861 };
 862
 863 &vpu {
 864         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 865         power-domains = <&pwrc_vpu>;
 866 };
 867
 868 &vdec {
 869         compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
 870         clocks = <&clkc CLKID_DOS_PARSER>,
 871                  <&clkc CLKID_DOS>,
 872                  <&clkc CLKID_VDEC_1>,
 873                  <&clkc CLKID_VDEC_HEVC>;
 874         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
 875         resets = <&reset RESET_PARSER>;
 876         reset-names = "esparser";
 877 };