arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/usb/pd.h>
   7 #include "imx8mn.dtsi"
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart2;
  12         };
  13
  14         gpio-leds {
  15                 compatible = "gpio-leds";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_led>;
  18
  19                 status {
  20                         label = "yellow:status";
  21                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  22                         default-state = "on";
  23                 };
  24         };
  25
  26         memory@40000000 {
  27                 device_type = "memory";
  28                 reg = <0x0 0x40000000 0 0x80000000>;
  29         };
  30
  31         reg_usdhc2_vmmc: regulator-usdhc2 {
  32                 compatible = "regulator-fixed";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  35                 regulator-name = "VSD_3V3";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  39                 enable-active-high;
  40         };
  41 };
  42
  43 &fec1 {
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_fec1>;
  46         phy-mode = "rgmii-id";
  47         phy-handle = <&ethphy0>;
  48         fsl,magic-packet;
  49         status = "okay";
  50
  51         mdio {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 ethphy0: ethernet-phy@0 {
  56                         compatible = "ethernet-phy-ieee802.3-c22";
  57                         reg = <0>;
  58                 };
  59         };
  60 };
  61
  62 &i2c1 {
  63         clock-frequency = <400000>;
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_i2c1>;
  66         status = "okay";
  67 };
  68
  69 &i2c2 {
  70         clock-frequency = <400000>;
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_i2c2>;
  73         status = "okay";
  74
  75         ptn5110: tcpc@50 {
  76                 compatible = "nxp,ptn5110";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_typec1>;
  79                 reg = <0x50>;
  80                 interrupt-parent = <&gpio2>;
  81                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  82                 status = "okay";
  83
  84                 port {
  85                         typec1_dr_sw: endpoint {
  86                                 remote-endpoint = <&usb1_drd_sw>;
  87                         };
  88                 };
  89
  90                 typec1_con: connector {
  91                         compatible = "usb-c-connector";
  92                         label = "USB-C";
  93                         power-role = "dual";
  94                         data-role = "dual";
  95                         try-power-role = "sink";
  96                         source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
  97                         sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
  98                                      PDO_VAR(5000, 20000, 3000)>;
  99                         op-sink-microwatt = <15000000>;
 100                         self-powered;
 101                 };
 102         };
 103 };
 104
 105 &i2c3 {
 106         clock-frequency = <400000>;
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_i2c3>;
 109         status = "okay";
 110
 111         pca6416: gpio@20 {
 112                 compatible = "ti,tca6416";
 113                 reg = <0x20>;
 114                 gpio-controller;
 115                 #gpio-cells = <2>;
 116         };
 117 };
 118
 119 &snvs_pwrkey {
 120         status = "okay";
 121 };
 122
 123 &uart2 { /* console */
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_uart2>;
 126         status = "okay";
 127 };
 128
 129 &usbotg1 {
 130         dr_mode = "otg";
 131         hnp-disable;
 132         srp-disable;
 133         adp-disable;
 134         usb-role-switch;
 135         status = "okay";
 136
 137         port {
 138                 usb1_drd_sw: endpoint {
 139                         remote-endpoint = <&typec1_dr_sw>;
 140                 };
 141         };
 142 };
 143
 144 &usdhc2 {
 145         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 146         assigned-clock-rates = <200000000>;
 147         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 148         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 149         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 150         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 151         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 152         bus-width = <4>;
 153         vmmc-supply = <&reg_usdhc2_vmmc>;
 154         status = "okay";
 155 };
 156
 157 &usdhc3 {
 158         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 159         assigned-clock-rates = <400000000>;
 160         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 161         pinctrl-0 = <&pinctrl_usdhc3>;
 162         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 163         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 164         bus-width = <8>;
 165         non-removable;
 166         status = "okay";
 167 };
 168
 169 &wdog1 {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_wdog>;
 172         fsl,ext-reset-output;
 173         status = "okay";
 174 };
 175
 176 &iomuxc {
 177         pinctrl-names = "default";
 178
 179         pinctrl_fec1: fec1grp {
 180                 fsl,pins = <
 181                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 182                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 183                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 184                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 185                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 186                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 187                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 188                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 189                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 190                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 191                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 192                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 193                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 194                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 195                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 196                 >;
 197         };
 198
 199         pinctrl_gpio_led: gpioledgrp {
 200                 fsl,pins = <
 201                         MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 202                 >;
 203         };
 204
 205         pinctrl_i2c1: i2c1grp {
 206                 fsl,pins = <
 207                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 208                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 209                 >;
 210         };
 211
 212         pinctrl_i2c2: i2c2grp {
 213                 fsl,pins = <
 214                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 215                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 216                 >;
 217         };
 218
 219         pinctrl_i2c3: i2c3grp {
 220                 fsl,pins = <
 221                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 222                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 223                 >;
 224         };
 225
 226         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
 227                 fsl,pins = <
 228                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 229                 >;
 230         };
 231
 232         pinctrl_typec1: typec1grp {
 233                 fsl,pins = <
 234                         MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11      0x159
 235                 >;
 236         };
 237
 238         pinctrl_uart2: uart2grp {
 239                 fsl,pins = <
 240                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 241                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 242                 >;
 243         };
 244
 245         pinctrl_usdhc2_gpio: usdhc2grpgpio {
 246                 fsl,pins = <
 247                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 248                 >;
 249         };
 250
 251         pinctrl_usdhc2: usdhc2grp {
 252                 fsl,pins = <
 253                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 254                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 255                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 256                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 257                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 258                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 259                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 260                 >;
 261         };
 262
 263         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 264                 fsl,pins = <
 265                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 266                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 267                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 268                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 269                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 270                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 271                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 272                 >;
 273         };
 274
 275         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 276                 fsl,pins = <
 277                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 278                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 279                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 280                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 281                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 282                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 283                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 284                 >;
 285         };
 286
 287         pinctrl_usdhc3: usdhc3grp {
 288                 fsl,pins = <
 289                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 290                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 291                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 292                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 293                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 294                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 295                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 296                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 297                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 298                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 299                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 300                 >;
 301         };
 302
 303         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 304                 fsl,pins = <
 305                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 306                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 307                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 308                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 309                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 310                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 311                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 312                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 313                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 314                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 315                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 316                 >;
 317         };
 318
 319         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 320                 fsl,pins = <
 321                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 322                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 323                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 324                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 325                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 326                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 327                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 328                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 329                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 330                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 331                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 332                 >;
 333         };
 334
 335         pinctrl_wdog: wdoggrp {
 336                 fsl,pins = <
 337                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 338                 >;
 339         };
 340 };