| blob | e7438c21ccee4165a37cd359a1089f8054bbc8c1 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2019 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP80x.
6 */
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
13 / {
14 #address-cells = <2>;
15 #size-cells = <2>;
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 gpio0 = &ap_gpio;
21 spi0 = &spi0;
22 };
24 psci {
25 compatible = "arm,psci-0.2";
26 method = "smc";
27 };
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
32 ranges;
34 /*
35 * This area matches the mapping done with a
36 * mainline U-Boot, and should be updated by the
37 * bootloader.
38 */
40 psci-area@4000000 {
41 reg = <0x0 0x4000000 0x0 0x200000>;
42 no-map;
43 };
44 };
46 AP_NAME {
47 #address-cells = <2>;
48 #size-cells = <2>;
49 compatible = "simple-bus";
50 interrupt-parent = <&gic>;
51 ranges;
53 config-space@f0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "simple-bus";
57 ranges = <0x0 0x0 0xf0000000 0x1000000>;
59 gic: interrupt-controller@210000 {
60 compatible = "arm,gic-400";
61 #interrupt-cells = <3>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65 interrupt-controller;
66 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
67 reg = <0x210000 0x10000>,
68 <0x220000 0x20000>,
69 <0x240000 0x20000>,
70 <0x260000 0x20000>;
72 gic_v2m0: v2m@280000 {
73 compatible = "arm,gic-v2m-frame";
74 msi-controller;
75 reg = <0x280000 0x1000>;
76 arm,msi-base-spi = <160>;
77 arm,msi-num-spis = <32>;
78 };
79 gic_v2m1: v2m@290000 {
80 compatible = "arm,gic-v2m-frame";
81 msi-controller;
82 reg = <0x290000 0x1000>;
83 arm,msi-base-spi = <192>;
84 arm,msi-num-spis = <32>;
85 };
86 gic_v2m2: v2m@2a0000 {
87 compatible = "arm,gic-v2m-frame";
88 msi-controller;
89 reg = <0x2a0000 0x1000>;
90 arm,msi-base-spi = <224>;
91 arm,msi-num-spis = <32>;
92 };
93 gic_v2m3: v2m@2b0000 {
94 compatible = "arm,gic-v2m-frame";
95 msi-controller;
96 reg = <0x2b0000 0x1000>;
97 arm,msi-base-spi = <256>;
98 arm,msi-num-spis = <32>;
99 };
100 };
102 timer {
103 compatible = "arm,armv8-timer";
104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
108 };
110 pmu {
111 compatible = "arm,cortex-a72-pmu";
112 interrupt-parent = <&pic>;
113 interrupts = <17>;
114 };
116 odmi: odmi@300000 {
117 compatible = "marvell,odmi-controller";
118 interrupt-controller;
119 msi-controller;
120 marvell,odmi-frames = <4>;
121 reg = <0x300000 0x4000>,
122 <0x304000 0x4000>,
123 <0x308000 0x4000>,
124 <0x30C000 0x4000>;
125 marvell,spi-base = <128>, <136>, <144>, <152>;
126 };
128 gicp: gicp@3f0040 {
129 compatible = "marvell,ap806-gicp";
130 reg = <0x3f0040 0x10>;
131 marvell,spi-ranges = <64 64>, <288 64>;
132 msi-controller;
133 };
135 pic: interrupt-controller@3f0100 {
136 compatible = "marvell,armada-8k-pic";
137 reg = <0x3f0100 0x10>;
138 #interrupt-cells = <1>;
139 interrupt-controller;
140 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
141 };
143 sei: interrupt-controller@3f0200 {
144 compatible = "marvell,ap806-sei";
145 reg = <0x3f0200 0x40>;
146 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
147 #interrupt-cells = <1>;
148 interrupt-controller;
149 msi-controller;
150 };
152 xor@400000 {
153 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
154 reg = <0x400000 0x1000>,
155 <0x410000 0x1000>;
156 msi-parent = <&gic_v2m0>;
157 clocks = <&ap_clk 3>;
158 dma-coherent;
159 };
161 xor@420000 {
162 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
163 reg = <0x420000 0x1000>,
164 <0x430000 0x1000>;
165 msi-parent = <&gic_v2m0>;
166 clocks = <&ap_clk 3>;
167 dma-coherent;
168 };
170 xor@440000 {
171 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
172 reg = <0x440000 0x1000>,
173 <0x450000 0x1000>;
174 msi-parent = <&gic_v2m0>;
175 clocks = <&ap_clk 3>;
176 dma-coherent;
177 };
179 xor@460000 {
180 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
181 reg = <0x460000 0x1000>,
182 <0x470000 0x1000>;
183 msi-parent = <&gic_v2m0>;
184 clocks = <&ap_clk 3>;
185 dma-coherent;
186 };
188 spi0: spi@510600 {
189 compatible = "marvell,armada-380-spi";
190 reg = <0x510600 0x50>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&ap_clk 3>;
195 status = "disabled";
196 };
198 i2c0: i2c@511000 {
199 compatible = "marvell,mv78230-i2c";
200 reg = <0x511000 0x20>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
204 timeout-ms = <1000>;
205 clocks = <&ap_clk 3>;
206 status = "disabled";
207 };
209 uart0: serial@512000 {
210 compatible = "snps,dw-apb-uart";
211 reg = <0x512000 0x100>;
212 reg-shift = <2>;
213 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
214 reg-io-width = <1>;
215 clocks = <&ap_clk 3>;
216 status = "disabled";
217 };
219 uart1: serial@512100 {
220 compatible = "snps,dw-apb-uart";
221 reg = <0x512100 0x100>;
222 reg-shift = <2>;
223 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
224 reg-io-width = <1>;
225 clocks = <&ap_clk 3>;
226 status = "disabled";
228 };
230 watchdog: watchdog@610000 {
231 compatible = "arm,sbsa-gwdt";
232 reg = <0x610000 0x1000>, <0x600000 0x1000>;
233 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
234 };
236 ap_sdhci0: sdhci@6e0000 {
237 compatible = "marvell,armada-ap806-sdhci";
238 reg = <0x6e0000 0x300>;
239 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
240 clock-names = "core";
241 clocks = <&ap_clk 4>;
242 dma-coherent;
243 marvell,xenon-phy-slow-mode;
244 status = "disabled";
245 };
247 ap_syscon0: system-controller@6f4000 {
248 compatible = "syscon", "simple-mfd";
249 reg = <0x6f4000 0x2000>;
251 ap_pinctrl: pinctrl {
252 compatible = "marvell,ap806-pinctrl";
254 uart0_pins: uart0-pins {
255 marvell,pins = "mpp11", "mpp19";
256 marvell,function = "uart0";
257 };
258 };
260 ap_gpio: gpio@1040 {
261 compatible = "marvell,armada-8k-gpio";
262 offset = <0x1040>;
263 ngpios = <20>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 gpio-ranges = <&ap_pinctrl 0 0 20>;
267 };
268 };
270 ap_syscon1: system-controller@6f8000 {
271 compatible = "syscon", "simple-mfd";
272 reg = <0x6f8000 0x1000>;
273 #address-cells = <1>;
274 #size-cells = <1>;
276 ap_thermal: thermal-sensor@80 {
277 compatible = "marvell,armada-ap806-thermal";
278 reg = <0x80 0x10>;
279 interrupt-parent = <&sei>;
280 interrupts = <18>;
281 #thermal-sensor-cells = <1>;
282 };
283 };
284 };
285 };
287 /*
288 * The thermal IP features one internal sensor plus, if applicable, one
289 * remote channel wired to one sensor per CPU.
290 *
291 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
292 * first one that will have a critical trip point will be chosen.
293 */
294 thermal-zones {
295 ap_thermal_ic: ap-thermal-ic {
296 polling-delay-passive = <0>; /* Interrupt driven */
297 polling-delay = <0>; /* Interrupt driven */
299 thermal-sensors = <&ap_thermal 0>;
301 trips {
302 ap_crit: ap-crit {
303 temperature = <100000>; /* mC degrees */
304 hysteresis = <2000>; /* mC degrees */
305 type = "critical";
306 };
307 };
309 cooling-maps { };
310 };
312 ap_thermal_cpu0: ap-thermal-cpu0 {
313 polling-delay-passive = <1000>;
314 polling-delay = <1000>;
316 thermal-sensors = <&ap_thermal 1>;
318 trips {
319 cpu0_hot: cpu0-hot {
320 temperature = <85000>;
321 hysteresis = <2000>;
322 type = "passive";
323 };
324 cpu0_emerg: cpu0-emerg {
325 temperature = <95000>;
326 hysteresis = <2000>;
327 type = "passive";
328 };
329 };
331 cooling-maps {
332 map0_hot: map0-hot {
333 trip = <&cpu0_hot>;
334 cooling-device = <&cpu0 1 2>,
335 <&cpu1 1 2>;
336 };
337 map0_emerg: map0-ermerg {
338 trip = <&cpu0_emerg>;
339 cooling-device = <&cpu0 3 3>,
340 <&cpu1 3 3>;
341 };
342 };
343 };
345 ap_thermal_cpu1: ap-thermal-cpu1 {
346 polling-delay-passive = <1000>;
347 polling-delay = <1000>;
349 thermal-sensors = <&ap_thermal 2>;
351 trips {
352 cpu1_hot: cpu1-hot {
353 temperature = <85000>;
354 hysteresis = <2000>;
355 type = "passive";
356 };
357 cpu1_emerg: cpu1-emerg {
358 temperature = <95000>;
359 hysteresis = <2000>;
360 type = "passive";
361 };
362 };
364 cooling-maps {
365 map1_hot: map1-hot {
366 trip = <&cpu1_hot>;
367 cooling-device = <&cpu0 1 2>,
368 <&cpu1 1 2>;
369 };
370 map1_emerg: map1-emerg {
371 trip = <&cpu1_emerg>;
372 cooling-device = <&cpu0 3 3>,
373 <&cpu1 3 3>;
374 };
375 };
376 };
378 ap_thermal_cpu2: ap-thermal-cpu2 {
379 polling-delay-passive = <1000>;
380 polling-delay = <1000>;
382 thermal-sensors = <&ap_thermal 3>;
384 trips {
385 cpu2_hot: cpu2-hot {
386 temperature = <85000>;
387 hysteresis = <2000>;
388 type = "passive";
389 };
390 cpu2_emerg: cpu2-emerg {
391 temperature = <95000>;
392 hysteresis = <2000>;
393 type = "passive";
394 };
395 };
397 cooling-maps {
398 map2_hot: map2-hot {
399 trip = <&cpu2_hot>;
400 cooling-device = <&cpu2 1 2>,
401 <&cpu3 1 2>;
402 };
403 map2_emerg: map2-emerg {
404 trip = <&cpu2_emerg>;
405 cooling-device = <&cpu2 3 3>,
406 <&cpu3 3 3>;
407 };
408 };
409 };
411 ap_thermal_cpu3: ap-thermal-cpu3 {
412 polling-delay-passive = <1000>;
413 polling-delay = <1000>;
415 thermal-sensors = <&ap_thermal 4>;
417 trips {
418 cpu3_hot: cpu3-hot {
419 temperature = <85000>;
420 hysteresis = <2000>;
421 type = "passive";
422 };
423 cpu3_emerg: cpu3-emerg {
424 temperature = <95000>;
425 hysteresis = <2000>;
426 type = "passive";
427 };
428 };
430 cooling-maps {
431 map3_hot: map3-bhot {
432 trip = <&cpu3_hot>;
433 cooling-device = <&cpu2 1 2>,
434 <&cpu3 1 2>;
435 };
436 map3_emerg: map3-emerg {
437 trip = <&cpu3_emerg>;
438 cooling-device = <&cpu2 3 3>,
439 <&cpu3 3 3>;
440 };
441 };
442 };
443 };
444 };