| blob | 64c46ce3849dd5e1edc392ac64305734b7697fd8 |
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
12 / {
13 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
18 pcie@1003000 {
19 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi";
29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
34 #address-cells = <3>;
35 #size-cells = <2>;
37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
43 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>,
49 <&tegra_car 72>,
50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "pcie_x";
53 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>;
57 status = "disabled";
59 pci@1,0 {
60 device_type = "pci";
61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
64 status = "disabled";
66 #address-cells = <3>;
67 #size-cells = <2>;
68 ranges;
70 nvidia,num-lanes = <4>;
71 };
73 pci@2,0 {
74 device_type = "pci";
75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
78 status = "disabled";
80 #address-cells = <3>;
81 #size-cells = <2>;
82 ranges;
84 nvidia,num-lanes = <1>;
85 };
86 };
88 host1x@50000000 {
89 compatible = "nvidia,tegra210-host1x", "simple-bus";
90 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
94 clock-names = "host1x";
95 resets = <&tegra_car 28>;
96 reset-names = "host1x";
98 #address-cells = <2>;
99 #size-cells = <2>;
101 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 iommus = <&mc TEGRA_SWGROUP_HC>;
105 dpaux1: dpaux@54040000 {
106 compatible = "nvidia,tegra210-dpaux";
107 reg = <0x0 0x54040000 0x0 0x00040000>;
108 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
110 <&tegra_car TEGRA210_CLK_PLL_DP>;
111 clock-names = "dpaux", "parent";
112 resets = <&tegra_car 207>;
113 reset-names = "dpaux";
114 power-domains = <&pd_sor>;
115 status = "disabled";
117 state_dpaux1_aux: pinmux-aux {
118 groups = "dpaux-io";
119 function = "aux";
120 };
122 state_dpaux1_i2c: pinmux-i2c {
123 groups = "dpaux-io";
124 function = "i2c";
125 };
127 state_dpaux1_off: pinmux-off {
128 groups = "dpaux-io";
129 function = "off";
130 };
132 i2c-bus {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 };
136 };
138 vi@54080000 {
139 compatible = "nvidia,tegra210-vi";
140 reg = <0x0 0x54080000 0x0 0x00040000>;
141 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
142 status = "disabled";
143 };
145 tsec@54100000 {
146 compatible = "nvidia,tegra210-tsec";
147 reg = <0x0 0x54100000 0x0 0x00040000>;
148 };
150 dc@54200000 {
151 compatible = "nvidia,tegra210-dc";
152 reg = <0x0 0x54200000 0x0 0x00040000>;
153 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
155 <&tegra_car TEGRA210_CLK_PLL_P>;
156 clock-names = "dc", "parent";
157 resets = <&tegra_car 27>;
158 reset-names = "dc";
160 iommus = <&mc TEGRA_SWGROUP_DC>;
162 nvidia,head = <0>;
163 };
165 dc@54240000 {
166 compatible = "nvidia,tegra210-dc";
167 reg = <0x0 0x54240000 0x0 0x00040000>;
168 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
170 <&tegra_car TEGRA210_CLK_PLL_P>;
171 clock-names = "dc", "parent";
172 resets = <&tegra_car 26>;
173 reset-names = "dc";
175 iommus = <&mc TEGRA_SWGROUP_DCB>;
177 nvidia,head = <1>;
178 };
180 dsi@54300000 {
181 compatible = "nvidia,tegra210-dsi";
182 reg = <0x0 0x54300000 0x0 0x00040000>;
183 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
184 <&tegra_car TEGRA210_CLK_DSIALP>,
185 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
186 clock-names = "dsi", "lp", "parent";
187 resets = <&tegra_car 48>;
188 reset-names = "dsi";
189 power-domains = <&pd_sor>;
190 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
192 status = "disabled";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
198 vic@54340000 {
199 compatible = "nvidia,tegra210-vic";
200 reg = <0x0 0x54340000 0x0 0x00040000>;
201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
203 clock-names = "vic";
204 resets = <&tegra_car 178>;
205 reset-names = "vic";
207 iommus = <&mc TEGRA_SWGROUP_VIC>;
208 power-domains = <&pd_vic>;
209 };
211 nvjpg@54380000 {
212 compatible = "nvidia,tegra210-nvjpg";
213 reg = <0x0 0x54380000 0x0 0x00040000>;
214 status = "disabled";
215 };
217 dsi@54400000 {
218 compatible = "nvidia,tegra210-dsi";
219 reg = <0x0 0x54400000 0x0 0x00040000>;
220 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
221 <&tegra_car TEGRA210_CLK_DSIBLP>,
222 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
223 clock-names = "dsi", "lp", "parent";
224 resets = <&tegra_car 82>;
225 reset-names = "dsi";
226 power-domains = <&pd_sor>;
227 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
229 status = "disabled";
231 #address-cells = <1>;
232 #size-cells = <0>;
233 };
235 nvdec@54480000 {
236 compatible = "nvidia,tegra210-nvdec";
237 reg = <0x0 0x54480000 0x0 0x00040000>;
238 status = "disabled";
239 };
241 nvenc@544c0000 {
242 compatible = "nvidia,tegra210-nvenc";
243 reg = <0x0 0x544c0000 0x0 0x00040000>;
244 status = "disabled";
245 };
247 tsec@54500000 {
248 compatible = "nvidia,tegra210-tsec";
249 reg = <0x0 0x54500000 0x0 0x00040000>;
250 status = "disabled";
251 };
253 sor@54540000 {
254 compatible = "nvidia,tegra210-sor";
255 reg = <0x0 0x54540000 0x0 0x00040000>;
256 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
258 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
259 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
260 <&tegra_car TEGRA210_CLK_PLL_DP>,
261 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
262 clock-names = "sor", "out", "parent", "dp", "safe";
263 resets = <&tegra_car 182>;
264 reset-names = "sor";
265 pinctrl-0 = <&state_dpaux_aux>;
266 pinctrl-1 = <&state_dpaux_i2c>;
267 pinctrl-2 = <&state_dpaux_off>;
268 pinctrl-names = "aux", "i2c", "off";
269 power-domains = <&pd_sor>;
270 status = "disabled";
271 };
273 sor@54580000 {
274 compatible = "nvidia,tegra210-sor1";
275 reg = <0x0 0x54580000 0x0 0x00040000>;
276 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
278 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
279 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
280 <&tegra_car TEGRA210_CLK_PLL_DP>,
281 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
282 clock-names = "sor", "out", "parent", "dp", "safe";
283 resets = <&tegra_car 183>;
284 reset-names = "sor";
285 pinctrl-0 = <&state_dpaux1_aux>;
286 pinctrl-1 = <&state_dpaux1_i2c>;
287 pinctrl-2 = <&state_dpaux1_off>;
288 pinctrl-names = "aux", "i2c", "off";
289 power-domains = <&pd_sor>;
290 status = "disabled";
291 };
293 dpaux: dpaux@545c0000 {
294 compatible = "nvidia,tegra124-dpaux";
295 reg = <0x0 0x545c0000 0x0 0x00040000>;
296 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
298 <&tegra_car TEGRA210_CLK_PLL_DP>;
299 clock-names = "dpaux", "parent";
300 resets = <&tegra_car 181>;
301 reset-names = "dpaux";
302 power-domains = <&pd_sor>;
303 status = "disabled";
305 state_dpaux_aux: pinmux-aux {
306 groups = "dpaux-io";
307 function = "aux";
308 };
310 state_dpaux_i2c: pinmux-i2c {
311 groups = "dpaux-io";
312 function = "i2c";
313 };
315 state_dpaux_off: pinmux-off {
316 groups = "dpaux-io";
317 function = "off";
318 };
320 i2c-bus {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
324 };
326 isp@54600000 {
327 compatible = "nvidia,tegra210-isp";
328 reg = <0x0 0x54600000 0x0 0x00040000>;
329 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
330 status = "disabled";
331 };
333 isp@54680000 {
334 compatible = "nvidia,tegra210-isp";
335 reg = <0x0 0x54680000 0x0 0x00040000>;
336 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
337 status = "disabled";
338 };
340 i2c@546c0000 {
341 compatible = "nvidia,tegra210-i2c-vi";
342 reg = <0x0 0x546c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
344 status = "disabled";
345 };
346 };
348 gic: interrupt-controller@50041000 {
349 compatible = "arm,gic-400";
350 #interrupt-cells = <3>;
351 interrupt-controller;
352 reg = <0x0 0x50041000 0x0 0x1000>,
353 <0x0 0x50042000 0x0 0x2000>,
354 <0x0 0x50044000 0x0 0x2000>,
355 <0x0 0x50046000 0x0 0x2000>;
356 interrupts = <GIC_PPI 9
357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
358 interrupt-parent = <&gic>;
359 };
361 gpu@57000000 {
362 compatible = "nvidia,gm20b";
363 reg = <0x0 0x57000000 0x0 0x01000000>,
364 <0x0 0x58000000 0x0 0x01000000>;
365 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-names = "stall", "nonstall";
368 clocks = <&tegra_car TEGRA210_CLK_GPU>,
369 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
370 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
371 clock-names = "gpu", "pwr", "ref";
372 resets = <&tegra_car 184>;
373 reset-names = "gpu";
375 iommus = <&mc TEGRA_SWGROUP_GPU>;
377 status = "disabled";
378 };
380 lic: interrupt-controller@60004000 {
381 compatible = "nvidia,tegra210-ictlr";
382 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
383 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
384 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
385 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
386 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
387 <0x0 0x60004500 0x0 0x40>; /* senary controller */
388 interrupt-controller;
389 #interrupt-cells = <3>;
390 interrupt-parent = <&gic>;
391 };
393 timer@60005000 {
394 compatible = "nvidia,tegra210-timer";
395 reg = <0x0 0x60005000 0x0 0x400>;
396 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
411 clock-names = "timer";
412 };
414 tegra_car: clock@60006000 {
415 compatible = "nvidia,tegra210-car";
416 reg = <0x0 0x60006000 0x0 0x1000>;
417 #clock-cells = <1>;
418 #reset-cells = <1>;
419 };
421 flow-controller@60007000 {
422 compatible = "nvidia,tegra210-flowctrl";
423 reg = <0x0 0x60007000 0x0 0x1000>;
424 };
426 gpio: gpio@6000d000 {
427 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
428 reg = <0x0 0x6000d000 0x0 0x1000>;
429 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
437 #gpio-cells = <2>;
438 gpio-controller;
439 #interrupt-cells = <2>;
440 interrupt-controller;
441 };
443 apbdma: dma@60020000 {
444 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
445 reg = <0x0 0x60020000 0x0 0x1400>;
446 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
479 clock-names = "dma";
480 resets = <&tegra_car 34>;
481 reset-names = "dma";
482 #dma-cells = <1>;
483 };
485 apbmisc@70000800 {
486 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
487 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
488 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
489 };
491 pinmux: pinmux@700008d4 {
492 compatible = "nvidia,tegra210-pinmux";
493 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
494 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
495 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
496 sdmmc1 {
497 nvidia,pins = "drive_sdmmc1";
498 nvidia,pull-down-strength = <0x8>;
499 nvidia,pull-up-strength = <0x8>;
500 };
501 };
502 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
503 sdmmc1 {
504 nvidia,pins = "drive_sdmmc1";
505 nvidia,pull-down-strength = <0x4>;
506 nvidia,pull-up-strength = <0x3>;
507 };
508 };
509 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
510 sdmmc2 {
511 nvidia,pins = "drive_sdmmc2";
512 nvidia,pull-down-strength = <0x10>;
513 nvidia,pull-up-strength = <0x10>;
514 };
515 };
516 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
517 sdmmc3 {
518 nvidia,pins = "drive_sdmmc3";
519 nvidia,pull-down-strength = <0x8>;
520 nvidia,pull-up-strength = <0x8>;
521 };
522 };
523 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
524 sdmmc3 {
525 nvidia,pins = "drive_sdmmc3";
526 nvidia,pull-down-strength = <0x4>;
527 nvidia,pull-up-strength = <0x3>;
528 };
529 };
530 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
531 sdmmc4 {
532 nvidia,pins = "drive_sdmmc4";
533 nvidia,pull-down-strength = <0x10>;
534 nvidia,pull-up-strength = <0x10>;
535 };
536 };
537 };
539 /*
540 * There are two serial driver i.e. 8250 based simple serial
541 * driver and APB DMA based serial driver for higher baudrate
542 * and performance. To enable the 8250 based driver, the compatible
543 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
544 * the APB DMA based serial driver, the compatible is
545 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
546 */
547 uarta: serial@70006000 {
548 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
549 reg = <0x0 0x70006000 0x0 0x40>;
550 reg-shift = <2>;
551 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
553 clock-names = "serial";
554 resets = <&tegra_car 6>;
555 reset-names = "serial";
556 dmas = <&apbdma 8>, <&apbdma 8>;
557 dma-names = "rx", "tx";
558 status = "disabled";
559 };
561 uartb: serial@70006040 {
562 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
563 reg = <0x0 0x70006040 0x0 0x40>;
564 reg-shift = <2>;
565 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
567 clock-names = "serial";
568 resets = <&tegra_car 7>;
569 reset-names = "serial";
570 dmas = <&apbdma 9>, <&apbdma 9>;
571 dma-names = "rx", "tx";
572 status = "disabled";
573 };
575 uartc: serial@70006200 {
576 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
577 reg = <0x0 0x70006200 0x0 0x40>;
578 reg-shift = <2>;
579 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
581 clock-names = "serial";
582 resets = <&tegra_car 55>;
583 reset-names = "serial";
584 dmas = <&apbdma 10>, <&apbdma 10>;
585 dma-names = "rx", "tx";
586 status = "disabled";
587 };
589 uartd: serial@70006300 {
590 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
591 reg = <0x0 0x70006300 0x0 0x40>;
592 reg-shift = <2>;
593 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
595 clock-names = "serial";
596 resets = <&tegra_car 65>;
597 reset-names = "serial";
598 dmas = <&apbdma 19>, <&apbdma 19>;
599 dma-names = "rx", "tx";
600 status = "disabled";
601 };
603 pwm: pwm@7000a000 {
604 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
605 reg = <0x0 0x7000a000 0x0 0x100>;
606 #pwm-cells = <2>;
607 clocks = <&tegra_car TEGRA210_CLK_PWM>;
608 clock-names = "pwm";
609 resets = <&tegra_car 17>;
610 reset-names = "pwm";
611 status = "disabled";
612 };
614 i2c@7000c000 {
615 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
616 reg = <0x0 0x7000c000 0x0 0x100>;
617 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
618 #address-cells = <1>;
619 #size-cells = <0>;
620 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
621 clock-names = "div-clk";
622 resets = <&tegra_car 12>;
623 reset-names = "i2c";
624 dmas = <&apbdma 21>, <&apbdma 21>;
625 dma-names = "rx", "tx";
626 status = "disabled";
627 };
629 i2c@7000c400 {
630 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
631 reg = <0x0 0x7000c400 0x0 0x100>;
632 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
636 clock-names = "div-clk";
637 resets = <&tegra_car 54>;
638 reset-names = "i2c";
639 dmas = <&apbdma 22>, <&apbdma 22>;
640 dma-names = "rx", "tx";
641 status = "disabled";
642 };
644 i2c@7000c500 {
645 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
646 reg = <0x0 0x7000c500 0x0 0x100>;
647 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
648 #address-cells = <1>;
649 #size-cells = <0>;
650 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
651 clock-names = "div-clk";
652 resets = <&tegra_car 67>;
653 reset-names = "i2c";
654 dmas = <&apbdma 23>, <&apbdma 23>;
655 dma-names = "rx", "tx";
656 status = "disabled";
657 };
659 i2c@7000c700 {
660 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
661 reg = <0x0 0x7000c700 0x0 0x100>;
662 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
666 clock-names = "div-clk";
667 resets = <&tegra_car 103>;
668 reset-names = "i2c";
669 dmas = <&apbdma 26>, <&apbdma 26>;
670 dma-names = "rx", "tx";
671 pinctrl-0 = <&state_dpaux1_i2c>;
672 pinctrl-1 = <&state_dpaux1_off>;
673 pinctrl-names = "default", "idle";
674 status = "disabled";
675 };
677 i2c@7000d000 {
678 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
679 reg = <0x0 0x7000d000 0x0 0x100>;
680 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
682 #size-cells = <0>;
683 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
684 clock-names = "div-clk";
685 resets = <&tegra_car 47>;
686 reset-names = "i2c";
687 dmas = <&apbdma 24>, <&apbdma 24>;
688 dma-names = "rx", "tx";
689 status = "disabled";
690 };
692 i2c@7000d100 {
693 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
694 reg = <0x0 0x7000d100 0x0 0x100>;
695 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
699 clock-names = "div-clk";
700 resets = <&tegra_car 166>;
701 reset-names = "i2c";
702 dmas = <&apbdma 30>, <&apbdma 30>;
703 dma-names = "rx", "tx";
704 pinctrl-0 = <&state_dpaux_i2c>;
705 pinctrl-1 = <&state_dpaux_off>;
706 pinctrl-names = "default", "idle";
707 status = "disabled";
708 };
710 spi@7000d400 {
711 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
712 reg = <0x0 0x7000d400 0x0 0x200>;
713 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
717 clock-names = "spi";
718 resets = <&tegra_car 41>;
719 reset-names = "spi";
720 dmas = <&apbdma 15>, <&apbdma 15>;
721 dma-names = "rx", "tx";
722 status = "disabled";
723 };
725 spi@7000d600 {
726 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
727 reg = <0x0 0x7000d600 0x0 0x200>;
728 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
729 #address-cells = <1>;
730 #size-cells = <0>;
731 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
732 clock-names = "spi";
733 resets = <&tegra_car 44>;
734 reset-names = "spi";
735 dmas = <&apbdma 16>, <&apbdma 16>;
736 dma-names = "rx", "tx";
737 status = "disabled";
738 };
740 spi@7000d800 {
741 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
742 reg = <0x0 0x7000d800 0x0 0x200>;
743 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
744 #address-cells = <1>;
745 #size-cells = <0>;
746 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
747 clock-names = "spi";
748 resets = <&tegra_car 46>;
749 reset-names = "spi";
750 dmas = <&apbdma 17>, <&apbdma 17>;
751 dma-names = "rx", "tx";
752 status = "disabled";
753 };
755 spi@7000da00 {
756 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
757 reg = <0x0 0x7000da00 0x0 0x200>;
758 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <1>;
760 #size-cells = <0>;
761 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
762 clock-names = "spi";
763 resets = <&tegra_car 68>;
764 reset-names = "spi";
765 dmas = <&apbdma 18>, <&apbdma 18>;
766 dma-names = "rx", "tx";
767 status = "disabled";
768 };
770 rtc@7000e000 {
771 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
772 reg = <0x0 0x7000e000 0x0 0x100>;
773 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-parent = <&tegra_pmc>;
775 clocks = <&tegra_car TEGRA210_CLK_RTC>;
776 clock-names = "rtc";
777 };
779 tegra_pmc: pmc@7000e400 {
780 compatible = "nvidia,tegra210-pmc";
781 reg = <0x0 0x7000e400 0x0 0x400>;
782 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
783 clock-names = "pclk", "clk32k_in";
784 #clock-cells = <1>;
785 #interrupt-cells = <2>;
786 interrupt-controller;
788 powergates {
789 pd_audio: aud {
790 clocks = <&tegra_car TEGRA210_CLK_APE>,
791 <&tegra_car TEGRA210_CLK_APB2APE>;
792 resets = <&tegra_car 198>;
793 #power-domain-cells = <0>;
794 };
796 pd_sor: sor {
797 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
798 <&tegra_car TEGRA210_CLK_SOR1>,
799 <&tegra_car TEGRA210_CLK_CSI>,
800 <&tegra_car TEGRA210_CLK_DSIA>,
801 <&tegra_car TEGRA210_CLK_DSIB>,
802 <&tegra_car TEGRA210_CLK_DPAUX>,
803 <&tegra_car TEGRA210_CLK_DPAUX1>,
804 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
805 resets = <&tegra_car TEGRA210_CLK_SOR0>,
806 <&tegra_car TEGRA210_CLK_SOR1>,
807 <&tegra_car TEGRA210_CLK_CSI>,
808 <&tegra_car TEGRA210_CLK_DSIA>,
809 <&tegra_car TEGRA210_CLK_DSIB>,
810 <&tegra_car TEGRA210_CLK_DPAUX>,
811 <&tegra_car TEGRA210_CLK_DPAUX1>,
812 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
813 #power-domain-cells = <0>;
814 };
816 pd_xusbss: xusba {
817 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
818 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
819 #power-domain-cells = <0>;
820 };
822 pd_xusbdev: xusbb {
823 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
824 resets = <&tegra_car 95>;
825 #power-domain-cells = <0>;
826 };
828 pd_xusbhost: xusbc {
829 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
830 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
831 #power-domain-cells = <0>;
832 };
834 pd_vic: vic {
835 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
836 clock-names = "vic";
837 resets = <&tegra_car 178>;
838 reset-names = "vic";
839 #power-domain-cells = <0>;
840 };
841 };
843 sdmmc1_3v3: sdmmc1-3v3 {
844 pins = "sdmmc1";
845 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
846 };
848 sdmmc1_1v8: sdmmc1-1v8 {
849 pins = "sdmmc1";
850 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
851 };
853 sdmmc3_3v3: sdmmc3-3v3 {
854 pins = "sdmmc3";
855 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
856 };
858 sdmmc3_1v8: sdmmc3-1v8 {
859 pins = "sdmmc3";
860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
861 };
863 pex_dpd_disable: pex_en {
864 pex-dpd-disable {
865 pins = "pex-bias", "pex-clk1", "pex-clk2";
866 low-power-disable;
867 };
868 };
870 pex_dpd_enable: pex_dis {
871 pex-dpd-enable {
872 pins = "pex-bias", "pex-clk1", "pex-clk2";
873 low-power-enable;
874 };
875 };
876 };
878 fuse@7000f800 {
879 compatible = "nvidia,tegra210-efuse";
880 reg = <0x0 0x7000f800 0x0 0x400>;
881 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
882 clock-names = "fuse";
883 resets = <&tegra_car 39>;
884 reset-names = "fuse";
885 };
887 mc: memory-controller@70019000 {
888 compatible = "nvidia,tegra210-mc";
889 reg = <0x0 0x70019000 0x0 0x1000>;
890 clocks = <&tegra_car TEGRA210_CLK_MC>;
891 clock-names = "mc";
893 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
895 #iommu-cells = <1>;
896 };
898 sata@70020000 {
899 compatible = "nvidia,tegra210-ahci";
900 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
901 <0x0 0x70020000 0x0 0x7000>, /* SATA */
902 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
903 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&tegra_car TEGRA210_CLK_SATA>,
905 <&tegra_car TEGRA210_CLK_SATA_OOB>;
906 clock-names = "sata", "sata-oob";
907 resets = <&tegra_car 124>,
908 <&tegra_car 123>,
909 <&tegra_car 129>;
910 reset-names = "sata", "sata-oob", "sata-cold";
911 status = "disabled";
912 };
914 hda@70030000 {
915 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
916 reg = <0x0 0x70030000 0x0 0x10000>;
917 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&tegra_car TEGRA210_CLK_HDA>,
919 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
920 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
921 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
922 resets = <&tegra_car 125>, /* hda */
923 <&tegra_car 128>, /* hda2hdmi */
924 <&tegra_car 111>; /* hda2codec_2x */
925 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
926 status = "disabled";
927 };
929 usb@70090000 {
930 compatible = "nvidia,tegra210-xusb";
931 reg = <0x0 0x70090000 0x0 0x8000>,
932 <0x0 0x70098000 0x0 0x1000>,
933 <0x0 0x70099000 0x0 0x1000>;
934 reg-names = "hcd", "fpci", "ipfs";
936 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
940 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
941 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
942 <&tegra_car TEGRA210_CLK_XUSB_SS>,
943 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
944 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
945 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
946 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
947 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
948 <&tegra_car TEGRA210_CLK_CLK_M>,
949 <&tegra_car TEGRA210_CLK_PLL_E>;
950 clock-names = "xusb_host", "xusb_host_src",
951 "xusb_falcon_src", "xusb_ss",
952 "xusb_ss_div2", "xusb_ss_src",
953 "xusb_hs_src", "xusb_fs_src",
954 "pll_u_480m", "clk_m", "pll_e";
955 resets = <&tegra_car 89>, <&tegra_car 156>,
956 <&tegra_car 143>;
957 reset-names = "xusb_host", "xusb_ss", "xusb_src";
958 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
959 power-domain-names = "xusb_host", "xusb_ss";
961 nvidia,xusb-padctl = <&padctl>;
963 status = "disabled";
964 };
966 padctl: padctl@7009f000 {
967 compatible = "nvidia,tegra210-xusb-padctl";
968 reg = <0x0 0x7009f000 0x0 0x1000>;
969 resets = <&tegra_car 142>;
970 reset-names = "padctl";
972 status = "disabled";
974 pads {
975 usb2 {
976 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
977 clock-names = "trk";
978 status = "disabled";
980 lanes {
981 usb2-0 {
982 status = "disabled";
983 #phy-cells = <0>;
984 };
986 usb2-1 {
987 status = "disabled";
988 #phy-cells = <0>;
989 };
991 usb2-2 {
992 status = "disabled";
993 #phy-cells = <0>;
994 };
996 usb2-3 {
997 status = "disabled";
998 #phy-cells = <0>;
999 };
1000 };
1001 };
1003 hsic {
1004 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1005 clock-names = "trk";
1006 status = "disabled";
1008 lanes {
1009 hsic-0 {
1010 status = "disabled";
1011 #phy-cells = <0>;
1012 };
1014 hsic-1 {
1015 status = "disabled";
1016 #phy-cells = <0>;
1017 };
1018 };
1019 };
1021 pcie {
1022 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1023 clock-names = "pll";
1024 resets = <&tegra_car 205>;
1025 reset-names = "phy";
1026 status = "disabled";
1028 lanes {
1029 pcie-0 {
1030 status = "disabled";
1031 #phy-cells = <0>;
1032 };
1034 pcie-1 {
1035 status = "disabled";
1036 #phy-cells = <0>;
1037 };
1039 pcie-2 {
1040 status = "disabled";
1041 #phy-cells = <0>;
1042 };
1044 pcie-3 {
1045 status = "disabled";
1046 #phy-cells = <0>;
1047 };
1049 pcie-4 {
1050 status = "disabled";
1051 #phy-cells = <0>;
1052 };
1054 pcie-5 {
1055 status = "disabled";
1056 #phy-cells = <0>;
1057 };
1059 pcie-6 {
1060 status = "disabled";
1061 #phy-cells = <0>;
1062 };
1063 };
1064 };
1066 sata {
1067 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1068 clock-names = "pll";
1069 resets = <&tegra_car 204>;
1070 reset-names = "phy";
1071 status = "disabled";
1073 lanes {
1074 sata-0 {
1075 status = "disabled";
1076 #phy-cells = <0>;
1077 };
1078 };
1079 };
1080 };
1082 ports {
1083 usb2-0 {
1084 status = "disabled";
1085 };
1087 usb2-1 {
1088 status = "disabled";
1089 };
1091 usb2-2 {
1092 status = "disabled";
1093 };
1095 usb2-3 {
1096 status = "disabled";
1097 };
1099 hsic-0 {
1100 status = "disabled";
1101 };
1103 usb3-0 {
1104 status = "disabled";
1105 };
1107 usb3-1 {
1108 status = "disabled";
1109 };
1111 usb3-2 {
1112 status = "disabled";
1113 };
1115 usb3-3 {
1116 status = "disabled";
1117 };
1118 };
1119 };
1121 sdhci@700b0000 {
1122 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1123 reg = <0x0 0x700b0000 0x0 0x200>;
1124 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1126 clock-names = "sdhci";
1127 resets = <&tegra_car 14>;
1128 reset-names = "sdhci";
1129 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1130 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1131 pinctrl-0 = <&sdmmc1_3v3>;
1132 pinctrl-1 = <&sdmmc1_1v8>;
1133 pinctrl-2 = <&sdmmc1_3v3_drv>;
1134 pinctrl-3 = <&sdmmc1_1v8_drv>;
1135 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1136 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1137 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1138 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1139 nvidia,default-tap = <0x2>;
1140 nvidia,default-trim = <0x4>;
1141 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1142 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1143 <&tegra_car TEGRA210_CLK_PLL_C4>;
1144 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1145 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1146 status = "disabled";
1147 };
1149 sdhci@700b0200 {
1150 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1151 reg = <0x0 0x700b0200 0x0 0x200>;
1152 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1153 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1154 clock-names = "sdhci";
1155 resets = <&tegra_car 9>;
1156 reset-names = "sdhci";
1157 pinctrl-names = "sdmmc-1v8-drv";
1158 pinctrl-0 = <&sdmmc2_1v8_drv>;
1159 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1160 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1161 nvidia,default-tap = <0x8>;
1162 nvidia,default-trim = <0x0>;
1163 status = "disabled";
1164 };
1166 sdhci@700b0400 {
1167 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1168 reg = <0x0 0x700b0400 0x0 0x200>;
1169 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1171 clock-names = "sdhci";
1172 resets = <&tegra_car 69>;
1173 reset-names = "sdhci";
1174 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1175 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1176 pinctrl-0 = <&sdmmc3_3v3>;
1177 pinctrl-1 = <&sdmmc3_1v8>;
1178 pinctrl-2 = <&sdmmc3_3v3_drv>;
1179 pinctrl-3 = <&sdmmc3_1v8_drv>;
1180 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1181 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1182 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1183 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1184 nvidia,default-tap = <0x3>;
1185 nvidia,default-trim = <0x3>;
1186 status = "disabled";
1187 };
1189 sdhci@700b0600 {
1190 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1191 reg = <0x0 0x700b0600 0x0 0x200>;
1192 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1194 clock-names = "sdhci";
1195 resets = <&tegra_car 15>;
1196 reset-names = "sdhci";
1197 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1198 pinctrl-0 = <&sdmmc4_1v8_drv>;
1199 pinctrl-1 = <&sdmmc4_1v8_drv>;
1200 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1201 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1202 nvidia,default-tap = <0x8>;
1203 nvidia,default-trim = <0x0>;
1204 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1205 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1206 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1207 nvidia,dqs-trim = <40>;
1208 mmc-hs400-1_8v;
1209 status = "disabled";
1210 };
1212 usb@700d0000 {
1213 compatible = "nvidia,tegra210-xudc";
1214 reg = <0x0 0x700d0000 0x0 0x8000>,
1215 <0x0 0x700d8000 0x0 0x1000>,
1216 <0x0 0x700d9000 0x0 0x1000>;
1217 reg-names = "base", "fpci", "ipfs";
1218 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1220 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1221 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1222 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1223 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1224 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1225 power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1226 power-domain-names = "dev", "ss";
1227 nvidia,xusb-padctl = <&padctl>;
1228 status = "disabled";
1229 };
1231 mipi: mipi@700e3000 {
1232 compatible = "nvidia,tegra210-mipi";
1233 reg = <0x0 0x700e3000 0x0 0x100>;
1234 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1235 clock-names = "mipi-cal";
1236 power-domains = <&pd_sor>;
1237 #nvidia,mipi-calibrate-cells = <1>;
1238 };
1240 dfll: clock@70110000 {
1241 compatible = "nvidia,tegra210-dfll";
1242 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1243 <0 0x70110000 0 0x100>, /* I2C output control */
1244 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1245 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1246 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1248 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1249 <&tegra_car TEGRA210_CLK_I2C5>;
1250 clock-names = "soc", "ref", "i2c";
1251 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1252 reset-names = "dvco";
1253 #clock-cells = <0>;
1254 clock-output-names = "dfllCPU_out";
1255 status = "disabled";
1256 };
1258 aconnect@702c0000 {
1259 compatible = "nvidia,tegra210-aconnect";
1260 clocks = <&tegra_car TEGRA210_CLK_APE>,
1261 <&tegra_car TEGRA210_CLK_APB2APE>;
1262 clock-names = "ape", "apb2ape";
1263 power-domains = <&pd_audio>;
1264 #address-cells = <1>;
1265 #size-cells = <1>;
1266 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1267 status = "disabled";
1269 adma: dma@702e2000 {
1270 compatible = "nvidia,tegra210-adma";
1271 reg = <0x702e2000 0x2000>;
1272 interrupt-parent = <&agic>;
1273 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1295 #dma-cells = <1>;
1296 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1297 clock-names = "d_audio";
1298 status = "disabled";
1299 };
1301 agic: agic@702f9000 {
1302 compatible = "nvidia,tegra210-agic";
1303 #interrupt-cells = <3>;
1304 interrupt-controller;
1305 reg = <0x702f9000 0x1000>,
1306 <0x702fa000 0x2000>;
1307 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1308 clocks = <&tegra_car TEGRA210_CLK_APE>;
1309 clock-names = "clk";
1310 status = "disabled";
1311 };
1312 };
1314 spi@70410000 {
1315 compatible = "nvidia,tegra210-qspi";
1316 reg = <0x0 0x70410000 0x0 0x1000>;
1317 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1318 #address-cells = <1>;
1319 #size-cells = <0>;
1320 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1321 clock-names = "qspi";
1322 resets = <&tegra_car 211>;
1323 reset-names = "qspi";
1324 dmas = <&apbdma 5>, <&apbdma 5>;
1325 dma-names = "rx", "tx";
1326 status = "disabled";
1327 };
1329 usb@7d000000 {
1330 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1331 reg = <0x0 0x7d000000 0x0 0x4000>;
1332 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1333 phy_type = "utmi";
1334 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1335 clock-names = "usb";
1336 resets = <&tegra_car 22>;
1337 reset-names = "usb";
1338 nvidia,phy = <&phy1>;
1339 status = "disabled";
1340 };
1342 phy1: usb-phy@7d000000 {
1343 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1344 reg = <0x0 0x7d000000 0x0 0x4000>,
1345 <0x0 0x7d000000 0x0 0x4000>;
1346 phy_type = "utmi";
1347 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1348 <&tegra_car TEGRA210_CLK_PLL_U>,
1349 <&tegra_car TEGRA210_CLK_USBD>;
1350 clock-names = "reg", "pll_u", "utmi-pads";
1351 resets = <&tegra_car 22>, <&tegra_car 22>;
1352 reset-names = "usb", "utmi-pads";
1353 nvidia,hssync-start-delay = <0>;
1354 nvidia,idle-wait-delay = <17>;
1355 nvidia,elastic-limit = <16>;
1356 nvidia,term-range-adj = <6>;
1357 nvidia,xcvr-setup = <9>;
1358 nvidia,xcvr-lsfslew = <0>;
1359 nvidia,xcvr-lsrslew = <3>;
1360 nvidia,hssquelch-level = <2>;
1361 nvidia,hsdiscon-level = <5>;
1362 nvidia,xcvr-hsslew = <12>;
1363 nvidia,has-utmi-pad-registers;
1364 status = "disabled";
1365 };
1367 usb@7d004000 {
1368 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1369 reg = <0x0 0x7d004000 0x0 0x4000>;
1370 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1371 phy_type = "utmi";
1372 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1373 clock-names = "usb";
1374 resets = <&tegra_car 58>;
1375 reset-names = "usb";
1376 nvidia,phy = <&phy2>;
1377 status = "disabled";
1378 };
1380 phy2: usb-phy@7d004000 {
1381 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1382 reg = <0x0 0x7d004000 0x0 0x4000>,
1383 <0x0 0x7d000000 0x0 0x4000>;
1384 phy_type = "utmi";
1385 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1386 <&tegra_car TEGRA210_CLK_PLL_U>,
1387 <&tegra_car TEGRA210_CLK_USBD>;
1388 clock-names = "reg", "pll_u", "utmi-pads";
1389 resets = <&tegra_car 58>, <&tegra_car 22>;
1390 reset-names = "usb", "utmi-pads";
1391 nvidia,hssync-start-delay = <0>;
1392 nvidia,idle-wait-delay = <17>;
1393 nvidia,elastic-limit = <16>;
1394 nvidia,term-range-adj = <6>;
1395 nvidia,xcvr-setup = <9>;
1396 nvidia,xcvr-lsfslew = <0>;
1397 nvidia,xcvr-lsrslew = <3>;
1398 nvidia,hssquelch-level = <2>;
1399 nvidia,hsdiscon-level = <5>;
1400 nvidia,xcvr-hsslew = <12>;
1401 status = "disabled";
1402 };
1404 cpus {
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1408 cpu@0 {
1409 device_type = "cpu";
1410 compatible = "arm,cortex-a57";
1411 reg = <0>;
1412 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1413 <&tegra_car TEGRA210_CLK_PLL_X>,
1414 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1415 <&dfll>;
1416 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1417 clock-latency = <300000>;
1418 cpu-idle-states = <&CPU_SLEEP>;
1419 next-level-cache = <&L2>;
1420 };
1422 cpu@1 {
1423 device_type = "cpu";
1424 compatible = "arm,cortex-a57";
1425 reg = <1>;
1426 cpu-idle-states = <&CPU_SLEEP>;
1427 next-level-cache = <&L2>;
1428 };
1430 cpu@2 {
1431 device_type = "cpu";
1432 compatible = "arm,cortex-a57";
1433 reg = <2>;
1434 cpu-idle-states = <&CPU_SLEEP>;
1435 next-level-cache = <&L2>;
1436 };
1438 cpu@3 {
1439 device_type = "cpu";
1440 compatible = "arm,cortex-a57";
1441 reg = <3>;
1442 cpu-idle-states = <&CPU_SLEEP>;
1443 next-level-cache = <&L2>;
1444 };
1446 idle-states {
1447 entry-method = "psci";
1449 CPU_SLEEP: cpu-sleep {
1450 compatible = "arm,idle-state";
1451 arm,psci-suspend-param = <0x40000007>;
1452 entry-latency-us = <100>;
1453 exit-latency-us = <30>;
1454 min-residency-us = <1000>;
1455 wakeup-latency-us = <130>;
1456 idle-state-name = "cpu-sleep";
1457 status = "disabled";
1458 };
1459 };
1461 L2: l2-cache {
1462 compatible = "cache";
1463 };
1464 };
1466 pmu {
1467 compatible = "arm,armv8-pmuv3";
1468 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1472 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1473 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
1474 };
1476 timer {
1477 compatible = "arm,armv8-timer";
1478 interrupts = <GIC_PPI 13
1479 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1480 <GIC_PPI 14
1481 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1482 <GIC_PPI 11
1483 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1484 <GIC_PPI 10
1485 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1486 interrupt-parent = <&gic>;
1487 arm,no-tick-in-suspend;
1488 };
1490 soctherm: thermal-sensor@700e2000 {
1491 compatible = "nvidia,tegra210-soctherm";
1492 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1493 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1494 reg-names = "soctherm-reg", "car-reg";
1495 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1497 interrupt-names = "thermal", "edp";
1498 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1499 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1500 clock-names = "tsensor", "soctherm";
1501 resets = <&tegra_car 78>;
1502 reset-names = "soctherm";
1503 #thermal-sensor-cells = <1>;
1505 throttle-cfgs {
1506 throttle_heavy: heavy {
1507 nvidia,priority = <100>;
1508 nvidia,cpu-throt-percent = <85>;
1510 #cooling-cells = <2>;
1511 };
1512 };
1513 };
1515 thermal-zones {
1516 cpu {
1517 polling-delay-passive = <1000>;
1518 polling-delay = <0>;
1520 thermal-sensors =
1521 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1523 trips {
1524 cpu-shutdown-trip {
1525 temperature = <102500>;
1526 hysteresis = <0>;
1527 type = "critical";
1528 };
1530 cpu_throttle_trip: throttle-trip {
1531 temperature = <98500>;
1532 hysteresis = <1000>;
1533 type = "hot";
1534 };
1535 };
1537 cooling-maps {
1538 map0 {
1539 trip = <&cpu_throttle_trip>;
1540 cooling-device = <&throttle_heavy 1 1>;
1541 };
1542 };
1543 };
1545 mem {
1546 polling-delay-passive = <0>;
1547 polling-delay = <0>;
1549 thermal-sensors =
1550 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1552 trips {
1553 mem-shutdown-trip {
1554 temperature = <103000>;
1555 hysteresis = <0>;
1556 type = "critical";
1557 };
1558 };
1560 cooling-maps {
1561 /*
1562 * There are currently no cooling maps,
1563 * because there are no cooling devices.
1564 */
1565 };
1566 };
1568 gpu {
1569 polling-delay-passive = <1000>;
1570 polling-delay = <0>;
1572 thermal-sensors =
1573 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1575 trips {
1576 gpu-shutdown-trip {
1577 temperature = <103000>;
1578 hysteresis = <0>;
1579 type = "critical";
1580 };
1582 gpu_throttle_trip: throttle-trip {
1583 temperature = <100000>;
1584 hysteresis = <1000>;
1585 type = "hot";
1586 };
1587 };
1589 cooling-maps {
1590 map0 {
1591 trip = <&gpu_throttle_trip>;
1592 cooling-device = <&throttle_heavy 1 1>;
1593 };
1594 };
1595 };
1597 pllx {
1598 polling-delay-passive = <0>;
1599 polling-delay = <0>;
1601 thermal-sensors =
1602 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1604 trips {
1605 pllx-shutdown-trip {
1606 temperature = <103000>;
1607 hysteresis = <0>;
1608 type = "critical";
1609 };
1610 };
1612 cooling-maps {
1613 /*
1614 * There are currently no cooling maps,
1615 * because there are no cooling devices.
1616 */
1617 };
1618 };
1619 };
1620 };