arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   8 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
   9 #include <dt-bindings/clock/qcom,rpmcc.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  20                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  21         };
  22
  23         chosen { };
  24
  25         memory {
  26                 device_type = "memory";
  27                 /* We expect the bootloader to fill in the reg */
  28                 reg = <0 0 0 0>;
  29         };
  30
  31         reserved-memory {
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35
  36                 tz-apps@86000000 {
  37                         reg = <0x0 0x86000000 0x0 0x300000>;
  38                         no-map;
  39                 };
  40
  41                 smem_mem: smem_region@86300000 {
  42                         reg = <0x0 0x86300000 0x0 0x100000>;
  43                         no-map;
  44                 };
  45
  46                 hypervisor@86400000 {
  47                         reg = <0x0 0x86400000 0x0 0x100000>;
  48                         no-map;
  49                 };
  50
  51                 tz@86500000 {
  52                         reg = <0x0 0x86500000 0x0 0x180000>;
  53                         no-map;
  54                 };
  55
  56                 reserved@8668000 {
  57                         reg = <0x0 0x86680000 0x0 0x80000>;
  58                         no-map;
  59                 };
  60
  61                 rmtfs@86700000 {
  62                         compatible = "qcom,rmtfs-mem";
  63                         reg = <0x0 0x86700000 0x0 0xe0000>;
  64                         no-map;
  65
  66                         qcom,client-id = <1>;
  67                 };
  68
  69                 rfsa@867e00000 {
  70                         reg = <0x0 0x867e0000 0x0 0x20000>;
  71                         no-map;
  72                 };
  73
  74                 mpss_mem: mpss@86800000 {
  75                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  76                         no-map;
  77                 };
  78
  79                 wcnss_mem: wcnss@89300000 {
  80                         reg = <0x0 0x89300000 0x0 0x600000>;
  81                         no-map;
  82                 };
  83
  84                 venus_mem: venus@89900000 {
  85                         reg = <0x0 0x89900000 0x0 0x600000>;
  86                         no-map;
  87                 };
  88
  89                 mba_mem: mba@8ea00000 {
  90                         no-map;
  91                         reg = <0 0x8ea00000 0 0x100000>;
  92                 };
  93         };
  94
  95         cpus {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 CPU0: cpu@0 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53";
 102                         reg = <0x0>;
 103                         next-level-cache = <&L2_0>;
 104                         enable-method = "psci";
 105                         clocks = <&apcs>;
 106                         operating-points-v2 = <&cpu_opp_table>;
 107                         #cooling-cells = <2>;
 108                         power-domains = <&CPU_PD0>;
 109                         power-domain-names = "psci";
 110                 };
 111
 112                 CPU1: cpu@1 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a53";
 115                         reg = <0x1>;
 116                         next-level-cache = <&L2_0>;
 117                         enable-method = "psci";
 118                         clocks = <&apcs>;
 119                         operating-points-v2 = <&cpu_opp_table>;
 120                         #cooling-cells = <2>;
 121                         power-domains = <&CPU_PD1>;
 122                         power-domain-names = "psci";
 123                 };
 124
 125                 CPU2: cpu@2 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53";
 128                         reg = <0x2>;
 129                         next-level-cache = <&L2_0>;
 130                         enable-method = "psci";
 131                         clocks = <&apcs>;
 132                         operating-points-v2 = <&cpu_opp_table>;
 133                         #cooling-cells = <2>;
 134                         power-domains = <&CPU_PD2>;
 135                         power-domain-names = "psci";
 136                 };
 137
 138                 CPU3: cpu@3 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a53";
 141                         reg = <0x3>;
 142                         next-level-cache = <&L2_0>;
 143                         enable-method = "psci";
 144                         clocks = <&apcs>;
 145                         operating-points-v2 = <&cpu_opp_table>;
 146                         #cooling-cells = <2>;
 147                         power-domains = <&CPU_PD3>;
 148                         power-domain-names = "psci";
 149                 };
 150
 151                 L2_0: l2-cache {
 152                       compatible = "cache";
 153                       cache-level = <2>;
 154                 };
 155
 156                 idle-states {
 157                         entry-method = "psci";
 158
 159                         CPU_SLEEP_0: cpu-sleep-0 {
 160                                 compatible = "arm,idle-state";
 161                                 idle-state-name = "standalone-power-collapse";
 162                                 arm,psci-suspend-param = <0x40000002>;
 163                                 entry-latency-us = <130>;
 164                                 exit-latency-us = <150>;
 165                                 min-residency-us = <2000>;
 166                                 local-timer-stop;
 167                         };
 168
 169                         CLUSTER_RET: cluster-retention {
 170                                 compatible = "domain-idle-state";
 171                                 arm,psci-suspend-param = <0x41000012>;
 172                                 entry-latency-us = <500>;
 173                                 exit-latency-us = <500>;
 174                                 min-residency-us = <2000>;
 175                         };
 176
 177                         CLUSTER_PWRDN: cluster-gdhs {
 178                                 compatible = "domain-idle-state";
 179                                 arm,psci-suspend-param = <0x41000032>;
 180                                 entry-latency-us = <2000>;
 181                                 exit-latency-us = <2000>;
 182                                 min-residency-us = <6000>;
 183                         };
 184                 };
 185         };
 186
 187         psci {
 188                 compatible = "arm,psci-1.0";
 189                 method = "smc";
 190
 191                 CPU_PD0: cpu-pd0 {
 192                         #power-domain-cells = <0>;
 193                         power-domains = <&CLUSTER_PD>;
 194                         domain-idle-states = <&CPU_SLEEP_0>;
 195                 };
 196
 197                 CPU_PD1: cpu-pd1 {
 198                         #power-domain-cells = <0>;
 199                         power-domains = <&CLUSTER_PD>;
 200                         domain-idle-states = <&CPU_SLEEP_0>;
 201                 };
 202
 203                 CPU_PD2: cpu-pd2 {
 204                         #power-domain-cells = <0>;
 205                         power-domains = <&CLUSTER_PD>;
 206                         domain-idle-states = <&CPU_SLEEP_0>;
 207                 };
 208
 209                 CPU_PD3: cpu-pd3 {
 210                         #power-domain-cells = <0>;
 211                         power-domains = <&CLUSTER_PD>;
 212                         domain-idle-states = <&CPU_SLEEP_0>;
 213                 };
 214
 215                 CLUSTER_PD: cluster-pd {
 216                         #power-domain-cells = <0>;
 217                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 218                 };
 219         };
 220
 221         pmu {
 222                 compatible = "arm,cortex-a53-pmu";
 223                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
 224         };
 225
 226         thermal-zones {
 227                 cpu0_1-thermal {
 228                         polling-delay-passive = <250>;
 229                         polling-delay = <1000>;
 230
 231                         thermal-sensors = <&tsens 5>;
 232
 233                         trips {
 234                                 cpu0_1_alert0: trip-point@0 {
 235                                         temperature = <75000>;
 236                                         hysteresis = <2000>;
 237                                         type = "passive";
 238                                 };
 239                                 cpu0_1_crit: cpu_crit {
 240                                         temperature = <110000>;
 241                                         hysteresis = <2000>;
 242                                         type = "critical";
 243                                 };
 244                         };
 245
 246                         cooling-maps {
 247                                 map0 {
 248                                         trip = <&cpu0_1_alert0>;
 249                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 250                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 251                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 252                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 253                                 };
 254                         };
 255                 };
 256
 257                 cpu2_3-thermal {
 258                         polling-delay-passive = <250>;
 259                         polling-delay = <1000>;
 260
 261                         thermal-sensors = <&tsens 4>;
 262
 263                         trips {
 264                                 cpu2_3_alert0: trip-point@0 {
 265                                         temperature = <75000>;
 266                                         hysteresis = <2000>;
 267                                         type = "passive";
 268                                 };
 269                                 cpu2_3_crit: cpu_crit {
 270                                         temperature = <110000>;
 271                                         hysteresis = <2000>;
 272                                         type = "critical";
 273                                 };
 274                         };
 275
 276                         cooling-maps {
 277                                 map0 {
 278                                         trip = <&cpu2_3_alert0>;
 279                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 280                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 281                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 282                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 283                                 };
 284                         };
 285                 };
 286
 287                 gpu-thermal {
 288                         polling-delay-passive = <250>;
 289                         polling-delay = <1000>;
 290
 291                         thermal-sensors = <&tsens 2>;
 292
 293                         trips {
 294                                 gpu_alert0: trip-point@0 {
 295                                         temperature = <75000>;
 296                                         hysteresis = <2000>;
 297                                         type = "passive";
 298                                 };
 299                                 gpu_crit: gpu_crit {
 300                                         temperature = <95000>;
 301                                         hysteresis = <2000>;
 302                                         type = "critical";
 303                                 };
 304                         };
 305                 };
 306
 307                 camera-thermal {
 308                         polling-delay-passive = <250>;
 309                         polling-delay = <1000>;
 310
 311                         thermal-sensors = <&tsens 1>;
 312
 313                         trips {
 314                                 cam_alert0: trip-point@0 {
 315                                         temperature = <75000>;
 316                                         hysteresis = <2000>;
 317                                         type = "hot";
 318                                 };
 319                         };
 320                 };
 321
 322                 modem-thermal {
 323                         polling-delay-passive = <250>;
 324                         polling-delay = <1000>;
 325
 326                         thermal-sensors = <&tsens 0>;
 327
 328                         trips {
 329                                 modem_alert0: trip-point@0 {
 330                                         temperature = <85000>;
 331                                         hysteresis = <2000>;
 332                                         type = "hot";
 333                                 };
 334                         };
 335                 };
 336
 337         };
 338
 339         cpu_opp_table: cpu_opp_table {
 340                 compatible = "operating-points-v2";
 341                 opp-shared;
 342
 343                 opp-200000000 {
 344                         opp-hz = /bits/ 64 <200000000>;
 345                 };
 346                 opp-400000000 {
 347                         opp-hz = /bits/ 64 <400000000>;
 348                 };
 349                 opp-800000000 {
 350                         opp-hz = /bits/ 64 <800000000>;
 351                 };
 352                 opp-998400000 {
 353                         opp-hz = /bits/ 64 <998400000>;
 354                 };
 355         };
 356
 357         gpu_opp_table: opp_table {
 358                 compatible = "operating-points-v2";
 359
 360                 opp-400000000 {
 361                         opp-hz = /bits/ 64 <400000000>;
 362                 };
 363                 opp-19200000 {
 364                         opp-hz = /bits/ 64 <19200000>;
 365                 };
 366         };
 367
 368         timer {
 369                 compatible = "arm,armv8-timer";
 370                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 371                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 372                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 373                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 374         };
 375
 376         clocks {
 377                 xo_board: xo_board {
 378                         compatible = "fixed-clock";
 379                         #clock-cells = <0>;
 380                         clock-frequency = <19200000>;
 381                 };
 382
 383                 sleep_clk: sleep_clk {
 384                         compatible = "fixed-clock";
 385                         #clock-cells = <0>;
 386                         clock-frequency = <32768>;
 387                 };
 388         };
 389
 390         smem {
 391                 compatible = "qcom,smem";
 392
 393                 memory-region = <&smem_mem>;
 394                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 395
 396                 hwlocks = <&tcsr_mutex 3>;
 397         };
 398
 399         firmware {
 400                 scm: scm {
 401                         compatible = "qcom,scm";
 402                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 403                         clock-names = "core", "bus", "iface";
 404                         #reset-cells = <1>;
 405
 406                         qcom,dload-mode = <&tcsr 0x6100>;
 407                 };
 408         };
 409
 410         soc: soc {
 411                 #address-cells = <1>;
 412                 #size-cells = <1>;
 413                 ranges = <0 0 0 0xffffffff>;
 414                 compatible = "simple-bus";
 415
 416                 restart@4ab000 {
 417                         compatible = "qcom,pshold";
 418                         reg = <0x4ab000 0x4>;
 419                 };
 420
 421                 msmgpio: pinctrl@1000000 {
 422                         compatible = "qcom,msm8916-pinctrl";
 423                         reg = <0x1000000 0x300000>;
 424                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 425                         gpio-controller;
 426                         #gpio-cells = <2>;
 427                         interrupt-controller;
 428                         #interrupt-cells = <2>;
 429                 };
 430
 431                 gcc: clock-controller@1800000 {
 432                         compatible = "qcom,gcc-msm8916";
 433                         #clock-cells = <1>;
 434                         #reset-cells = <1>;
 435                         #power-domain-cells = <1>;
 436                         reg = <0x1800000 0x80000>;
 437                 };
 438
 439                 tcsr_mutex_regs: syscon@1905000 {
 440                         compatible = "syscon";
 441                         reg = <0x1905000 0x20000>;
 442                 };
 443
 444                 tcsr: syscon@1937000 {
 445                         compatible = "qcom,tcsr-msm8916", "syscon";
 446                         reg = <0x1937000 0x30000>;
 447                 };
 448
 449                 tcsr_mutex: hwlock {
 450                         compatible = "qcom,tcsr-mutex";
 451                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 452                         #hwlock-cells = <1>;
 453                 };
 454
 455                 rpm_msg_ram: memory@60000 {
 456                         compatible = "qcom,rpm-msg-ram";
 457                         reg = <0x60000 0x8000>;
 458                 };
 459
 460                 blsp1_uart1: serial@78af000 {
 461                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 462                         reg = <0x78af000 0x200>;
 463                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 465                         clock-names = "core", "iface";
 466                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 467                         dma-names = "rx", "tx";
 468                         status = "disabled";
 469                 };
 470
 471                 a53pll: clock@b016000 {
 472                         compatible = "qcom,msm8916-a53pll";
 473                         reg = <0xb016000 0x40>;
 474                         #clock-cells = <0>;
 475                 };
 476
 477                 apcs: mailbox@b011000 {
 478                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
 479                         reg = <0xb011000 0x1000>;
 480                         #mbox-cells = <1>;
 481                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
 482                         clock-names = "pll", "aux";
 483                         #clock-cells = <0>;
 484                 };
 485
 486                 blsp1_uart2: serial@78b0000 {
 487                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 488                         reg = <0x78b0000 0x200>;
 489                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 491                         clock-names = "core", "iface";
 492                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 493                         dma-names = "rx", "tx";
 494                         status = "disabled";
 495                 };
 496
 497                 blsp_dma: dma@7884000 {
 498                         compatible = "qcom,bam-v1.7.0";
 499                         reg = <0x07884000 0x23000>;
 500                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 502                         clock-names = "bam_clk";
 503                         #dma-cells = <1>;
 504                         qcom,ee = <0>;
 505                         status = "disabled";
 506                 };
 507
 508                 blsp_spi1: spi@78b5000 {
 509                         compatible = "qcom,spi-qup-v2.2.1";
 510                         reg = <0x078b5000 0x500>;
 511                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 513                                  <&gcc GCC_BLSP1_AHB_CLK>;
 514                         clock-names = "core", "iface";
 515                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 516                         dma-names = "rx", "tx";
 517                         pinctrl-names = "default", "sleep";
 518                         pinctrl-0 = <&spi1_default>;
 519                         pinctrl-1 = <&spi1_sleep>;
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         status = "disabled";
 523                 };
 524
 525                 blsp_spi2: spi@78b6000 {
 526                         compatible = "qcom,spi-qup-v2.2.1";
 527                         reg = <0x078b6000 0x500>;
 528                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 530                                  <&gcc GCC_BLSP1_AHB_CLK>;
 531                         clock-names = "core", "iface";
 532                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 533                         dma-names = "rx", "tx";
 534                         pinctrl-names = "default", "sleep";
 535                         pinctrl-0 = <&spi2_default>;
 536                         pinctrl-1 = <&spi2_sleep>;
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         status = "disabled";
 540                 };
 541
 542                 blsp_spi3: spi@78b7000 {
 543                         compatible = "qcom,spi-qup-v2.2.1";
 544                         reg = <0x078b7000 0x500>;
 545                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 547                                  <&gcc GCC_BLSP1_AHB_CLK>;
 548                         clock-names = "core", "iface";
 549                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 550                         dma-names = "rx", "tx";
 551                         pinctrl-names = "default", "sleep";
 552                         pinctrl-0 = <&spi3_default>;
 553                         pinctrl-1 = <&spi3_sleep>;
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         status = "disabled";
 557                 };
 558
 559                 blsp_spi4: spi@78b8000 {
 560                         compatible = "qcom,spi-qup-v2.2.1";
 561                         reg = <0x078b8000 0x500>;
 562                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 564                                  <&gcc GCC_BLSP1_AHB_CLK>;
 565                         clock-names = "core", "iface";
 566                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 567                         dma-names = "rx", "tx";
 568                         pinctrl-names = "default", "sleep";
 569                         pinctrl-0 = <&spi4_default>;
 570                         pinctrl-1 = <&spi4_sleep>;
 571                         #address-cells = <1>;
 572                         #size-cells = <0>;
 573                         status = "disabled";
 574                 };
 575
 576                 blsp_spi5: spi@78b9000 {
 577                         compatible = "qcom,spi-qup-v2.2.1";
 578                         reg = <0x078b9000 0x500>;
 579                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 581                                  <&gcc GCC_BLSP1_AHB_CLK>;
 582                         clock-names = "core", "iface";
 583                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 584                         dma-names = "rx", "tx";
 585                         pinctrl-names = "default", "sleep";
 586                         pinctrl-0 = <&spi5_default>;
 587                         pinctrl-1 = <&spi5_sleep>;
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         status = "disabled";
 591                 };
 592
 593                 blsp_spi6: spi@78ba000 {
 594                         compatible = "qcom,spi-qup-v2.2.1";
 595                         reg = <0x078ba000 0x500>;
 596                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 597                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 598                                  <&gcc GCC_BLSP1_AHB_CLK>;
 599                         clock-names = "core", "iface";
 600                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 601                         dma-names = "rx", "tx";
 602                         pinctrl-names = "default", "sleep";
 603                         pinctrl-0 = <&spi6_default>;
 604                         pinctrl-1 = <&spi6_sleep>;
 605                         #address-cells = <1>;
 606                         #size-cells = <0>;
 607                         status = "disabled";
 608                 };
 609
 610                 blsp_i2c2: i2c@78b6000 {
 611                         compatible = "qcom,i2c-qup-v2.2.1";
 612                         reg = <0x078b6000 0x500>;
 613                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 614                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 615                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 616                         clock-names = "iface", "core";
 617                         pinctrl-names = "default", "sleep";
 618                         pinctrl-0 = <&i2c2_default>;
 619                         pinctrl-1 = <&i2c2_sleep>;
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                         status = "disabled";
 623                 };
 624
 625                 blsp_i2c4: i2c@78b8000 {
 626                         compatible = "qcom,i2c-qup-v2.2.1";
 627                         reg = <0x078b8000 0x500>;
 628                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 629                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 630                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 631                         clock-names = "iface", "core";
 632                         pinctrl-names = "default", "sleep";
 633                         pinctrl-0 = <&i2c4_default>;
 634                         pinctrl-1 = <&i2c4_sleep>;
 635                         #address-cells = <1>;
 636                         #size-cells = <0>;
 637                         status = "disabled";
 638                 };
 639
 640                 blsp_i2c6: i2c@78ba000 {
 641                         compatible = "qcom,i2c-qup-v2.2.1";
 642                         reg = <0x078ba000 0x500>;
 643                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 644                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 645                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 646                         clock-names = "iface", "core";
 647                         pinctrl-names = "default", "sleep";
 648                         pinctrl-0 = <&i2c6_default>;
 649                         pinctrl-1 = <&i2c6_sleep>;
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         status = "disabled";
 653                 };
 654
 655                 lpass: lpass@7708000 {
 656                         status = "disabled";
 657                         compatible = "qcom,lpass-cpu-apq8016";
 658                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 659                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 660                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 661                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 662                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 663                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 664                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 665
 666                         clock-names = "ahbix-clk",
 667                                         "pcnoc-mport-clk",
 668                                         "pcnoc-sway-clk",
 669                                         "mi2s-bit-clk0",
 670                                         "mi2s-bit-clk1",
 671                                         "mi2s-bit-clk2",
 672                                         "mi2s-bit-clk3";
 673                         #sound-dai-cells = <1>;
 674
 675                         interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
 676                         interrupt-names = "lpass-irq-lpaif";
 677                         reg = <0x07708000 0x10000>;
 678                         reg-names = "lpass-lpaif";
 679                 };
 680
 681                 lpass_codec: codec{
 682                         compatible = "qcom,msm8916-wcd-digital-codec";
 683                         reg = <0x0771c000 0x400>;
 684                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 685                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
 686                         clock-names = "ahbix-clk", "mclk";
 687                         #sound-dai-cells = <1>;
 688                 };
 689
 690                 sdhc_1: sdhci@7824000 {
 691                         compatible = "qcom,sdhci-msm-v4";
 692                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 693                         reg-names = "hc_mem", "core_mem";
 694
 695                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
 696                         interrupt-names = "hc_irq", "pwr_irq";
 697                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 698                                  <&gcc GCC_SDCC1_AHB_CLK>,
 699                                  <&xo_board>;
 700                         clock-names = "core", "iface", "xo";
 701                         mmc-ddr-1_8v;
 702                         bus-width = <8>;
 703                         non-removable;
 704                         status = "disabled";
 705                 };
 706
 707                 sdhc_2: sdhci@7864000 {
 708                         compatible = "qcom,sdhci-msm-v4";
 709                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 710                         reg-names = "hc_mem", "core_mem";
 711
 712                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
 713                         interrupt-names = "hc_irq", "pwr_irq";
 714                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 715                                  <&gcc GCC_SDCC2_AHB_CLK>,
 716                                  <&xo_board>;
 717                         clock-names = "core", "iface", "xo";
 718                         bus-width = <4>;
 719                         status = "disabled";
 720                 };
 721
 722                 otg: usb@78d9000 {
 723                         compatible = "qcom,ci-hdrc";
 724                         reg = <0x78d9000 0x200>,
 725                               <0x78d9200 0x200>;
 726                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 728                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 729                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 730                         clock-names = "iface", "core";
 731                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 732                         assigned-clock-rates = <80000000>;
 733                         resets = <&gcc GCC_USB_HS_BCR>;
 734                         reset-names = "core";
 735                         phy_type = "ulpi";
 736                         dr_mode = "otg";
 737                         ahb-burst-config = <0>;
 738                         phy-names = "usb-phy";
 739                         phys = <&usb_hs_phy>;
 740                         status = "disabled";
 741                         #reset-cells = <1>;
 742
 743                         ulpi {
 744                                 usb_hs_phy: phy {
 745                                         compatible = "qcom,usb-hs-phy-msm8916",
 746                                                      "qcom,usb-hs-phy";
 747                                         #phy-cells = <0>;
 748                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 749                                         clock-names = "ref", "sleep";
 750                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 751                                         reset-names = "phy", "por";
 752                                         qcom,init-seq = /bits/ 8 <0x0 0x44
 753                                                 0x1 0x6b 0x2 0x24 0x3 0x13>;
 754                                 };
 755                         };
 756                 };
 757
 758                 intc: interrupt-controller@b000000 {
 759                         compatible = "qcom,msm-qgic2";
 760                         interrupt-controller;
 761                         #interrupt-cells = <3>;
 762                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 763                 };
 764
 765                 timer@b020000 {
 766                         #address-cells = <1>;
 767                         #size-cells = <1>;
 768                         ranges;
 769                         compatible = "arm,armv7-timer-mem";
 770                         reg = <0xb020000 0x1000>;
 771                         clock-frequency = <19200000>;
 772
 773                         frame@b021000 {
 774                                 frame-number = <0>;
 775                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 776                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 777                                 reg = <0xb021000 0x1000>,
 778                                       <0xb022000 0x1000>;
 779                         };
 780
 781                         frame@b023000 {
 782                                 frame-number = <1>;
 783                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 784                                 reg = <0xb023000 0x1000>;
 785                                 status = "disabled";
 786                         };
 787
 788                         frame@b024000 {
 789                                 frame-number = <2>;
 790                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 791                                 reg = <0xb024000 0x1000>;
 792                                 status = "disabled";
 793                         };
 794
 795                         frame@b025000 {
 796                                 frame-number = <3>;
 797                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 798                                 reg = <0xb025000 0x1000>;
 799                                 status = "disabled";
 800                         };
 801
 802                         frame@b026000 {
 803                                 frame-number = <4>;
 804                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 805                                 reg = <0xb026000 0x1000>;
 806                                 status = "disabled";
 807                         };
 808
 809                         frame@b027000 {
 810                                 frame-number = <5>;
 811                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 812                                 reg = <0xb027000 0x1000>;
 813                                 status = "disabled";
 814                         };
 815
 816                         frame@b028000 {
 817                                 frame-number = <6>;
 818                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 819                                 reg = <0xb028000 0x1000>;
 820                                 status = "disabled";
 821                         };
 822                 };
 823
 824                 spmi_bus: spmi@200f000 {
 825                         compatible = "qcom,spmi-pmic-arb";
 826                         reg = <0x200f000 0x001000>,
 827                               <0x2400000 0x400000>,
 828                               <0x2c00000 0x400000>,
 829                               <0x3800000 0x200000>,
 830                               <0x200a000 0x002100>;
 831                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 832                         interrupt-names = "periph_irq";
 833                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 834                         qcom,ee = <0>;
 835                         qcom,channel = <0>;
 836                         #address-cells = <2>;
 837                         #size-cells = <0>;
 838                         interrupt-controller;
 839                         #interrupt-cells = <4>;
 840                 };
 841
 842                 rng@22000 {
 843                         compatible = "qcom,prng";
 844                         reg = <0x00022000 0x200>;
 845                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 846                         clock-names = "core";
 847                 };
 848
 849                 qfprom: qfprom@5c000 {
 850                         compatible = "qcom,qfprom";
 851                         reg = <0x5c000 0x1000>;
 852                         #address-cells = <1>;
 853                         #size-cells = <1>;
 854                         tsens_caldata: caldata@d0 {
 855                                 reg = <0xd0 0x8>;
 856                         };
 857                         tsens_calsel: calsel@ec {
 858                                 reg = <0xec 0x4>;
 859                         };
 860                 };
 861
 862                 tsens: thermal-sensor@4a9000 {
 863                         compatible = "qcom,msm8916-tsens";
 864                         reg = <0x4a9000 0x1000>, /* TM */
 865                               <0x4a8000 0x1000>; /* SROT */
 866                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 867                         nvmem-cell-names = "calib", "calib_sel";
 868                         #qcom,sensors = <5>;
 869                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 870                         interrupt-names = "uplow";
 871                         #thermal-sensor-cells = <1>;
 872                 };
 873
 874                 apps_iommu: iommu@1ef0000 {
 875                         #address-cells = <1>;
 876                         #size-cells = <1>;
 877                         #iommu-cells = <1>;
 878                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 879                         ranges = <0 0x1e20000 0x40000>;
 880                         reg = <0x1ef0000 0x3000>;
 881                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 882                                  <&gcc GCC_APSS_TCU_CLK>;
 883                         clock-names = "iface", "bus";
 884                         qcom,iommu-secure-id = <17>;
 885
 886                         // vfe:
 887                         iommu-ctx@3000 {
 888                                 compatible = "qcom,msm-iommu-v1-sec";
 889                                 reg = <0x3000 0x1000>;
 890                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 891                         };
 892
 893                         // mdp_0:
 894                         iommu-ctx@4000 {
 895                                 compatible = "qcom,msm-iommu-v1-ns";
 896                                 reg = <0x4000 0x1000>;
 897                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 898                         };
 899
 900                         // venus_ns:
 901                         iommu-ctx@5000 {
 902                                 compatible = "qcom,msm-iommu-v1-sec";
 903                                 reg = <0x5000 0x1000>;
 904                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 905                         };
 906                 };
 907
 908                 gpu_iommu: iommu@1f08000 {
 909                         #address-cells = <1>;
 910                         #size-cells = <1>;
 911                         #iommu-cells = <1>;
 912                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 913                         ranges = <0 0x1f08000 0x10000>;
 914                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 915                                  <&gcc GCC_GFX_TCU_CLK>;
 916                         clock-names = "iface", "bus";
 917                         qcom,iommu-secure-id = <18>;
 918
 919                         // gfx3d_user:
 920                         iommu-ctx@1000 {
 921                                 compatible = "qcom,msm-iommu-v1-ns";
 922                                 reg = <0x1000 0x1000>;
 923                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 924                         };
 925
 926                         // gfx3d_priv:
 927                         iommu-ctx@2000 {
 928                                 compatible = "qcom,msm-iommu-v1-ns";
 929                                 reg = <0x2000 0x1000>;
 930                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 931                         };
 932                 };
 933
 934                 gpu@1c00000 {
 935                         compatible = "qcom,adreno-306.0", "qcom,adreno";
 936                         reg = <0x01c00000 0x20000>;
 937                         reg-names = "kgsl_3d0_reg_memory";
 938                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 939                         interrupt-names = "kgsl_3d0_irq";
 940                         clock-names =
 941                             "core",
 942                             "iface",
 943                             "mem",
 944                             "mem_iface",
 945                             "alt_mem_iface",
 946                             "gfx3d";
 947                         clocks =
 948                             <&gcc GCC_OXILI_GFX3D_CLK>,
 949                             <&gcc GCC_OXILI_AHB_CLK>,
 950                             <&gcc GCC_OXILI_GMEM_CLK>,
 951                             <&gcc GCC_BIMC_GFX_CLK>,
 952                             <&gcc GCC_BIMC_GPU_CLK>,
 953                             <&gcc GFX3D_CLK_SRC>;
 954                         power-domains = <&gcc OXILI_GDSC>;
 955                         operating-points-v2 = <&gpu_opp_table>;
 956                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
 957                 };
 958
 959                 mdss: mdss@1a00000 {
 960                         compatible = "qcom,mdss";
 961                         reg = <0x1a00000 0x1000>,
 962                               <0x1ac8000 0x3000>;
 963                         reg-names = "mdss_phys", "vbif_phys";
 964
 965                         power-domains = <&gcc MDSS_GDSC>;
 966
 967                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 968                                  <&gcc GCC_MDSS_AXI_CLK>,
 969                                  <&gcc GCC_MDSS_VSYNC_CLK>;
 970                         clock-names = "iface",
 971                                       "bus",
 972                                       "vsync";
 973
 974                         interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 975
 976                         interrupt-controller;
 977                         #interrupt-cells = <1>;
 978
 979                         #address-cells = <1>;
 980                         #size-cells = <1>;
 981                         ranges;
 982
 983                         mdp: mdp@1a01000 {
 984                                 compatible = "qcom,mdp5";
 985                                 reg = <0x1a01000 0x89000>;
 986                                 reg-names = "mdp_phys";
 987
 988                                 interrupt-parent = <&mdss>;
 989                                 interrupts = <0 0>;
 990
 991                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 992                                          <&gcc GCC_MDSS_AXI_CLK>,
 993                                          <&gcc GCC_MDSS_MDP_CLK>,
 994                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 995                                 clock-names = "iface",
 996                                               "bus",
 997                                               "core",
 998                                               "vsync";
 999
1000                                 iommus = <&apps_iommu 4>;
1001
1002                                 ports {
1003                                         #address-cells = <1>;
1004                                         #size-cells = <0>;
1005
1006                                         port@0 {
1007                                                 reg = <0>;
1008                                                 mdp5_intf1_out: endpoint {
1009                                                         remote-endpoint = <&dsi0_in>;
1010                                                 };
1011                                         };
1012                                 };
1013                         };
1014
1015                         dsi0: dsi@1a98000 {
1016                                 compatible = "qcom,mdss-dsi-ctrl";
1017                                 reg = <0x1a98000 0x25c>;
1018                                 reg-names = "dsi_ctrl";
1019
1020                                 interrupt-parent = <&mdss>;
1021                                 interrupts = <4 0>;
1022
1023                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1024                                                   <&gcc PCLK0_CLK_SRC>;
1025                                 assigned-clock-parents = <&dsi_phy0 0>,
1026                                                          <&dsi_phy0 1>;
1027
1028                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1029                                          <&gcc GCC_MDSS_AHB_CLK>,
1030                                          <&gcc GCC_MDSS_AXI_CLK>,
1031                                          <&gcc GCC_MDSS_BYTE0_CLK>,
1032                                          <&gcc GCC_MDSS_PCLK0_CLK>,
1033                                          <&gcc GCC_MDSS_ESC0_CLK>;
1034                                 clock-names = "mdp_core",
1035                                               "iface",
1036                                               "bus",
1037                                               "byte",
1038                                               "pixel",
1039                                               "core";
1040                                 phys = <&dsi_phy0>;
1041                                 phy-names = "dsi-phy";
1042
1043                                 ports {
1044                                         #address-cells = <1>;
1045                                         #size-cells = <0>;
1046
1047                                         port@0 {
1048                                                 reg = <0>;
1049                                                 dsi0_in: endpoint {
1050                                                         remote-endpoint = <&mdp5_intf1_out>;
1051                                                 };
1052                                         };
1053
1054                                         port@1 {
1055                                                 reg = <1>;
1056                                                 dsi0_out: endpoint {
1057                                                 };
1058                                         };
1059                                 };
1060                         };
1061
1062                         dsi_phy0: dsi-phy@1a98300 {
1063                                 compatible = "qcom,dsi-phy-28nm-lp";
1064                                 reg = <0x1a98300 0xd4>,
1065                                       <0x1a98500 0x280>,
1066                                       <0x1a98780 0x30>;
1067                                 reg-names = "dsi_pll",
1068                                             "dsi_phy",
1069                                             "dsi_phy_regulator";
1070
1071                                 #clock-cells = <1>;
1072                                 #phy-cells = <0>;
1073
1074                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1075                                          <&xo_board>;
1076                                 clock-names = "iface", "ref";
1077                         };
1078                 };
1079
1080
1081                 hexagon@4080000 {
1082                         compatible = "qcom,q6v5-pil";
1083                         reg = <0x04080000 0x100>,
1084                               <0x04020000 0x040>;
1085
1086                         reg-names = "qdsp6", "rmb";
1087
1088                         interrupts-extended = <&intc 0 24 1>,
1089                                               <&hexagon_smp2p_in 0 0>,
1090                                               <&hexagon_smp2p_in 1 0>,
1091                                               <&hexagon_smp2p_in 2 0>,
1092                                               <&hexagon_smp2p_in 3 0>;
1093                         interrupt-names = "wdog", "fatal", "ready",
1094                                           "handover", "stop-ack";
1095
1096                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1097                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1098                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1099                                  <&xo_board>;
1100                         clock-names = "iface", "bus", "mem", "xo";
1101
1102                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1103                         qcom,smem-state-names = "stop";
1104
1105                         resets = <&scm 0>;
1106                         reset-names = "mss_restart";
1107
1108                         cx-supply = <&pm8916_s1>;
1109                         mx-supply = <&pm8916_l3>;
1110                         pll-supply = <&pm8916_l7>;
1111
1112                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1113
1114                         status = "disabled";
1115
1116                         mba {
1117                                 memory-region = <&mba_mem>;
1118                         };
1119
1120                         mpss {
1121                                 memory-region = <&mpss_mem>;
1122                         };
1123
1124                         smd-edge {
1125                                 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1126
1127                                 qcom,smd-edge = <0>;
1128                                 qcom,ipc = <&apcs 8 12>;
1129                                 qcom,remote-pid = <1>;
1130
1131                                 label = "hexagon";
1132                         };
1133                 };
1134
1135                 pronto: wcnss@a21b000 {
1136                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1137                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1138                         reg-names = "ccu", "dxe", "pmu";
1139
1140                         memory-region = <&wcnss_mem>;
1141
1142                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1143                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1144                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1145                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1146                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1147                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1148
1149                         vddmx-supply = <&pm8916_l3>;
1150                         vddpx-supply = <&pm8916_l7>;
1151
1152                         qcom,state = <&wcnss_smp2p_out 0>;
1153                         qcom,state-names = "stop";
1154
1155                         pinctrl-names = "default";
1156                         pinctrl-0 = <&wcnss_pin_a>;
1157
1158                         status = "disabled";
1159
1160                         iris {
1161                                 compatible = "qcom,wcn3620";
1162
1163                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1164                                 clock-names = "xo";
1165
1166                                 vddxo-supply = <&pm8916_l7>;
1167                                 vddrfa-supply = <&pm8916_s3>;
1168                                 vddpa-supply = <&pm8916_l9>;
1169                                 vdddig-supply = <&pm8916_l5>;
1170                         };
1171
1172                         smd-edge {
1173                                 interrupts = <0 142 1>;
1174
1175                                 qcom,ipc = <&apcs 8 17>;
1176                                 qcom,smd-edge = <6>;
1177                                 qcom,remote-pid = <4>;
1178
1179                                 label = "pronto";
1180
1181                                 wcnss {
1182                                         compatible = "qcom,wcnss";
1183                                         qcom,smd-channels = "WCNSS_CTRL";
1184
1185                                         qcom,mmio = <&pronto>;
1186
1187                                         bt {
1188                                                 compatible = "qcom,wcnss-bt";
1189                                         };
1190
1191                                         wifi {
1192                                                 compatible = "qcom,wcnss-wlan";
1193
1194                                                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1195                                                              <0 146 IRQ_TYPE_LEVEL_HIGH>;
1196                                                 interrupt-names = "tx", "rx";
1197
1198                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1199                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1200                                         };
1201                                 };
1202                         };
1203                 };
1204
1205                 tpiu@820000 {
1206                         compatible = "arm,coresight-tpiu", "arm,primecell";
1207                         reg = <0x820000 0x1000>;
1208
1209                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1210                         clock-names = "apb_pclk", "atclk";
1211
1212                         in-ports {
1213                                 port {
1214                                         tpiu_in: endpoint {
1215                                                 remote-endpoint = <&replicator_out1>;
1216                                         };
1217                                 };
1218                         };
1219                 };
1220
1221                 funnel@821000 {
1222                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1223                         reg = <0x821000 0x1000>;
1224
1225                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1226                         clock-names = "apb_pclk", "atclk";
1227
1228                         in-ports {
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231
1232                                 /*
1233                                  * Not described input ports:
1234                                  * 0 - connected to Resource and Power Manger CPU ETM
1235                                  * 1 - not-connected
1236                                  * 2 - connected to Modem CPU ETM
1237                                  * 3 - not-connected
1238                                  * 5 - not-connected
1239                                  * 6 - connected trought funnel to Wireless CPU ETM
1240                                  * 7 - connected to STM component
1241                                  */
1242
1243                                 port@4 {
1244                                         reg = <4>;
1245                                         funnel0_in4: endpoint {
1246                                                 remote-endpoint = <&funnel1_out>;
1247                                         };
1248                                 };
1249                         };
1250
1251                         out-ports {
1252                                 port {
1253                                         funnel0_out: endpoint {
1254                                                 remote-endpoint = <&etf_in>;
1255                                         };
1256                                 };
1257                         };
1258                 };
1259
1260                 replicator@824000 {
1261                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1262                         reg = <0x824000 0x1000>;
1263
1264                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1265                         clock-names = "apb_pclk", "atclk";
1266
1267                         out-ports {
1268                                 #address-cells = <1>;
1269                                 #size-cells = <0>;
1270
1271                                 port@0 {
1272                                         reg = <0>;
1273                                         replicator_out0: endpoint {
1274                                                 remote-endpoint = <&etr_in>;
1275                                         };
1276                                 };
1277                                 port@1 {
1278                                         reg = <1>;
1279                                         replicator_out1: endpoint {
1280                                                 remote-endpoint = <&tpiu_in>;
1281                                         };
1282                                 };
1283                         };
1284
1285                         in-ports {
1286                                 port {
1287                                         replicator_in: endpoint {
1288                                                 remote-endpoint = <&etf_out>;
1289                                         };
1290                                 };
1291                         };
1292                 };
1293
1294                 etf@825000 {
1295                         compatible = "arm,coresight-tmc", "arm,primecell";
1296                         reg = <0x825000 0x1000>;
1297
1298                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1299                         clock-names = "apb_pclk", "atclk";
1300
1301                         in-ports {
1302                                 port {
1303                                         etf_in: endpoint {
1304                                                 remote-endpoint = <&funnel0_out>;
1305                                         };
1306                                 };
1307                         };
1308
1309                         out-ports {
1310                                 port {
1311                                         etf_out: endpoint {
1312                                                 remote-endpoint = <&replicator_in>;
1313                                         };
1314                                 };
1315                         };
1316                 };
1317
1318                 etr@826000 {
1319                         compatible = "arm,coresight-tmc", "arm,primecell";
1320                         reg = <0x826000 0x1000>;
1321
1322                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1323                         clock-names = "apb_pclk", "atclk";
1324
1325                         in-ports {
1326                                 port {
1327                                         etr_in: endpoint {
1328                                                 remote-endpoint = <&replicator_out0>;
1329                                         };
1330                                 };
1331                         };
1332                 };
1333
1334                 funnel@841000 { /* APSS funnel only 4 inputs are used */
1335                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1336                         reg = <0x841000 0x1000>;
1337
1338                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1339                         clock-names = "apb_pclk", "atclk";
1340
1341                         in-ports {
1342                                 #address-cells = <1>;
1343                                 #size-cells = <0>;
1344
1345                                 port@0 {
1346                                         reg = <0>;
1347                                         funnel1_in0: endpoint {
1348                                                 remote-endpoint = <&etm0_out>;
1349                                         };
1350                                 };
1351                                 port@1 {
1352                                         reg = <1>;
1353                                         funnel1_in1: endpoint {
1354                                                 remote-endpoint = <&etm1_out>;
1355                                         };
1356                                 };
1357                                 port@2 {
1358                                         reg = <2>;
1359                                         funnel1_in2: endpoint {
1360                                                 remote-endpoint = <&etm2_out>;
1361                                         };
1362                                 };
1363                                 port@3 {
1364                                         reg = <3>;
1365                                         funnel1_in3: endpoint {
1366                                                 remote-endpoint = <&etm3_out>;
1367                                         };
1368                                 };
1369                         };
1370
1371                         out-ports {
1372                                 port {
1373                                         funnel1_out: endpoint {
1374                                                 remote-endpoint = <&funnel0_in4>;
1375                                         };
1376                                 };
1377                         };
1378                 };
1379
1380                 debug@850000 {
1381                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1382                         reg = <0x850000 0x1000>;
1383                         clocks = <&rpmcc RPM_QDSS_CLK>;
1384                         clock-names = "apb_pclk";
1385                         cpu = <&CPU0>;
1386                 };
1387
1388                 debug@852000 {
1389                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1390                         reg = <0x852000 0x1000>;
1391                         clocks = <&rpmcc RPM_QDSS_CLK>;
1392                         clock-names = "apb_pclk";
1393                         cpu = <&CPU1>;
1394                 };
1395
1396                 debug@854000 {
1397                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1398                         reg = <0x854000 0x1000>;
1399                         clocks = <&rpmcc RPM_QDSS_CLK>;
1400                         clock-names = "apb_pclk";
1401                         cpu = <&CPU2>;
1402                 };
1403
1404                 debug@856000 {
1405                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1406                         reg = <0x856000 0x1000>;
1407                         clocks = <&rpmcc RPM_QDSS_CLK>;
1408                         clock-names = "apb_pclk";
1409                         cpu = <&CPU3>;
1410                 };
1411
1412                 etm@85c000 {
1413                         compatible = "arm,coresight-etm4x", "arm,primecell";
1414                         reg = <0x85c000 0x1000>;
1415
1416                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1417                         clock-names = "apb_pclk", "atclk";
1418
1419                         cpu = <&CPU0>;
1420
1421                         out-ports {
1422                                 port {
1423                                         etm0_out: endpoint {
1424                                                 remote-endpoint = <&funnel1_in0>;
1425                                         };
1426                                 };
1427                         };
1428                 };
1429
1430                 etm@85d000 {
1431                         compatible = "arm,coresight-etm4x", "arm,primecell";
1432                         reg = <0x85d000 0x1000>;
1433
1434                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1435                         clock-names = "apb_pclk", "atclk";
1436
1437                         cpu = <&CPU1>;
1438
1439                         out-ports {
1440                                 port {
1441                                         etm1_out: endpoint {
1442                                                 remote-endpoint = <&funnel1_in1>;
1443                                         };
1444                                 };
1445                         };
1446                 };
1447
1448                 etm@85e000 {
1449                         compatible = "arm,coresight-etm4x", "arm,primecell";
1450                         reg = <0x85e000 0x1000>;
1451
1452                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1453                         clock-names = "apb_pclk", "atclk";
1454
1455                         cpu = <&CPU2>;
1456
1457                         out-ports {
1458                                 port {
1459                                         etm2_out: endpoint {
1460                                                 remote-endpoint = <&funnel1_in2>;
1461                                         };
1462                                 };
1463                         };
1464                 };
1465
1466                 etm@85f000 {
1467                         compatible = "arm,coresight-etm4x", "arm,primecell";
1468                         reg = <0x85f000 0x1000>;
1469
1470                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1471                         clock-names = "apb_pclk", "atclk";
1472
1473                         cpu = <&CPU3>;
1474
1475                         out-ports {
1476                                 port {
1477                                         etm3_out: endpoint {
1478                                                 remote-endpoint = <&funnel1_in3>;
1479                                         };
1480                                 };
1481                         };
1482                 };
1483
1484                 venus: video-codec@1d00000 {
1485                         compatible = "qcom,msm8916-venus";
1486                         reg = <0x01d00000 0xff000>;
1487                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1488                         power-domains = <&gcc VENUS_GDSC>;
1489                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1490                                  <&gcc GCC_VENUS0_AHB_CLK>,
1491                                  <&gcc GCC_VENUS0_AXI_CLK>;
1492                         clock-names = "core", "iface", "bus";
1493                         iommus = <&apps_iommu 5>;
1494                         memory-region = <&venus_mem>;
1495                         status = "okay";
1496
1497                         video-decoder {
1498                                 compatible = "venus-decoder";
1499                         };
1500
1501                         video-encoder {
1502                                 compatible = "venus-encoder";
1503                         };
1504                 };
1505
1506                 camss: camss@1b00000 {
1507                         compatible = "qcom,msm8916-camss";
1508                         reg = <0x1b0ac00 0x200>,
1509                                 <0x1b00030 0x4>,
1510                                 <0x1b0b000 0x200>,
1511                                 <0x1b00038 0x4>,
1512                                 <0x1b08000 0x100>,
1513                                 <0x1b08400 0x100>,
1514                                 <0x1b0a000 0x500>,
1515                                 <0x1b00020 0x10>,
1516                                 <0x1b10000 0x1000>;
1517                         reg-names = "csiphy0",
1518                                 "csiphy0_clk_mux",
1519                                 "csiphy1",
1520                                 "csiphy1_clk_mux",
1521                                 "csid0",
1522                                 "csid1",
1523                                 "ispif",
1524                                 "csi_clk_mux",
1525                                 "vfe0";
1526                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1527                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1528                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1529                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1530                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1531                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1532                         interrupt-names = "csiphy0",
1533                                 "csiphy1",
1534                                 "csid0",
1535                                 "csid1",
1536                                 "ispif",
1537                                 "vfe0";
1538                         power-domains = <&gcc VFE_GDSC>;
1539                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1540                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1541                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1542                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1543                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1544                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1545                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1546                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1547                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1548                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1549                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1550                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1551                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1552                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1553                                 <&gcc GCC_CAMSS_AHB_CLK>,
1554                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1555                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1556                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1557                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1558                         clock-names = "top_ahb",
1559                                 "ispif_ahb",
1560                                 "csiphy0_timer",
1561                                 "csiphy1_timer",
1562                                 "csi0_ahb",
1563                                 "csi0",
1564                                 "csi0_phy",
1565                                 "csi0_pix",
1566                                 "csi0_rdi",
1567                                 "csi1_ahb",
1568                                 "csi1",
1569                                 "csi1_phy",
1570                                 "csi1_pix",
1571                                 "csi1_rdi",
1572                                 "ahb",
1573                                 "vfe0",
1574                                 "csi_vfe0",
1575                                 "vfe_ahb",
1576                                 "vfe_axi";
1577                         vdda-supply = <&pm8916_l2>;
1578                         iommus = <&apps_iommu 3>;
1579                         status = "disabled";
1580                         ports {
1581                                 #address-cells = <1>;
1582                                 #size-cells = <0>;
1583                         };
1584                 };
1585         };
1586
1587         smd {
1588                 compatible = "qcom,smd";
1589
1590                 rpm {
1591                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1592                         qcom,ipc = <&apcs 8 0>;
1593                         qcom,smd-edge = <15>;
1594
1595                         rpm_requests {
1596                                 compatible = "qcom,rpm-msm8916";
1597                                 qcom,smd-channels = "rpm_requests";
1598
1599                                 rpmcc: qcom,rpmcc {
1600                                         compatible = "qcom,rpmcc-msm8916";
1601                                         #clock-cells = <1>;
1602                                 };
1603
1604                                 smd_rpm_regulators: pm8916-regulators {
1605                                         compatible = "qcom,rpm-pm8916-regulators";
1606
1607                                         pm8916_s1: s1 {};
1608                                         pm8916_s3: s3 {};
1609                                         pm8916_s4: s4 {};
1610
1611                                         pm8916_l1: l1 {};
1612                                         pm8916_l2: l2 {};
1613                                         pm8916_l3: l3 {};
1614                                         pm8916_l4: l4 {};
1615                                         pm8916_l5: l5 {};
1616                                         pm8916_l6: l6 {};
1617                                         pm8916_l7: l7 {};
1618                                         pm8916_l8: l8 {};
1619                                         pm8916_l9: l9 {};
1620                                         pm8916_l10: l10 {};
1621                                         pm8916_l11: l11 {};
1622                                         pm8916_l12: l12 {};
1623                                         pm8916_l13: l13 {};
1624                                         pm8916_l14: l14 {};
1625                                         pm8916_l15: l15 {};
1626                                         pm8916_l16: l16 {};
1627                                         pm8916_l17: l17 {};
1628                                         pm8916_l18: l18 {};
1629                                 };
1630                         };
1631                 };
1632         };
1633
1634         hexagon-smp2p {
1635                 compatible = "qcom,smp2p";
1636                 qcom,smem = <435>, <428>;
1637
1638                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1639
1640                 qcom,ipc = <&apcs 8 14>;
1641
1642                 qcom,local-pid = <0>;
1643                 qcom,remote-pid = <1>;
1644
1645                 hexagon_smp2p_out: master-kernel {
1646                         qcom,entry-name = "master-kernel";
1647
1648                         #qcom,smem-state-cells = <1>;
1649                 };
1650
1651                 hexagon_smp2p_in: slave-kernel {
1652                         qcom,entry-name = "slave-kernel";
1653
1654                         interrupt-controller;
1655                         #interrupt-cells = <2>;
1656                 };
1657         };
1658
1659         wcnss-smp2p {
1660                 compatible = "qcom,smp2p";
1661                 qcom,smem = <451>, <431>;
1662
1663                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1664
1665                 qcom,ipc = <&apcs 8 18>;
1666
1667                 qcom,local-pid = <0>;
1668                 qcom,remote-pid = <4>;
1669
1670                 wcnss_smp2p_out: master-kernel {
1671                         qcom,entry-name = "master-kernel";
1672
1673                         #qcom,smem-state-cells = <1>;
1674                 };
1675
1676                 wcnss_smp2p_in: slave-kernel {
1677                         qcom,entry-name = "slave-kernel";
1678
1679                         interrupt-controller;
1680                         #interrupt-cells = <2>;
1681                 };
1682         };
1683
1684         smsm {
1685                 compatible = "qcom,smsm";
1686
1687                 #address-cells = <1>;
1688                 #size-cells = <0>;
1689
1690                 qcom,ipc-1 = <&apcs 8 13>;
1691                 qcom,ipc-3 = <&apcs 8 19>;
1692
1693                 apps_smsm: apps@0 {
1694                         reg = <0>;
1695
1696                         #qcom,smem-state-cells = <1>;
1697                 };
1698
1699                 hexagon_smsm: hexagon@1 {
1700                         reg = <1>;
1701                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1702
1703                         interrupt-controller;
1704                         #interrupt-cells = <2>;
1705                 };
1706
1707                 wcnss_smsm: wcnss@6 {
1708                         reg = <6>;
1709                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1710
1711                         interrupt-controller;
1712                         #interrupt-cells = <2>;
1713                 };
1714         };
1715 };
1716
1717 #include "msm8916-pins.dtsi"