arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
   4  *
   5  * Copyright (C) 2019 Renesas Electronics Corp.
   6  */
   7
   8 / {
   9         aliases {
  10                 ethernet0 = &avb;
  11         };
  12
  13         chosen {
  14                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  15         };
  16
  17         backlight {
  18                 compatible = "pwm-backlight";
  19                 pwms = <&pwm0 0 50000>;
  20
  21                 brightness-levels = <0 2 8 16 32 64 128 255>;
  22                 default-brightness-level = <6>;
  23         };
  24 };
  25
  26 &avb {
  27         pinctrl-0 = <&avb_pins>;
  28         pinctrl-names = "default";
  29         phy-handle = <&phy0>;
  30         phy-mode = "rgmii-txid";
  31         status = "okay";
  32
  33         phy0: ethernet-phy@0 {
  34                 rxc-skew-ps = <1500>;
  35                 reg = <0>;
  36                 interrupt-parent = <&gpio2>;
  37                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  38                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  39         };
  40 };
  41
  42 &can0 {
  43         pinctrl-0 = <&can0_pins>;
  44         pinctrl-names = "default";
  45         status = "okay";
  46 };
  47
  48 &can1 {
  49         pinctrl-0 = <&can1_pins>;
  50         pinctrl-names = "default";
  51         status = "okay";
  52 };
  53
  54 &gpio1 {
  55         /*
  56          * When GP1_20 is LOW LVDS0 is connected to the LVDS connector
  57          * When GP1_20 is HIGH LVDS0 is connected to the LT8918L
  58          */
  59         lvds-connector-en-gpio {
  60                 gpio-hog;
  61                 gpios = <20 GPIO_ACTIVE_HIGH>;
  62                 output-low;
  63                 line-name = "lvds-connector-en-gpio";
  64         };
  65 };
  66
  67 &lvds0 {
  68         /*
  69          * Please include the LVDS panel .dtsi file and uncomment the below line
  70          * to enable LVDS panel connected to RZ/G2[MN] boards.
  71          */
  72
  73         /* status = "okay"; */
  74
  75         ports {
  76                 port@1 {
  77                         lvds_connector: endpoint {
  78                         };
  79                 };
  80         };
  81 };
  82
  83 &pciec0 {
  84         status = "okay";
  85 };
  86
  87 &pfc {
  88         pinctrl-0 = <&scif_clk_pins>;
  89         pinctrl-names = "default";
  90
  91         avb_pins: avb {
  92                 mux {
  93                         groups = "avb_link", "avb_mdio", "avb_mii";
  94                         function = "avb";
  95                 };
  96
  97                 pins_mdio {
  98                         groups = "avb_mdio";
  99                         drive-strength = <24>;
 100                 };
 101
 102                 pins_mii_tx {
 103                         pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 104                                "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 105                         drive-strength = <12>;
 106                 };
 107         };
 108
 109         can0_pins: can0 {
 110                 groups = "can0_data_a";
 111                 function = "can0";
 112         };
 113
 114         can1_pins: can1 {
 115                 groups = "can1_data";
 116                 function = "can1";
 117         };
 118
 119         pwm0_pins: pwm0 {
 120                 groups = "pwm0";
 121                 function = "pwm0";
 122         };
 123 };
 124
 125 &pwm0 {
 126         pinctrl-0 = <&pwm0_pins>;
 127         pinctrl-names = "default";
 128
 129         status = "okay";
 130 };