| blob | 0d96f2d3492b6972e85ab92237724d2e9b6494f0 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
12 #define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4
14 / {
15 compatible = "renesas,r8a77961";
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /*
20 * The external audio clocks are configured as 0 Hz fixed frequency
21 * clocks by default.
22 * Boards that provide audio clocks should override them.
23 */
24 audio_clk_a: audio_clk_a {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <0>;
28 };
30 audio_clk_b: audio_clk_b {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <0>;
34 };
36 audio_clk_c: audio_clk_c {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
40 };
42 /* External CAN clock - to be overridden by boards that provide it */
43 can_clk: can {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <0>;
47 };
49 cluster0_opp: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-500000000 {
54 opp-hz = /bits/ 64 <500000000>;
55 opp-microvolt = <820000>;
56 clock-latency-ns = <300000>;
57 };
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <820000>;
61 clock-latency-ns = <300000>;
62 };
63 opp-1500000000 {
64 opp-hz = /bits/ 64 <1500000000>;
65 opp-microvolt = <820000>;
66 clock-latency-ns = <300000>;
67 };
68 opp-1600000000 {
69 opp-hz = /bits/ 64 <1600000000>;
70 opp-microvolt = <900000>;
71 clock-latency-ns = <300000>;
72 turbo-mode;
73 };
74 opp-1700000000 {
75 opp-hz = /bits/ 64 <1700000000>;
76 opp-microvolt = <900000>;
77 clock-latency-ns = <300000>;
78 turbo-mode;
79 };
80 opp-1800000000 {
81 opp-hz = /bits/ 64 <1800000000>;
82 opp-microvolt = <960000>;
83 clock-latency-ns = <300000>;
84 turbo-mode;
85 };
86 };
88 cluster1_opp: opp_table1 {
89 compatible = "operating-points-v2";
90 opp-shared;
92 opp-800000000 {
93 opp-hz = /bits/ 64 <800000000>;
94 opp-microvolt = <820000>;
95 clock-latency-ns = <300000>;
96 };
97 opp-1000000000 {
98 opp-hz = /bits/ 64 <1000000000>;
99 opp-microvolt = <820000>;
100 clock-latency-ns = <300000>;
101 };
102 opp-1200000000 {
103 opp-hz = /bits/ 64 <1200000000>;
104 opp-microvolt = <820000>;
105 clock-latency-ns = <300000>;
106 };
107 opp-1300000000 {
108 opp-hz = /bits/ 64 <1300000000>;
109 opp-microvolt = <820000>;
110 clock-latency-ns = <300000>;
111 turbo-mode;
112 };
113 };
115 cpus {
116 #address-cells = <1>;
117 #size-cells = <0>;
119 cpu-map {
120 cluster0 {
121 core0 {
122 cpu = <&a57_0>;
123 };
124 core1 {
125 cpu = <&a57_1>;
126 };
127 };
129 cluster1 {
130 core0 {
131 cpu = <&a53_0>;
132 };
133 core1 {
134 cpu = <&a53_1>;
135 };
136 core2 {
137 cpu = <&a53_2>;
138 };
139 core3 {
140 cpu = <&a53_3>;
141 };
142 };
143 };
145 a57_0: cpu@0 {
146 compatible = "arm,cortex-a57";
147 reg = <0x0>;
148 device_type = "cpu";
149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>;
150 next-level-cache = <&L2_CA57>;
151 enable-method = "psci";
152 cpu-idle-states = <&CPU_SLEEP_0>;
153 dynamic-power-coefficient = <854>;
154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
155 operating-points-v2 = <&cluster0_opp>;
156 capacity-dmips-mhz = <1024>;
157 #cooling-cells = <2>;
158 };
160 a57_1: cpu@1 {
161 compatible = "arm,cortex-a57";
162 reg = <0x1>;
163 device_type = "cpu";
164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>;
165 next-level-cache = <&L2_CA57>;
166 enable-method = "psci";
167 cpu-idle-states = <&CPU_SLEEP_0>;
168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
169 operating-points-v2 = <&cluster0_opp>;
170 capacity-dmips-mhz = <1024>;
171 #cooling-cells = <2>;
172 };
174 a53_0: cpu@100 {
175 compatible = "arm,cortex-a53";
176 reg = <0x100>;
177 device_type = "cpu";
178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>;
179 next-level-cache = <&L2_CA53>;
180 enable-method = "psci";
181 cpu-idle-states = <&CPU_SLEEP_1>;
182 #cooling-cells = <2>;
183 dynamic-power-coefficient = <277>;
184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
185 operating-points-v2 = <&cluster1_opp>;
186 capacity-dmips-mhz = <535>;
187 };
189 a53_1: cpu@101 {
190 compatible = "arm,cortex-a53";
191 reg = <0x101>;
192 device_type = "cpu";
193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>;
194 next-level-cache = <&L2_CA53>;
195 enable-method = "psci";
196 cpu-idle-states = <&CPU_SLEEP_1>;
197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
198 operating-points-v2 = <&cluster1_opp>;
199 capacity-dmips-mhz = <535>;
200 };
202 a53_2: cpu@102 {
203 compatible = "arm,cortex-a53";
204 reg = <0x102>;
205 device_type = "cpu";
206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>;
207 next-level-cache = <&L2_CA53>;
208 enable-method = "psci";
209 cpu-idle-states = <&CPU_SLEEP_1>;
210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
211 operating-points-v2 = <&cluster1_opp>;
212 capacity-dmips-mhz = <535>;
213 };
215 a53_3: cpu@103 {
216 compatible = "arm,cortex-a53";
217 reg = <0x103>;
218 device_type = "cpu";
219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>;
220 next-level-cache = <&L2_CA53>;
221 enable-method = "psci";
222 cpu-idle-states = <&CPU_SLEEP_1>;
223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
224 operating-points-v2 = <&cluster1_opp>;
225 capacity-dmips-mhz = <535>;
226 };
228 L2_CA57: cache-controller-0 {
229 compatible = "cache";
230 power-domains = <&sysc R8A77961_PD_CA57_SCU>;
231 cache-unified;
232 cache-level = <2>;
233 };
235 L2_CA53: cache-controller-1 {
236 compatible = "cache";
237 power-domains = <&sysc R8A77961_PD_CA53_SCU>;
238 cache-unified;
239 cache-level = <2>;
240 };
242 idle-states {
243 entry-method = "psci";
245 CPU_SLEEP_0: cpu-sleep-0 {
246 compatible = "arm,idle-state";
247 arm,psci-suspend-param = <0x0010000>;
248 local-timer-stop;
249 entry-latency-us = <400>;
250 exit-latency-us = <500>;
251 min-residency-us = <4000>;
252 };
254 CPU_SLEEP_1: cpu-sleep-1 {
255 compatible = "arm,idle-state";
256 arm,psci-suspend-param = <0x0010000>;
257 local-timer-stop;
258 entry-latency-us = <700>;
259 exit-latency-us = <700>;
260 min-residency-us = <5000>;
261 };
262 };
263 };
265 extal_clk: extal {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
268 /* This value must be overridden by the board */
269 clock-frequency = <0>;
270 };
272 extalr_clk: extalr {
273 compatible = "fixed-clock";
274 #clock-cells = <0>;
275 /* This value must be overridden by the board */
276 clock-frequency = <0>;
277 };
279 /* External PCIe clock - can be overridden by the board */
280 pcie_bus_clk: pcie_bus {
281 compatible = "fixed-clock";
282 #clock-cells = <0>;
283 clock-frequency = <0>;
284 };
286 pmu_a53 {
287 compatible = "arm,cortex-a53-pmu";
288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
293 };
295 pmu_a57 {
296 compatible = "arm,cortex-a57-pmu";
297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-affinity = <&a57_0>, <&a57_1>;
300 };
302 psci {
303 compatible = "arm,psci-1.0", "arm,psci-0.2";
304 method = "smc";
305 };
307 /* External SCIF clock - to be overridden by boards that provide it */
308 scif_clk: scif {
309 compatible = "fixed-clock";
310 #clock-cells = <0>;
311 clock-frequency = <0>;
312 };
314 soc {
315 compatible = "simple-bus";
316 interrupt-parent = <&gic>;
317 #address-cells = <2>;
318 #size-cells = <2>;
319 ranges;
321 rwdt: watchdog@e6020000 {
322 compatible = "renesas,r8a77961-wdt",
323 "renesas,rcar-gen3-wdt";
324 reg = <0 0xe6020000 0 0x0c>;
325 clocks = <&cpg CPG_MOD 402>;
326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
327 resets = <&cpg 402>;
328 status = "disabled";
329 };
331 gpio0: gpio@e6050000 {
332 compatible = "renesas,gpio-r8a77961",
333 "renesas,rcar-gen3-gpio";
334 reg = <0 0xe6050000 0 0x50>;
335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
336 #gpio-cells = <2>;
337 gpio-controller;
338 gpio-ranges = <&pfc 0 0 16>;
339 #interrupt-cells = <2>;
340 interrupt-controller;
341 clocks = <&cpg CPG_MOD 912>;
342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
343 resets = <&cpg 912>;
344 };
346 gpio1: gpio@e6051000 {
347 compatible = "renesas,gpio-r8a77961",
348 "renesas,rcar-gen3-gpio";
349 reg = <0 0xe6051000 0 0x50>;
350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
351 #gpio-cells = <2>;
352 gpio-controller;
353 gpio-ranges = <&pfc 0 32 29>;
354 #interrupt-cells = <2>;
355 interrupt-controller;
356 clocks = <&cpg CPG_MOD 911>;
357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
358 resets = <&cpg 911>;
359 };
361 gpio2: gpio@e6052000 {
362 compatible = "renesas,gpio-r8a77961",
363 "renesas,rcar-gen3-gpio";
364 reg = <0 0xe6052000 0 0x50>;
365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
366 #gpio-cells = <2>;
367 gpio-controller;
368 gpio-ranges = <&pfc 0 64 15>;
369 #interrupt-cells = <2>;
370 interrupt-controller;
371 clocks = <&cpg CPG_MOD 910>;
372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
373 resets = <&cpg 910>;
374 };
376 gpio3: gpio@e6053000 {
377 compatible = "renesas,gpio-r8a77961",
378 "renesas,rcar-gen3-gpio";
379 reg = <0 0xe6053000 0 0x50>;
380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
381 #gpio-cells = <2>;
382 gpio-controller;
383 gpio-ranges = <&pfc 0 96 16>;
384 #interrupt-cells = <2>;
385 interrupt-controller;
386 clocks = <&cpg CPG_MOD 909>;
387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
388 resets = <&cpg 909>;
389 };
391 gpio4: gpio@e6054000 {
392 compatible = "renesas,gpio-r8a77961",
393 "renesas,rcar-gen3-gpio";
394 reg = <0 0xe6054000 0 0x50>;
395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
396 #gpio-cells = <2>;
397 gpio-controller;
398 gpio-ranges = <&pfc 0 128 18>;
399 #interrupt-cells = <2>;
400 interrupt-controller;
401 clocks = <&cpg CPG_MOD 908>;
402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
403 resets = <&cpg 908>;
404 };
406 gpio5: gpio@e6055000 {
407 compatible = "renesas,gpio-r8a77961",
408 "renesas,rcar-gen3-gpio";
409 reg = <0 0xe6055000 0 0x50>;
410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
411 #gpio-cells = <2>;
412 gpio-controller;
413 gpio-ranges = <&pfc 0 160 26>;
414 #interrupt-cells = <2>;
415 interrupt-controller;
416 clocks = <&cpg CPG_MOD 907>;
417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
418 resets = <&cpg 907>;
419 };
421 gpio6: gpio@e6055400 {
422 compatible = "renesas,gpio-r8a77961",
423 "renesas,rcar-gen3-gpio";
424 reg = <0 0xe6055400 0 0x50>;
425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
426 #gpio-cells = <2>;
427 gpio-controller;
428 gpio-ranges = <&pfc 0 192 32>;
429 #interrupt-cells = <2>;
430 interrupt-controller;
431 clocks = <&cpg CPG_MOD 906>;
432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
433 resets = <&cpg 906>;
434 };
436 gpio7: gpio@e6055800 {
437 compatible = "renesas,gpio-r8a77961",
438 "renesas,rcar-gen3-gpio";
439 reg = <0 0xe6055800 0 0x50>;
440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
441 #gpio-cells = <2>;
442 gpio-controller;
443 gpio-ranges = <&pfc 0 224 4>;
444 #interrupt-cells = <2>;
445 interrupt-controller;
446 clocks = <&cpg CPG_MOD 905>;
447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
448 resets = <&cpg 905>;
449 };
451 pfc: pin-controller@e6060000 {
452 compatible = "renesas,pfc-r8a77961";
453 reg = <0 0xe6060000 0 0x50c>;
454 };
456 cpg: clock-controller@e6150000 {
457 compatible = "renesas,r8a77961-cpg-mssr";
458 reg = <0 0xe6150000 0 0x1000>;
459 clocks = <&extal_clk>, <&extalr_clk>;
460 clock-names = "extal", "extalr";
461 #clock-cells = <2>;
462 #power-domain-cells = <0>;
463 #reset-cells = <1>;
464 };
466 rst: reset-controller@e6160000 {
467 compatible = "renesas,r8a77961-rst";
468 reg = <0 0xe6160000 0 0x0200>;
469 };
471 sysc: system-controller@e6180000 {
472 compatible = "renesas,r8a77961-sysc";
473 reg = <0 0xe6180000 0 0x0400>;
474 #power-domain-cells = <1>;
475 };
477 tsc: thermal@e6198000 {
478 compatible = "renesas,r8a77961-thermal";
479 reg = <0 0xe6198000 0 0x100>,
480 <0 0xe61a0000 0 0x100>,
481 <0 0xe61a8000 0 0x100>;
482 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cpg CPG_MOD 522>;
486 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
487 resets = <&cpg 522>;
488 #thermal-sensor-cells = <1>;
489 };
491 intc_ex: interrupt-controller@e61c0000 {
492 #interrupt-cells = <2>;
493 interrupt-controller;
494 reg = <0 0xe61c0000 0 0x200>;
495 /* placeholder */
496 };
498 i2c0: i2c@e6500000 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 compatible = "renesas,i2c-r8a77961",
502 "renesas,rcar-gen3-i2c";
503 reg = <0 0xe6500000 0 0x40>;
504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&cpg CPG_MOD 931>;
506 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
507 resets = <&cpg 931>;
508 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
509 <&dmac2 0x91>, <&dmac2 0x90>;
510 dma-names = "tx", "rx", "tx", "rx";
511 i2c-scl-internal-delay-ns = <110>;
512 status = "disabled";
513 };
515 i2c1: i2c@e6508000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,i2c-r8a77961",
519 "renesas,rcar-gen3-i2c";
520 reg = <0 0xe6508000 0 0x40>;
521 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cpg CPG_MOD 930>;
523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
524 resets = <&cpg 930>;
525 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
526 <&dmac2 0x93>, <&dmac2 0x92>;
527 dma-names = "tx", "rx", "tx", "rx";
528 i2c-scl-internal-delay-ns = <6>;
529 status = "disabled";
530 };
532 i2c2: i2c@e6510000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,i2c-r8a77961",
536 "renesas,rcar-gen3-i2c";
537 reg = <0 0xe6510000 0 0x40>;
538 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&cpg CPG_MOD 929>;
540 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
541 resets = <&cpg 929>;
542 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
543 <&dmac2 0x95>, <&dmac2 0x94>;
544 dma-names = "tx", "rx", "tx", "rx";
545 i2c-scl-internal-delay-ns = <6>;
546 status = "disabled";
547 };
549 i2c3: i2c@e66d0000 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "renesas,i2c-r8a77961",
553 "renesas,rcar-gen3-i2c";
554 reg = <0 0xe66d0000 0 0x40>;
555 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&cpg CPG_MOD 928>;
557 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
558 resets = <&cpg 928>;
559 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
560 dma-names = "tx", "rx";
561 i2c-scl-internal-delay-ns = <110>;
562 status = "disabled";
563 };
565 i2c4: i2c@e66d8000 {
566 #address-cells = <1>;
567 #size-cells = <0>;
568 compatible = "renesas,i2c-r8a77961",
569 "renesas,rcar-gen3-i2c";
570 reg = <0 0xe66d8000 0 0x40>;
571 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&cpg CPG_MOD 927>;
573 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
574 resets = <&cpg 927>;
575 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
576 dma-names = "tx", "rx";
577 i2c-scl-internal-delay-ns = <110>;
578 status = "disabled";
579 };
581 i2c5: i2c@e66e0000 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "renesas,i2c-r8a77961",
585 "renesas,rcar-gen3-i2c";
586 reg = <0 0xe66e0000 0 0x40>;
587 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cpg CPG_MOD 919>;
589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
590 resets = <&cpg 919>;
591 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
592 dma-names = "tx", "rx";
593 i2c-scl-internal-delay-ns = <110>;
594 status = "disabled";
595 };
597 i2c6: i2c@e66e8000 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "renesas,i2c-r8a77961",
601 "renesas,rcar-gen3-i2c";
602 reg = <0 0xe66e8000 0 0x40>;
603 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 918>;
605 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
606 resets = <&cpg 918>;
607 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
608 dma-names = "tx", "rx";
609 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled";
611 };
613 i2c_dvfs: i2c@e60b0000 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "renesas,iic-r8a77961",
617 "renesas,rcar-gen3-iic",
618 "renesas,rmobile-iic";
619 reg = <0 0xe60b0000 0 0x425>;
620 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cpg CPG_MOD 926>;
622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
623 resets = <&cpg 926>;
624 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
625 dma-names = "tx", "rx";
626 status = "disabled";
627 };
630 hscif1: serial@e6550000 {
631 reg = <0 0xe6550000 0 0x60>;
632 /* placeholder */
633 };
635 hsusb: usb@e6590000 {
636 reg = <0 0xe6590000 0 0x200>;
637 /* placeholder */
638 };
640 usb3_phy0: usb-phy@e65ee000 {
641 reg = <0 0xe65ee000 0 0x90>;
642 #phy-cells = <0>;
643 /* placeholder */
644 };
646 arm_cc630p: crypto@e6601000 {
647 compatible = "arm,cryptocell-630p-ree";
648 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
649 reg = <0x0 0xe6601000 0 0x1000>;
650 clocks = <&cpg CPG_MOD 229>;
651 resets = <&cpg 229>;
652 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
653 };
655 dmac0: dma-controller@e6700000 {
656 compatible = "renesas,dmac-r8a77961",
657 "renesas,rcar-dmac";
658 reg = <0 0xe6700000 0 0x10000>;
659 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
676 interrupt-names = "error",
677 "ch0", "ch1", "ch2", "ch3",
678 "ch4", "ch5", "ch6", "ch7",
679 "ch8", "ch9", "ch10", "ch11",
680 "ch12", "ch13", "ch14", "ch15";
681 clocks = <&cpg CPG_MOD 219>;
682 clock-names = "fck";
683 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
684 resets = <&cpg 219>;
685 #dma-cells = <1>;
686 dma-channels = <16>;
687 };
689 dmac1: dma-controller@e7300000 {
690 compatible = "renesas,dmac-r8a77961",
691 "renesas,rcar-dmac";
692 reg = <0 0xe7300000 0 0x10000>;
693 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
710 interrupt-names = "error",
711 "ch0", "ch1", "ch2", "ch3",
712 "ch4", "ch5", "ch6", "ch7",
713 "ch8", "ch9", "ch10", "ch11",
714 "ch12", "ch13", "ch14", "ch15";
715 clocks = <&cpg CPG_MOD 218>;
716 clock-names = "fck";
717 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
718 resets = <&cpg 218>;
719 #dma-cells = <1>;
720 dma-channels = <16>;
721 };
723 dmac2: dma-controller@e7310000 {
724 compatible = "renesas,dmac-r8a77961",
725 "renesas,rcar-dmac";
726 reg = <0 0xe7310000 0 0x10000>;
727 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
744 interrupt-names = "error",
745 "ch0", "ch1", "ch2", "ch3",
746 "ch4", "ch5", "ch6", "ch7",
747 "ch8", "ch9", "ch10", "ch11",
748 "ch12", "ch13", "ch14", "ch15";
749 clocks = <&cpg CPG_MOD 217>;
750 clock-names = "fck";
751 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
752 resets = <&cpg 217>;
753 #dma-cells = <1>;
754 dma-channels = <16>;
755 };
757 avb: ethernet@e6800000 {
758 compatible = "renesas,etheravb-r8a77961",
759 "renesas,etheravb-rcar-gen3";
760 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
761 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
786 interrupt-names = "ch0", "ch1", "ch2", "ch3",
787 "ch4", "ch5", "ch6", "ch7",
788 "ch8", "ch9", "ch10", "ch11",
789 "ch12", "ch13", "ch14", "ch15",
790 "ch16", "ch17", "ch18", "ch19",
791 "ch20", "ch21", "ch22", "ch23",
792 "ch24";
793 clocks = <&cpg CPG_MOD 812>;
794 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
795 resets = <&cpg 812>;
796 phy-mode = "rgmii";
797 #address-cells = <1>;
798 #size-cells = <0>;
799 status = "disabled";
800 };
802 pwm1: pwm@e6e31000 {
803 reg = <0 0xe6e31000 0 8>;
804 #pwm-cells = <2>;
805 /* placeholder */
806 };
808 scif1: serial@e6e68000 {
809 reg = <0 0xe6e68000 0 64>;
810 /* placeholder */
811 };
813 scif2: serial@e6e88000 {
814 compatible = "renesas,scif-r8a77961",
815 "renesas,rcar-gen3-scif", "renesas,scif";
816 reg = <0 0xe6e88000 0 64>;
817 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&cpg CPG_MOD 310>,
819 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
820 <&scif_clk>;
821 clock-names = "fck", "brg_int", "scif_clk";
822 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
823 resets = <&cpg 310>;
824 status = "disabled";
825 };
827 vin0: video@e6ef0000 {
828 reg = <0 0xe6ef0000 0 0x1000>;
829 /* placeholder */
830 };
832 vin1: video@e6ef1000 {
833 reg = <0 0xe6ef1000 0 0x1000>;
834 /* placeholder */
835 };
837 vin2: video@e6ef2000 {
838 reg = <0 0xe6ef2000 0 0x1000>;
839 /* placeholder */
840 };
842 vin3: video@e6ef3000 {
843 reg = <0 0xe6ef3000 0 0x1000>;
844 /* placeholder */
845 };
847 vin4: video@e6ef4000 {
848 reg = <0 0xe6ef4000 0 0x1000>;
849 /* placeholder */
850 };
852 vin5: video@e6ef5000 {
853 reg = <0 0xe6ef5000 0 0x1000>;
854 /* placeholder */
855 };
857 vin6: video@e6ef6000 {
858 reg = <0 0xe6ef6000 0 0x1000>;
859 /* placeholder */
860 };
862 vin7: video@e6ef7000 {
863 reg = <0 0xe6ef7000 0 0x1000>;
864 /* placeholder */
865 };
867 rcar_sound: sound@ec500000 {
868 reg = <0 0xec500000 0 0x1000>, /* SCU */
869 <0 0xec5a0000 0 0x100>, /* ADG */
870 <0 0xec540000 0 0x1000>, /* SSIU */
871 <0 0xec541000 0 0x280>, /* SSI */
872 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
873 /* placeholder */
874 rcar_sound,dvc {
875 dvc0: dvc-0 { };
876 dvc1: dvc-1 { };
877 };
879 rcar_sound,src {
880 src0: src-0 { };
881 src1: src-1 { };
882 };
884 rcar_sound,ssi {
885 ssi0: ssi-0 { };
886 ssi1: ssi-1 { };
887 ssi2: ssi-2 { };
888 };
889 };
891 xhci0: usb@ee000000 {
892 reg = <0 0xee000000 0 0xc00>;
893 /* placeholder */
894 };
896 usb3_peri0: usb@ee020000 {
897 reg = <0 0xee020000 0 0x400>;
898 /* placeholder */
899 };
901 ohci0: usb@ee080000 {
902 reg = <0 0xee080000 0 0x100>;
903 /* placeholder */
904 };
906 ohci1: usb@ee0a0000 {
907 reg = <0 0xee0a0000 0 0x100>;
908 /* placeholder */
909 };
911 ehci0: usb@ee080100 {
912 reg = <0 0xee080100 0 0x100>;
913 /* placeholder */
914 };
916 ehci1: usb@ee0a0100 {
917 reg = <0 0xee0a0100 0 0x100>;
918 /* placeholder */
919 };
921 usb2_phy0: usb-phy@ee080200 {
922 reg = <0 0xee080200 0 0x700>;
923 /* placeholder */
924 };
926 usb2_phy1: usb-phy@ee0a0200 {
927 reg = <0 0xee0a0200 0 0x700>;
928 /* placeholder */
929 };
931 sdhi0: sd@ee100000 {
932 compatible = "renesas,sdhi-r8a77961",
933 "renesas,rcar-gen3-sdhi";
934 reg = <0 0xee100000 0 0x2000>;
935 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&cpg CPG_MOD 314>;
937 max-frequency = <200000000>;
938 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
939 resets = <&cpg 314>;
940 status = "disabled";
941 };
943 sdhi1: sd@ee120000 {
944 compatible = "renesas,sdhi-r8a77961",
945 "renesas,rcar-gen3-sdhi";
946 reg = <0 0xee120000 0 0x2000>;
947 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cpg CPG_MOD 313>;
949 max-frequency = <200000000>;
950 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
951 resets = <&cpg 313>;
952 status = "disabled";
953 };
955 sdhi2: sd@ee140000 {
956 compatible = "renesas,sdhi-r8a77961",
957 "renesas,rcar-gen3-sdhi";
958 reg = <0 0xee140000 0 0x2000>;
959 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cpg CPG_MOD 312>;
961 max-frequency = <200000000>;
962 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
963 resets = <&cpg 312>;
964 status = "disabled";
965 };
967 sdhi3: sd@ee160000 {
968 compatible = "renesas,sdhi-r8a77961",
969 "renesas,rcar-gen3-sdhi";
970 reg = <0 0xee160000 0 0x2000>;
971 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&cpg CPG_MOD 311>;
973 max-frequency = <200000000>;
974 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
975 resets = <&cpg 311>;
976 status = "disabled";
977 };
979 gic: interrupt-controller@f1010000 {
980 compatible = "arm,gic-400";
981 #interrupt-cells = <3>;
982 #address-cells = <0>;
983 interrupt-controller;
984 reg = <0x0 0xf1010000 0 0x1000>,
985 <0x0 0xf1020000 0 0x20000>,
986 <0x0 0xf1040000 0 0x20000>,
987 <0x0 0xf1060000 0 0x20000>;
988 interrupts = <GIC_PPI 9
989 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
990 clocks = <&cpg CPG_MOD 408>;
991 clock-names = "clk";
992 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
993 resets = <&cpg 408>;
994 };
996 pciec0: pcie@fe000000 {
997 reg = <0 0xfe000000 0 0x80000>;
998 /* placeholder */
999 };
1001 pciec1: pcie@ee800000 {
1002 reg = <0 0xee800000 0 0x80000>;
1003 /* placeholder */
1004 };
1006 csi20: csi2@fea80000 {
1007 reg = <0 0xfea80000 0 0x10000>;
1008 /* placeholder */
1010 ports {
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1014 port@1 {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 reg = <1>;
1018 };
1019 };
1020 };
1022 csi40: csi2@feaa0000 {
1023 reg = <0 0xfeaa0000 0 0x10000>;
1024 /* placeholder */
1026 ports {
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1030 port@1 {
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1034 reg = <1>;
1035 };
1036 };
1037 };
1039 hdmi0: hdmi@fead0000 {
1040 reg = <0 0xfead0000 0 0x10000>;
1041 /* placeholder */
1043 ports {
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 port@0 {
1047 reg = <0>;
1048 };
1049 port@1 {
1050 reg = <1>;
1051 };
1052 port@2 {
1053 /* HDMI sound */
1054 reg = <2>;
1055 };
1056 };
1057 };
1059 du: display@feb00000 {
1060 reg = <0 0xfeb00000 0 0x70000>;
1061 /* placeholder */
1063 ports {
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1067 port@0 {
1068 reg = <0>;
1069 du_out_rgb: endpoint {
1070 };
1071 };
1072 port@1 {
1073 reg = <1>;
1074 du_out_hdmi0: endpoint {
1075 };
1076 };
1077 port@2 {
1078 reg = <2>;
1079 du_out_lvds0: endpoint {
1080 };
1081 };
1082 };
1083 };
1085 prr: chipid@fff00044 {
1086 compatible = "renesas,prr";
1087 reg = <0 0xfff00044 0 4>;
1088 };
1089 };
1091 thermal-zones {
1092 sensor_thermal1: sensor-thermal1 {
1093 polling-delay-passive = <250>;
1094 polling-delay = <1000>;
1095 thermal-sensors = <&tsc 0>;
1096 sustainable-power = <3874>;
1098 trips {
1099 sensor1_crit: sensor1-crit {
1100 temperature = <120000>;
1101 hysteresis = <1000>;
1102 type = "critical";
1103 };
1104 };
1105 };
1107 sensor_thermal2: sensor-thermal2 {
1108 polling-delay-passive = <250>;
1109 polling-delay = <1000>;
1110 thermal-sensors = <&tsc 1>;
1111 sustainable-power = <3874>;
1113 trips {
1114 sensor2_crit: sensor2-crit {
1115 temperature = <120000>;
1116 hysteresis = <1000>;
1117 type = "critical";
1118 };
1119 };
1120 };
1122 sensor_thermal3: sensor-thermal3 {
1123 polling-delay-passive = <250>;
1124 polling-delay = <1000>;
1125 thermal-sensors = <&tsc 2>;
1126 sustainable-power = <3874>;
1128 cooling-maps {
1129 map0 {
1130 trip = <&target>;
1131 cooling-device = <&a57_0 2 4>;
1132 contribution = <1024>;
1133 };
1134 map1 {
1135 trip = <&target>;
1136 cooling-device = <&a53_0 0 2>;
1137 contribution = <1024>;
1138 };
1139 };
1140 trips {
1141 target: trip-point1 {
1142 temperature = <100000>;
1143 hysteresis = <1000>;
1144 type = "passive";
1145 };
1147 sensor3_crit: sensor3-crit {
1148 temperature = <120000>;
1149 hysteresis = <1000>;
1150 type = "critical";
1151 };
1152 };
1153 };
1154 };
1156 timer {
1157 compatible = "arm,armv8-timer";
1158 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1159 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1160 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1161 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
1162 };
1164 /* External USB clocks - can be overridden by the board */
1165 usb3s0_clk: usb3s0 {
1166 compatible = "fixed-clock";
1167 #clock-cells = <0>;
1168 clock-frequency = <0>;
1169 };
1171 usb_extal_clk: usb_extal {
1172 compatible = "fixed-clock";
1173 #clock-cells = <0>;
1174 clock-frequency = <0>;
1175 };
1176 };