1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
4 * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399.dtsi"
11 #include "rk3399-opp.dtsi"
14 model = "Radxa ROCK Pi 4";
15 compatible = "radxa,rockpi4", "rockchip,rk3399";
18 stdout-path = "serial2:1500000n8";
21 clkin_gmac: external-gmac-clock {
22 compatible = "fixed-clock";
23 clock-frequency = <125000000>;
24 clock-output-names = "clkin_gmac";
28 sdio_pwrseq: sdio-pwrseq {
29 compatible = "mmc-pwrseq-simple";
31 clock-names = "ext_clock";
32 pinctrl-names = "default";
33 pinctrl-0 = <&wifi_enable_h>;
34 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
38 compatible = "regulator-fixed";
39 regulator-name = "vcc12v_dcin";
42 regulator-min-microvolt = <12000000>;
43 regulator-max-microvolt = <12000000>;
47 compatible = "regulator-fixed";
48 regulator-name = "vcc5v0_sys";
51 regulator-min-microvolt = <5000000>;
52 regulator-max-microvolt = <5000000>;
53 vin-supply = <&vcc12v_dcin>;
57 compatible = "regulator-fixed";
58 regulator-name = "vcc_0v9";
61 regulator-min-microvolt = <900000>;
62 regulator-max-microvolt = <900000>;
63 vin-supply = <&vcc3v3_sys>;
66 vcc3v3_pcie: vcc3v3-pcie-regulator {
67 compatible = "regulator-fixed";
69 gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pcie_pwr_en>;
72 regulator-name = "vcc3v3_pcie";
75 vin-supply = <&vcc5v0_sys>;
78 vcc3v3_sys: vcc3v3-sys {
79 compatible = "regulator-fixed";
80 regulator-name = "vcc3v3_sys";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 vin-supply = <&vcc5v0_sys>;
88 vcc5v0_host: vcc5v0-host-regulator {
89 compatible = "regulator-fixed";
91 gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&vcc5v0_host_en>;
94 regulator-name = "vcc5v0_host";
96 vin-supply = <&vcc5v0_sys>;
99 vcc5v0_typec: vcc5v0-typec-regulator {
100 compatible = "regulator-fixed";
102 gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&vcc5v0_typec_en>;
105 regulator-name = "vcc5v0_typec";
107 vin-supply = <&vcc5v0_sys>;
110 vcc_lan: vcc3v3-phy-regulator {
111 compatible = "regulator-fixed";
112 regulator-name = "vcc_lan";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
118 regulator-state-mem {
119 regulator-off-in-suspend;
124 compatible = "pwm-regulator";
125 pwms = <&pwm2 0 25000 1>;
126 regulator-name = "vdd_log";
129 regulator-min-microvolt = <800000>;
130 regulator-max-microvolt = <1400000>;
131 vin-supply = <&vcc5v0_sys>;
136 cpu-supply = <&vdd_cpu_l>;
140 cpu-supply = <&vdd_cpu_l>;
144 cpu-supply = <&vdd_cpu_l>;
148 cpu-supply = <&vdd_cpu_l>;
152 cpu-supply = <&vdd_cpu_b>;
156 cpu-supply = <&vdd_cpu_b>;
164 assigned-clocks = <&cru SCLK_RMII_SRC>;
165 assigned-clock-parents = <&clkin_gmac>;
166 clock_in_out = "input";
167 phy-supply = <&vcc_lan>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&rgmii_pins>;
171 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
172 snps,reset-active-low;
173 snps,reset-delays-us = <0 10000 50000>;
180 mali-supply = <&vdd_gpu>;
185 ddc-i2c-bus = <&i2c3>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&hdmi_cec>;
196 clock-frequency = <400000>;
197 i2c-scl-rising-time-ns = <168>;
198 i2c-scl-falling-time-ns = <4>;
202 compatible = "rockchip,rk808";
204 interrupt-parent = <&gpio1>;
205 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
207 clock-output-names = "xin32k", "rk808-clkout2";
208 pinctrl-names = "default";
209 pinctrl-0 = <&pmic_int_l>;
210 rockchip,system-power-controller;
213 vcc1-supply = <&vcc5v0_sys>;
214 vcc2-supply = <&vcc5v0_sys>;
215 vcc3-supply = <&vcc5v0_sys>;
216 vcc4-supply = <&vcc5v0_sys>;
217 vcc6-supply = <&vcc5v0_sys>;
218 vcc7-supply = <&vcc5v0_sys>;
219 vcc8-supply = <&vcc3v3_sys>;
220 vcc9-supply = <&vcc5v0_sys>;
221 vcc10-supply = <&vcc5v0_sys>;
222 vcc11-supply = <&vcc5v0_sys>;
223 vcc12-supply = <&vcc3v3_sys>;
224 vddio-supply = <&vcc_1v8>;
227 vdd_center: DCDC_REG1 {
228 regulator-name = "vdd_center";
231 regulator-min-microvolt = <750000>;
232 regulator-max-microvolt = <1350000>;
233 regulator-ramp-delay = <6001>;
234 regulator-state-mem {
235 regulator-off-in-suspend;
239 vdd_cpu_l: DCDC_REG2 {
240 regulator-name = "vdd_cpu_l";
243 regulator-min-microvolt = <750000>;
244 regulator-max-microvolt = <1350000>;
245 regulator-ramp-delay = <6001>;
246 regulator-state-mem {
247 regulator-off-in-suspend;
252 regulator-name = "vcc_ddr";
255 regulator-state-mem {
256 regulator-on-in-suspend;
261 regulator-name = "vcc_1v8";
264 regulator-min-microvolt = <1800000>;
265 regulator-max-microvolt = <1800000>;
266 regulator-state-mem {
267 regulator-on-in-suspend;
268 regulator-suspend-microvolt = <1800000>;
272 vcc1v8_codec: LDO_REG1 {
273 regulator-name = "vcc1v8_codec";
276 regulator-min-microvolt = <1800000>;
277 regulator-max-microvolt = <1800000>;
278 regulator-state-mem {
279 regulator-off-in-suspend;
283 vcc1v8_hdmi: LDO_REG2 {
284 regulator-name = "vcc1v8_hdmi";
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <1800000>;
289 regulator-state-mem {
290 regulator-off-in-suspend;
295 regulator-name = "vcca_1v8";
298 regulator-min-microvolt = <1800000>;
299 regulator-max-microvolt = <1800000>;
300 regulator-state-mem {
301 regulator-on-in-suspend;
302 regulator-suspend-microvolt = <1800000>;
307 regulator-name = "vcc_sdio";
310 regulator-min-microvolt = <3000000>;
311 regulator-max-microvolt = <3000000>;
312 regulator-state-mem {
313 regulator-on-in-suspend;
314 regulator-suspend-microvolt = <3000000>;
318 vcca3v0_codec: LDO_REG5 {
319 regulator-name = "vcca3v0_codec";
322 regulator-min-microvolt = <3000000>;
323 regulator-max-microvolt = <3000000>;
324 regulator-state-mem {
325 regulator-off-in-suspend;
330 regulator-name = "vcc_1v5";
333 regulator-min-microvolt = <1500000>;
334 regulator-max-microvolt = <1500000>;
335 regulator-state-mem {
336 regulator-on-in-suspend;
337 regulator-suspend-microvolt = <1500000>;
341 vcc0v9_hdmi: LDO_REG7 {
342 regulator-name = "vcc0v9_hdmi";
345 regulator-min-microvolt = <900000>;
346 regulator-max-microvolt = <900000>;
347 regulator-state-mem {
348 regulator-off-in-suspend;
353 regulator-name = "vcc_3v0";
356 regulator-min-microvolt = <3000000>;
357 regulator-max-microvolt = <3000000>;
358 regulator-state-mem {
359 regulator-on-in-suspend;
360 regulator-suspend-microvolt = <3000000>;
364 vcc_cam: SWITCH_REG1 {
365 regulator-name = "vcc_cam";
368 regulator-min-microvolt = <3300000>;
369 regulator-max-microvolt = <3300000>;
370 regulator-state-mem {
371 regulator-off-in-suspend;
375 vcc_mipi: SWITCH_REG2 {
376 regulator-name = "vcc_mipi";
379 regulator-min-microvolt = <3300000>;
380 regulator-max-microvolt = <3300000>;
381 regulator-state-mem {
382 regulator-off-in-suspend;
388 vdd_cpu_b: regulator@40 {
389 compatible = "silergy,syr827";
391 fcs,suspend-voltage-selector = <1>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&vsel1_gpio>;
394 regulator-name = "vdd_cpu_b";
395 regulator-min-microvolt = <712500>;
396 regulator-max-microvolt = <1500000>;
397 regulator-ramp-delay = <1000>;
400 vin-supply = <&vcc5v0_sys>;
402 regulator-state-mem {
403 regulator-off-in-suspend;
407 vdd_gpu: regulator@41 {
408 compatible = "silergy,syr828";
410 fcs,suspend-voltage-selector = <1>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&vsel2_gpio>;
413 regulator-name = "vdd_gpu";
414 regulator-min-microvolt = <712500>;
415 regulator-max-microvolt = <1500000>;
416 regulator-ramp-delay = <1000>;
419 vin-supply = <&vcc5v0_sys>;
421 regulator-state-mem {
422 regulator-off-in-suspend;
428 i2c-scl-rising-time-ns = <300>;
429 i2c-scl-falling-time-ns = <15>;
434 i2c-scl-rising-time-ns = <450>;
435 i2c-scl-falling-time-ns = <15>;
440 i2c-scl-rising-time-ns = <600>;
441 i2c-scl-falling-time-ns = <20>;
446 rockchip,playback-channels = <8>;
447 rockchip,capture-channels = <8>;
452 rockchip,playback-channels = <2>;
453 rockchip,capture-channels = <2>;
464 bt656-supply = <&vcc_3v0>;
465 audio-supply = <&vcc_3v0>;
466 sdmmc-supply = <&vcc_sdio>;
467 gpio1830-supply = <&vcc_3v0>;
473 pmu1830-supply = <&vcc_3v0>;
481 ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
482 max-link-speed = <2>;
484 pinctrl-0 = <&pcie_clkreqnb_cpm>;
485 pinctrl-names = "default";
486 vpcie0v9-supply = <&vcc_0v9>;
487 vpcie1v8-supply = <&vcc_1v8>;
488 vpcie3v3-supply = <&vcc3v3_pcie>;
494 bt_enable_h: bt-enable-h {
495 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
498 bt_host_wake_l: bt-host-wake-l {
499 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
502 bt_wake_l: bt-wake-l {
503 rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
508 pcie_pwr_en: pcie-pwr-en {
509 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
514 sdio0_bus4: sdio0-bus4 {
515 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
516 <2 RK_PC5 1 &pcfg_pull_up_20ma>,
517 <2 RK_PC6 1 &pcfg_pull_up_20ma>,
518 <2 RK_PC7 1 &pcfg_pull_up_20ma>;
521 sdio0_cmd: sdio0-cmd {
522 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>;
525 sdio0_clk: sdio0-clk {
526 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>;
531 pmic_int_l: pmic-int-l {
532 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
535 vsel1_gpio: vsel1-gpio {
536 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
539 vsel2_gpio: vsel2-gpio {
540 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
545 vcc5v0_typec_en: vcc5v0-typec-en {
546 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
551 vcc5v0_host_en: vcc5v0-host-en {
552 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
557 wifi_enable_h: wifi-enable-h {
558 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
561 wifi_host_wake_l: wifi-host-wake-l {
562 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
574 vref-supply = <&vcc_1v8>;
578 #address-cells = <1>;
581 clock-frequency = <50000000>;
584 keep-power-in-suspend;
585 mmc-pwrseq = <&sdio_pwrseq>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
593 compatible = "brcm,bcm4329-fmac";
595 interrupt-parent = <&gpio0>;
596 interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
597 interrupt-names = "host-wake";
598 pinctrl-names = "default";
599 pinctrl-0 = <&wifi_host_wake_l>;
607 cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
609 max-frequency = <150000000>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
618 mmc-hs400-enhanced-strobe;
634 /* tshut mode 0:CRU 1:GPIO */
635 rockchip,hw-tshut-mode = <1>;
636 /* tshut polarity 0:LOW 1:HIGH */
637 rockchip,hw-tshut-polarity = <1>;
643 u2phy0_otg: otg-port {
647 u2phy0_host: host-port {
648 phy-supply = <&vcc5v0_host>;
656 u2phy1_otg: otg-port {
660 u2phy1_host: host-port {
661 phy-supply = <&vcc5v0_host>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
672 compatible = "brcm,bcm43438-bt";
674 clock-names = "ext_clock";
675 device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
676 host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
677 shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;