| blob | e23a10831b275951e6fb4fb1e261c6301d7016f3 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
8 &cbass_mcu {
9 mcu_conf: scm_conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
11 reg = <0x0 0x40f00000 0x0 0x20000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
16 phy_gmii_sel: phy@4040 {
17 compatible = "ti,am654-phy-gmii-sel";
18 reg = <0x4040 0x4>;
19 #phy-cells = <1>;
20 };
21 };
23 mcu_uart0: serial@40a00000 {
24 compatible = "ti,am654-uart";
25 reg = <0x00 0x40a00000 0x00 0x100>;
26 reg-shift = <2>;
27 reg-io-width = <4>;
28 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
29 clock-frequency = <96000000>;
30 current-speed = <115200>;
31 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
32 };
34 mcu_ram: sram@41c00000 {
35 compatible = "mmio-sram";
36 reg = <0x00 0x41c00000 0x00 0x80000>;
37 ranges = <0x0 0x00 0x41c00000 0x80000>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 };
42 mcu_i2c0: i2c@40b00000 {
43 compatible = "ti,am654-i2c", "ti,omap4-i2c";
44 reg = <0x0 0x40b00000 0x0 0x100>;
45 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
46 #address-cells = <1>;
47 #size-cells = <0>;
48 clock-names = "fck";
49 clocks = <&k3_clks 114 1>;
50 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
51 };
53 mcu_spi0: spi@40300000 {
54 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
55 reg = <0x0 0x40300000 0x0 0x400>;
56 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&k3_clks 142 1>;
58 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 };
63 mcu_spi1: spi@40310000 {
64 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
65 reg = <0x0 0x40310000 0x0 0x400>;
66 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
67 clocks = <&k3_clks 143 1>;
68 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
69 #address-cells = <1>;
70 #size-cells = <0>;
71 };
73 mcu_spi2: spi@40320000 {
74 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
75 reg = <0x0 0x40320000 0x0 0x400>;
76 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&k3_clks 144 1>;
78 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81 };
83 tscadc0: tscadc@40200000 {
84 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
85 reg = <0x0 0x40200000 0x0 0x1000>;
86 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
87 clocks = <&k3_clks 0 2>;
88 assigned-clocks = <&k3_clks 0 2>;
89 assigned-clock-rates = <60000000>;
90 clock-names = "adc_tsc_fck";
91 dmas = <&mcu_udmap 0x7100>,
92 <&mcu_udmap 0x7101 >;
93 dma-names = "fifo0", "fifo1";
95 adc {
96 #io-channel-cells = <1>;
97 compatible = "ti,am654-adc", "ti,am3359-adc";
98 };
99 };
101 tscadc1: tscadc@40210000 {
102 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
103 reg = <0x0 0x40210000 0x0 0x1000>;
104 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&k3_clks 1 2>;
106 assigned-clocks = <&k3_clks 1 2>;
107 assigned-clock-rates = <60000000>;
108 clock-names = "adc_tsc_fck";
109 dmas = <&mcu_udmap 0x7102>,
110 <&mcu_udmap 0x7103>;
111 dma-names = "fifo0", "fifo1";
113 adc {
114 #io-channel-cells = <1>;
115 compatible = "ti,am654-adc", "ti,am3359-adc";
116 };
117 };
119 mcu_navss {
120 compatible = "simple-mfd";
121 #address-cells = <2>;
122 #size-cells = <2>;
123 ranges;
124 dma-coherent;
125 dma-ranges;
127 ti,sci-dev-id = <119>;
129 mcu_ringacc: ringacc@2b800000 {
130 compatible = "ti,am654-navss-ringacc";
131 reg = <0x0 0x2b800000 0x0 0x400000>,
132 <0x0 0x2b000000 0x0 0x400000>,
133 <0x0 0x28590000 0x0 0x100>,
134 <0x0 0x2a500000 0x0 0x40000>;
135 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
136 ti,num-rings = <286>;
137 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
138 ti,dma-ring-reset-quirk;
139 ti,sci = <&dmsc>;
140 ti,sci-dev-id = <195>;
141 msi-parent = <&inta_main_udmass>;
142 };
144 mcu_udmap: dma-controller@285c0000 {
145 compatible = "ti,am654-navss-mcu-udmap";
146 reg = <0x0 0x285c0000 0x0 0x100>,
147 <0x0 0x2a800000 0x0 0x40000>,
148 <0x0 0x2aa00000 0x0 0x40000>;
149 reg-names = "gcfg", "rchanrt", "tchanrt";
150 msi-parent = <&inta_main_udmass>;
151 #dma-cells = <1>;
153 ti,sci = <&dmsc>;
154 ti,sci-dev-id = <194>;
155 ti,ringacc = <&mcu_ringacc>;
157 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
158 <0x2>; /* TX_CHAN */
159 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
160 <0x4>; /* RX_CHAN */
161 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
162 };
163 };
165 fss: fss@47000000 {
166 compatible = "simple-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
169 ranges;
171 ospi0: spi@47040000 {
172 compatible = "ti,am654-ospi", "cdns,qspi-nor";
173 reg = <0x0 0x47040000 0x0 0x100>,
174 <0x5 0x00000000 0x1 0x0000000>;
175 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
176 cdns,fifo-depth = <256>;
177 cdns,fifo-width = <4>;
178 cdns,trigger-address = <0x0>;
179 clocks = <&k3_clks 248 0>;
180 assigned-clocks = <&k3_clks 248 0>;
181 assigned-clock-parents = <&k3_clks 248 2>;
182 assigned-clock-rates = <166666666>;
183 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 };
188 ospi1: spi@47050000 {
189 compatible = "ti,am654-ospi", "cdns,qspi-nor";
190 reg = <0x0 0x47050000 0x0 0x100>,
191 <0x7 0x00000000 0x1 0x00000000>;
192 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
193 cdns,fifo-depth = <256>;
194 cdns,fifo-width = <4>;
195 cdns,trigger-address = <0x0>;
196 clocks = <&k3_clks 249 6>;
197 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201 };
202 };