| blob | 0b9d14b838a17f155c6440b097bca3aac24261a1 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
8 &cbass_main {
9 msmc_ram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x0 0x70000000 0x0 0x800000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x70000000 0x800000>;
16 atf-sram@0 {
17 reg = <0x0 0x20000>;
18 };
19 };
21 gic500: interrupt-controller@1800000 {
22 compatible = "arm,gic-v3";
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26 #interrupt-cells = <3>;
27 interrupt-controller;
28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
29 <0x00 0x01900000 0x00 0x100000>; /* GICR */
31 /* vcpumntirq: virtual CPU interface maintenance interrupt */
32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
34 gic_its: gic-its@1820000 {
35 compatible = "arm,gic-v3-its";
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
38 msi-controller;
39 #msi-cells = <1>;
40 };
41 };
43 main_gpio_intr: interrupt-controller0 {
44 compatible = "ti,sci-intr";
45 ti,intr-trigger-type = <1>;
46 interrupt-controller;
47 interrupt-parent = <&gic500>;
48 #interrupt-cells = <2>;
49 ti,sci = <&dmsc>;
50 ti,sci-dst-id = <14>;
51 ti,sci-rm-range-girq = <0x1>;
52 };
54 main_navss {
55 compatible = "simple-mfd";
56 #address-cells = <2>;
57 #size-cells = <2>;
58 ranges;
59 dma-coherent;
60 dma-ranges;
62 ti,sci-dev-id = <199>;
64 main_navss_intr: interrupt-controller1 {
65 compatible = "ti,sci-intr";
66 ti,intr-trigger-type = <4>;
67 interrupt-controller;
68 interrupt-parent = <&gic500>;
69 #interrupt-cells = <2>;
70 ti,sci = <&dmsc>;
71 ti,sci-dst-id = <14>;
72 ti,sci-rm-range-girq = <0>, <2>;
73 };
75 main_udmass_inta: interrupt-controller@33d00000 {
76 compatible = "ti,sci-inta";
77 reg = <0x0 0x33d00000 0x0 0x100000>;
78 interrupt-controller;
79 interrupt-parent = <&main_navss_intr>;
80 msi-controller;
81 ti,sci = <&dmsc>;
82 ti,sci-dev-id = <209>;
83 ti,sci-rm-range-vint = <0xa>;
84 ti,sci-rm-range-global-event = <0xd>;
85 };
87 secure_proxy_main: mailbox@32c00000 {
88 compatible = "ti,am654-secure-proxy";
89 #mbox-cells = <1>;
90 reg-names = "target_data", "rt", "scfg";
91 reg = <0x00 0x32c00000 0x00 0x100000>,
92 <0x00 0x32400000 0x00 0x100000>,
93 <0x00 0x32800000 0x00 0x100000>;
94 interrupt-names = "rx_011";
95 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
96 };
98 smmu0: smmu@36600000 {
99 compatible = "arm,smmu-v3";
100 reg = <0x0 0x36600000 0x0 0x100000>;
101 interrupt-parent = <&gic500>;
102 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
103 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
104 interrupt-names = "eventq", "gerror";
105 #iommu-cells = <1>;
106 };
108 hwspinlock: spinlock@30e00000 {
109 compatible = "ti,am654-hwspinlock";
110 reg = <0x00 0x30e00000 0x00 0x1000>;
111 #hwlock-cells = <1>;
112 };
114 mailbox0_cluster0: mailbox@31f80000 {
115 compatible = "ti,am654-mailbox";
116 reg = <0x00 0x31f80000 0x00 0x200>;
117 #mbox-cells = <1>;
118 ti,mbox-num-users = <4>;
119 ti,mbox-num-fifos = <16>;
120 interrupt-parent = <&main_navss_intr>;
121 };
123 mailbox0_cluster1: mailbox@31f81000 {
124 compatible = "ti,am654-mailbox";
125 reg = <0x00 0x31f81000 0x00 0x200>;
126 #mbox-cells = <1>;
127 ti,mbox-num-users = <4>;
128 ti,mbox-num-fifos = <16>;
129 interrupt-parent = <&main_navss_intr>;
130 };
132 mailbox0_cluster2: mailbox@31f82000 {
133 compatible = "ti,am654-mailbox";
134 reg = <0x00 0x31f82000 0x00 0x200>;
135 #mbox-cells = <1>;
136 ti,mbox-num-users = <4>;
137 ti,mbox-num-fifos = <16>;
138 interrupt-parent = <&main_navss_intr>;
139 };
141 mailbox0_cluster3: mailbox@31f83000 {
142 compatible = "ti,am654-mailbox";
143 reg = <0x00 0x31f83000 0x00 0x200>;
144 #mbox-cells = <1>;
145 ti,mbox-num-users = <4>;
146 ti,mbox-num-fifos = <16>;
147 interrupt-parent = <&main_navss_intr>;
148 };
150 mailbox0_cluster4: mailbox@31f84000 {
151 compatible = "ti,am654-mailbox";
152 reg = <0x00 0x31f84000 0x00 0x200>;
153 #mbox-cells = <1>;
154 ti,mbox-num-users = <4>;
155 ti,mbox-num-fifos = <16>;
156 interrupt-parent = <&main_navss_intr>;
157 };
159 mailbox0_cluster5: mailbox@31f85000 {
160 compatible = "ti,am654-mailbox";
161 reg = <0x00 0x31f85000 0x00 0x200>;
162 #mbox-cells = <1>;
163 ti,mbox-num-users = <4>;
164 ti,mbox-num-fifos = <16>;
165 interrupt-parent = <&main_navss_intr>;
166 };
168 mailbox0_cluster6: mailbox@31f86000 {
169 compatible = "ti,am654-mailbox";
170 reg = <0x00 0x31f86000 0x00 0x200>;
171 #mbox-cells = <1>;
172 ti,mbox-num-users = <4>;
173 ti,mbox-num-fifos = <16>;
174 interrupt-parent = <&main_navss_intr>;
175 };
177 mailbox0_cluster7: mailbox@31f87000 {
178 compatible = "ti,am654-mailbox";
179 reg = <0x00 0x31f87000 0x00 0x200>;
180 #mbox-cells = <1>;
181 ti,mbox-num-users = <4>;
182 ti,mbox-num-fifos = <16>;
183 interrupt-parent = <&main_navss_intr>;
184 };
186 mailbox0_cluster8: mailbox@31f88000 {
187 compatible = "ti,am654-mailbox";
188 reg = <0x00 0x31f88000 0x00 0x200>;
189 #mbox-cells = <1>;
190 ti,mbox-num-users = <4>;
191 ti,mbox-num-fifos = <16>;
192 interrupt-parent = <&main_navss_intr>;
193 };
195 mailbox0_cluster9: mailbox@31f89000 {
196 compatible = "ti,am654-mailbox";
197 reg = <0x00 0x31f89000 0x00 0x200>;
198 #mbox-cells = <1>;
199 ti,mbox-num-users = <4>;
200 ti,mbox-num-fifos = <16>;
201 interrupt-parent = <&main_navss_intr>;
202 };
204 mailbox0_cluster10: mailbox@31f8a000 {
205 compatible = "ti,am654-mailbox";
206 reg = <0x00 0x31f8a000 0x00 0x200>;
207 #mbox-cells = <1>;
208 ti,mbox-num-users = <4>;
209 ti,mbox-num-fifos = <16>;
210 interrupt-parent = <&main_navss_intr>;
211 };
213 mailbox0_cluster11: mailbox@31f8b000 {
214 compatible = "ti,am654-mailbox";
215 reg = <0x00 0x31f8b000 0x00 0x200>;
216 #mbox-cells = <1>;
217 ti,mbox-num-users = <4>;
218 ti,mbox-num-fifos = <16>;
219 interrupt-parent = <&main_navss_intr>;
220 };
222 main_ringacc: ringacc@3c000000 {
223 compatible = "ti,am654-navss-ringacc";
224 reg = <0x0 0x3c000000 0x0 0x400000>,
225 <0x0 0x38000000 0x0 0x400000>,
226 <0x0 0x31120000 0x0 0x100>,
227 <0x0 0x33000000 0x0 0x40000>;
228 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
229 ti,num-rings = <1024>;
230 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
231 ti,sci = <&dmsc>;
232 ti,sci-dev-id = <211>;
233 msi-parent = <&main_udmass_inta>;
234 };
236 main_udmap: dma-controller@31150000 {
237 compatible = "ti,j721e-navss-main-udmap";
238 reg = <0x0 0x31150000 0x0 0x100>,
239 <0x0 0x34000000 0x0 0x100000>,
240 <0x0 0x35000000 0x0 0x100000>;
241 reg-names = "gcfg", "rchanrt", "tchanrt";
242 msi-parent = <&main_udmass_inta>;
243 #dma-cells = <1>;
245 ti,sci = <&dmsc>;
246 ti,sci-dev-id = <212>;
247 ti,ringacc = <&main_ringacc>;
249 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
250 <0x0f>, /* TX_HCHAN */
251 <0x10>; /* TX_UHCHAN */
252 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
253 <0x0b>, /* RX_HCHAN */
254 <0x0c>; /* RX_UHCHAN */
255 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
256 };
257 };
259 main_pmx0: pinmux@11c000 {
260 compatible = "pinctrl-single";
261 /* Proxy 0 addressing */
262 reg = <0x0 0x11c000 0x0 0x2b4>;
263 #pinctrl-cells = <1>;
264 pinctrl-single,register-width = <32>;
265 pinctrl-single,function-mask = <0xffffffff>;
266 };
268 main_uart0: serial@2800000 {
269 compatible = "ti,j721e-uart", "ti,am654-uart";
270 reg = <0x00 0x02800000 0x00 0x100>;
271 reg-shift = <2>;
272 reg-io-width = <4>;
273 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
274 clock-frequency = <48000000>;
275 current-speed = <115200>;
276 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
277 clocks = <&k3_clks 146 0>;
278 clock-names = "fclk";
279 };
281 main_uart1: serial@2810000 {
282 compatible = "ti,j721e-uart", "ti,am654-uart";
283 reg = <0x00 0x02810000 0x00 0x100>;
284 reg-shift = <2>;
285 reg-io-width = <4>;
286 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
287 clock-frequency = <48000000>;
288 current-speed = <115200>;
289 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
290 clocks = <&k3_clks 278 0>;
291 clock-names = "fclk";
292 };
294 main_uart2: serial@2820000 {
295 compatible = "ti,j721e-uart", "ti,am654-uart";
296 reg = <0x00 0x02820000 0x00 0x100>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
299 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
300 clock-frequency = <48000000>;
301 current-speed = <115200>;
302 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
303 clocks = <&k3_clks 279 0>;
304 clock-names = "fclk";
305 };
307 main_uart3: serial@2830000 {
308 compatible = "ti,j721e-uart", "ti,am654-uart";
309 reg = <0x00 0x02830000 0x00 0x100>;
310 reg-shift = <2>;
311 reg-io-width = <4>;
312 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
313 clock-frequency = <48000000>;
314 current-speed = <115200>;
315 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
316 clocks = <&k3_clks 280 0>;
317 clock-names = "fclk";
318 };
320 main_uart4: serial@2840000 {
321 compatible = "ti,j721e-uart", "ti,am654-uart";
322 reg = <0x00 0x02840000 0x00 0x100>;
323 reg-shift = <2>;
324 reg-io-width = <4>;
325 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
326 clock-frequency = <48000000>;
327 current-speed = <115200>;
328 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
329 clocks = <&k3_clks 281 0>;
330 clock-names = "fclk";
331 };
333 main_uart5: serial@2850000 {
334 compatible = "ti,j721e-uart", "ti,am654-uart";
335 reg = <0x00 0x02850000 0x00 0x100>;
336 reg-shift = <2>;
337 reg-io-width = <4>;
338 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
339 clock-frequency = <48000000>;
340 current-speed = <115200>;
341 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
342 clocks = <&k3_clks 282 0>;
343 clock-names = "fclk";
344 };
346 main_uart6: serial@2860000 {
347 compatible = "ti,j721e-uart", "ti,am654-uart";
348 reg = <0x00 0x02860000 0x00 0x100>;
349 reg-shift = <2>;
350 reg-io-width = <4>;
351 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
352 clock-frequency = <48000000>;
353 current-speed = <115200>;
354 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
355 clocks = <&k3_clks 283 0>;
356 clock-names = "fclk";
357 };
359 main_uart7: serial@2870000 {
360 compatible = "ti,j721e-uart", "ti,am654-uart";
361 reg = <0x00 0x02870000 0x00 0x100>;
362 reg-shift = <2>;
363 reg-io-width = <4>;
364 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
365 clock-frequency = <48000000>;
366 current-speed = <115200>;
367 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
368 clocks = <&k3_clks 284 0>;
369 clock-names = "fclk";
370 };
372 main_uart8: serial@2880000 {
373 compatible = "ti,j721e-uart", "ti,am654-uart";
374 reg = <0x00 0x02880000 0x00 0x100>;
375 reg-shift = <2>;
376 reg-io-width = <4>;
377 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
378 clock-frequency = <48000000>;
379 current-speed = <115200>;
380 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
381 clocks = <&k3_clks 285 0>;
382 clock-names = "fclk";
383 };
385 main_uart9: serial@2890000 {
386 compatible = "ti,j721e-uart", "ti,am654-uart";
387 reg = <0x00 0x02890000 0x00 0x100>;
388 reg-shift = <2>;
389 reg-io-width = <4>;
390 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
391 clock-frequency = <48000000>;
392 current-speed = <115200>;
393 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
394 clocks = <&k3_clks 286 0>;
395 clock-names = "fclk";
396 };
398 main_gpio0: gpio@600000 {
399 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
400 reg = <0x0 0x00600000 0x0 0x100>;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-parent = <&main_gpio_intr>;
404 interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
405 <105 4>, <105 5>, <105 6>, <105 7>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 ti,ngpio = <128>;
409 ti,davinci-gpio-unbanked = <0>;
410 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
411 clocks = <&k3_clks 105 0>;
412 clock-names = "gpio";
413 };
415 main_gpio1: gpio@601000 {
416 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
417 reg = <0x0 0x00601000 0x0 0x100>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-parent = <&main_gpio_intr>;
421 interrupts = <106 0>, <106 1>, <106 2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 ti,ngpio = <36>;
425 ti,davinci-gpio-unbanked = <0>;
426 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
427 clocks = <&k3_clks 106 0>;
428 clock-names = "gpio";
429 };
431 main_gpio2: gpio@610000 {
432 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
433 reg = <0x0 0x00610000 0x0 0x100>;
434 gpio-controller;
435 #gpio-cells = <2>;
436 interrupt-parent = <&main_gpio_intr>;
437 interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
438 <107 4>, <107 5>, <107 6>, <107 7>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 ti,ngpio = <128>;
442 ti,davinci-gpio-unbanked = <0>;
443 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
444 clocks = <&k3_clks 107 0>;
445 clock-names = "gpio";
446 };
448 main_gpio3: gpio@611000 {
449 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
450 reg = <0x0 0x00611000 0x0 0x100>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-parent = <&main_gpio_intr>;
454 interrupts = <108 0>, <108 1>, <108 2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 ti,ngpio = <36>;
458 ti,davinci-gpio-unbanked = <0>;
459 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
460 clocks = <&k3_clks 108 0>;
461 clock-names = "gpio";
462 };
464 main_gpio4: gpio@620000 {
465 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
466 reg = <0x0 0x00620000 0x0 0x100>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-parent = <&main_gpio_intr>;
470 interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
471 <109 4>, <109 5>, <109 6>, <109 7>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 ti,ngpio = <128>;
475 ti,davinci-gpio-unbanked = <0>;
476 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
477 clocks = <&k3_clks 109 0>;
478 clock-names = "gpio";
479 };
481 main_gpio5: gpio@621000 {
482 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
483 reg = <0x0 0x00621000 0x0 0x100>;
484 gpio-controller;
485 #gpio-cells = <2>;
486 interrupt-parent = <&main_gpio_intr>;
487 interrupts = <110 0>, <110 1>, <110 2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 ti,ngpio = <36>;
491 ti,davinci-gpio-unbanked = <0>;
492 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
493 clocks = <&k3_clks 110 0>;
494 clock-names = "gpio";
495 };
497 main_gpio6: gpio@630000 {
498 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
499 reg = <0x0 0x00630000 0x0 0x100>;
500 gpio-controller;
501 #gpio-cells = <2>;
502 interrupt-parent = <&main_gpio_intr>;
503 interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
504 <111 4>, <111 5>, <111 6>, <111 7>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 ti,ngpio = <128>;
508 ti,davinci-gpio-unbanked = <0>;
509 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
510 clocks = <&k3_clks 111 0>;
511 clock-names = "gpio";
512 };
514 main_gpio7: gpio@631000 {
515 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
516 reg = <0x0 0x00631000 0x0 0x100>;
517 gpio-controller;
518 #gpio-cells = <2>;
519 interrupt-parent = <&main_gpio_intr>;
520 interrupts = <112 0>, <112 1>, <112 2>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 ti,ngpio = <36>;
524 ti,davinci-gpio-unbanked = <0>;
525 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
526 clocks = <&k3_clks 112 0>;
527 clock-names = "gpio";
528 };
530 main_sdhci0: sdhci@4f80000 {
531 compatible = "ti,j721e-sdhci-8bit";
532 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
533 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
534 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
535 clock-names = "clk_xin", "clk_ahb";
536 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
537 assigned-clocks = <&k3_clks 91 1>;
538 assigned-clock-parents = <&k3_clks 91 2>;
539 bus-width = <8>;
540 mmc-hs400-1_8v;
541 mmc-ddr-1_8v;
542 ti,otap-del-sel = <0x2>;
543 ti,trm-icp = <0x8>;
544 ti,strobe-sel = <0x77>;
545 dma-coherent;
546 };
548 main_sdhci1: sdhci@4fb0000 {
549 compatible = "ti,j721e-sdhci-4bit";
550 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
551 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
552 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
553 clock-names = "clk_xin", "clk_ahb";
554 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
555 assigned-clocks = <&k3_clks 92 0>;
556 assigned-clock-parents = <&k3_clks 92 1>;
557 ti,otap-del-sel = <0x2>;
558 ti,trm-icp = <0x8>;
559 ti,clkbuf-sel = <0x7>;
560 dma-coherent;
561 no-1-8-v;
562 };
564 main_sdhci2: sdhci@4f98000 {
565 compatible = "ti,j721e-sdhci-4bit";
566 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
567 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
568 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
569 clock-names = "clk_xin", "clk_ahb";
570 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
571 assigned-clocks = <&k3_clks 93 0>;
572 assigned-clock-parents = <&k3_clks 93 1>;
573 ti,otap-del-sel = <0x2>;
574 ti,trm-icp = <0x8>;
575 ti,clkbuf-sel = <0x7>;
576 dma-coherent;
577 no-1-8-v;
578 };
580 usbss0: cdns_usb@4104000 {
581 compatible = "ti,j721e-usb";
582 reg = <0x00 0x4104000 0x00 0x100>;
583 dma-coherent;
584 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
585 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
586 clock-names = "ref", "lpm";
587 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
588 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
589 #address-cells = <2>;
590 #size-cells = <2>;
591 ranges;
593 usb0: usb@6000000 {
594 compatible = "cdns,usb3";
595 reg = <0x00 0x6000000 0x00 0x10000>,
596 <0x00 0x6010000 0x00 0x10000>,
597 <0x00 0x6020000 0x00 0x10000>;
598 reg-names = "otg", "xhci", "dev";
599 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
600 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
601 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
602 interrupt-names = "host",
603 "peripheral",
604 "otg";
605 maximum-speed = "super-speed";
606 dr_mode = "otg";
607 };
608 };
610 usbss1: cdns_usb@4114000 {
611 compatible = "ti,j721e-usb";
612 reg = <0x00 0x4114000 0x00 0x100>;
613 dma-coherent;
614 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
615 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
616 clock-names = "ref", "lpm";
617 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
618 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
619 #address-cells = <2>;
620 #size-cells = <2>;
621 ranges;
623 usb1: usb@6400000 {
624 compatible = "cdns,usb3";
625 reg = <0x00 0x6400000 0x00 0x10000>,
626 <0x00 0x6410000 0x00 0x10000>,
627 <0x00 0x6420000 0x00 0x10000>;
628 reg-names = "otg", "xhci", "dev";
629 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
630 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
631 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
632 interrupt-names = "host",
633 "peripheral",
634 "otg";
635 maximum-speed = "super-speed";
636 dr_mode = "otg";
637 };
638 };
640 main_i2c0: i2c@2000000 {
641 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
642 reg = <0x0 0x2000000 0x0 0x100>;
643 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 clock-names = "fck";
647 clocks = <&k3_clks 187 0>;
648 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
649 };
651 main_i2c1: i2c@2010000 {
652 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
653 reg = <0x0 0x2010000 0x0 0x100>;
654 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 clock-names = "fck";
658 clocks = <&k3_clks 188 0>;
659 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
660 };
662 main_i2c2: i2c@2020000 {
663 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
664 reg = <0x0 0x2020000 0x0 0x100>;
665 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 clock-names = "fck";
669 clocks = <&k3_clks 189 0>;
670 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
671 };
673 main_i2c3: i2c@2030000 {
674 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
675 reg = <0x0 0x2030000 0x0 0x100>;
676 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>;
678 #size-cells = <0>;
679 clock-names = "fck";
680 clocks = <&k3_clks 190 0>;
681 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
682 };
684 main_i2c4: i2c@2040000 {
685 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
686 reg = <0x0 0x2040000 0x0 0x100>;
687 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 clock-names = "fck";
691 clocks = <&k3_clks 191 0>;
692 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
693 };
695 main_i2c5: i2c@2050000 {
696 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
697 reg = <0x0 0x2050000 0x0 0x100>;
698 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 clock-names = "fck";
702 clocks = <&k3_clks 192 0>;
703 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
704 };
706 main_i2c6: i2c@2060000 {
707 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
708 reg = <0x0 0x2060000 0x0 0x100>;
709 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
710 #address-cells = <1>;
711 #size-cells = <0>;
712 clock-names = "fck";
713 clocks = <&k3_clks 193 0>;
714 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
715 };
717 ufs_wrapper: ufs-wrapper@4e80000 {
718 compatible = "ti,j721e-ufs";
719 reg = <0x0 0x4e80000 0x0 0x100>;
720 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
721 clocks = <&k3_clks 277 1>;
722 assigned-clocks = <&k3_clks 277 1>;
723 assigned-clock-parents = <&k3_clks 277 4>;
724 ranges;
725 #address-cells = <2>;
726 #size-cells = <2>;
728 ufs@4e84000 {
729 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
730 reg = <0x0 0x4e84000 0x0 0x10000>;
731 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
732 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
733 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
734 clock-names = "core_clk", "phy_clk", "ref_clk";
735 dma-coherent;
736 };
737 };
739 mcasp0: mcasp@2b00000 {
740 compatible = "ti,am33xx-mcasp-audio";
741 reg = <0x0 0x02b00000 0x0 0x2000>,
742 <0x0 0x02b08000 0x0 0x1000>;
743 reg-names = "mpu","dat";
744 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
746 interrupt-names = "tx", "rx";
748 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
749 dma-names = "tx", "rx";
751 clocks = <&k3_clks 174 1>;
752 clock-names = "fck";
753 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
755 status = "disabled";
756 };
758 mcasp1: mcasp@2b10000 {
759 compatible = "ti,am33xx-mcasp-audio";
760 reg = <0x0 0x02b10000 0x0 0x2000>,
761 <0x0 0x02b18000 0x0 0x1000>;
762 reg-names = "mpu","dat";
763 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-names = "tx", "rx";
767 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
768 dma-names = "tx", "rx";
770 clocks = <&k3_clks 175 1>;
771 clock-names = "fck";
772 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
774 status = "disabled";
775 };
777 mcasp2: mcasp@2b20000 {
778 compatible = "ti,am33xx-mcasp-audio";
779 reg = <0x0 0x02b20000 0x0 0x2000>,
780 <0x0 0x02b28000 0x0 0x1000>;
781 reg-names = "mpu","dat";
782 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
784 interrupt-names = "tx", "rx";
786 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
787 dma-names = "tx", "rx";
789 clocks = <&k3_clks 176 1>;
790 clock-names = "fck";
791 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
793 status = "disabled";
794 };
796 mcasp3: mcasp@2b30000 {
797 compatible = "ti,am33xx-mcasp-audio";
798 reg = <0x0 0x02b30000 0x0 0x2000>,
799 <0x0 0x02b38000 0x0 0x1000>;
800 reg-names = "mpu","dat";
801 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
803 interrupt-names = "tx", "rx";
805 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
806 dma-names = "tx", "rx";
808 clocks = <&k3_clks 177 1>;
809 clock-names = "fck";
810 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
812 status = "disabled";
813 };
815 mcasp4: mcasp@2b40000 {
816 compatible = "ti,am33xx-mcasp-audio";
817 reg = <0x0 0x02b40000 0x0 0x2000>,
818 <0x0 0x02b48000 0x0 0x1000>;
819 reg-names = "mpu","dat";
820 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
822 interrupt-names = "tx", "rx";
824 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
825 dma-names = "tx", "rx";
827 clocks = <&k3_clks 178 1>;
828 clock-names = "fck";
829 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
831 status = "disabled";
832 };
834 mcasp5: mcasp@2b50000 {
835 compatible = "ti,am33xx-mcasp-audio";
836 reg = <0x0 0x02b50000 0x0 0x2000>,
837 <0x0 0x02b58000 0x0 0x1000>;
838 reg-names = "mpu","dat";
839 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
841 interrupt-names = "tx", "rx";
843 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
844 dma-names = "tx", "rx";
846 clocks = <&k3_clks 179 1>;
847 clock-names = "fck";
848 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
850 status = "disabled";
851 };
853 mcasp6: mcasp@2b60000 {
854 compatible = "ti,am33xx-mcasp-audio";
855 reg = <0x0 0x02b60000 0x0 0x2000>,
856 <0x0 0x02b68000 0x0 0x1000>;
857 reg-names = "mpu","dat";
858 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "tx", "rx";
862 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
863 dma-names = "tx", "rx";
865 clocks = <&k3_clks 180 1>;
866 clock-names = "fck";
867 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
869 status = "disabled";
870 };
872 mcasp7: mcasp@2b70000 {
873 compatible = "ti,am33xx-mcasp-audio";
874 reg = <0x0 0x02b70000 0x0 0x2000>,
875 <0x0 0x02b78000 0x0 0x1000>;
876 reg-names = "mpu","dat";
877 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "tx", "rx";
881 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
882 dma-names = "tx", "rx";
884 clocks = <&k3_clks 181 1>;
885 clock-names = "fck";
886 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
888 status = "disabled";
889 };
891 mcasp8: mcasp@2b80000 {
892 compatible = "ti,am33xx-mcasp-audio";
893 reg = <0x0 0x02b80000 0x0 0x2000>,
894 <0x0 0x02b88000 0x0 0x1000>;
895 reg-names = "mpu","dat";
896 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
898 interrupt-names = "tx", "rx";
900 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
901 dma-names = "tx", "rx";
903 clocks = <&k3_clks 182 1>;
904 clock-names = "fck";
905 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
907 status = "disabled";
908 };
910 mcasp9: mcasp@2b90000 {
911 compatible = "ti,am33xx-mcasp-audio";
912 reg = <0x0 0x02b90000 0x0 0x2000>,
913 <0x0 0x02b98000 0x0 0x1000>;
914 reg-names = "mpu","dat";
915 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
917 interrupt-names = "tx", "rx";
919 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
920 dma-names = "tx", "rx";
922 clocks = <&k3_clks 183 1>;
923 clock-names = "fck";
924 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
926 status = "disabled";
927 };
929 mcasp10: mcasp@2ba0000 {
930 compatible = "ti,am33xx-mcasp-audio";
931 reg = <0x0 0x02ba0000 0x0 0x2000>,
932 <0x0 0x02ba8000 0x0 0x1000>;
933 reg-names = "mpu","dat";
934 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
936 interrupt-names = "tx", "rx";
938 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
939 dma-names = "tx", "rx";
941 clocks = <&k3_clks 184 1>;
942 clock-names = "fck";
943 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
945 status = "disabled";
946 };
948 mcasp11: mcasp@2bb0000 {
949 compatible = "ti,am33xx-mcasp-audio";
950 reg = <0x0 0x02bb0000 0x0 0x2000>,
951 <0x0 0x02bb8000 0x0 0x1000>;
952 reg-names = "mpu","dat";
953 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
955 interrupt-names = "tx", "rx";
957 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
958 dma-names = "tx", "rx";
960 clocks = <&k3_clks 185 1>;
961 clock-names = "fck";
962 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
964 status = "disabled";
965 };
966 };