arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
   4  *
   5  * (C) Copyright 2015 - 2019, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 / {
  17         model = "ZynqMP zc1751-xm016-dc2 RevA";
  18         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  19
  20         aliases {
  21                 can0 = &can0;
  22                 can1 = &can1;
  23                 ethernet0 = &gem2;
  24                 i2c0 = &i2c0;
  25                 rtc0 = &rtc;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28                 spi0 = &spi0;
  29                 spi1 = &spi1;
  30         };
  31
  32         chosen {
  33                 bootargs = "earlycon";
  34                 stdout-path = "serial0:115200n8";
  35         };
  36
  37         memory@0 {
  38                 device_type = "memory";
  39                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  40         };
  41 };
  42
  43 &can0 {
  44         status = "okay";
  45 };
  46
  47 &can1 {
  48         status = "okay";
  49 };
  50
  51 &fpd_dma_chan1 {
  52         status = "okay";
  53 };
  54
  55 &fpd_dma_chan2 {
  56         status = "okay";
  57 };
  58
  59 &fpd_dma_chan3 {
  60         status = "okay";
  61 };
  62
  63 &fpd_dma_chan4 {
  64         status = "okay";
  65 };
  66
  67 &fpd_dma_chan5 {
  68         status = "okay";
  69 };
  70
  71 &fpd_dma_chan6 {
  72         status = "okay";
  73 };
  74
  75 &fpd_dma_chan7 {
  76         status = "okay";
  77 };
  78
  79 &fpd_dma_chan8 {
  80         status = "okay";
  81 };
  82
  83 &gem2 {
  84         status = "okay";
  85         phy-handle = <&phy0>;
  86         phy-mode = "rgmii-id";
  87         phy0: ethernet-phy@5 {
  88                 reg = <5>;
  89                 ti,rx-internal-delay = <0x8>;
  90                 ti,tx-internal-delay = <0xa>;
  91                 ti,fifo-depth = <0x1>;
  92                 ti,dp83867-rxctrl-strap-quirk;
  93         };
  94 };
  95
  96 &gpio {
  97         status = "okay";
  98 };
  99
 100 &i2c0 {
 101         status = "okay";
 102         clock-frequency = <400000>;
 103
 104         tca6416_u26: gpio@20 {
 105                 compatible = "ti,tca6416";
 106                 reg = <0x20>;
 107                 gpio-controller;
 108                 #gpio-cells = <2>;
 109                 /* IRQ not connected */
 110         };
 111
 112         rtc@68 {
 113                 compatible = "dallas,ds1339";
 114                 reg = <0x68>;
 115         };
 116 };
 117
 118 &rtc {
 119         status = "okay";
 120 };
 121
 122 &spi0 {
 123         status = "okay";
 124         num-cs = <1>;
 125
 126         spi0_flash0: flash@0 {
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129                 compatible = "sst,sst25wf080", "jedec,spi-nor";
 130                 spi-max-frequency = <50000000>;
 131                 reg = <0>;
 132
 133                 partition@0 {
 134                         label = "data";
 135                         reg = <0x0 0x100000>;
 136                 };
 137         };
 138 };
 139
 140 &spi1 {
 141         status = "okay";
 142         num-cs = <1>;
 143
 144         spi1_flash0: flash@0 {
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
 148                 spi-max-frequency = <20000000>;
 149                 reg = <0>;
 150
 151                 partition@0 {
 152                         label = "data";
 153                         reg = <0x0 0x84000>;
 154                 };
 155         };
 156 };
 157
 158 /* ULPI SMSC USB3320 */
 159 &usb1 {
 160         status = "okay";
 161         dr_mode = "host";
 162 };
 163
 164 &uart0 {
 165         status = "okay";
 166 };
 167
 168 &uart1 {
 169         status = "okay";
 170 };