2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
14 * Platform devices for Atheros AR5312 SoCs
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/bitops.h>
20 #include <linux/irqdomain.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/mtd/physmap.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
29 #include <ath25_platform.h>
33 #include "ar5312_regs.h"
35 static void __iomem
*ar5312_rst_base
;
36 static struct irq_domain
*ar5312_misc_irq_domain
;
38 static inline u32
ar5312_rst_reg_read(u32 reg
)
40 return __raw_readl(ar5312_rst_base
+ reg
);
43 static inline void ar5312_rst_reg_write(u32 reg
, u32 val
)
45 __raw_writel(val
, ar5312_rst_base
+ reg
);
48 static inline void ar5312_rst_reg_mask(u32 reg
, u32 mask
, u32 val
)
50 u32 ret
= ar5312_rst_reg_read(reg
);
54 ar5312_rst_reg_write(reg
, ret
);
57 static irqreturn_t
ar5312_ahb_err_handler(int cpl
, void *dev_id
)
59 u32 proc1
= ar5312_rst_reg_read(AR5312_PROC1
);
60 u32 proc_addr
= ar5312_rst_reg_read(AR5312_PROCADDR
); /* clears error */
61 u32 dma1
= ar5312_rst_reg_read(AR5312_DMA1
);
62 u32 dma_addr
= ar5312_rst_reg_read(AR5312_DMAADDR
); /* clears error */
64 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
65 proc_addr
, proc1
, dma_addr
, dma1
);
67 machine_restart("AHB error"); /* Catastrophic failure */
71 static struct irqaction ar5312_ahb_err_interrupt
= {
72 .handler
= ar5312_ahb_err_handler
,
73 .name
= "ar5312-ahb-error",
76 static void ar5312_misc_irq_handler(struct irq_desc
*desc
)
78 u32 pending
= ar5312_rst_reg_read(AR5312_ISR
) &
79 ar5312_rst_reg_read(AR5312_IMR
);
80 unsigned nr
, misc_irq
= 0;
83 struct irq_domain
*domain
= irq_desc_get_handler_data(desc
);
86 misc_irq
= irq_find_mapping(domain
, nr
);
90 generic_handle_irq(misc_irq
);
91 if (nr
== AR5312_MISC_IRQ_TIMER
)
92 ar5312_rst_reg_read(AR5312_TIMER
);
98 /* Enable the specified AR5312_MISC_IRQ interrupt */
99 static void ar5312_misc_irq_unmask(struct irq_data
*d
)
101 ar5312_rst_reg_mask(AR5312_IMR
, 0, BIT(d
->hwirq
));
104 /* Disable the specified AR5312_MISC_IRQ interrupt */
105 static void ar5312_misc_irq_mask(struct irq_data
*d
)
107 ar5312_rst_reg_mask(AR5312_IMR
, BIT(d
->hwirq
), 0);
108 ar5312_rst_reg_read(AR5312_IMR
); /* flush write buffer */
111 static struct irq_chip ar5312_misc_irq_chip
= {
112 .name
= "ar5312-misc",
113 .irq_unmask
= ar5312_misc_irq_unmask
,
114 .irq_mask
= ar5312_misc_irq_mask
,
117 static int ar5312_misc_irq_map(struct irq_domain
*d
, unsigned irq
,
120 irq_set_chip_and_handler(irq
, &ar5312_misc_irq_chip
, handle_level_irq
);
124 static struct irq_domain_ops ar5312_misc_irq_domain_ops
= {
125 .map
= ar5312_misc_irq_map
,
128 static void ar5312_irq_dispatch(void)
130 u32 pending
= read_c0_status() & read_c0_cause();
132 if (pending
& CAUSEF_IP2
)
133 do_IRQ(AR5312_IRQ_WLAN0
);
134 else if (pending
& CAUSEF_IP5
)
135 do_IRQ(AR5312_IRQ_WLAN1
);
136 else if (pending
& CAUSEF_IP6
)
137 do_IRQ(AR5312_IRQ_MISC
);
138 else if (pending
& CAUSEF_IP7
)
139 do_IRQ(ATH25_IRQ_CPU_CLOCK
);
141 spurious_interrupt();
144 void __init
ar5312_arch_init_irq(void)
146 struct irq_domain
*domain
;
149 ath25_irq_dispatch
= ar5312_irq_dispatch
;
151 domain
= irq_domain_add_linear(NULL
, AR5312_MISC_IRQ_COUNT
,
152 &ar5312_misc_irq_domain_ops
, NULL
);
154 panic("Failed to add IRQ domain");
156 irq
= irq_create_mapping(domain
, AR5312_MISC_IRQ_AHB_PROC
);
157 setup_irq(irq
, &ar5312_ahb_err_interrupt
);
159 irq_set_chained_handler_and_data(AR5312_IRQ_MISC
,
160 ar5312_misc_irq_handler
, domain
);
162 ar5312_misc_irq_domain
= domain
;
165 static struct physmap_flash_data ar5312_flash_data
= {
169 static struct resource ar5312_flash_resource
= {
170 .start
= AR5312_FLASH_BASE
,
171 .end
= AR5312_FLASH_BASE
+ AR5312_FLASH_SIZE
- 1,
172 .flags
= IORESOURCE_MEM
,
175 static struct platform_device ar5312_physmap_flash
= {
176 .name
= "physmap-flash",
178 .dev
.platform_data
= &ar5312_flash_data
,
179 .resource
= &ar5312_flash_resource
,
183 static void __init
ar5312_flash_init(void)
185 void __iomem
*flashctl_base
;
188 flashctl_base
= ioremap(AR5312_FLASHCTL_BASE
,
189 AR5312_FLASHCTL_SIZE
);
191 ctl
= __raw_readl(flashctl_base
+ AR5312_FLASHCTL0
);
192 ctl
&= AR5312_FLASHCTL_MW
;
194 /* fixup flash width */
196 case AR5312_FLASHCTL_MW16
:
197 ar5312_flash_data
.width
= 2;
199 case AR5312_FLASHCTL_MW8
:
201 ar5312_flash_data
.width
= 1;
206 * Configure flash bank 0.
207 * Assume 8M window size. Flash will be aliased if it's smaller
209 ctl
|= AR5312_FLASHCTL_E
| AR5312_FLASHCTL_AC_8M
| AR5312_FLASHCTL_RBLE
;
210 ctl
|= 0x01 << AR5312_FLASHCTL_IDCY_S
;
211 ctl
|= 0x07 << AR5312_FLASHCTL_WST1_S
;
212 ctl
|= 0x07 << AR5312_FLASHCTL_WST2_S
;
213 __raw_writel(ctl
, flashctl_base
+ AR5312_FLASHCTL0
);
215 /* Disable other flash banks */
216 ctl
= __raw_readl(flashctl_base
+ AR5312_FLASHCTL1
);
217 ctl
&= ~(AR5312_FLASHCTL_E
| AR5312_FLASHCTL_AC
);
218 __raw_writel(ctl
, flashctl_base
+ AR5312_FLASHCTL1
);
219 ctl
= __raw_readl(flashctl_base
+ AR5312_FLASHCTL2
);
220 ctl
&= ~(AR5312_FLASHCTL_E
| AR5312_FLASHCTL_AC
);
221 __raw_writel(ctl
, flashctl_base
+ AR5312_FLASHCTL2
);
223 iounmap(flashctl_base
);
226 void __init
ar5312_init_devices(void)
228 struct ath25_boarddata
*config
;
232 /* Locate board/radio config data */
233 ath25_find_config(AR5312_FLASH_BASE
, AR5312_FLASH_SIZE
);
234 config
= ath25_board
.config
;
236 /* AR2313 has CPU minor rev. 10 */
237 if ((current_cpu_data
.processor_id
& 0xff) == 0x0a)
238 ath25_soc
= ATH25_SOC_AR2313
;
240 /* AR2312 shares the same Silicon ID as AR5312 */
241 else if (config
->flags
& BD_ISCASPER
)
242 ath25_soc
= ATH25_SOC_AR2312
;
244 /* Everything else is probably AR5312 or compatible */
246 ath25_soc
= ATH25_SOC_AR5312
;
248 platform_device_register(&ar5312_physmap_flash
);
251 case ATH25_SOC_AR5312
:
252 if (!ath25_board
.radio
)
255 if (!(config
->flags
& BD_WLAN0
))
258 ath25_add_wmac(0, AR5312_WLAN0_BASE
, AR5312_IRQ_WLAN0
);
260 case ATH25_SOC_AR2312
:
261 case ATH25_SOC_AR2313
:
262 if (!ath25_board
.radio
)
269 if (config
->flags
& BD_WLAN1
)
270 ath25_add_wmac(1, AR5312_WLAN1_BASE
, AR5312_IRQ_WLAN1
);
273 static void ar5312_restart(char *command
)
275 /* reset the system */
278 ar5312_rst_reg_write(AR5312_RESET
, AR5312_RESET_SYSTEM
);
282 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
283 * to determine the predevisor value.
285 static unsigned clockctl1_predivide_table
[4] __initdata
= { 1, 2, 4, 5 };
287 static unsigned __init
ar5312_cpu_frequency(void)
289 u32 scratch
, devid
, clock_ctl1
;
290 u32 predivide_mask
, multiplier_mask
, doubler_mask
;
291 unsigned predivide_shift
, multiplier_shift
;
292 unsigned predivide_select
, predivisor
, multiplier
;
294 /* Trust the bootrom's idea of cpu frequency. */
295 scratch
= ar5312_rst_reg_read(AR5312_SCRATCH
);
299 devid
= ar5312_rst_reg_read(AR5312_REV
);
300 devid
= (devid
& AR5312_REV_MAJ
) >> AR5312_REV_MAJ_S
;
301 if (devid
== AR5312_REV_MAJ_AR2313
) {
302 predivide_mask
= AR2313_CLOCKCTL1_PREDIVIDE_MASK
;
303 predivide_shift
= AR2313_CLOCKCTL1_PREDIVIDE_SHIFT
;
304 multiplier_mask
= AR2313_CLOCKCTL1_MULTIPLIER_MASK
;
305 multiplier_shift
= AR2313_CLOCKCTL1_MULTIPLIER_SHIFT
;
306 doubler_mask
= AR2313_CLOCKCTL1_DOUBLER_MASK
;
307 } else { /* AR5312 and AR2312 */
308 predivide_mask
= AR5312_CLOCKCTL1_PREDIVIDE_MASK
;
309 predivide_shift
= AR5312_CLOCKCTL1_PREDIVIDE_SHIFT
;
310 multiplier_mask
= AR5312_CLOCKCTL1_MULTIPLIER_MASK
;
311 multiplier_shift
= AR5312_CLOCKCTL1_MULTIPLIER_SHIFT
;
312 doubler_mask
= AR5312_CLOCKCTL1_DOUBLER_MASK
;
316 * Clocking is derived from a fixed 40MHz input clock.
318 * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
319 * sys_freq = cpu_freq / 4 (used for APB clock, serial,
320 * flash, Timer, Watchdog Timer)
322 * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
324 * So, for example, with a PLL multiplier of 5, we have
330 * We compute the CPU frequency, based on PLL settings.
333 clock_ctl1
= ar5312_rst_reg_read(AR5312_CLOCKCTL1
);
334 predivide_select
= (clock_ctl1
& predivide_mask
) >> predivide_shift
;
335 predivisor
= clockctl1_predivide_table
[predivide_select
];
336 multiplier
= (clock_ctl1
& multiplier_mask
) >> multiplier_shift
;
338 if (clock_ctl1
& doubler_mask
)
341 return (40000000 / predivisor
) * multiplier
;
344 static inline unsigned ar5312_sys_frequency(void)
346 return ar5312_cpu_frequency() / 4;
349 void __init
ar5312_plat_time_init(void)
351 mips_hpt_frequency
= ar5312_cpu_frequency() / 2;
354 void __init
ar5312_plat_mem_setup(void)
356 void __iomem
*sdram_base
;
357 u32 memsize
, memcfg
, bank0_ac
, bank1_ac
;
360 /* Detect memory size */
361 sdram_base
= ioremap(AR5312_SDRAMCTL_BASE
,
362 AR5312_SDRAMCTL_SIZE
);
363 memcfg
= __raw_readl(sdram_base
+ AR5312_MEM_CFG1
);
364 bank0_ac
= ATH25_REG_MS(memcfg
, AR5312_MEM_CFG1_AC0
);
365 bank1_ac
= ATH25_REG_MS(memcfg
, AR5312_MEM_CFG1_AC1
);
366 memsize
= (bank0_ac
? (1 << (bank0_ac
+ 1)) : 0) +
367 (bank1_ac
? (1 << (bank1_ac
+ 1)) : 0);
369 add_memory_region(0, memsize
, BOOT_MEM_RAM
);
372 ar5312_rst_base
= ioremap(AR5312_RST_BASE
, AR5312_RST_SIZE
);
374 devid
= ar5312_rst_reg_read(AR5312_REV
);
375 devid
>>= AR5312_REV_WMAC_MIN_S
;
376 devid
&= AR5312_REV_CHIP
;
377 ath25_board
.devid
= (u16
)devid
;
379 /* Clear any lingering AHB errors */
380 ar5312_rst_reg_read(AR5312_PROCADDR
);
381 ar5312_rst_reg_read(AR5312_DMAADDR
);
382 ar5312_rst_reg_write(AR5312_WDT_CTRL
, AR5312_WDT_CTRL_IGNORE
);
384 _machine_restart
= ar5312_restart
;
387 void __init
ar5312_arch_init(void)
389 unsigned irq
= irq_create_mapping(ar5312_misc_irq_domain
,
390 AR5312_MISC_IRQ_UART0
);
392 ath25_serial_setup(AR5312_UART0_BASE
, irq
, ar5312_sys_frequency());