2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
15 #include "pci-bcm63xx.h"
18 * swizzle 32bits data to return only the needed part
20 static int postprocess_read(u32 data
, int where
, unsigned int size
)
27 ret
= (data
>> ((where
& 3) << 3)) & 0xff;
30 ret
= (data
>> ((where
& 3) << 3)) & 0xffff;
39 static int preprocess_write(u32 orig_data
, u32 val
, int where
,
47 ret
= (orig_data
& ~(0xff << ((where
& 3) << 3))) |
48 (val
<< ((where
& 3) << 3));
51 ret
= (orig_data
& ~(0xffff << ((where
& 3) << 3))) |
52 (val
<< ((where
& 3) << 3));
62 * setup hardware for a configuration cycle with given parameters
64 static int bcm63xx_setup_cfg_access(int type
, unsigned int busn
,
65 unsigned int devfn
, int where
)
67 unsigned int slot
, func
, reg
;
70 slot
= PCI_SLOT(devfn
);
71 func
= PCI_FUNC(devfn
);
75 if (slot
> (MPI_L2PCFG_DEVNUM_MASK
>> MPI_L2PCFG_DEVNUM_SHIFT
))
78 if (func
> (MPI_L2PCFG_FUNC_MASK
>> MPI_L2PCFG_FUNC_SHIFT
))
81 if (reg
> (MPI_L2PCFG_REG_MASK
>> MPI_L2PCFG_REG_SHIFT
))
84 /* ok, setup config access */
85 val
= (reg
<< MPI_L2PCFG_REG_SHIFT
);
86 val
|= (func
<< MPI_L2PCFG_FUNC_SHIFT
);
87 val
|= (slot
<< MPI_L2PCFG_DEVNUM_SHIFT
);
88 val
|= MPI_L2PCFG_CFG_USEREG_MASK
;
89 val
|= MPI_L2PCFG_CFG_SEL_MASK
;
90 /* type 0 cycle for local bus, type 1 cycle for anything else */
92 /* FIXME: how to specify bus ??? */
93 val
|= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT
);
95 bcm_mpi_writel(val
, MPI_L2PCFG_REG
);
100 static int bcm63xx_do_cfg_read(int type
, unsigned int busn
,
101 unsigned int devfn
, int where
, int size
,
106 /* two phase cycle, first we write address, then read data at
107 * another location, caller already has a spinlock so no need
109 if (bcm63xx_setup_cfg_access(type
, busn
, devfn
, where
))
110 return PCIBIOS_DEVICE_NOT_FOUND
;
112 data
= le32_to_cpu(__raw_readl(pci_iospace_start
));
113 /* restore IO space normal behaviour */
114 bcm_mpi_writel(0, MPI_L2PCFG_REG
);
116 *val
= postprocess_read(data
, where
, size
);
118 return PCIBIOS_SUCCESSFUL
;
121 static int bcm63xx_do_cfg_write(int type
, unsigned int busn
,
122 unsigned int devfn
, int where
, int size
,
127 /* two phase cycle, first we write address, then write data to
128 * another location, caller already has a spinlock so no need
130 if (bcm63xx_setup_cfg_access(type
, busn
, devfn
, where
))
131 return PCIBIOS_DEVICE_NOT_FOUND
;
134 data
= le32_to_cpu(__raw_readl(pci_iospace_start
));
135 data
= preprocess_write(data
, val
, where
, size
);
137 __raw_writel(cpu_to_le32(data
), pci_iospace_start
);
139 /* no way to know the access is done, we have to wait */
141 /* restore IO space normal behaviour */
142 bcm_mpi_writel(0, MPI_L2PCFG_REG
);
144 return PCIBIOS_SUCCESSFUL
;
147 static int bcm63xx_pci_read(struct pci_bus
*bus
, unsigned int devfn
,
148 int where
, int size
, u32
*val
)
152 type
= bus
->parent
? 1 : 0;
154 if (type
== 0 && PCI_SLOT(devfn
) == CARDBUS_PCI_IDSEL
)
155 return PCIBIOS_DEVICE_NOT_FOUND
;
157 return bcm63xx_do_cfg_read(type
, bus
->number
, devfn
,
161 static int bcm63xx_pci_write(struct pci_bus
*bus
, unsigned int devfn
,
162 int where
, int size
, u32 val
)
166 type
= bus
->parent
? 1 : 0;
168 if (type
== 0 && PCI_SLOT(devfn
) == CARDBUS_PCI_IDSEL
)
169 return PCIBIOS_DEVICE_NOT_FOUND
;
171 return bcm63xx_do_cfg_write(type
, bus
->number
, devfn
,
175 struct pci_ops bcm63xx_pci_ops
= {
176 .read
= bcm63xx_pci_read
,
177 .write
= bcm63xx_pci_write
180 #ifdef CONFIG_CARDBUS
182 * emulate configuration read access on a cardbus bridge
184 #define FAKE_CB_BRIDGE_SLOT 0x1e
186 static int fake_cb_bridge_bus_number
= -1;
206 } fake_cb_bridge_regs
;
208 static int fake_cb_bridge_read(int where
, int size
, u32
*val
)
216 case (PCI_VENDOR_ID
>> 2):
217 case (PCI_CB_SUBSYSTEM_VENDOR_ID
>> 2):
218 /* create dummy vendor/device id from our cpu id */
219 data
= (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM
;
222 case (PCI_COMMAND
>> 2):
223 data
= (PCI_STATUS_DEVSEL_SLOW
<< 16);
224 data
|= fake_cb_bridge_regs
.pci_command
;
227 case (PCI_CLASS_REVISION
>> 2):
228 data
= (PCI_CLASS_BRIDGE_CARDBUS
<< 16);
231 case (PCI_CACHE_LINE_SIZE
>> 2):
232 data
= (PCI_HEADER_TYPE_CARDBUS
<< 16);
235 case (PCI_INTERRUPT_LINE
>> 2):
237 data
= (fake_cb_bridge_regs
.bridge_control
<< 16);
238 /* pin:intA line:0xff */
239 data
|= (0x1 << 8) | 0xff;
242 case (PCI_CB_PRIMARY_BUS
>> 2):
243 data
= (fake_cb_bridge_regs
.cb_latency
<< 24);
244 data
|= (fake_cb_bridge_regs
.subordinate_busn
<< 16);
245 data
|= (fake_cb_bridge_regs
.cardbus_busn
<< 8);
246 data
|= fake_cb_bridge_regs
.pci_busn
;
249 case (PCI_CB_MEMORY_BASE_0
>> 2):
250 data
= fake_cb_bridge_regs
.mem_base0
;
253 case (PCI_CB_MEMORY_LIMIT_0
>> 2):
254 data
= fake_cb_bridge_regs
.mem_limit0
;
257 case (PCI_CB_MEMORY_BASE_1
>> 2):
258 data
= fake_cb_bridge_regs
.mem_base1
;
261 case (PCI_CB_MEMORY_LIMIT_1
>> 2):
262 data
= fake_cb_bridge_regs
.mem_limit1
;
265 case (PCI_CB_IO_BASE_0
>> 2):
266 /* | 1 for 32bits io support */
267 data
= fake_cb_bridge_regs
.io_base0
| 0x1;
270 case (PCI_CB_IO_LIMIT_0
>> 2):
271 data
= fake_cb_bridge_regs
.io_limit0
;
274 case (PCI_CB_IO_BASE_1
>> 2):
275 /* | 1 for 32bits io support */
276 data
= fake_cb_bridge_regs
.io_base1
| 0x1;
279 case (PCI_CB_IO_LIMIT_1
>> 2):
280 data
= fake_cb_bridge_regs
.io_limit1
;
284 *val
= postprocess_read(data
, where
, size
);
285 return PCIBIOS_SUCCESSFUL
;
289 * emulate configuration write access on a cardbus bridge
291 static int fake_cb_bridge_write(int where
, int size
, u32 val
)
297 ret
= fake_cb_bridge_read((where
& ~0x3), 4, &data
);
298 if (ret
!= PCIBIOS_SUCCESSFUL
)
301 data
= preprocess_write(data
, val
, where
, size
);
305 case (PCI_COMMAND
>> 2):
306 fake_cb_bridge_regs
.pci_command
= (data
& 0xffff);
309 case (PCI_CB_PRIMARY_BUS
>> 2):
310 fake_cb_bridge_regs
.cb_latency
= (data
>> 24) & 0xff;
311 fake_cb_bridge_regs
.subordinate_busn
= (data
>> 16) & 0xff;
312 fake_cb_bridge_regs
.cardbus_busn
= (data
>> 8) & 0xff;
313 fake_cb_bridge_regs
.pci_busn
= data
& 0xff;
314 if (fake_cb_bridge_regs
.cardbus_busn
)
315 fake_cb_bridge_regs
.bus_assigned
= 1;
318 case (PCI_INTERRUPT_LINE
>> 2):
319 tmp
= (data
>> 16) & 0xffff;
320 /* disable memory prefetch support */
321 tmp
&= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
;
322 tmp
&= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1
;
323 fake_cb_bridge_regs
.bridge_control
= tmp
;
326 case (PCI_CB_MEMORY_BASE_0
>> 2):
327 fake_cb_bridge_regs
.mem_base0
= data
;
330 case (PCI_CB_MEMORY_LIMIT_0
>> 2):
331 fake_cb_bridge_regs
.mem_limit0
= data
;
334 case (PCI_CB_MEMORY_BASE_1
>> 2):
335 fake_cb_bridge_regs
.mem_base1
= data
;
338 case (PCI_CB_MEMORY_LIMIT_1
>> 2):
339 fake_cb_bridge_regs
.mem_limit1
= data
;
342 case (PCI_CB_IO_BASE_0
>> 2):
343 fake_cb_bridge_regs
.io_base0
= data
;
346 case (PCI_CB_IO_LIMIT_0
>> 2):
347 fake_cb_bridge_regs
.io_limit0
= data
;
350 case (PCI_CB_IO_BASE_1
>> 2):
351 fake_cb_bridge_regs
.io_base1
= data
;
354 case (PCI_CB_IO_LIMIT_1
>> 2):
355 fake_cb_bridge_regs
.io_limit1
= data
;
359 return PCIBIOS_SUCCESSFUL
;
362 static int bcm63xx_cb_read(struct pci_bus
*bus
, unsigned int devfn
,
363 int where
, int size
, u32
*val
)
365 /* snoop access to slot 0x1e on root bus, we fake a cardbus
366 * bridge at this location */
367 if (!bus
->parent
&& PCI_SLOT(devfn
) == FAKE_CB_BRIDGE_SLOT
) {
368 fake_cb_bridge_bus_number
= bus
->number
;
369 return fake_cb_bridge_read(where
, size
, val
);
372 /* a configuration cycle for the device behind the cardbus
373 * bridge is actually done as a type 0 cycle on the primary
374 * bus. This means that only one device can be on the cardbus
376 if (fake_cb_bridge_regs
.bus_assigned
&&
377 bus
->number
== fake_cb_bridge_regs
.cardbus_busn
&&
378 PCI_SLOT(devfn
) == 0)
379 return bcm63xx_do_cfg_read(0, 0,
380 PCI_DEVFN(CARDBUS_PCI_IDSEL
, 0),
383 return PCIBIOS_DEVICE_NOT_FOUND
;
386 static int bcm63xx_cb_write(struct pci_bus
*bus
, unsigned int devfn
,
387 int where
, int size
, u32 val
)
389 if (!bus
->parent
&& PCI_SLOT(devfn
) == FAKE_CB_BRIDGE_SLOT
) {
390 fake_cb_bridge_bus_number
= bus
->number
;
391 return fake_cb_bridge_write(where
, size
, val
);
394 if (fake_cb_bridge_regs
.bus_assigned
&&
395 bus
->number
== fake_cb_bridge_regs
.cardbus_busn
&&
396 PCI_SLOT(devfn
) == 0)
397 return bcm63xx_do_cfg_write(0, 0,
398 PCI_DEVFN(CARDBUS_PCI_IDSEL
, 0),
401 return PCIBIOS_DEVICE_NOT_FOUND
;
404 struct pci_ops bcm63xx_cb_ops
= {
405 .read
= bcm63xx_cb_read
,
406 .write
= bcm63xx_cb_write
,
410 * only one IO window, so it cannot be shared by PCI and cardbus, use
411 * fixup to choose and detect unhandled configuration
413 static void bcm63xx_fixup(struct pci_dev
*dev
)
415 static int io_window
= -1;
416 int i
, found
, new_io_window
;
419 /* look for any io resource */
421 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
422 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
) {
431 /* skip our fake bus with only cardbus bridge on it */
432 if (dev
->bus
->number
== fake_cb_bridge_bus_number
)
435 /* find on which bus the device is */
436 if (fake_cb_bridge_regs
.bus_assigned
&&
437 dev
->bus
->number
== fake_cb_bridge_regs
.cardbus_busn
&&
438 PCI_SLOT(dev
->devfn
) == 0)
443 if (new_io_window
== io_window
)
446 if (io_window
!= -1) {
447 printk(KERN_ERR
"bcm63xx: both PCI and cardbus devices "
448 "need IO, which hardware cannot do\n");
452 printk(KERN_INFO
"bcm63xx: PCI IO window assigned to %s\n",
453 (new_io_window
== 0) ? "PCI" : "cardbus");
455 val
= bcm_mpi_readl(MPI_L2PIOREMAP_REG
);
457 val
|= MPI_L2PREMAP_IS_CARDBUS_MASK
;
459 val
&= ~MPI_L2PREMAP_IS_CARDBUS_MASK
;
460 bcm_mpi_writel(val
, MPI_L2PIOREMAP_REG
);
462 io_window
= new_io_window
;
465 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID
, PCI_ANY_ID
, bcm63xx_fixup
);
468 static int bcm63xx_pcie_can_access(struct pci_bus
*bus
, int devfn
)
470 switch (bus
->number
) {
471 case PCIE_BUS_BRIDGE
:
472 return PCI_SLOT(devfn
) == 0;
473 case PCIE_BUS_DEVICE
:
474 if (PCI_SLOT(devfn
) == 0)
475 return bcm_pcie_readl(PCIE_DLSTATUS_REG
)
476 & DLSTATUS_PHYLINKUP
;
477 /* else, fall through */
483 static int bcm63xx_pcie_read(struct pci_bus
*bus
, unsigned int devfn
,
484 int where
, int size
, u32
*val
)
487 u32 reg
= where
& ~3;
489 if (!bcm63xx_pcie_can_access(bus
, devfn
))
490 return PCIBIOS_DEVICE_NOT_FOUND
;
492 if (bus
->number
== PCIE_BUS_DEVICE
)
493 reg
+= PCIE_DEVICE_OFFSET
;
495 data
= bcm_pcie_readl(reg
);
497 *val
= postprocess_read(data
, where
, size
);
499 return PCIBIOS_SUCCESSFUL
;
503 static int bcm63xx_pcie_write(struct pci_bus
*bus
, unsigned int devfn
,
504 int where
, int size
, u32 val
)
507 u32 reg
= where
& ~3;
509 if (!bcm63xx_pcie_can_access(bus
, devfn
))
510 return PCIBIOS_DEVICE_NOT_FOUND
;
512 if (bus
->number
== PCIE_BUS_DEVICE
)
513 reg
+= PCIE_DEVICE_OFFSET
;
516 data
= bcm_pcie_readl(reg
);
518 data
= preprocess_write(data
, val
, where
, size
);
519 bcm_pcie_writel(data
, reg
);
521 return PCIBIOS_SUCCESSFUL
;
525 struct pci_ops bcm63xx_pcie_ops
= {
526 .read
= bcm63xx_pcie_read
,
527 .write
= bcm63xx_pcie_write