arch/mips/pci/pci-ar71xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Atheros AR71xx PCI host controller driver
   4  *
   5  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros' 2.6.15 BSP
   9  */
  10
  11 #include <linux/resource.h>
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/bitops.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_regs.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <asm/mach-ath79/ar71xx_regs.h>
  22 #include <asm/mach-ath79/ath79.h>
  23
  24 #define AR71XX_PCI_REG_CRP_AD_CBE       0x00
  25 #define AR71XX_PCI_REG_CRP_WRDATA       0x04
  26 #define AR71XX_PCI_REG_CRP_RDDATA       0x08
  27 #define AR71XX_PCI_REG_CFG_AD           0x0c
  28 #define AR71XX_PCI_REG_CFG_CBE          0x10
  29 #define AR71XX_PCI_REG_CFG_WRDATA       0x14
  30 #define AR71XX_PCI_REG_CFG_RDDATA       0x18
  31 #define AR71XX_PCI_REG_PCI_ERR          0x1c
  32 #define AR71XX_PCI_REG_PCI_ERR_ADDR     0x20
  33 #define AR71XX_PCI_REG_AHB_ERR          0x24
  34 #define AR71XX_PCI_REG_AHB_ERR_ADDR     0x28
  35
  36 #define AR71XX_PCI_CRP_CMD_WRITE        0x00010000
  37 #define AR71XX_PCI_CRP_CMD_READ         0x00000000
  38 #define AR71XX_PCI_CFG_CMD_READ         0x0000000a
  39 #define AR71XX_PCI_CFG_CMD_WRITE        0x0000000b
  40
  41 #define AR71XX_PCI_INT_CORE             BIT(4)
  42 #define AR71XX_PCI_INT_DEV2             BIT(2)
  43 #define AR71XX_PCI_INT_DEV1             BIT(1)
  44 #define AR71XX_PCI_INT_DEV0             BIT(0)
  45
  46 #define AR71XX_PCI_IRQ_COUNT            5
  47
  48 struct ar71xx_pci_controller {
  49         void __iomem *cfg_base;
  50         int irq;
  51         int irq_base;
  52         struct pci_controller pci_ctrl;
  53         struct resource io_res;
  54         struct resource mem_res;
  55 };
  56
  57 /* Byte lane enable bits */
  58 static const u8 ar71xx_pci_ble_table[4][4] = {
  59         {0x0, 0xf, 0xf, 0xf},
  60         {0xe, 0xd, 0xb, 0x7},
  61         {0xc, 0xf, 0x3, 0xf},
  62         {0xf, 0xf, 0xf, 0xf},
  63 };
  64
  65 static const u32 ar71xx_pci_read_mask[8] = {
  66         0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
  67 };
  68
  69 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  70 {
  71         u32 t;
  72
  73         t = ar71xx_pci_ble_table[size & 3][where & 3];
  74         BUG_ON(t == 0xf);
  75         t <<= (local) ? 20 : 4;
  76
  77         return t;
  78 }
  79
  80 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
  81                                       int where)
  82 {
  83         u32 ret;
  84
  85         if (!bus->number) {
  86                 /* type 0 */
  87                 ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
  88                       (where & ~3);
  89         } else {
  90                 /* type 1 */
  91                 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
  92                       (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
  93         }
  94
  95         return ret;
  96 }
  97
  98 static inline struct ar71xx_pci_controller *
  99 pci_bus_to_ar71xx_controller(struct pci_bus *bus)
 100 {
 101         struct pci_controller *hose;
 102
 103         hose = (struct pci_controller *) bus->sysdata;
 104         return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
 105 }
 106
 107 static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
 108 {
 109         void __iomem *base = apc->cfg_base;
 110         u32 pci_err;
 111         u32 ahb_err;
 112
 113         pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
 114         if (pci_err) {
 115                 if (!quiet) {
 116                         u32 addr;
 117
 118                         addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
 119                         pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
 120                                 "PCI", pci_err, addr);
 121                 }
 122
 123                 /* clear PCI error status */
 124                 __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
 125         }
 126
 127         ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
 128         if (ahb_err) {
 129                 if (!quiet) {
 130                         u32 addr;
 131
 132                         addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
 133                         pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
 134                                 "AHB", ahb_err, addr);
 135                 }
 136
 137                 /* clear AHB error status */
 138                 __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
 139         }
 140
 141         return !!(ahb_err | pci_err);
 142 }
 143
 144 static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
 145                                           int where, int size, u32 value)
 146 {
 147         void __iomem *base = apc->cfg_base;
 148         u32 ad_cbe;
 149
 150         value = value << (8 * (where & 3));
 151
 152         ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
 153         ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
 154
 155         __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
 156         __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
 157 }
 158
 159 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
 160                                          unsigned int devfn,
 161                                          int where, int size, u32 cmd)
 162 {
 163         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 164         void __iomem *base = apc->cfg_base;
 165         u32 addr;
 166
 167         addr = ar71xx_pci_bus_addr(bus, devfn, where);
 168
 169         __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
 170         __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
 171                      base + AR71XX_PCI_REG_CFG_CBE);
 172
 173         return ar71xx_pci_check_error(apc, 1);
 174 }
 175
 176 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 177                                   int where, int size, u32 *value)
 178 {
 179         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 180         void __iomem *base = apc->cfg_base;
 181         u32 data;
 182         int err;
 183         int ret;
 184
 185         ret = PCIBIOS_SUCCESSFUL;
 186         data = ~0;
 187
 188         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 189                                      AR71XX_PCI_CFG_CMD_READ);
 190         if (err)
 191                 ret = PCIBIOS_DEVICE_NOT_FOUND;
 192         else
 193                 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
 194
 195         *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
 196
 197         return ret;
 198 }
 199
 200 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 201                                    int where, int size, u32 value)
 202 {
 203         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 204         void __iomem *base = apc->cfg_base;
 205         int err;
 206         int ret;
 207
 208         value = value << (8 * (where & 3));
 209         ret = PCIBIOS_SUCCESSFUL;
 210
 211         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 212                                      AR71XX_PCI_CFG_CMD_WRITE);
 213         if (err)
 214                 ret = PCIBIOS_DEVICE_NOT_FOUND;
 215         else
 216                 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
 217
 218         return ret;
 219 }
 220
 221 static struct pci_ops ar71xx_pci_ops = {
 222         .read   = ar71xx_pci_read_config,
 223         .write  = ar71xx_pci_write_config,
 224 };
 225
 226 static void ar71xx_pci_irq_handler(struct irq_desc *desc)
 227 {
 228         struct ar71xx_pci_controller *apc;
 229         void __iomem *base = ath79_reset_base;
 230         u32 pending;
 231
 232         apc = irq_desc_get_handler_data(desc);
 233
 234         pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
 235                   __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 236
 237         if (pending & AR71XX_PCI_INT_DEV0)
 238                 generic_handle_irq(apc->irq_base + 0);
 239
 240         else if (pending & AR71XX_PCI_INT_DEV1)
 241                 generic_handle_irq(apc->irq_base + 1);
 242
 243         else if (pending & AR71XX_PCI_INT_DEV2)
 244                 generic_handle_irq(apc->irq_base + 2);
 245
 246         else if (pending & AR71XX_PCI_INT_CORE)
 247                 generic_handle_irq(apc->irq_base + 4);
 248
 249         else
 250                 spurious_interrupt();
 251 }
 252
 253 static void ar71xx_pci_irq_unmask(struct irq_data *d)
 254 {
 255         struct ar71xx_pci_controller *apc;
 256         unsigned int irq;
 257         void __iomem *base = ath79_reset_base;
 258         u32 t;
 259
 260         apc = irq_data_get_irq_chip_data(d);
 261         irq = d->irq - apc->irq_base;
 262
 263         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 264         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 265
 266         /* flush write */
 267         __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 268 }
 269
 270 static void ar71xx_pci_irq_mask(struct irq_data *d)
 271 {
 272         struct ar71xx_pci_controller *apc;
 273         unsigned int irq;
 274         void __iomem *base = ath79_reset_base;
 275         u32 t;
 276
 277         apc = irq_data_get_irq_chip_data(d);
 278         irq = d->irq - apc->irq_base;
 279
 280         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 281         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 282
 283         /* flush write */
 284         __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 285 }
 286
 287 static struct irq_chip ar71xx_pci_irq_chip = {
 288         .name           = "AR71XX PCI",
 289         .irq_mask       = ar71xx_pci_irq_mask,
 290         .irq_unmask     = ar71xx_pci_irq_unmask,
 291         .irq_mask_ack   = ar71xx_pci_irq_mask,
 292 };
 293
 294 static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 295 {
 296         void __iomem *base = ath79_reset_base;
 297         int i;
 298
 299         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 300         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 301
 302         BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
 303
 304         apc->irq_base = ATH79_PCI_IRQ_BASE;
 305         for (i = apc->irq_base;
 306              i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
 307                 irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 308                                          handle_level_irq);
 309                 irq_set_chip_data(i, apc);
 310         }
 311
 312         irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
 313                                          apc);
 314 }
 315
 316 static void ar71xx_pci_reset(void)
 317 {
 318         ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 319         mdelay(100);
 320
 321         ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 322         mdelay(100);
 323
 324         ath79_ddr_set_pci_windows();
 325         mdelay(100);
 326 }
 327
 328 static int ar71xx_pci_probe(struct platform_device *pdev)
 329 {
 330         struct ar71xx_pci_controller *apc;
 331         struct resource *res;
 332         u32 t;
 333
 334         apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
 335                            GFP_KERNEL);
 336         if (!apc)
 337                 return -ENOMEM;
 338
 339         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
 340         apc->cfg_base = devm_ioremap_resource(&pdev->dev, res);
 341         if (IS_ERR(apc->cfg_base))
 342                 return PTR_ERR(apc->cfg_base);
 343
 344         apc->irq = platform_get_irq(pdev, 0);
 345         if (apc->irq < 0)
 346                 return -EINVAL;
 347
 348         res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
 349         if (!res)
 350                 return -EINVAL;
 351
 352         apc->io_res.parent = res;
 353         apc->io_res.name = "PCI IO space";
 354         apc->io_res.start = res->start;
 355         apc->io_res.end = res->end;
 356         apc->io_res.flags = IORESOURCE_IO;
 357
 358         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
 359         if (!res)
 360                 return -EINVAL;
 361
 362         apc->mem_res.parent = res;
 363         apc->mem_res.name = "PCI memory space";
 364         apc->mem_res.start = res->start;
 365         apc->mem_res.end = res->end;
 366         apc->mem_res.flags = IORESOURCE_MEM;
 367
 368         ar71xx_pci_reset();
 369
 370         /* setup COMMAND register */
 371         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 372           | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 373         ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
 374
 375         /* clear bus errors */
 376         ar71xx_pci_check_error(apc, 1);
 377
 378         ar71xx_pci_irq_init(apc);
 379
 380         apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 381         apc->pci_ctrl.mem_resource = &apc->mem_res;
 382         apc->pci_ctrl.io_resource = &apc->io_res;
 383
 384         register_pci_controller(&apc->pci_ctrl);
 385
 386         return 0;
 387 }
 388
 389 static struct platform_driver ar71xx_pci_driver = {
 390         .probe = ar71xx_pci_probe,
 391         .driver = {
 392                 .name = "ar71xx-pci",
 393         },
 394 };
 395
 396 static int __init ar71xx_pci_init(void)
 397 {
 398         return platform_driver_register(&ar71xx_pci_driver);
 399 }
 400
 401 postcore_initcall(ar71xx_pci_init);