arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * MPC8641 HPCN Device Tree Source
   4  *
   5  * Copyright 2006 Freescale Semiconductor Inc.
   6  */
   7
   8 /include/ "mpc8641si-pre.dtsi"
   9
  10 / {
  11         model = "MPC8641HPCN";
  12         compatible = "fsl,mpc8641hpcn";
  13
  14         memory {
  15                 device_type = "memory";
  16                 reg = <0x00000000 0x40000000>;  // 1G at 0x0
  17         };
  18
  19         lbc: localbus@ffe05000 {
  20                 reg = <0xffe05000 0x1000>;
  21
  22                 ranges = <0 0 0xef800000 0x00800000
  23                           2 0 0xffdf8000 0x00008000
  24                           3 0 0xffdf0000 0x00008000>;
  25
  26                 flash@0,0 {
  27                         compatible = "cfi-flash";
  28                         reg = <0 0 0x00800000>;
  29                         bank-width = <2>;
  30                         device-width = <2>;
  31                         #address-cells = <1>;
  32                         #size-cells = <1>;
  33                         partition@0 {
  34                                 label = "kernel";
  35                                 reg = <0x00000000 0x00300000>;
  36                         };
  37                         partition@300000 {
  38                                 label = "firmware b";
  39                                 reg = <0x00300000 0x00100000>;
  40                                 read-only;
  41                         };
  42                         partition@400000 {
  43                                 label = "fs";
  44                                 reg = <0x00400000 0x00300000>;
  45                         };
  46                         partition@700000 {
  47                                 label = "firmware a";
  48                                 reg = <0x00700000 0x00100000>;
  49                                 read-only;
  50                         };
  51                 };
  52         };
  53
  54         soc: soc8641@ffe00000 {
  55                 ranges = <0x00000000 0xffe00000 0x00100000>;
  56
  57                 enet0: ethernet@24000 {
  58                         tbi-handle = <&tbi0>;
  59                         phy-handle = <&phy0>;
  60                         phy-connection-type = "rgmii-id";
  61                 };
  62
  63                 mdio@24520 {
  64                         phy0: ethernet-phy@0 {
  65                                 interrupts = <10 1 0 0>;
  66                                 reg = <0>;
  67                         };
  68                         phy1: ethernet-phy@1 {
  69                                 interrupts = <10 1 0 0>;
  70                                 reg = <1>;
  71                         };
  72                         phy2: ethernet-phy@2 {
  73                                 interrupts = <10 1 0 0>;
  74                                 reg = <2>;
  75                         };
  76                         phy3: ethernet-phy@3 {
  77                                 interrupts = <10 1 0 0>;
  78                                 reg = <3>;
  79                         };
  80                         tbi0: tbi-phy@11 {
  81                                 reg = <0x11>;
  82                                 device_type = "tbi-phy";
  83                         };
  84                 };
  85
  86                 enet1: ethernet@25000 {
  87                         tbi-handle = <&tbi1>;
  88                         phy-handle = <&phy1>;
  89                         phy-connection-type = "rgmii-id";
  90                 };
  91
  92                 mdio@25520 {
  93                         tbi1: tbi-phy@11 {
  94                                 reg = <0x11>;
  95                                 device_type = "tbi-phy";
  96                         };
  97                 };
  98
  99                 enet2: ethernet@26000 {
 100                         tbi-handle = <&tbi2>;
 101                         phy-handle = <&phy2>;
 102                         phy-connection-type = "rgmii-id";
 103                 };
 104
 105                 mdio@26520 {
 106                         tbi2: tbi-phy@11 {
 107                                 reg = <0x11>;
 108                                 device_type = "tbi-phy";
 109                         };
 110                 };
 111
 112                 enet3: ethernet@27000 {
 113                         tbi-handle = <&tbi3>;
 114                         phy-handle = <&phy3>;
 115                         phy-connection-type = "rgmii-id";
 116                 };
 117
 118                 mdio@27520 {
 119                         tbi3: tbi-phy@11 {
 120                                 reg = <0x11>;
 121                                 device_type = "tbi-phy";
 122                         };
 123                 };
 124
 125                 rmu: rmu@d3000 {
 126                         #address-cells = <1>;
 127                         #size-cells = <1>;
 128                         compatible = "fsl,srio-rmu";
 129                         reg = <0xd3000 0x500>;
 130                         ranges = <0x0 0xd3000 0x500>;
 131
 132                         message-unit@0 {
 133                                 compatible = "fsl,srio-msg-unit";
 134                                 reg = <0x0 0x100>;
 135                                 interrupts = <
 136                                         53 2 0 0  /* msg1_tx_irq */
 137                                         54 2 0 0>;/* msg1_rx_irq */
 138                         };
 139                         message-unit@100 {
 140                                 compatible = "fsl,srio-msg-unit";
 141                                 reg = <0x100 0x100>;
 142                                 interrupts = <
 143                                         55 2 0 0  /* msg2_tx_irq */
 144                                         56 2 0 0>;/* msg2_rx_irq */
 145                         };
 146                         doorbell-unit@400 {
 147                                 compatible = "fsl,srio-dbell-unit";
 148                                 reg = <0x400 0x80>;
 149                                 interrupts = <
 150                                         49 2 0 0  /* bell_outb_irq */
 151                                         50 2 0 0>;/* bell_inb_irq */
 152                         };
 153                         port-write-unit@4e0 {
 154                                 compatible = "fsl,srio-port-write-unit";
 155                                 reg = <0x4e0 0x20>;
 156                                 interrupts = <48 2 0 0>;
 157                         };
 158                 };
 159         };
 160
 161         pci0: pcie@ffe08000 {
 162                 reg = <0xffe08000 0x1000>;
 163                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 164                           0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
 165                 interrupt-map-mask = <0xff00 0 0 7>;
 166                 interrupt-map = <
 167                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 168                         0x8800 0 0 1 &mpic 2 1 0 0
 169                         0x8800 0 0 2 &mpic 3 1 0 0
 170                         0x8800 0 0 3 &mpic 4 1 0 0
 171                         0x8800 0 0 4 &mpic 1 1 0 0
 172
 173                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 174                         0x8900 0 0 1 &mpic 2 1 0 0
 175                         0x8900 0 0 2 &mpic 3 1 0 0
 176                         0x8900 0 0 3 &mpic 4 1 0 0
 177                         0x8900 0 0 4 &mpic 1 1 0 0
 178
 179                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 180                         0x8a00 0 0 1 &mpic 2 1 0 0
 181                         0x8a00 0 0 2 &mpic 3 1 0 0
 182                         0x8a00 0 0 3 &mpic 4 1 0 0
 183                         0x8a00 0 0 4 &mpic 1 1 0 0
 184
 185                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 186                         0x8b00 0 0 1 &mpic 2 1 0 0
 187                         0x8b00 0 0 2 &mpic 3 1 0 0
 188                         0x8b00 0 0 3 &mpic 4 1 0 0
 189                         0x8b00 0 0 4 &mpic 1 1 0 0
 190
 191                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 192                         0x8c00 0 0 1 &mpic 2 1 0 0
 193                         0x8c00 0 0 2 &mpic 3 1 0 0
 194                         0x8c00 0 0 3 &mpic 4 1 0 0
 195                         0x8c00 0 0 4 &mpic 1 1 0 0
 196
 197                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 198                         0x8d00 0 0 1 &mpic 2 1 0 0
 199                         0x8d00 0 0 2 &mpic 3 1 0 0
 200                         0x8d00 0 0 3 &mpic 4 1 0 0
 201                         0x8d00 0 0 4 &mpic 1 1 0 0
 202
 203                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 204                         0x8e00 0 0 1 &mpic 2 1 0 0
 205                         0x8e00 0 0 2 &mpic 3 1 0 0
 206                         0x8e00 0 0 3 &mpic 4 1 0 0
 207                         0x8e00 0 0 4 &mpic 1 1 0 0
 208
 209                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 210                         0x8f00 0 0 1 &mpic 2 1 0 0
 211                         0x8f00 0 0 2 &mpic 3 1 0 0
 212                         0x8f00 0 0 3 &mpic 4 1 0 0
 213                         0x8f00 0 0 4 &mpic 1 1 0 0
 214
 215                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 216                         0x9000 0 0 1 &mpic 3 1 0 0
 217                         0x9000 0 0 2 &mpic 4 1 0 0
 218                         0x9000 0 0 3 &mpic 1 1 0 0
 219                         0x9000 0 0 4 &mpic 2 1 0 0
 220
 221                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 222                         0x9100 0 0 1 &mpic 3 1 0 0
 223                         0x9100 0 0 2 &mpic 4 1 0 0
 224                         0x9100 0 0 3 &mpic 1 1 0 0
 225                         0x9100 0 0 4 &mpic 2 1 0 0
 226
 227                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 228                         0x9200 0 0 1 &mpic 3 1 0 0
 229                         0x9200 0 0 2 &mpic 4 1 0 0
 230                         0x9200 0 0 3 &mpic 1 1 0 0
 231                         0x9200 0 0 4 &mpic 2 1 0 0
 232
 233                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 234                         0x9300 0 0 1 &mpic 3 1 0 0
 235                         0x9300 0 0 2 &mpic 4 1 0 0
 236                         0x9300 0 0 3 &mpic 1 1 0 0
 237                         0x9300 0 0 4 &mpic 2 1 0 0
 238
 239                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 240                         0x9400 0 0 1 &mpic 3 1 0 0
 241                         0x9400 0 0 2 &mpic 4 1 0 0
 242                         0x9400 0 0 3 &mpic 1 1 0 0
 243                         0x9400 0 0 4 &mpic 2 1 0 0
 244
 245                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 246                         0x9500 0 0 1 &mpic 3 1 0 0
 247                         0x9500 0 0 2 &mpic 4 1 0 0
 248                         0x9500 0 0 3 &mpic 1 1 0 0
 249                         0x9500 0 0 4 &mpic 2 1 0 0
 250
 251                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 252                         0x9600 0 0 1 &mpic 3 1 0 0
 253                         0x9600 0 0 2 &mpic 4 1 0 0
 254                         0x9600 0 0 3 &mpic 1 1 0 0
 255                         0x9600 0 0 4 &mpic 2 1 0 0
 256
 257                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 258                         0x9700 0 0 1 &mpic 3 1 0 0
 259                         0x9700 0 0 2 &mpic 4 1 0 0
 260                         0x9700 0 0 3 &mpic 1 1 0 0
 261                         0x9700 0 0 4 &mpic 2 1 0 0
 262
 263                         // IDSEL 0x1c  USB
 264                         0xe000 0 0 1 &i8259 12 2
 265                         0xe100 0 0 2 &i8259 9 2
 266                         0xe200 0 0 3 &i8259 10 2
 267                         0xe300 0 0 4 &i8259 11 2
 268
 269                         // IDSEL 0x1d  Audio
 270                         0xe800 0 0 1 &i8259 6 2
 271
 272                         // IDSEL 0x1e Legacy
 273                         0xf000 0 0 1 &i8259 7 2
 274                         0xf100 0 0 1 &i8259 7 2
 275
 276                         // IDSEL 0x1f IDE/SATA
 277                         0xf800 0 0 1 &i8259 14 2
 278                         0xf900 0 0 1 &i8259 5 2
 279                         >;
 280
 281                 pcie@0 {
 282                         ranges = <0x02000000 0x0 0x80000000
 283                                   0x02000000 0x0 0x80000000
 284                                   0x0 0x20000000
 285
 286                                   0x01000000 0x0 0x00000000
 287                                   0x01000000 0x0 0x00000000
 288                                   0x0 0x00010000>;
 289                         uli1575@0 {
 290                                 reg = <0 0 0 0 0>;
 291                                 #size-cells = <2>;
 292                                 #address-cells = <3>;
 293                                 ranges = <0x02000000 0x0 0x80000000
 294                                           0x02000000 0x0 0x80000000
 295                                           0x0 0x20000000
 296                                           0x01000000 0x0 0x00000000
 297                                           0x01000000 0x0 0x00000000
 298                                           0x0 0x00010000>;
 299                                 isa@1e {
 300                                         device_type = "isa";
 301                                         #size-cells = <1>;
 302                                         #address-cells = <2>;
 303                                         reg = <0xf000 0 0 0 0>;
 304                                         ranges = <1 0 0x01000000 0 0
 305                                                   0x00001000>;
 306                                         interrupt-parent = <&i8259>;
 307
 308                                         i8259: interrupt-controller@20 {
 309                                                 reg = <1 0x20 2
 310                                                        1 0xa0 2
 311                                                        1 0x4d0 2>;
 312                                                 interrupt-controller;
 313                                                 device_type = "interrupt-controller";
 314                                                 #address-cells = <0>;
 315                                                 #interrupt-cells = <2>;
 316                                                 compatible = "chrp,iic";
 317                                                 interrupts = <9 2 0 0>;
 318                                         };
 319
 320                                         i8042@60 {
 321                                                 #size-cells = <0>;
 322                                                 #address-cells = <1>;
 323                                                 reg = <1 0x60 1 1 0x64 1>;
 324                                                 interrupts = <1 3 12 3>;
 325                                                 interrupt-parent = <&i8259>;
 326
 327                                                 keyboard@0 {
 328                                                         reg = <0>;
 329                                                         compatible = "pnpPNP,303";
 330                                                 };
 331
 332                                                 mouse@1 {
 333                                                         reg = <1>;
 334                                                         compatible = "pnpPNP,f03";
 335                                                 };
 336                                         };
 337
 338                                         rtc@70 {
 339                                                 compatible =
 340                                                         "pnpPNP,b00";
 341                                                 reg = <1 0x70 2>;
 342                                         };
 343
 344                                         gpio@400 {
 345                                                 reg = <1 0x400 0x80>;
 346                                         };
 347                                 };
 348                         };
 349                 };
 350
 351         };
 352
 353         pci1: pcie@ffe09000 {
 354                 reg = <0xffe09000 0x1000>;
 355                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 356                           0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
 357
 358                 pcie@0 {
 359                         ranges = <0x02000000 0x0 0xa0000000
 360                                   0x02000000 0x0 0xa0000000
 361                                   0x0 0x20000000
 362
 363                                   0x01000000 0x0 0x00000000
 364                                   0x01000000 0x0 0x00000000
 365                                   0x0 0x00010000>;
 366                 };
 367         };
 368 /*
 369  * Only one of Rapid IO or PCI can be present due to HW limitations and
 370  * due to the fact that the 2 now share address space in the new memory
 371  * map.  The most likely case is that we have PCI, so comment out the
 372  * rapidio node.  Leave it here for reference.
 373
 374         rapidio@ffec0000 {
 375                 reg = <0xffec0000 0x11000>;
 376                 compatible = "fsl,srio";
 377                 interrupts = <48 2 0 0>;
 378                 #address-cells = <2>;
 379                 #size-cells = <2>;
 380                 fsl,srio-rmu-handle = <&rmu>;
 381                 ranges;
 382
 383                 port1 {
 384                         #address-cells = <2>;
 385                         #size-cells = <2>;
 386                         cell-index = <1>;
 387                         ranges = <0 0 0x80000000 0 0x20000000>;
 388                 };
 389         };
 390 */
 391
 392 };
 393
 394 /include/ "mpc8641si-post.dtsi"