1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low level CPU setup functions.
4 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
7 #include <asm/processor.h>
9 #include <asm/cputable.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/asm-offsets.h>
12 #include <asm/cache.h>
14 #include <asm/feature-fixups.h>
16 _GLOBAL(__setup_cpu_603)
20 mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
21 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
24 bl __init_fpu_registers
25 END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
26 bl setup_common_caches
29 _GLOBAL(__setup_cpu_604)
31 bl setup_common_caches
35 _GLOBAL(__setup_cpu_750)
37 bl __init_fpu_registers
38 bl setup_common_caches
39 bl setup_750_7400_hid0
42 _GLOBAL(__setup_cpu_750cx)
44 bl __init_fpu_registers
45 bl setup_common_caches
46 bl setup_750_7400_hid0
50 _GLOBAL(__setup_cpu_750fx)
52 bl __init_fpu_registers
53 bl setup_common_caches
54 bl setup_750_7400_hid0
58 _GLOBAL(__setup_cpu_7400)
60 bl __init_fpu_registers
61 bl setup_7400_workarounds
62 bl setup_common_caches
63 bl setup_750_7400_hid0
66 _GLOBAL(__setup_cpu_7410)
68 bl __init_fpu_registers
69 bl setup_7410_workarounds
70 bl setup_common_caches
71 bl setup_750_7400_hid0
76 _GLOBAL(__setup_cpu_745x)
78 bl setup_common_caches
79 bl setup_745x_specifics
83 /* Enable caches for 603's, 604, 750 & 7400 */
87 ori r11,r11,HID0_ICE|HID0_DCE
89 bne 1f /* don't invalidate the D-cache */
90 ori r8,r8,HID0_DCI /* unless it wasn't enabled */
92 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
94 mtspr SPRN_HID0,r11 /* enable caches */
99 /* 604, 604e, 604ev, ...
100 * Enable superscalar execution & branch history table
104 ori r11,r11,HID0_SIED|HID0_BHTE
107 mtspr SPRN_HID0,r8 /* flush branch target address cache */
108 sync /* on 604e/604r */
114 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
115 * erratas we work around here.
116 * Moto MPC710CE.pdf describes them, those are errata
118 * Note that we assume the firmware didn't choose to
119 * apply other workarounds (there are other ones documented
120 * in the .pdf). It appear that Apple firmware only works
121 * around #3 and with the same fix we use. We may want to
122 * check if the CPU is using 60x bus mode in which case
123 * the workaround for errata #4 is useless. Also, we may
124 * want to explicitly clear HID0_NOPDST as this is not
125 * needed once we have applied workaround #5 (though it's
126 * not set by Apple's firmware at least).
128 setup_7400_workarounds:
134 setup_7410_workarounds:
140 mfspr r11,SPRN_MSSSR0
141 /* Errata #3: Set L1OPQ_SIZE to 0x10 */
144 /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
146 /* Errata #5: Set DRLT_SIZE to 0x01 */
150 mtspr SPRN_MSSSR0,r11
156 * Enable Store Gathering (SGE), Address Broadcast (ABE),
157 * Branch History Table (BHTE), Branch Target ICache (BTIC)
158 * Dynamic Power Management (DPM), Speculative (SPD)
159 * Clear Instruction cache throttling (ICTC)
163 ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
164 oris r11,r11,HID0_DPM@h
166 xori r11,r11,HID0_BTIC
167 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
169 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
170 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
172 andc r11,r11,r3 /* clear SPD: enable speculative */
174 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
182 * Looks like we have to disable NAP feature for some PLL settings...
183 * (waiting for confirmation)
187 rlwinm r10,r10,4,28,31
191 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
192 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
194 lwz r6,CPU_SPEC_FEATURES(r4)
195 li r7,CPU_FTR_CAN_NAP
197 stw r6,CPU_SPEC_FEATURES(r4)
206 * Enable Store Gathering (SGE), Branch Folding (FOLD)
207 * Branch History Table (BHTE), Branch Target ICache (BTIC)
208 * Dynamic Power Management (DPM), Speculative (SPD)
209 * Ensure our data cache instructions really operate.
210 * Timebase has to be running or we wouldn't have made it here,
211 * just ensure we don't disable it.
212 * Clear Instruction cache throttling (ICTC)
213 * Enable L2 HW prefetch
215 setup_745x_specifics:
216 /* We check for the presence of an L3 cache setup by
217 * the firmware. If any, we disable NAP capability as
218 * it's known to be bogus on rev 2.1 and earlier
222 andis. r11,r11,L3CR_L3E@h
224 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
225 lwz r6,CPU_SPEC_FEATURES(r4)
226 andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
228 li r7,CPU_FTR_CAN_NAP
230 stw r6,CPU_SPEC_FEATURES(r4)
234 /* All of the bits we have to set.....
236 ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
237 ori r11,r11,HID0_LRSTK | HID0_BTIC
238 oris r11,r11,HID0_DPM@h
239 BEGIN_MMU_FTR_SECTION
240 oris r11,r11,HID0_HIGH_BAT@h
241 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
243 xori r11,r11,HID0_BTIC
244 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
246 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
247 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
249 /* All of the bits we have to clear....
251 li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
252 andc r11,r11,r3 /* clear SPD: enable speculative */
255 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
261 /* Enable L2 HW prefetch, if L2 is enabled
264 andis. r3,r3,L2CR_L2E@h
275 * Initialize the FPU registers. This is needed to work around an errata
276 * in some 750 cpus where using a not yet initialized FPU register after
277 * power on reset may hang the CPU
279 _GLOBAL(__init_fpu_registers)
284 addis r9,r3,empty_zero_page@ha
285 addi r9,r9,empty_zero_page@l
293 /* Definitions for the table use to save CPU states */
305 .balign L1_CACHE_BYTES
308 .balign L1_CACHE_BYTES,0
311 /* Called in normal context to backup CPU 0 state. This
312 * does not include cache settings. This function is also
313 * called for machine sleep. This does not include the MMU
314 * setup, BATs, etc... but rather the "special" registers
315 * like HID0, HID1, MSSCR0, etc...
317 _GLOBAL(__save_cpu_setup)
318 /* Some CR fields are volatile, we back it up all */
321 /* Get storage ptr */
322 lis r5,cpu_state_storage@h
323 ori r5,r5,cpu_state_storage@l
325 /* Save HID0 (common to all CONFIG_PPC_BOOK3S_32 cpus) */
329 /* Now deal with CPU type dependent registers */
332 cmplwi cr0,r3,0x8000 /* 7450 */
333 cmplwi cr1,r3,0x000c /* 7400 */
334 cmplwi cr2,r3,0x800c /* 7410 */
335 cmplwi cr3,r3,0x8001 /* 7455 */
336 cmplwi cr4,r3,0x8002 /* 7457 */
337 cmplwi cr5,r3,0x8003 /* 7447A */
338 cmplwi cr6,r3,0x7000 /* 750FX */
339 cmplwi cr7,r3,0x8004 /* 7448 */
340 /* cr1 is 7400 || 7410 */
341 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
343 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
344 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
345 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
346 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
347 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
349 /* Backup 74xx specific regs */
355 /* Backup 745x specific registers */
366 /* Backup 750FX specific registers */
369 /* If rev 2.x, backup HID2 */
380 /* Called with no MMU context (typically MSR:IR/DR off) to
381 * restore CPU state as backed up by the previous
382 * function. This does not include cache setting
384 _GLOBAL(__restore_cpu_setup)
385 /* Some CR fields are volatile, we back it up all */
388 /* Get storage ptr */
389 lis r5,(cpu_state_storage-KERNELBASE)@h
390 ori r5,r5,cpu_state_storage@l
400 /* Now deal with CPU type dependent registers */
403 cmplwi cr0,r3,0x8000 /* 7450 */
404 cmplwi cr1,r3,0x000c /* 7400 */
405 cmplwi cr2,r3,0x800c /* 7410 */
406 cmplwi cr3,r3,0x8001 /* 7455 */
407 cmplwi cr4,r3,0x8002 /* 7457 */
408 cmplwi cr5,r3,0x8003 /* 7447A */
409 cmplwi cr6,r3,0x7000 /* 750FX */
410 cmplwi cr7,r3,0x8004 /* 7448 */
411 /* cr1 is 7400 || 7410 */
412 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
414 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
415 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
416 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
417 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
418 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
420 /* Restore 74xx specific regs */
432 /* Clear 7410 L2CR2 */
436 /* Restore 745x specific registers */
458 /* Restore 750FX specific registers
459 * that is restore HID2 on rev 2.x and PLL config & switch
462 /* If rev 2.x, restore HID2 with low voltage bit cleared */
475 /* Wait for PLL to stabilize */
481 /* Setup final PLL */