1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Dave Liu <daveliu@freescale.com>
5 * copy from idle_6xx.S and modify for e500 based processor,
6 * implement the power_save function in idle.
9 #include <linux/threads.h>
12 #include <asm/cputable.h>
13 #include <asm/thread_info.h>
14 #include <asm/ppc_asm.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
21 lwz r4,TI_LOCAL_FLAGS(r2) /* set napping bit */
22 ori r4,r4,_TLF_NAPPING /* so when we take an exception */
23 stw r4,TI_LOCAL_FLAGS(r2) /* it will return to our caller */
25 #ifdef CONFIG_PPC_E500MC
30 * Guard against spurious wakeups (e.g. from a hypervisor) --
31 * any real interrupt will cause us to return to LR due to
36 /* Check if we can nap or doze, put HID0 mask in r3 */
40 END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
43 /* Now check if user enabled NAP mode */
44 lis r4,powersave_nap@ha
45 lwz r4,powersave_nap@l(r4)
56 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
58 /* Go to NAP or DOZE now */
60 rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
76 * Return from NAP/DOZE mode, restore some CPU specific registers,
77 * r2 containing physical address of current.
78 * r11 points to the exception frame (physical address).
79 * We have to preserve r10.
81 _GLOBAL(power_save_ppc32_restore)
82 lwz r9,_LINK(r11) /* interrupted in e500_idle */
83 stw r9,_NIP(r11) /* make it do a blr */
86 lwz r11,TASK_CPU(r2) /* get cpu number * 4 */
92 b transfer_to_handler_cont