arm64: dts: Revert "specify console via command line"
[linux/fpc-iii.git] / arch / powerpc / kernel / idle_e500.S
blob308f499e146c0b0f7623a3aac49b3d74fd3ba37e
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
4  * Dave Liu <daveliu@freescale.com>
5  * copy from idle_6xx.S and modify for e500 based processor,
6  * implement the power_save function in idle.
7  */
9 #include <linux/threads.h>
10 #include <asm/reg.h>
11 #include <asm/page.h>
12 #include <asm/cputable.h>
13 #include <asm/thread_info.h>
14 #include <asm/ppc_asm.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
18         .text
20 _GLOBAL(e500_idle)
21         lwz     r4,TI_LOCAL_FLAGS(r2)   /* set napping bit */
22         ori     r4,r4,_TLF_NAPPING      /* so when we take an exception */
23         stw     r4,TI_LOCAL_FLAGS(r2)   /* it will return to our caller */
25 #ifdef CONFIG_PPC_E500MC
26         wrteei  1
27 1:      wait
29         /*
30          * Guard against spurious wakeups (e.g. from a hypervisor) --
31          * any real interrupt will cause us to return to LR due to
32          * _TLF_NAPPING.
33          */
34         b       1b
35 #else
36         /* Check if we can nap or doze, put HID0 mask in r3 */
37         lis     r3,0
38 BEGIN_FTR_SECTION
39         lis     r3,HID0_DOZE@h
40 END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
42 BEGIN_FTR_SECTION
43         /* Now check if user enabled NAP mode */
44         lis     r4,powersave_nap@ha
45         lwz     r4,powersave_nap@l(r4)
46         cmpwi   0,r4,0
47         beq     1f
48         stwu    r1,-16(r1)
49         mflr    r0
50         stw     r0,20(r1)
51         bl      flush_dcache_L1
52         lwz     r0,20(r1)
53         addi    r1,r1,16
54         mtlr    r0
55         lis     r3,HID0_NAP@h
56 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
58         /* Go to NAP or DOZE now */
59         mfspr   r4,SPRN_HID0
60         rlwinm  r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
61         or      r4,r4,r3
62         isync
63         mtspr   SPRN_HID0,r4
64         isync
66         mfmsr   r7
67         oris    r7,r7,MSR_WE@h
68         ori     r7,r7,MSR_EE
69         msync
70         mtmsr   r7
71         isync
72 2:      b       2b
73 #endif /* !E500MC */
76  * Return from NAP/DOZE mode, restore some CPU specific registers,
77  * r2 containing physical address of current.
78  * r11 points to the exception frame (physical address).
79  * We have to preserve r10.
80  */
81 _GLOBAL(power_save_ppc32_restore)
82         lwz     r9,_LINK(r11)           /* interrupted in e500_idle */
83         stw     r9,_NIP(r11)            /* make it do a blr */
85 #ifdef CONFIG_SMP
86         lwz     r11,TASK_CPU(r2)                /* get cpu number * 4 */
87         slwi    r11,r11,2
88 #else
89         li      r11,0
90 #endif
92         b       transfer_to_handler_cont