1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 - First public release, contributed by PowerLogix.
12 - Terry: Made sure code disabled interrupts before running. (Previously
13 it was assumed interrupts were already disabled).
14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
15 instead of 2MB. (Prob. only 3 is necessary).
16 - Terry: Updated for workaround to HID0[DPM] processor bug
17 during global invalidates.
20 - Terry: Added isync to correct for an errata.
23 - DanM: Finally added the 7450 patch I've had for the past
24 several months. The L2CR is similar, but I'm going
25 to assume the user of this functions knows what they
28 Author: Terry Greeniaus (tgree@phys.ualberta.ca)
29 Please e-mail updates to this file to me, thanks!
31 #include <asm/processor.h>
32 #include <asm/cputable.h>
33 #include <asm/ppc_asm.h>
34 #include <asm/cache.h>
36 #include <asm/feature-fixups.h>
40 When setting the L2CR register, you must do a few special
41 things. If you are enabling the cache, you must perform a
42 global invalidate. If you are disabling the cache, you must
43 flush the cache contents first. This routine takes care of
44 doing these things. When first enabling the cache, make sure
45 you pass in the L2CR you want, as well as passing in the
46 global invalidate bit set. A global invalidate will only be
47 performed if the L2I bit is set in applyThis. When enabling
48 the cache, you should also set the L2E bit in applyThis. If
49 you want to modify the L2CR contents after the cache has been
50 enabled, the recommended procedure is to first call
51 __setL2CR(0) to disable the cache and then call it again with
52 the new values for L2CR. Examples:
54 _setL2CR(0) - disables the cache
55 _setL2CR(0xB3A04000) - enables my G3 upgrade card:
56 - L2E set to turn on the cache
59 - L2RAM set to pipelined synchronous late-write
60 - L2I set to perform a global invalidation
62 - L2DF set because this upgrade card
65 A similar call should work for your card. You need to know
66 the correct setting for your card and then place them in the
67 fields I have outlined above. Other fields support optional
68 features, such as L2DO which caches only data, or L2TS which
69 causes cache pushes from the L1 cache to go to the L2 cache
70 instead of to main memory.
73 Starting with the 7450, the bits in this register have moved
74 or behave differently. The Enable, Parity Enable, Size,
75 and L2 Invalidate are the only bits that have not moved.
76 The size is read-only for these processors with internal L2
77 cache, and the invalidate is a control as well as status.
82 * Summary: this procedure ignores the L2I bit in the value passed in,
83 * flushes the cache if it was already enabled, always invalidates the
84 * cache, then enables the cache if the L2E bit is set in the value
89 /* Make sure this is a 750 or 7400 chip */
93 END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
97 /* Stop DST streams */
101 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
103 /* Turn off interrupts and data relocation. */
104 mfmsr r7 /* Save MSR in r7 */
106 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
111 /* Before we perform the global invalidation, we must disable dynamic
112 * power management via HID0[DPM] to work around a processor bug where
113 * DPM can possibly interfere with the state machine in the processor
114 * that invalidates the L2 cache tags.
116 mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
117 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
119 mtspr SPRN_HID0,r4 /* Disable DPM */
122 /* Get the current enable bit of the L2CR into r4 */
125 /* Tweak some bits */
126 rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
127 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
128 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
130 /* Check to see if we need to flush */
134 /* Flush the cache. First, read the first 4MB of memory (physical) to
135 * put new data in the cache. (Actually we only need
136 * the size of the L2 cache plus the size of the L1 cache, but 4MB will
137 * cover everything just to be safe).
140 /**** Might be a good idea to set L2DO here - to prevent instructions
141 from getting into the cache. But since we invalidate
142 the next time we enable the cache it doesn't really matter.
143 Don't do this unless you accommodate all processor variations.
144 The bit moved on the 7450.....
148 /* Disable L2 prefetch on some 745x and try to ensure
149 * L2 prefetch engines are idle. As explained by errata
150 * text, we can't be sure they are, we just hope very hard
151 * that well be enough (sic !). At least I noticed Apple
152 * doesn't even bother doing the dcbf's here...
165 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
167 /* TODO: use HW flush assist when available */
174 addi r4,r4,32 /* Go to start of next cache line */
178 /* Now, flush the first 4MB of memory */
185 addi r4,r4,32 /* Go to start of next cache line */
189 /* Set up the L2CR configuration bits (and switch L2 off) */
190 /* CPU errata: Make sure the mtspr below is already in the
194 .balign L1_CACHE_BYTES
207 /* Perform a global invalidation */
212 isync /* For errata */
215 /* On the 7450, we wait for the L2I bit to clear......
217 10: mfspr r3,SPRN_L2CR
221 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
223 /* Wait for the invalidation to complete */
224 3: mfspr r3,SPRN_L2CR
225 rlwinm. r4,r3,0,31,31
228 11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
233 /* See if we need to enable the cache */
237 /* Enable the cache */
242 /* Enable L2 HW prefetch on 744x/745x */
250 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
253 /* Restore HID0[DPM] to whatever it was before */
258 /* Restore MSR (restores EE and DR bits to original state) */
267 /* Return the L2CR contents */
271 END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
276 * Here is a similar routine for dealing with the L3 cache
277 * on the 745x family of chips
281 /* Make sure this is a 745x chip */
285 END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
287 /* Turn off interrupts and data relocation. */
288 mfmsr r7 /* Save MSR in r7 */
290 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
295 /* Stop DST streams */
299 /* Get the current enable bit of the L3CR into r4 */
302 /* Tweak some bits */
303 rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
304 rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
305 rlwinm r3,r3,0,2,31 /* Turn off the enable & PE bits */
306 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
307 /* Check to see if we need to flush */
314 /* TODO: use HW flush assist */
322 addi r4,r4,32 /* Go to start of next cache line */
326 /* Set up the L3CR configuration bits (and switch L3 off) */
331 oris r3,r3,L3CR_L3RES@h /* Set reserved bit 5 */
334 oris r3,r3,L3CR_L3CLKEN@h /* Set clken */
338 /* Wait for stabilize */
343 /* Perform a global invalidation */
350 /* We wait for the L3I bit to clear...... */
351 10: mfspr r3,SPRN_L3CR
356 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
360 /* Wait for stabilize */
365 /* See if we need to enable the cache */
369 /* Enable the cache */
370 oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
374 /* Wait for stabilize */
379 /* Restore MSR (restores EE and DR bits to original state) */
386 /* Return the L3CR contents */
390 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
393 /* --- End of PowerLogix code ---
397 /* flush_disable_L1() - Flush and disable L1 cache
399 * clobbers r0, r3, ctr, cr0
400 * Must be called with interrupts disabled and MMU enabled.
402 _GLOBAL(__flush_disable_L1)
403 /* Stop pending alitvec streams and memory accesses */
406 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
409 /* Load counter to 0x4000 cache lines (512k) and
410 * load cache with datas
412 li r3,0x4000 /* 512kB / 32B */
417 addi r3,r3,0x0020 /* Go to start of next cache line */
422 /* Now flush those cache lines */
423 li r3,0x4000 /* 512kB / 32B */
428 addi r3,r3,0x0020 /* Go to start of next cache line */
432 /* We can now disable the L1 cache (HID0:DCE, HID0:ICE) */
440 /* inval_enable_L1 - Invalidate and enable L1 cache
442 * Assumes L1 is already disabled and MSR:EE is off
446 _GLOBAL(__inval_enable_L1)
447 /* Enable and then Flash inval the instruction & data cache */
449 ori r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI
453 xori r3,r3, HID0_ICFI|HID0_DCI