1 // SPDX-License-Identifier: GPL-2.0-only
3 * Common prep/pmac/chrp boot and setup code.
6 #include <linux/module.h>
7 #include <linux/string.h>
8 #include <linux/sched.h>
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/reboot.h>
12 #include <linux/delay.h>
13 #include <linux/initrd.h>
14 #include <linux/tty.h>
15 #include <linux/seq_file.h>
16 #include <linux/root_dev.h>
17 #include <linux/cpu.h>
18 #include <linux/console.h>
19 #include <linux/memblock.h>
20 #include <linux/export.h>
21 #include <linux/nvram.h>
25 #include <asm/processor.h>
26 #include <asm/pgtable.h>
27 #include <asm/setup.h>
30 #include <asm/cputable.h>
31 #include <asm/bootx.h>
32 #include <asm/btext.h>
33 #include <asm/machdep.h>
34 #include <linux/uaccess.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/sections.h>
37 #include <asm/nvram.h>
40 #include <asm/serial.h>
42 #include <asm/code-patching.h>
43 #include <asm/cpu_has_feature.h>
44 #include <asm/asm-prototypes.h>
45 #include <asm/kdump.h>
46 #include <asm/feature-fixups.h>
47 #include <asm/early_ioremap.h>
53 extern void bootx_init(unsigned long r4
, unsigned long phys
);
56 EXPORT_SYMBOL_GPL(boot_cpuid_phys
);
58 int smp_hw_index
[NR_CPUS
];
59 EXPORT_SYMBOL(smp_hw_index
);
61 unsigned long ISA_DMA_THRESHOLD
;
62 unsigned int DMA_MODE_READ
;
63 unsigned int DMA_MODE_WRITE
;
65 EXPORT_SYMBOL(DMA_MODE_READ
);
66 EXPORT_SYMBOL(DMA_MODE_WRITE
);
69 * This is run before start_kernel(), the kernel has been relocated
70 * and we are running with enough of the MMU enabled to have our
71 * proper kernel virtual addresses
73 * We do the initial parsing of the flat device-tree and prepares
74 * for the MMU to be fully initialized.
76 notrace
void __init
machine_init(u64 dt_ptr
)
78 unsigned int *addr
= (unsigned int *)patch_site_addr(&patch__memset_nocache
);
81 /* Configure static keys first, now that we're relocated. */
84 early_ioremap_setup();
86 /* Enable early debugging if any specified (see udbg.h) */
89 patch_instruction_site(&patch__memcpy_nocache
, PPC_INST_NOP
);
91 insn
= create_cond_branch(addr
, branch_target(addr
), 0x820000);
92 patch_instruction(addr
, insn
); /* replace b by bne cr0 */
94 /* Do some early initialization based on the flat device tree */
95 early_init_devtree(__va(dt_ptr
));
99 setup_kdump_trampoline();
102 /* Checks "l2cr=xxxx" command-line option */
103 static int __init
ppc_setup_l2cr(char *str
)
105 if (cpu_has_feature(CPU_FTR_L2CR
)) {
106 unsigned long val
= simple_strtoul(str
, NULL
, 0);
107 printk(KERN_INFO
"l2cr set to %lx\n", val
);
108 _set_L2CR(0); /* force invalidate by disable cache */
109 _set_L2CR(val
); /* and enable it */
113 __setup("l2cr=", ppc_setup_l2cr
);
115 /* Checks "l3cr=xxxx" command-line option */
116 static int __init
ppc_setup_l3cr(char *str
)
118 if (cpu_has_feature(CPU_FTR_L3CR
)) {
119 unsigned long val
= simple_strtoul(str
, NULL
, 0);
120 printk(KERN_INFO
"l3cr set to %lx\n", val
);
121 _set_L3CR(val
); /* and enable it */
125 __setup("l3cr=", ppc_setup_l3cr
);
127 static int __init
ppc_init(void)
129 /* clear the progress line */
131 ppc_md
.progress(" ", 0xffff);
133 /* call platform init */
134 if (ppc_md
.init
!= NULL
) {
139 arch_initcall(ppc_init
);
141 static void *__init
alloc_stack(void)
143 void *ptr
= memblock_alloc(THREAD_SIZE
, THREAD_ALIGN
);
146 panic("cannot allocate %d bytes for stack at %pS\n",
147 THREAD_SIZE
, (void *)_RET_IP_
);
152 void __init
irqstack_early_init(void)
156 if (IS_ENABLED(CONFIG_VMAP_STACK
))
159 /* interrupt stacks must be in lowmem, we get that for free on ppc32
160 * as the memblock is limited to lowmem by default */
161 for_each_possible_cpu(i
) {
162 softirq_ctx
[i
] = alloc_stack();
163 hardirq_ctx
[i
] = alloc_stack();
167 #ifdef CONFIG_VMAP_STACK
168 void *emergency_ctx
[NR_CPUS
] __ro_after_init
;
170 void __init
emergency_stack_init(void)
174 for_each_possible_cpu(i
)
175 emergency_ctx
[i
] = alloc_stack();
179 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
180 void __init
exc_lvl_early_init(void)
182 unsigned int i
, hw_cpu
;
184 /* interrupt stacks must be in lowmem, we get that for free on ppc32
185 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
186 for_each_possible_cpu(i
) {
188 hw_cpu
= get_hard_smp_processor_id(i
);
193 critirq_ctx
[hw_cpu
] = alloc_stack();
195 dbgirq_ctx
[hw_cpu
] = alloc_stack();
196 mcheckirq_ctx
[hw_cpu
] = alloc_stack();
202 void __init
setup_power_save(void)
204 #ifdef CONFIG_PPC_BOOK3S_32
205 if (cpu_has_feature(CPU_FTR_CAN_DOZE
) ||
206 cpu_has_feature(CPU_FTR_CAN_NAP
))
207 ppc_md
.power_save
= ppc6xx_idle
;
211 if (cpu_has_feature(CPU_FTR_CAN_DOZE
) ||
212 cpu_has_feature(CPU_FTR_CAN_NAP
))
213 ppc_md
.power_save
= e500_idle
;
217 __init
void initialize_cache_info(void)
220 * Set cache line size based on type of cpu as a default.
221 * Systems with OF can look in the properties on the cpu node(s)
222 * for a possibly more accurate value.
224 dcache_bsize
= cur_cpu_spec
->dcache_bsize
;
225 icache_bsize
= cur_cpu_spec
->icache_bsize
;
227 if (IS_ENABLED(CONFIG_PPC_BOOK3S_601
) || IS_ENABLED(CONFIG_E200
))
228 ucache_bsize
= icache_bsize
= dcache_bsize
;