1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@samba.org)
11 * This file handles the architecture-dependent parts of hardware exceptions
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/kernel.h>
19 #include <linux/pkeys.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/module.h> /* print_modules */
28 #include <linux/prctl.h>
29 #include <linux/delay.h>
30 #include <linux/kprobes.h>
31 #include <linux/kexec.h>
32 #include <linux/backlight.h>
33 #include <linux/bug.h>
34 #include <linux/kdebug.h>
35 #include <linux/ratelimit.h>
36 #include <linux/context_tracking.h>
37 #include <linux/smp.h>
38 #include <linux/console.h>
39 #include <linux/kmsg_dump.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
69 #include <asm/stacktrace.h>
72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
73 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
74 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
75 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
76 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
77 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
78 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
79 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
81 EXPORT_SYMBOL(__debugger
);
82 EXPORT_SYMBOL(__debugger_ipi
);
83 EXPORT_SYMBOL(__debugger_bpt
);
84 EXPORT_SYMBOL(__debugger_sstep
);
85 EXPORT_SYMBOL(__debugger_iabr_match
);
86 EXPORT_SYMBOL(__debugger_break_match
);
87 EXPORT_SYMBOL(__debugger_fault_handler
);
90 /* Transactional Memory trap debug */
92 #define TM_DEBUG(x...) printk(KERN_INFO x)
94 #define TM_DEBUG(x...) do { } while(0)
97 static const char *signame(int signr
)
100 case SIGBUS
: return "bus error";
101 case SIGFPE
: return "floating point exception";
102 case SIGILL
: return "illegal instruction";
103 case SIGSEGV
: return "segfault";
104 case SIGTRAP
: return "unhandled trap";
107 return "unknown signal";
111 * Trap & Exception support
114 #ifdef CONFIG_PMAC_BACKLIGHT
115 static void pmac_backlight_unblank(void)
117 mutex_lock(&pmac_backlight_mutex
);
118 if (pmac_backlight
) {
119 struct backlight_properties
*props
;
121 props
= &pmac_backlight
->props
;
122 props
->brightness
= props
->max_brightness
;
123 props
->power
= FB_BLANK_UNBLANK
;
124 backlight_update_status(pmac_backlight
);
126 mutex_unlock(&pmac_backlight_mutex
);
129 static inline void pmac_backlight_unblank(void) { }
133 * If oops/die is expected to crash the machine, return true here.
135 * This should not be expected to be 100% accurate, there may be
136 * notifiers registered or other unexpected conditions that may bring
137 * down the kernel. Or if the current process in the kernel is holding
138 * locks or has other critical state, the kernel may become effectively
141 bool die_will_crash(void)
143 if (should_fadump_crash())
145 if (kexec_should_crash(current
))
147 if (in_interrupt() || panic_on_oops
||
148 !current
->pid
|| is_global_init(current
))
154 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
155 static int die_owner
= -1;
156 static unsigned int die_nest_count
;
157 static int die_counter
;
159 extern void panic_flush_kmsg_start(void)
162 * These are mostly taken from kernel/panic.c, but tries to do
163 * relatively minimal work. Don't use delay functions (TB may
164 * be broken), don't crash dump (need to set a firmware log),
165 * don't run notifiers. We do want to get some information to
172 extern void panic_flush_kmsg_end(void)
174 printk_safe_flush_on_panic();
175 kmsg_dump(KMSG_DUMP_PANIC
);
178 console_flush_on_panic(CONSOLE_FLUSH_PENDING
);
181 static unsigned long oops_begin(struct pt_regs
*regs
)
188 /* racy, but better than risking deadlock. */
189 raw_local_irq_save(flags
);
190 cpu
= smp_processor_id();
191 if (!arch_spin_trylock(&die_lock
)) {
192 if (cpu
== die_owner
)
193 /* nested oops. should stop eventually */;
195 arch_spin_lock(&die_lock
);
201 if (machine_is(powermac
))
202 pmac_backlight_unblank();
205 NOKPROBE_SYMBOL(oops_begin
);
207 static void oops_end(unsigned long flags
, struct pt_regs
*regs
,
211 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
215 if (!die_nest_count
) {
216 /* Nest count reaches zero, release the lock. */
218 arch_spin_unlock(&die_lock
);
220 raw_local_irq_restore(flags
);
223 * system_reset_excption handles debugger, crash dump, panic, for 0x100
225 if (TRAP(regs
) == 0x100)
228 crash_fadump(regs
, "die oops");
230 if (kexec_should_crash(current
))
237 * While our oops output is serialised by a spinlock, output
238 * from panic() called below can race and corrupt it. If we
239 * know we are going to panic, delay for 1 second so we have a
240 * chance to get clean backtraces from all CPUs that are oopsing.
242 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
243 is_global_init(current
)) {
244 mdelay(MSEC_PER_SEC
);
248 panic("Fatal exception");
251 NOKPROBE_SYMBOL(oops_end
);
253 static char *get_mmu_str(void)
255 if (early_radix_enabled())
257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE
))
262 static int __die(const char *str
, struct pt_regs
*regs
, long err
)
264 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN
) ? "LE" : "BE",
268 PAGE_SIZE
/ 1024, get_mmu_str(),
269 IS_ENABLED(CONFIG_PREEMPT
) ? " PREEMPT" : "",
270 IS_ENABLED(CONFIG_SMP
) ? " SMP" : "",
271 IS_ENABLED(CONFIG_SMP
) ? (" NR_CPUS=" __stringify(NR_CPUS
)) : "",
272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
273 IS_ENABLED(CONFIG_NUMA
) ? " NUMA" : "",
274 ppc_md
.name
? ppc_md
.name
: "");
276 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
284 NOKPROBE_SYMBOL(__die
);
286 void die(const char *str
, struct pt_regs
*regs
, long err
)
291 * system_reset_excption handles debugger, crash dump, panic, for 0x100
293 if (TRAP(regs
) != 0x100) {
298 flags
= oops_begin(regs
);
299 if (__die(str
, regs
, err
))
301 oops_end(flags
, regs
, err
);
303 NOKPROBE_SYMBOL(die
);
305 void user_single_step_report(struct pt_regs
*regs
)
307 force_sig_fault(SIGTRAP
, TRAP_TRACE
, (void __user
*)regs
->nip
);
310 static void show_signal_msg(int signr
, struct pt_regs
*regs
, int code
,
313 static DEFINE_RATELIMIT_STATE(rs
, DEFAULT_RATELIMIT_INTERVAL
,
314 DEFAULT_RATELIMIT_BURST
);
316 if (!show_unhandled_signals
)
319 if (!unhandled_signal(current
, signr
))
322 if (!__ratelimit(&rs
))
325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
326 current
->comm
, current
->pid
, signame(signr
), signr
,
327 addr
, regs
->nip
, regs
->link
, code
);
329 print_vma_addr(KERN_CONT
" in ", regs
->nip
);
333 show_user_instructions(regs
);
336 static bool exception_common(int signr
, struct pt_regs
*regs
, int code
,
339 if (!user_mode(regs
)) {
340 die("Exception in kernel mode", regs
, signr
);
344 show_signal_msg(signr
, regs
, code
, addr
);
346 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
349 current
->thread
.trap_nr
= code
;
352 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
353 * to capture the content, if the task gets killed.
355 thread_pkey_regs_save(¤t
->thread
);
360 void _exception_pkey(struct pt_regs
*regs
, unsigned long addr
, int key
)
362 if (!exception_common(SIGSEGV
, regs
, SEGV_PKUERR
, addr
))
365 force_sig_pkuerr((void __user
*) addr
, key
);
368 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
370 if (!exception_common(signr
, regs
, code
, addr
))
373 force_sig_fault(signr
, code
, (void __user
*)addr
);
377 * The interrupt architecture has a quirk in that the HV interrupts excluding
378 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
379 * that an interrupt handler must do is save off a GPR into a scratch register,
380 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
381 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
382 * that it is non-reentrant, which leads to random data corruption.
384 * The solution is for NMI interrupts in HV mode to check if they originated
385 * from these critical HV interrupt regions. If so, then mark them not
388 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
389 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
390 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
391 * that would work. However any other guest OS that may have the SPRG live
392 * and MSR[RI]=1 could encounter silent corruption.
394 * Builds that do not support KVM could take this second option to increase
395 * the recoverability of NMIs.
397 void hv_nmi_check_nonrecoverable(struct pt_regs
*regs
)
399 #ifdef CONFIG_PPC_POWERNV
400 unsigned long kbase
= (unsigned long)_stext
;
401 unsigned long nip
= regs
->nip
;
403 if (!(regs
->msr
& MSR_RI
))
405 if (!(regs
->msr
& MSR_HV
))
407 if (regs
->msr
& MSR_PR
)
411 * Now test if the interrupt has hit a range that may be using
412 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
413 * problem ranges all run un-relocated. Test real and virt modes
414 * at the same time by droping the high bit of the nip (virt mode
415 * entry points still have the +0x4000 offset).
417 nip
&= ~0xc000000000000000ULL
;
418 if ((nip
>= 0x500 && nip
< 0x600) || (nip
>= 0x4500 && nip
< 0x4600))
420 if ((nip
>= 0x980 && nip
< 0xa00) || (nip
>= 0x4980 && nip
< 0x4a00))
422 if ((nip
>= 0xe00 && nip
< 0xec0) || (nip
>= 0x4e00 && nip
< 0x4ec0))
424 if ((nip
>= 0xf80 && nip
< 0xfa0) || (nip
>= 0x4f80 && nip
< 0x4fa0))
427 /* Trampoline code runs un-relocated so subtract kbase. */
428 if (nip
>= (unsigned long)(start_real_trampolines
- kbase
) &&
429 nip
< (unsigned long)(end_real_trampolines
- kbase
))
431 if (nip
>= (unsigned long)(start_virt_trampolines
- kbase
) &&
432 nip
< (unsigned long)(end_virt_trampolines
- kbase
))
437 regs
->msr
&= ~MSR_RI
;
441 void system_reset_exception(struct pt_regs
*regs
)
443 unsigned long hsrr0
, hsrr1
;
444 bool nested
= in_nmi();
445 bool saved_hsrrs
= false;
448 * Avoid crashes in case of nested NMI exceptions. Recoverability
449 * is determined by RI and in_nmi
455 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
456 * The system reset interrupt itself may clobber HSRRs (e.g., to call
457 * OPAL), so save them here and restore them before returning.
459 * Machine checks don't need to save HSRRs, as the real mode handler
460 * is careful to avoid them, and the regular handler is not delivered
463 if (cpu_has_feature(CPU_FTR_HVMODE
)) {
464 hsrr0
= mfspr(SPRN_HSRR0
);
465 hsrr1
= mfspr(SPRN_HSRR1
);
469 hv_nmi_check_nonrecoverable(regs
);
471 __this_cpu_inc(irq_stat
.sreset_irqs
);
473 /* See if any machine dependent calls */
474 if (ppc_md
.system_reset_exception
) {
475 if (ppc_md
.system_reset_exception(regs
))
482 kmsg_dump(KMSG_DUMP_OOPS
);
484 * A system reset is a request to dump, so we always send
485 * it through the crashdump code (if fadump or kdump are
488 crash_fadump(regs
, "System Reset");
493 * We aren't the primary crash CPU. We need to send it
494 * to a holding pattern to avoid it ending up in the panic
497 crash_kexec_secondary(regs
);
500 * No debugger or crash dump registered, print logs then
503 die("System Reset", regs
, SIGABRT
);
505 mdelay(2*MSEC_PER_SEC
); /* Wait a little while for others to print */
506 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
507 nmi_panic(regs
, "System Reset");
510 #ifdef CONFIG_PPC_BOOK3S_64
511 BUG_ON(get_paca()->in_nmi
== 0);
512 if (get_paca()->in_nmi
> 1)
513 nmi_panic(regs
, "Unrecoverable nested System Reset");
515 /* Must die if the interrupt is not recoverable */
516 if (!(regs
->msr
& MSR_RI
))
517 nmi_panic(regs
, "Unrecoverable System Reset");
520 mtspr(SPRN_HSRR0
, hsrr0
);
521 mtspr(SPRN_HSRR1
, hsrr1
);
527 /* What should we do here? We could issue a shutdown or hard reset. */
531 * I/O accesses can cause machine checks on powermacs.
532 * Check if the NIP corresponds to the address of a sync
533 * instruction for which there is an entry in the exception
535 * Note that the 601 only takes a machine check on TEA
536 * (transfer error ack) signal assertion, and does not
537 * set any of the top 16 bits of SRR1.
540 static inline int check_io_access(struct pt_regs
*regs
)
543 unsigned long msr
= regs
->msr
;
544 const struct exception_table_entry
*entry
;
545 unsigned int *nip
= (unsigned int *)regs
->nip
;
547 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
548 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
550 * Check that it's a sync instruction, or somewhere
551 * in the twi; isync; nop sequence that inb/inw/inl uses.
552 * As the address is in the exception table
553 * we should be able to read the instr there.
554 * For the debug message, we look at the preceding
557 if (*nip
== PPC_INST_NOP
)
559 else if (*nip
== PPC_INST_ISYNC
)
561 if (*nip
== PPC_INST_SYNC
|| (*nip
>> 26) == OP_TRAP
) {
565 rb
= (*nip
>> 11) & 0x1f;
566 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
567 (*nip
& 0x100)? "OUT to": "IN from",
568 regs
->gpr
[rb
] - _IO_BASE
, nip
);
570 regs
->nip
= extable_fixup(entry
);
574 #endif /* CONFIG_PPC32 */
578 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
579 /* On 4xx, the reason for the machine check or program exception
581 #define get_reason(regs) ((regs)->dsisr)
582 #define REASON_FP ESR_FP
583 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
584 #define REASON_PRIVILEGED ESR_PPR
585 #define REASON_TRAP ESR_PTR
587 /* single-step stuff */
588 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
589 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
590 #define clear_br_trace(regs) do {} while(0)
592 /* On non-4xx, the reason for the machine check or program
593 exception is in the MSR. */
594 #define get_reason(regs) ((regs)->msr)
595 #define REASON_TM SRR1_PROGTM
596 #define REASON_FP SRR1_PROGFPE
597 #define REASON_ILLEGAL SRR1_PROGILL
598 #define REASON_PRIVILEGED SRR1_PROGPRIV
599 #define REASON_TRAP SRR1_PROGTRAP
601 #define single_stepping(regs) ((regs)->msr & MSR_SE)
602 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
603 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
606 #if defined(CONFIG_E500)
607 int machine_check_e500mc(struct pt_regs
*regs
)
609 unsigned long mcsr
= mfspr(SPRN_MCSR
);
610 unsigned long pvr
= mfspr(SPRN_PVR
);
611 unsigned long reason
= mcsr
;
614 if (reason
& MCSR_LD
) {
615 recoverable
= fsl_rio_mcheck_exception(regs
);
616 if (recoverable
== 1)
620 printk("Machine check in kernel mode.\n");
621 printk("Caused by (from MCSR=%lx): ", reason
);
623 if (reason
& MCSR_MCP
)
624 pr_cont("Machine Check Signal\n");
626 if (reason
& MCSR_ICPERR
) {
627 pr_cont("Instruction Cache Parity Error\n");
630 * This is recoverable by invalidating the i-cache.
632 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
633 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
637 * This will generally be accompanied by an instruction
638 * fetch error report -- only treat MCSR_IF as fatal
639 * if it wasn't due to an L1 parity error.
644 if (reason
& MCSR_DCPERR_MC
) {
645 pr_cont("Data Cache Parity Error\n");
648 * In write shadow mode we auto-recover from the error, but it
649 * may still get logged and cause a machine check. We should
650 * only treat the non-write shadow case as non-recoverable.
652 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
653 * is not implemented but L1 data cache always runs in write
654 * shadow mode. Hence on data cache parity errors HW will
655 * automatically invalidate the L1 Data Cache.
657 if (PVR_VER(pvr
) != PVR_VER_E6500
) {
658 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
663 if (reason
& MCSR_L2MMU_MHIT
) {
664 pr_cont("Hit on multiple TLB entries\n");
668 if (reason
& MCSR_NMI
)
669 pr_cont("Non-maskable interrupt\n");
671 if (reason
& MCSR_IF
) {
672 pr_cont("Instruction Fetch Error Report\n");
676 if (reason
& MCSR_LD
) {
677 pr_cont("Load Error Report\n");
681 if (reason
& MCSR_ST
) {
682 pr_cont("Store Error Report\n");
686 if (reason
& MCSR_LDG
) {
687 pr_cont("Guarded Load Error Report\n");
691 if (reason
& MCSR_TLBSYNC
)
692 pr_cont("Simultaneous tlbsync operations\n");
694 if (reason
& MCSR_BSL2_ERR
) {
695 pr_cont("Level 2 Cache Error\n");
699 if (reason
& MCSR_MAV
) {
702 addr
= mfspr(SPRN_MCAR
);
703 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
705 pr_cont("Machine Check %s Address: %#llx\n",
706 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
710 mtspr(SPRN_MCSR
, mcsr
);
711 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
714 int machine_check_e500(struct pt_regs
*regs
)
716 unsigned long reason
= mfspr(SPRN_MCSR
);
718 if (reason
& MCSR_BUS_RBERR
) {
719 if (fsl_rio_mcheck_exception(regs
))
721 if (fsl_pci_mcheck_exception(regs
))
725 printk("Machine check in kernel mode.\n");
726 printk("Caused by (from MCSR=%lx): ", reason
);
728 if (reason
& MCSR_MCP
)
729 pr_cont("Machine Check Signal\n");
730 if (reason
& MCSR_ICPERR
)
731 pr_cont("Instruction Cache Parity Error\n");
732 if (reason
& MCSR_DCP_PERR
)
733 pr_cont("Data Cache Push Parity Error\n");
734 if (reason
& MCSR_DCPERR
)
735 pr_cont("Data Cache Parity Error\n");
736 if (reason
& MCSR_BUS_IAERR
)
737 pr_cont("Bus - Instruction Address Error\n");
738 if (reason
& MCSR_BUS_RAERR
)
739 pr_cont("Bus - Read Address Error\n");
740 if (reason
& MCSR_BUS_WAERR
)
741 pr_cont("Bus - Write Address Error\n");
742 if (reason
& MCSR_BUS_IBERR
)
743 pr_cont("Bus - Instruction Data Error\n");
744 if (reason
& MCSR_BUS_RBERR
)
745 pr_cont("Bus - Read Data Bus Error\n");
746 if (reason
& MCSR_BUS_WBERR
)
747 pr_cont("Bus - Write Data Bus Error\n");
748 if (reason
& MCSR_BUS_IPERR
)
749 pr_cont("Bus - Instruction Parity Error\n");
750 if (reason
& MCSR_BUS_RPERR
)
751 pr_cont("Bus - Read Parity Error\n");
756 int machine_check_generic(struct pt_regs
*regs
)
760 #elif defined(CONFIG_E200)
761 int machine_check_e200(struct pt_regs
*regs
)
763 unsigned long reason
= mfspr(SPRN_MCSR
);
765 printk("Machine check in kernel mode.\n");
766 printk("Caused by (from MCSR=%lx): ", reason
);
768 if (reason
& MCSR_MCP
)
769 pr_cont("Machine Check Signal\n");
770 if (reason
& MCSR_CP_PERR
)
771 pr_cont("Cache Push Parity Error\n");
772 if (reason
& MCSR_CPERR
)
773 pr_cont("Cache Parity Error\n");
774 if (reason
& MCSR_EXCP_ERR
)
775 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
776 if (reason
& MCSR_BUS_IRERR
)
777 pr_cont("Bus - Read Bus Error on instruction fetch\n");
778 if (reason
& MCSR_BUS_DRERR
)
779 pr_cont("Bus - Read Bus Error on data load\n");
780 if (reason
& MCSR_BUS_WRERR
)
781 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
785 #elif defined(CONFIG_PPC32)
786 int machine_check_generic(struct pt_regs
*regs
)
788 unsigned long reason
= regs
->msr
;
790 printk("Machine check in kernel mode.\n");
791 printk("Caused by (from SRR1=%lx): ", reason
);
792 switch (reason
& 0x601F0000) {
794 pr_cont("Machine check signal\n");
796 case 0: /* for 601 */
798 case 0x140000: /* 7450 MSS error and TEA */
799 pr_cont("Transfer error ack signal\n");
802 pr_cont("Data parity error signal\n");
805 pr_cont("Address parity error signal\n");
808 pr_cont("L1 Data Cache error\n");
811 pr_cont("L1 Instruction Cache error\n");
814 pr_cont("L2 data cache parity error\n");
817 pr_cont("Unknown values in msr\n");
821 #endif /* everything else */
823 void machine_check_exception(struct pt_regs
*regs
)
826 bool nested
= in_nmi();
830 __this_cpu_inc(irq_stat
.mce_exceptions
);
832 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
834 /* See if any machine dependent calls. In theory, we would want
835 * to call the CPU first, and call the ppc_md. one if the CPU
836 * one returns a positive number. However there is existing code
837 * that assumes the board gets a first chance, so let's keep it
838 * that way for now and fix things later. --BenH.
840 if (ppc_md
.machine_check_exception
)
841 recover
= ppc_md
.machine_check_exception(regs
);
842 else if (cur_cpu_spec
->machine_check
)
843 recover
= cur_cpu_spec
->machine_check(regs
);
848 if (debugger_fault_handler(regs
))
851 if (check_io_access(regs
))
857 die("Machine check", regs
, SIGBUS
);
859 /* Must die if the interrupt is not recoverable */
860 if (!(regs
->msr
& MSR_RI
))
861 nmi_panic(regs
, "Unrecoverable Machine check");
870 void SMIException(struct pt_regs
*regs
)
872 die("System Management Interrupt", regs
, SIGABRT
);
876 static void p9_hmi_special_emu(struct pt_regs
*regs
)
878 unsigned int ra
, rb
, t
, i
, sel
, instr
, rc
;
879 const void __user
*addr
;
881 unsigned long ea
, msr
, msr_mask
;
884 if (__get_user_inatomic(instr
, (unsigned int __user
*)regs
->nip
))
888 * lxvb16x opcode: 0x7c0006d8
889 * lxvd2x opcode: 0x7c000698
890 * lxvh8x opcode: 0x7c000658
891 * lxvw4x opcode: 0x7c000618
893 if ((instr
& 0xfc00073e) != 0x7c000618) {
894 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
896 smp_processor_id(), current
->comm
, current
->pid
,
901 /* Grab vector registers into the task struct */
902 msr
= regs
->msr
; /* Grab msr before we flush the bits */
903 flush_vsx_to_thread(current
);
904 enable_kernel_altivec();
907 * Is userspace running with a different endian (this is rare but
910 swap
= (msr
& MSR_LE
) != (MSR_KERNEL
& MSR_LE
);
912 /* Decode the instruction */
913 ra
= (instr
>> 16) & 0x1f;
914 rb
= (instr
>> 11) & 0x1f;
915 t
= (instr
>> 21) & 0x1f;
917 vdst
= (u8
*)¤t
->thread
.vr_state
.vr
[t
];
919 vdst
= (u8
*)¤t
->thread
.fp_state
.fpr
[t
][0];
921 /* Grab the vector address */
922 ea
= regs
->gpr
[rb
] + (ra
? regs
->gpr
[ra
] : 0);
925 addr
= (__force
const void __user
*)ea
;
928 if (!access_ok(addr
, 16)) {
929 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
930 " instr=%08x addr=%016lx\n",
931 smp_processor_id(), current
->comm
, current
->pid
,
932 regs
->nip
, instr
, (unsigned long)addr
);
936 /* Read the vector */
938 if ((unsigned long)addr
& 0xfUL
)
940 rc
= __copy_from_user_inatomic(vbuf
, addr
, 16);
942 __get_user_atomic_128_aligned(vbuf
, addr
, rc
);
944 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
945 " instr=%08x addr=%016lx\n",
946 smp_processor_id(), current
->comm
, current
->pid
,
947 regs
->nip
, instr
, (unsigned long)addr
);
951 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
952 " instr=%08x addr=%016lx\n",
953 smp_processor_id(), current
->comm
, current
->pid
, regs
->nip
,
954 instr
, (unsigned long) addr
);
956 /* Grab instruction "selector" */
957 sel
= (instr
>> 6) & 3;
960 * Check to make sure the facility is actually enabled. This
961 * could happen if we get a false positive hit.
963 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
964 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
967 if ((sel
& 1) && (instr
& 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
969 if (!(msr
& msr_mask
)) {
970 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
971 " instr=%08x msr:%016lx\n",
972 smp_processor_id(), current
->comm
, current
->pid
,
973 regs
->nip
, instr
, msr
);
977 /* Do logging here before we modify sel based on endian */
980 PPC_WARN_EMULATED(lxvw4x
, regs
);
983 PPC_WARN_EMULATED(lxvh8x
, regs
);
986 PPC_WARN_EMULATED(lxvd2x
, regs
);
988 case 3: /* lxvb16x */
989 PPC_WARN_EMULATED(lxvb16x
, regs
);
993 #ifdef __LITTLE_ENDIAN__
995 * An LE kernel stores the vector in the task struct as an LE
996 * byte array (effectively swapping both the components and
997 * the content of the components). Those instructions expect
998 * the components to remain in ascending address order, so we
1001 * If we are running a BE user space, the expectation is that
1002 * of a simple memcpy, so forcing the emulation to look like
1003 * a lxvb16x should do the trick.
1009 case 0: /* lxvw4x */
1010 for (i
= 0; i
< 4; i
++)
1011 ((u32
*)vdst
)[i
] = ((u32
*)vbuf
)[3-i
];
1013 case 1: /* lxvh8x */
1014 for (i
= 0; i
< 8; i
++)
1015 ((u16
*)vdst
)[i
] = ((u16
*)vbuf
)[7-i
];
1017 case 2: /* lxvd2x */
1018 for (i
= 0; i
< 2; i
++)
1019 ((u64
*)vdst
)[i
] = ((u64
*)vbuf
)[1-i
];
1021 case 3: /* lxvb16x */
1022 for (i
= 0; i
< 16; i
++)
1023 vdst
[i
] = vbuf
[15-i
];
1026 #else /* __LITTLE_ENDIAN__ */
1027 /* On a big endian kernel, a BE userspace only needs a memcpy */
1031 /* Otherwise, we need to swap the content of the components */
1033 case 0: /* lxvw4x */
1034 for (i
= 0; i
< 4; i
++)
1035 ((u32
*)vdst
)[i
] = cpu_to_le32(((u32
*)vbuf
)[i
]);
1037 case 1: /* lxvh8x */
1038 for (i
= 0; i
< 8; i
++)
1039 ((u16
*)vdst
)[i
] = cpu_to_le16(((u16
*)vbuf
)[i
]);
1041 case 2: /* lxvd2x */
1042 for (i
= 0; i
< 2; i
++)
1043 ((u64
*)vdst
)[i
] = cpu_to_le64(((u64
*)vbuf
)[i
]);
1045 case 3: /* lxvb16x */
1046 memcpy(vdst
, vbuf
, 16);
1049 #endif /* !__LITTLE_ENDIAN__ */
1051 /* Go to next instruction */
1054 #endif /* CONFIG_VSX */
1056 void handle_hmi_exception(struct pt_regs
*regs
)
1058 struct pt_regs
*old_regs
;
1060 old_regs
= set_irq_regs(regs
);
1064 /* Real mode flagged P9 special emu is needed */
1065 if (local_paca
->hmi_p9_special_emu
) {
1066 local_paca
->hmi_p9_special_emu
= 0;
1069 * We don't want to take page faults while doing the
1070 * emulation, we just replay the instruction if necessary.
1072 pagefault_disable();
1073 p9_hmi_special_emu(regs
);
1076 #endif /* CONFIG_VSX */
1078 if (ppc_md
.handle_hmi_exception
)
1079 ppc_md
.handle_hmi_exception(regs
);
1082 set_irq_regs(old_regs
);
1085 void unknown_exception(struct pt_regs
*regs
)
1087 enum ctx_state prev_state
= exception_enter();
1089 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1090 regs
->nip
, regs
->msr
, regs
->trap
);
1092 _exception(SIGTRAP
, regs
, TRAP_UNK
, 0);
1094 exception_exit(prev_state
);
1097 void instruction_breakpoint_exception(struct pt_regs
*regs
)
1099 enum ctx_state prev_state
= exception_enter();
1101 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
1102 5, SIGTRAP
) == NOTIFY_STOP
)
1104 if (debugger_iabr_match(regs
))
1106 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1109 exception_exit(prev_state
);
1112 void RunModeException(struct pt_regs
*regs
)
1114 _exception(SIGTRAP
, regs
, TRAP_UNK
, 0);
1117 void single_step_exception(struct pt_regs
*regs
)
1119 enum ctx_state prev_state
= exception_enter();
1121 clear_single_step(regs
);
1122 clear_br_trace(regs
);
1124 if (kprobe_post_handler(regs
))
1127 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1128 5, SIGTRAP
) == NOTIFY_STOP
)
1130 if (debugger_sstep(regs
))
1133 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1136 exception_exit(prev_state
);
1138 NOKPROBE_SYMBOL(single_step_exception
);
1141 * After we have successfully emulated an instruction, we have to
1142 * check if the instruction was being single-stepped, and if so,
1143 * pretend we got a single-step exception. This was pointed out
1144 * by Kumar Gala. -- paulus
1146 static void emulate_single_step(struct pt_regs
*regs
)
1148 if (single_stepping(regs
))
1149 single_step_exception(regs
);
1152 static inline int __parse_fpscr(unsigned long fpscr
)
1154 int ret
= FPE_FLTUNK
;
1156 /* Invalid operation */
1157 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
1161 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
1165 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
1168 /* Divide by zero */
1169 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
1172 /* Inexact result */
1173 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
1179 static void parse_fpe(struct pt_regs
*regs
)
1183 flush_fp_to_thread(current
);
1185 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1187 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1191 * Illegal instruction emulation support. Originally written to
1192 * provide the PVR to user applications using the mfspr rd, PVR.
1193 * Return non-zero if we can't emulate, or -EFAULT if the associated
1194 * memory access caused an access fault. Return zero on success.
1196 * There are a couple of ways to do this, either "decode" the instruction
1197 * or directly match lots of bits. In this case, matching lots of
1198 * bits is faster and easier.
1201 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
1203 u8 rT
= (instword
>> 21) & 0x1f;
1204 u8 rA
= (instword
>> 16) & 0x1f;
1205 u8 NB_RB
= (instword
>> 11) & 0x1f;
1210 /* Early out if we are an invalid form of lswx */
1211 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
1212 if ((rT
== rA
) || (rT
== NB_RB
))
1215 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1217 switch (instword
& PPC_INST_STRING_MASK
) {
1219 case PPC_INST_STSWX
:
1221 num_bytes
= regs
->xer
& 0x7f;
1224 case PPC_INST_STSWI
:
1225 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
1231 while (num_bytes
!= 0)
1234 u32 shift
= 8 * (3 - (pos
& 0x3));
1236 /* if process is 32-bit, clear upper 32 bits of EA */
1237 if ((regs
->msr
& MSR_64BIT
) == 0)
1240 switch ((instword
& PPC_INST_STRING_MASK
)) {
1243 if (get_user(val
, (u8 __user
*)EA
))
1245 /* first time updating this reg,
1249 regs
->gpr
[rT
] |= val
<< shift
;
1251 case PPC_INST_STSWI
:
1252 case PPC_INST_STSWX
:
1253 val
= regs
->gpr
[rT
] >> shift
;
1254 if (put_user(val
, (u8 __user
*)EA
))
1258 /* move EA to next address */
1262 /* manage our position within the register */
1273 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
1278 ra
= (instword
>> 16) & 0x1f;
1279 rs
= (instword
>> 21) & 0x1f;
1281 tmp
= regs
->gpr
[rs
];
1282 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
1283 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
1284 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
1285 regs
->gpr
[ra
] = tmp
;
1290 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
1292 u8 rT
= (instword
>> 21) & 0x1f;
1293 u8 rA
= (instword
>> 16) & 0x1f;
1294 u8 rB
= (instword
>> 11) & 0x1f;
1295 u8 BC
= (instword
>> 6) & 0x1f;
1299 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1300 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
1302 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
1307 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1308 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
1310 /* If we're emulating a load/store in an active transaction, we cannot
1311 * emulate it as the kernel operates in transaction suspended context.
1312 * We need to abort the transaction. This creates a persistent TM
1313 * abort so tell the user what caused it with a new code.
1315 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1323 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1329 static int emulate_instruction(struct pt_regs
*regs
)
1334 if (!user_mode(regs
))
1336 CHECK_FULL_REGS(regs
);
1338 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1341 /* Emulate the mfspr rD, PVR. */
1342 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1343 PPC_WARN_EMULATED(mfpvr
, regs
);
1344 rd
= (instword
>> 21) & 0x1f;
1345 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1349 /* Emulating the dcba insn is just a no-op. */
1350 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1351 PPC_WARN_EMULATED(dcba
, regs
);
1355 /* Emulate the mcrxr insn. */
1356 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1357 int shift
= (instword
>> 21) & 0x1c;
1358 unsigned long msk
= 0xf0000000UL
>> shift
;
1360 PPC_WARN_EMULATED(mcrxr
, regs
);
1361 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1362 regs
->xer
&= ~0xf0000000UL
;
1366 /* Emulate load/store string insn. */
1367 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1368 if (tm_abort_check(regs
,
1369 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1371 PPC_WARN_EMULATED(string
, regs
);
1372 return emulate_string_inst(regs
, instword
);
1375 /* Emulate the popcntb (Population Count Bytes) instruction. */
1376 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1377 PPC_WARN_EMULATED(popcntb
, regs
);
1378 return emulate_popcntb_inst(regs
, instword
);
1381 /* Emulate isel (Integer Select) instruction */
1382 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1383 PPC_WARN_EMULATED(isel
, regs
);
1384 return emulate_isel(regs
, instword
);
1387 /* Emulate sync instruction variants */
1388 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1389 PPC_WARN_EMULATED(sync
, regs
);
1390 asm volatile("sync");
1395 /* Emulate the mfspr rD, DSCR. */
1396 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1397 PPC_INST_MFSPR_DSCR_USER
) ||
1398 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1399 PPC_INST_MFSPR_DSCR
)) &&
1400 cpu_has_feature(CPU_FTR_DSCR
)) {
1401 PPC_WARN_EMULATED(mfdscr
, regs
);
1402 rd
= (instword
>> 21) & 0x1f;
1403 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1406 /* Emulate the mtspr DSCR, rD. */
1407 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1408 PPC_INST_MTSPR_DSCR_USER
) ||
1409 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1410 PPC_INST_MTSPR_DSCR
)) &&
1411 cpu_has_feature(CPU_FTR_DSCR
)) {
1412 PPC_WARN_EMULATED(mtdscr
, regs
);
1413 rd
= (instword
>> 21) & 0x1f;
1414 current
->thread
.dscr
= regs
->gpr
[rd
];
1415 current
->thread
.dscr_inherit
= 1;
1416 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1424 int is_valid_bugaddr(unsigned long addr
)
1426 return is_kernel_addr(addr
);
1429 #ifdef CONFIG_MATH_EMULATION
1430 static int emulate_math(struct pt_regs
*regs
)
1433 extern int do_mathemu(struct pt_regs
*regs
);
1435 ret
= do_mathemu(regs
);
1437 PPC_WARN_EMULATED(math
, regs
);
1441 emulate_single_step(regs
);
1445 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1446 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1450 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1457 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1460 void program_check_exception(struct pt_regs
*regs
)
1462 enum ctx_state prev_state
= exception_enter();
1463 unsigned int reason
= get_reason(regs
);
1465 /* We can now get here via a FP Unavailable exception if the core
1466 * has no FPU, in that case the reason flags will be 0 */
1468 if (reason
& REASON_FP
) {
1469 /* IEEE FP exception */
1473 if (reason
& REASON_TRAP
) {
1474 unsigned long bugaddr
;
1475 /* Debugger is first in line to stop recursive faults in
1476 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1477 if (debugger_bpt(regs
))
1480 if (kprobe_handler(regs
))
1483 /* trap exception */
1484 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1488 bugaddr
= regs
->nip
;
1490 * Fixup bugaddr for BUG_ON() in real mode
1492 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1493 bugaddr
+= PAGE_OFFSET
;
1495 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1496 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1500 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1503 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1504 if (reason
& REASON_TM
) {
1505 /* This is a TM "Bad Thing Exception" program check.
1507 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1508 * transition in TM states.
1509 * - A trechkpt is attempted when transactional.
1510 * - A treclaim is attempted when non transactional.
1511 * - A tend is illegally attempted.
1512 * - writing a TM SPR when transactional.
1514 * If usermode caused this, it's done something illegal and
1515 * gets a SIGILL slap on the wrist. We call it an illegal
1516 * operand to distinguish from the instruction just being bad
1517 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1518 * illegal /placement/ of a valid instruction.
1520 if (user_mode(regs
)) {
1521 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1524 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1525 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1526 regs
->nip
, regs
->msr
, get_paca()->tm_scratch
);
1527 die("Unrecoverable exception", regs
, SIGABRT
);
1533 * If we took the program check in the kernel skip down to sending a
1534 * SIGILL. The subsequent cases all relate to emulating instructions
1535 * which we should only do for userspace. We also do not want to enable
1536 * interrupts for kernel faults because that might lead to further
1537 * faults, and loose the context of the original exception.
1539 if (!user_mode(regs
))
1542 /* We restore the interrupt state now */
1543 if (!arch_irq_disabled_regs(regs
))
1546 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1547 * but there seems to be a hardware bug on the 405GP (RevD)
1548 * that means ESR is sometimes set incorrectly - either to
1549 * ESR_DST (!?) or 0. In the process of chasing this with the
1550 * hardware people - not sure if it can happen on any illegal
1551 * instruction or only on FP instructions, whether there is a
1552 * pattern to occurrences etc. -dgibson 31/Mar/2003
1554 if (!emulate_math(regs
))
1557 /* Try to emulate it if we should. */
1558 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1559 switch (emulate_instruction(regs
)) {
1562 emulate_single_step(regs
);
1565 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1571 if (reason
& REASON_PRIVILEGED
)
1572 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1574 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1577 exception_exit(prev_state
);
1579 NOKPROBE_SYMBOL(program_check_exception
);
1582 * This occurs when running in hypervisor mode on POWER6 or later
1583 * and an illegal instruction is encountered.
1585 void emulation_assist_interrupt(struct pt_regs
*regs
)
1587 regs
->msr
|= REASON_ILLEGAL
;
1588 program_check_exception(regs
);
1590 NOKPROBE_SYMBOL(emulation_assist_interrupt
);
1592 void alignment_exception(struct pt_regs
*regs
)
1594 enum ctx_state prev_state
= exception_enter();
1595 int sig
, code
, fixed
= 0;
1597 /* We restore the interrupt state now */
1598 if (!arch_irq_disabled_regs(regs
))
1601 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1604 /* we don't implement logging of alignment exceptions */
1605 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1606 fixed
= fix_alignment(regs
);
1609 regs
->nip
+= 4; /* skip over emulated instruction */
1610 emulate_single_step(regs
);
1614 /* Operand address was bad */
1615 if (fixed
== -EFAULT
) {
1622 if (user_mode(regs
))
1623 _exception(sig
, regs
, code
, regs
->dar
);
1625 bad_page_fault(regs
, regs
->dar
, sig
);
1628 exception_exit(prev_state
);
1631 void StackOverflow(struct pt_regs
*regs
)
1633 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1634 current
->comm
, task_pid_nr(current
), regs
->gpr
[1]);
1637 panic("kernel stack overflow");
1640 void stack_overflow_exception(struct pt_regs
*regs
)
1642 enum ctx_state prev_state
= exception_enter();
1644 die("Kernel stack overflow", regs
, SIGSEGV
);
1646 exception_exit(prev_state
);
1649 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1651 enum ctx_state prev_state
= exception_enter();
1653 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1654 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1655 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1657 exception_exit(prev_state
);
1660 void altivec_unavailable_exception(struct pt_regs
*regs
)
1662 enum ctx_state prev_state
= exception_enter();
1664 if (user_mode(regs
)) {
1665 /* A user program has executed an altivec instruction,
1666 but this kernel doesn't support altivec. */
1667 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1671 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1672 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1673 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1676 exception_exit(prev_state
);
1679 void vsx_unavailable_exception(struct pt_regs
*regs
)
1681 if (user_mode(regs
)) {
1682 /* A user program has executed an vsx instruction,
1683 but this kernel doesn't support vsx. */
1684 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1688 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1689 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1690 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1694 static void tm_unavailable(struct pt_regs
*regs
)
1696 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1697 if (user_mode(regs
)) {
1698 current
->thread
.load_tm
++;
1699 regs
->msr
|= MSR_TM
;
1701 tm_restore_sprs(¤t
->thread
);
1705 pr_emerg("Unrecoverable TM Unavailable Exception "
1706 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1707 die("Unrecoverable TM Unavailable Exception", regs
, SIGABRT
);
1710 void facility_unavailable_exception(struct pt_regs
*regs
)
1712 static char *facility_strings
[] = {
1713 [FSCR_FP_LG
] = "FPU",
1714 [FSCR_VECVSX_LG
] = "VMX/VSX",
1715 [FSCR_DSCR_LG
] = "DSCR",
1716 [FSCR_PM_LG
] = "PMU SPRs",
1717 [FSCR_BHRB_LG
] = "BHRB",
1718 [FSCR_TM_LG
] = "TM",
1719 [FSCR_EBB_LG
] = "EBB",
1720 [FSCR_TAR_LG
] = "TAR",
1721 [FSCR_MSGP_LG
] = "MSGP",
1722 [FSCR_SCV_LG
] = "SCV",
1724 char *facility
= "unknown";
1730 hv
= (TRAP(regs
) == 0xf80);
1732 value
= mfspr(SPRN_HFSCR
);
1734 value
= mfspr(SPRN_FSCR
);
1736 status
= value
>> 56;
1737 if ((hv
|| status
>= 2) &&
1738 (status
< ARRAY_SIZE(facility_strings
)) &&
1739 facility_strings
[status
])
1740 facility
= facility_strings
[status
];
1742 /* We should not have taken this interrupt in kernel */
1743 if (!user_mode(regs
)) {
1744 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1745 facility
, status
, regs
->nip
);
1746 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1749 /* We restore the interrupt state now */
1750 if (!arch_irq_disabled_regs(regs
))
1753 if (status
== FSCR_DSCR_LG
) {
1755 * User is accessing the DSCR register using the problem
1756 * state only SPR number (0x03) either through a mfspr or
1757 * a mtspr instruction. If it is a write attempt through
1758 * a mtspr, then we set the inherit bit. This also allows
1759 * the user to write or read the register directly in the
1760 * future by setting via the FSCR DSCR bit. But in case it
1761 * is a read DSCR attempt through a mfspr instruction, we
1762 * just emulate the instruction instead. This code path will
1763 * always emulate all the mfspr instructions till the user
1764 * has attempted at least one mtspr instruction. This way it
1765 * preserves the same behaviour when the user is accessing
1766 * the DSCR through privilege level only SPR number (0x11)
1767 * which is emulated through illegal instruction exception.
1768 * We always leave HFSCR DSCR set.
1770 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1771 pr_err("Failed to fetch the user instruction\n");
1775 /* Write into DSCR (mtspr 0x03, RS) */
1776 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1777 == PPC_INST_MTSPR_DSCR_USER
) {
1778 rd
= (instword
>> 21) & 0x1f;
1779 current
->thread
.dscr
= regs
->gpr
[rd
];
1780 current
->thread
.dscr_inherit
= 1;
1781 current
->thread
.fscr
|= FSCR_DSCR
;
1782 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1785 /* Read from DSCR (mfspr RT, 0x03) */
1786 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1787 == PPC_INST_MFSPR_DSCR_USER
) {
1788 if (emulate_instruction(regs
)) {
1789 pr_err("DSCR based mfspr emulation failed\n");
1793 emulate_single_step(regs
);
1798 if (status
== FSCR_TM_LG
) {
1800 * If we're here then the hardware is TM aware because it
1801 * generated an exception with FSRM_TM set.
1803 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1804 * told us not to do TM, or the kernel is not built with TM
1807 * If both of those things are true, then userspace can spam the
1808 * console by triggering the printk() below just by continually
1809 * doing tbegin (or any TM instruction). So in that case just
1810 * send the process a SIGILL immediately.
1812 if (!cpu_has_feature(CPU_FTR_TM
))
1815 tm_unavailable(regs
);
1819 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1820 hv
? "Hypervisor " : "", facility
, status
, regs
->nip
, regs
->msr
);
1823 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1827 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1829 void fp_unavailable_tm(struct pt_regs
*regs
)
1831 /* Note: This does not handle any kind of FP laziness. */
1833 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1834 regs
->nip
, regs
->msr
);
1836 /* We can only have got here if the task started using FP after
1837 * beginning the transaction. So, the transactional regs are just a
1838 * copy of the checkpointed ones. But, we still need to recheckpoint
1839 * as we're enabling FP for the process; it will return, abort the
1840 * transaction, and probably retry but now with FP enabled. So the
1841 * checkpointed FP registers need to be loaded.
1843 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1846 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1847 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1849 * At this point, ck{fp,vr}_state contains the exact values we want to
1853 /* Enable FP for the task: */
1854 current
->thread
.load_fp
= 1;
1857 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1859 tm_recheckpoint(¤t
->thread
);
1862 void altivec_unavailable_tm(struct pt_regs
*regs
)
1864 /* See the comments in fp_unavailable_tm(). This function operates
1868 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1870 regs
->nip
, regs
->msr
);
1871 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1872 current
->thread
.load_vec
= 1;
1873 tm_recheckpoint(¤t
->thread
);
1874 current
->thread
.used_vr
= 1;
1877 void vsx_unavailable_tm(struct pt_regs
*regs
)
1879 /* See the comments in fp_unavailable_tm(). This works similarly,
1880 * though we're loading both FP and VEC registers in here.
1882 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1883 * regs. Either way, set MSR_VSX.
1886 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1888 regs
->nip
, regs
->msr
);
1890 current
->thread
.used_vsr
= 1;
1892 /* This reclaims FP and/or VR regs if they're already enabled */
1893 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1895 current
->thread
.load_vec
= 1;
1896 current
->thread
.load_fp
= 1;
1898 tm_recheckpoint(¤t
->thread
);
1900 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1902 void performance_monitor_exception(struct pt_regs
*regs
)
1904 __this_cpu_inc(irq_stat
.pmu_irqs
);
1909 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1910 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1914 * Determine the cause of the debug event, clear the
1915 * event flags and send a trap to the handler. Torez
1917 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1918 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1919 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1920 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1922 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
,
1925 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1926 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1927 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
,
1930 } else if (debug_status
& DBSR_IAC1
) {
1931 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1932 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1933 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
,
1936 } else if (debug_status
& DBSR_IAC2
) {
1937 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1938 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
,
1941 } else if (debug_status
& DBSR_IAC3
) {
1942 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1943 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1944 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
,
1947 } else if (debug_status
& DBSR_IAC4
) {
1948 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1949 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
,
1954 * At the point this routine was called, the MSR(DE) was turned off.
1955 * Check all other debug flags and see if that bit needs to be turned
1958 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1959 current
->thread
.debug
.dbcr1
))
1960 regs
->msr
|= MSR_DE
;
1962 /* Make sure the IDM flag is off */
1963 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1966 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1969 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1971 current
->thread
.debug
.dbsr
= debug_status
;
1973 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1974 * on server, it stops on the target of the branch. In order to simulate
1975 * the server behaviour, we thus restart right away with a single step
1976 * instead of stopping here when hitting a BT
1978 if (debug_status
& DBSR_BT
) {
1979 regs
->msr
&= ~MSR_DE
;
1982 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1983 /* Clear the BT event */
1984 mtspr(SPRN_DBSR
, DBSR_BT
);
1986 /* Do the single step trick only when coming from userspace */
1987 if (user_mode(regs
)) {
1988 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1989 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1990 regs
->msr
|= MSR_DE
;
1994 if (kprobe_post_handler(regs
))
1997 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1998 5, SIGTRAP
) == NOTIFY_STOP
) {
2001 if (debugger_sstep(regs
))
2003 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
2004 regs
->msr
&= ~MSR_DE
;
2006 /* Disable instruction completion */
2007 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
2008 /* Clear the instruction completion event */
2009 mtspr(SPRN_DBSR
, DBSR_IC
);
2011 if (kprobe_post_handler(regs
))
2014 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
2015 5, SIGTRAP
) == NOTIFY_STOP
) {
2019 if (debugger_sstep(regs
))
2022 if (user_mode(regs
)) {
2023 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
2024 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
2025 current
->thread
.debug
.dbcr1
))
2026 regs
->msr
|= MSR_DE
;
2028 /* Make sure the IDM bit is off */
2029 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2032 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
2034 handle_debug(regs
, debug_status
);
2036 NOKPROBE_SYMBOL(DebugException
);
2037 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2039 #if !defined(CONFIG_TAU_INT)
2040 void TAUException(struct pt_regs
*regs
)
2042 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
2043 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
2045 #endif /* CONFIG_INT_TAU */
2047 #ifdef CONFIG_ALTIVEC
2048 void altivec_assist_exception(struct pt_regs
*regs
)
2052 if (!user_mode(regs
)) {
2053 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
2054 " at %lx\n", regs
->nip
);
2055 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
2058 flush_altivec_to_thread(current
);
2060 PPC_WARN_EMULATED(altivec
, regs
);
2061 err
= emulate_altivec(regs
);
2063 regs
->nip
+= 4; /* skip emulated instruction */
2064 emulate_single_step(regs
);
2068 if (err
== -EFAULT
) {
2069 /* got an error reading the instruction */
2070 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2072 /* didn't recognize the instruction */
2073 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2074 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
2075 "in %s at %lx\n", current
->comm
, regs
->nip
);
2076 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
2079 #endif /* CONFIG_ALTIVEC */
2081 #ifdef CONFIG_FSL_BOOKE
2082 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
2083 unsigned long error_code
)
2085 /* We treat cache locking instructions from the user
2086 * as priv ops, in the future we could try to do
2089 if (error_code
& (ESR_DLK
|ESR_ILK
))
2090 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
2093 #endif /* CONFIG_FSL_BOOKE */
2096 void SPEFloatingPointException(struct pt_regs
*regs
)
2098 extern int do_spe_mathemu(struct pt_regs
*regs
);
2099 unsigned long spefscr
;
2101 int code
= FPE_FLTUNK
;
2104 /* We restore the interrupt state now */
2105 if (!arch_irq_disabled_regs(regs
))
2108 flush_spe_to_thread(current
);
2110 spefscr
= current
->thread
.spefscr
;
2111 fpexc_mode
= current
->thread
.fpexc_mode
;
2113 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
2116 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
2119 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
2121 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
2124 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
2127 err
= do_spe_mathemu(regs
);
2129 regs
->nip
+= 4; /* skip emulated instruction */
2130 emulate_single_step(regs
);
2134 if (err
== -EFAULT
) {
2135 /* got an error reading the instruction */
2136 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2137 } else if (err
== -EINVAL
) {
2138 /* didn't recognize the instruction */
2139 printk(KERN_ERR
"unrecognized spe instruction "
2140 "in %s at %lx\n", current
->comm
, regs
->nip
);
2142 _exception(SIGFPE
, regs
, code
, regs
->nip
);
2148 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
2150 extern int speround_handler(struct pt_regs
*regs
);
2153 /* We restore the interrupt state now */
2154 if (!arch_irq_disabled_regs(regs
))
2158 if (regs
->msr
& MSR_SPE
)
2159 giveup_spe(current
);
2163 err
= speround_handler(regs
);
2165 regs
->nip
+= 4; /* skip emulated instruction */
2166 emulate_single_step(regs
);
2170 if (err
== -EFAULT
) {
2171 /* got an error reading the instruction */
2172 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2173 } else if (err
== -EINVAL
) {
2174 /* didn't recognize the instruction */
2175 printk(KERN_ERR
"unrecognized spe instruction "
2176 "in %s at %lx\n", current
->comm
, regs
->nip
);
2178 _exception(SIGFPE
, regs
, FPE_FLTUNK
, regs
->nip
);
2185 * We enter here if we get an unrecoverable exception, that is, one
2186 * that happened at a point where the RI (recoverable interrupt) bit
2187 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2188 * we therefore lost state by taking this exception.
2190 void unrecoverable_exception(struct pt_regs
*regs
)
2192 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2193 regs
->trap
, regs
->nip
, regs
->msr
);
2194 die("Unrecoverable exception", regs
, SIGABRT
);
2196 NOKPROBE_SYMBOL(unrecoverable_exception
);
2198 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2200 * Default handler for a Watchdog exception,
2201 * spins until a reboot occurs
2203 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
2205 /* Generic WatchdogHandler, implement your own */
2206 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
2210 void WatchdogException(struct pt_regs
*regs
)
2212 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
2213 WatchdogHandler(regs
);
2218 * We enter here if we discover during exception entry that we are
2219 * running in supervisor mode with a userspace value in the stack pointer.
2221 void kernel_bad_stack(struct pt_regs
*regs
)
2223 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
2224 regs
->gpr
[1], regs
->nip
);
2225 die("Bad kernel stack pointer", regs
, SIGABRT
);
2227 NOKPROBE_SYMBOL(kernel_bad_stack
);
2229 void __init
trap_init(void)
2234 #ifdef CONFIG_PPC_EMULATED_STATS
2236 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2238 struct ppc_emulated ppc_emulated
= {
2239 #ifdef CONFIG_ALTIVEC
2240 WARN_EMULATED_SETUP(altivec
),
2242 WARN_EMULATED_SETUP(dcba
),
2243 WARN_EMULATED_SETUP(dcbz
),
2244 WARN_EMULATED_SETUP(fp_pair
),
2245 WARN_EMULATED_SETUP(isel
),
2246 WARN_EMULATED_SETUP(mcrxr
),
2247 WARN_EMULATED_SETUP(mfpvr
),
2248 WARN_EMULATED_SETUP(multiple
),
2249 WARN_EMULATED_SETUP(popcntb
),
2250 WARN_EMULATED_SETUP(spe
),
2251 WARN_EMULATED_SETUP(string
),
2252 WARN_EMULATED_SETUP(sync
),
2253 WARN_EMULATED_SETUP(unaligned
),
2254 #ifdef CONFIG_MATH_EMULATION
2255 WARN_EMULATED_SETUP(math
),
2258 WARN_EMULATED_SETUP(vsx
),
2261 WARN_EMULATED_SETUP(mfdscr
),
2262 WARN_EMULATED_SETUP(mtdscr
),
2263 WARN_EMULATED_SETUP(lq_stq
),
2264 WARN_EMULATED_SETUP(lxvw4x
),
2265 WARN_EMULATED_SETUP(lxvh8x
),
2266 WARN_EMULATED_SETUP(lxvd2x
),
2267 WARN_EMULATED_SETUP(lxvb16x
),
2271 u32 ppc_warn_emulated
;
2273 void ppc_warn_emulated_print(const char *type
)
2275 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
2279 static int __init
ppc_warn_emulated_init(void)
2281 struct dentry
*dir
, *d
;
2283 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
2285 if (!powerpc_debugfs_root
)
2288 dir
= debugfs_create_dir("emulated_instructions",
2289 powerpc_debugfs_root
);
2293 d
= debugfs_create_u32("do_warn", 0644, dir
,
2294 &ppc_warn_emulated
);
2298 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
2299 d
= debugfs_create_u32(entries
[i
].name
, 0644, dir
,
2300 (u32
*)&entries
[i
].val
.counter
);
2308 debugfs_remove_recursive(dir
);
2312 device_initcall(ppc_warn_emulated_init
);
2314 #endif /* CONFIG_PPC_EMULATED_STATS */