1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2012 Michael Ellerman, IBM Corporation.
4 * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
7 #include <linux/kernel.h>
8 #include <linux/kvm_host.h>
10 #include <linux/kernel_stat.h>
12 #include <asm/kvm_book3s.h>
13 #include <asm/kvm_ppc.h>
14 #include <asm/hvcall.h>
16 #include <asm/synch.h>
17 #include <asm/cputhreads.h>
18 #include <asm/pgtable.h>
19 #include <asm/ppc-opcode.h>
20 #include <asm/pnv-pci.h>
24 #include "book3s_xics.h"
28 int h_ipi_redirect
= 1;
29 EXPORT_SYMBOL(h_ipi_redirect
);
30 int kvm_irq_bypass
= 1;
31 EXPORT_SYMBOL(kvm_irq_bypass
);
33 static void icp_rm_deliver_irq(struct kvmppc_xics
*xics
, struct kvmppc_icp
*icp
,
34 u32 new_irq
, bool check_resend
);
35 static int xics_opal_set_server(unsigned int hw_irq
, int server_cpu
);
37 /* -- ICS routines -- */
38 static void ics_rm_check_resend(struct kvmppc_xics
*xics
,
39 struct kvmppc_ics
*ics
, struct kvmppc_icp
*icp
)
43 for (i
= 0; i
< KVMPPC_XICS_IRQ_PER_ICS
; i
++) {
44 struct ics_irq_state
*state
= &ics
->irq_state
[i
];
46 icp_rm_deliver_irq(xics
, icp
, state
->number
, true);
51 /* -- ICP routines -- */
54 static inline void icp_send_hcore_msg(int hcore
, struct kvm_vcpu
*vcpu
)
58 hcpu
= hcore
<< threads_shift
;
59 kvmppc_host_rm_ops_hv
->rm_core
[hcore
].rm_data
= vcpu
;
60 smp_muxed_ipi_set_message(hcpu
, PPC_MSG_RM_HOST_ACTION
);
61 kvmppc_set_host_ipi(hcpu
);
63 kvmhv_rm_send_ipi(hcpu
);
66 static inline void icp_send_hcore_msg(int hcore
, struct kvm_vcpu
*vcpu
) { }
70 * We start the search from our current CPU Id in the core map
71 * and go in a circle until we get back to our ID looking for a
72 * core that is running in host context and that hasn't already
73 * been targeted for another rm_host_ops.
75 * In the future, could consider using a fairer algorithm (one
76 * that distributes the IPIs better)
78 * Returns -1, if no CPU could be found in the host
79 * Else, returns a CPU Id which has been reserved for use
81 static inline int grab_next_hostcore(int start
,
82 struct kvmppc_host_rm_core
*rm_core
, int max
, int action
)
86 union kvmppc_rm_state old
, new;
88 for (core
= start
+ 1; core
< max
; core
++) {
89 old
= new = READ_ONCE(rm_core
[core
].rm_state
);
91 if (!old
.in_host
|| old
.rm_action
)
94 /* Try to grab this host core if not taken already. */
95 new.rm_action
= action
;
97 success
= cmpxchg64(&rm_core
[core
].rm_state
.raw
,
98 old
.raw
, new.raw
) == old
.raw
;
101 * Make sure that the store to the rm_action is made
102 * visible before we return to caller (and the
103 * subsequent store to rm_data) to synchronize with
114 static inline int find_available_hostcore(int action
)
117 int my_core
= smp_processor_id() >> threads_shift
;
118 struct kvmppc_host_rm_core
*rm_core
= kvmppc_host_rm_ops_hv
->rm_core
;
120 core
= grab_next_hostcore(my_core
, rm_core
, cpu_nr_cores(), action
);
122 core
= grab_next_hostcore(core
, rm_core
, my_core
, action
);
127 static void icp_rm_set_vcpu_irq(struct kvm_vcpu
*vcpu
,
128 struct kvm_vcpu
*this_vcpu
)
130 struct kvmppc_icp
*this_icp
= this_vcpu
->arch
.icp
;
134 /* Mark the target VCPU as having an interrupt pending */
135 vcpu
->stat
.queue_intr
++;
136 set_bit(BOOK3S_IRQPRIO_EXTERNAL
, &vcpu
->arch
.pending_exceptions
);
138 /* Kick self ? Just set MER and return */
139 if (vcpu
== this_vcpu
) {
140 mtspr(SPRN_LPCR
, mfspr(SPRN_LPCR
) | LPCR_MER
);
144 if (xive_enabled() && kvmhv_on_pseries()) {
145 /* No XICS access or hypercalls available, too hard */
146 this_icp
->rm_action
|= XICS_RM_KICK_VCPU
;
147 this_icp
->rm_kick_target
= vcpu
;
152 * Check if the core is loaded,
153 * if not, find an available host core to post to wake the VCPU,
154 * if we can't find one, set up state to eventually return too hard.
156 cpu
= vcpu
->arch
.thread_cpu
;
157 if (cpu
< 0 || cpu
>= nr_cpu_ids
) {
159 if (kvmppc_host_rm_ops_hv
&& h_ipi_redirect
)
160 hcore
= find_available_hostcore(XICS_RM_KICK_VCPU
);
162 icp_send_hcore_msg(hcore
, vcpu
);
164 this_icp
->rm_action
|= XICS_RM_KICK_VCPU
;
165 this_icp
->rm_kick_target
= vcpu
;
171 kvmhv_rm_send_ipi(cpu
);
174 static void icp_rm_clr_vcpu_irq(struct kvm_vcpu
*vcpu
)
176 /* Note: Only called on self ! */
177 clear_bit(BOOK3S_IRQPRIO_EXTERNAL
, &vcpu
->arch
.pending_exceptions
);
178 mtspr(SPRN_LPCR
, mfspr(SPRN_LPCR
) & ~LPCR_MER
);
181 static inline bool icp_rm_try_update(struct kvmppc_icp
*icp
,
182 union kvmppc_icp_state old
,
183 union kvmppc_icp_state
new)
185 struct kvm_vcpu
*this_vcpu
= local_paca
->kvm_hstate
.kvm_vcpu
;
188 /* Calculate new output value */
189 new.out_ee
= (new.xisr
&& (new.pending_pri
< new.cppr
));
191 /* Attempt atomic update */
192 success
= cmpxchg64(&icp
->state
.raw
, old
.raw
, new.raw
) == old
.raw
;
197 * Check for output state update
199 * Note that this is racy since another processor could be updating
200 * the state already. This is why we never clear the interrupt output
201 * here, we only ever set it. The clear only happens prior to doing
202 * an update and only by the processor itself. Currently we do it
203 * in Accept (H_XIRR) and Up_Cppr (H_XPPR).
205 * We also do not try to figure out whether the EE state has changed,
206 * we unconditionally set it if the new state calls for it. The reason
207 * for that is that we opportunistically remove the pending interrupt
208 * flag when raising CPPR, so we need to set it back here if an
209 * interrupt is still pending.
212 icp_rm_set_vcpu_irq(icp
->vcpu
, this_vcpu
);
214 /* Expose the state change for debug purposes */
215 this_vcpu
->arch
.icp
->rm_dbgstate
= new;
216 this_vcpu
->arch
.icp
->rm_dbgtgt
= icp
->vcpu
;
222 static inline int check_too_hard(struct kvmppc_xics
*xics
,
223 struct kvmppc_icp
*icp
)
225 return (xics
->real_mode_dbg
|| icp
->rm_action
) ? H_TOO_HARD
: H_SUCCESS
;
228 static void icp_rm_check_resend(struct kvmppc_xics
*xics
,
229 struct kvmppc_icp
*icp
)
233 /* Order this load with the test for need_resend in the caller */
235 for_each_set_bit(icsid
, icp
->resend_map
, xics
->max_icsid
+ 1) {
236 struct kvmppc_ics
*ics
= xics
->ics
[icsid
];
238 if (!test_and_clear_bit(icsid
, icp
->resend_map
))
242 ics_rm_check_resend(xics
, ics
, icp
);
246 static bool icp_rm_try_to_deliver(struct kvmppc_icp
*icp
, u32 irq
, u8 priority
,
249 union kvmppc_icp_state old_state
, new_state
;
253 old_state
= new_state
= READ_ONCE(icp
->state
);
257 /* See if we can deliver */
258 success
= new_state
.cppr
> priority
&&
259 new_state
.mfrr
> priority
&&
260 new_state
.pending_pri
> priority
;
263 * If we can, check for a rejection and perform the
267 *reject
= new_state
.xisr
;
268 new_state
.xisr
= irq
;
269 new_state
.pending_pri
= priority
;
272 * If we failed to deliver we set need_resend
273 * so a subsequent CPPR state change causes us
274 * to try a new delivery.
276 new_state
.need_resend
= true;
279 } while (!icp_rm_try_update(icp
, old_state
, new_state
));
284 static void icp_rm_deliver_irq(struct kvmppc_xics
*xics
, struct kvmppc_icp
*icp
,
285 u32 new_irq
, bool check_resend
)
287 struct ics_irq_state
*state
;
288 struct kvmppc_ics
*ics
;
293 * This is used both for initial delivery of an interrupt and
294 * for subsequent rejection.
296 * Rejection can be racy vs. resends. We have evaluated the
297 * rejection in an atomic ICP transaction which is now complete,
298 * so potentially the ICP can already accept the interrupt again.
300 * So we need to retry the delivery. Essentially the reject path
301 * boils down to a failed delivery. Always.
303 * Now the interrupt could also have moved to a different target,
304 * thus we may need to re-do the ICP lookup as well
308 /* Get the ICS state and lock it */
309 ics
= kvmppc_xics_find_ics(xics
, new_irq
, &src
);
311 /* Unsafe increment, but this does not need to be accurate */
315 state
= &ics
->irq_state
[src
];
317 /* Get a lock on the ICS */
318 arch_spin_lock(&ics
->lock
);
321 if (!icp
|| state
->server
!= icp
->server_num
) {
322 icp
= kvmppc_xics_find_server(xics
->kvm
, state
->server
);
324 /* Unsafe increment again*/
334 /* Clear the resend bit of that interrupt */
338 * If masked, bail out
340 * Note: PAPR doesn't mention anything about masked pending
341 * when doing a resend, only when doing a delivery.
343 * However that would have the effect of losing a masked
344 * interrupt that was rejected and isn't consistent with
345 * the whole masked_pending business which is about not
346 * losing interrupts that occur while masked.
348 * I don't differentiate normal deliveries and resends, this
349 * implementation will differ from PAPR and not lose such
352 if (state
->priority
== MASKED
) {
353 state
->masked_pending
= 1;
358 * Try the delivery, this will set the need_resend flag
359 * in the ICP as part of the atomic transaction if the
360 * delivery is not possible.
362 * Note that if successful, the new delivery might have itself
363 * rejected an interrupt that was "delivered" before we took the
366 * In this case we do the whole sequence all over again for the
367 * new guy. We cannot assume that the rejected interrupt is less
368 * favored than the new one, and thus doesn't need to be delivered,
369 * because by the time we exit icp_rm_try_to_deliver() the target
370 * processor may well have already consumed & completed it, and thus
371 * the rejected interrupt might actually be already acceptable.
373 if (icp_rm_try_to_deliver(icp
, new_irq
, state
->priority
, &reject
)) {
375 * Delivery was successful, did we reject somebody else ?
377 if (reject
&& reject
!= XICS_IPI
) {
378 arch_spin_unlock(&ics
->lock
);
386 * We failed to deliver the interrupt we need to set the
387 * resend map bit and mark the ICS state as needing a resend
392 * Make sure when checking resend, we don't miss the resend
393 * if resend_map bit is seen and cleared.
396 set_bit(ics
->icsid
, icp
->resend_map
);
399 * If the need_resend flag got cleared in the ICP some time
400 * between icp_rm_try_to_deliver() atomic update and now, then
401 * we know it might have missed the resend_map bit. So we
405 if (!icp
->state
.need_resend
) {
407 arch_spin_unlock(&ics
->lock
);
413 arch_spin_unlock(&ics
->lock
);
416 static void icp_rm_down_cppr(struct kvmppc_xics
*xics
, struct kvmppc_icp
*icp
,
419 union kvmppc_icp_state old_state
, new_state
;
423 * This handles several related states in one operation:
425 * ICP State: Down_CPPR
427 * Load CPPR with new value and if the XISR is 0
428 * then check for resends:
432 * If MFRR is more favored than CPPR, check for IPIs
433 * and notify ICS of a potential resend. This is done
434 * asynchronously (when used in real mode, we will have
437 * We do not handle the complete Check_IPI as documented
438 * here. In the PAPR, this state will be used for both
439 * Set_MFRR and Down_CPPR. However, we know that we aren't
440 * changing the MFRR state here so we don't need to handle
441 * the case of an MFRR causing a reject of a pending irq,
442 * this will have been handled when the MFRR was set in the
445 * Thus we don't have to handle rejects, only resends.
447 * When implementing real mode for HV KVM, resend will lead to
448 * a H_TOO_HARD return and the whole transaction will be handled
452 old_state
= new_state
= READ_ONCE(icp
->state
);
455 new_state
.cppr
= new_cppr
;
458 * Cut down Resend / Check_IPI / IPI
460 * The logic is that we cannot have a pending interrupt
461 * trumped by an IPI at this point (see above), so we
462 * know that either the pending interrupt is already an
463 * IPI (in which case we don't care to override it) or
464 * it's either more favored than us or non existent
466 if (new_state
.mfrr
< new_cppr
&&
467 new_state
.mfrr
<= new_state
.pending_pri
) {
468 new_state
.pending_pri
= new_state
.mfrr
;
469 new_state
.xisr
= XICS_IPI
;
472 /* Latch/clear resend bit */
473 resend
= new_state
.need_resend
;
474 new_state
.need_resend
= 0;
476 } while (!icp_rm_try_update(icp
, old_state
, new_state
));
479 * Now handle resend checks. Those are asynchronous to the ICP
480 * state update in HW (ie bus transactions) so we can handle them
481 * separately here as well.
484 icp
->n_check_resend
++;
485 icp_rm_check_resend(xics
, icp
);
490 unsigned long xics_rm_h_xirr(struct kvm_vcpu
*vcpu
)
492 union kvmppc_icp_state old_state
, new_state
;
493 struct kvmppc_xics
*xics
= vcpu
->kvm
->arch
.xics
;
494 struct kvmppc_icp
*icp
= vcpu
->arch
.icp
;
497 if (!xics
|| !xics
->real_mode
)
500 /* First clear the interrupt */
501 icp_rm_clr_vcpu_irq(icp
->vcpu
);
504 * ICP State: Accept_Interrupt
506 * Return the pending interrupt (if any) along with the
507 * current CPPR, then clear the XISR & set CPPR to the
511 old_state
= new_state
= READ_ONCE(icp
->state
);
513 xirr
= old_state
.xisr
| (((u32
)old_state
.cppr
) << 24);
516 new_state
.cppr
= new_state
.pending_pri
;
517 new_state
.pending_pri
= 0xff;
520 } while (!icp_rm_try_update(icp
, old_state
, new_state
));
522 /* Return the result in GPR4 */
523 vcpu
->arch
.regs
.gpr
[4] = xirr
;
525 return check_too_hard(xics
, icp
);
528 int xics_rm_h_ipi(struct kvm_vcpu
*vcpu
, unsigned long server
,
531 union kvmppc_icp_state old_state
, new_state
;
532 struct kvmppc_xics
*xics
= vcpu
->kvm
->arch
.xics
;
533 struct kvmppc_icp
*icp
, *this_icp
= vcpu
->arch
.icp
;
538 if (!xics
|| !xics
->real_mode
)
541 local
= this_icp
->server_num
== server
;
545 icp
= kvmppc_xics_find_server(vcpu
->kvm
, server
);
550 * ICP state: Set_MFRR
552 * If the CPPR is more favored than the new MFRR, then
553 * nothing needs to be done as there can be no XISR to
556 * ICP state: Check_IPI
558 * If the CPPR is less favored, then we might be replacing
559 * an interrupt, and thus need to possibly reject it.
563 * Besides rejecting any pending interrupts, we also
564 * update XISR and pending_pri to mark IPI as pending.
566 * PAPR does not describe this state, but if the MFRR is being
567 * made less favored than its earlier value, there might be
568 * a previously-rejected interrupt needing to be resent.
569 * Ideally, we would want to resend only if
570 * prio(pending_interrupt) < mfrr &&
571 * prio(pending_interrupt) < cppr
572 * where pending interrupt is the one that was rejected. But
573 * we don't have that state, so we simply trigger a resend
574 * whenever the MFRR is made less favored.
577 old_state
= new_state
= READ_ONCE(icp
->state
);
580 new_state
.mfrr
= mfrr
;
585 if (mfrr
< new_state
.cppr
) {
586 /* Reject a pending interrupt if not an IPI */
587 if (mfrr
<= new_state
.pending_pri
) {
588 reject
= new_state
.xisr
;
589 new_state
.pending_pri
= mfrr
;
590 new_state
.xisr
= XICS_IPI
;
594 if (mfrr
> old_state
.mfrr
) {
595 resend
= new_state
.need_resend
;
596 new_state
.need_resend
= 0;
598 } while (!icp_rm_try_update(icp
, old_state
, new_state
));
600 /* Handle reject in real mode */
601 if (reject
&& reject
!= XICS_IPI
) {
602 this_icp
->n_reject
++;
603 icp_rm_deliver_irq(xics
, icp
, reject
, false);
606 /* Handle resends in real mode */
608 this_icp
->n_check_resend
++;
609 icp_rm_check_resend(xics
, icp
);
612 return check_too_hard(xics
, this_icp
);
615 int xics_rm_h_cppr(struct kvm_vcpu
*vcpu
, unsigned long cppr
)
617 union kvmppc_icp_state old_state
, new_state
;
618 struct kvmppc_xics
*xics
= vcpu
->kvm
->arch
.xics
;
619 struct kvmppc_icp
*icp
= vcpu
->arch
.icp
;
622 if (!xics
|| !xics
->real_mode
)
626 * ICP State: Set_CPPR
628 * We can safely compare the new value with the current
629 * value outside of the transaction as the CPPR is only
630 * ever changed by the processor on itself
632 if (cppr
> icp
->state
.cppr
) {
633 icp_rm_down_cppr(xics
, icp
, cppr
);
635 } else if (cppr
== icp
->state
.cppr
)
641 * The processor is raising its priority, this can result
642 * in a rejection of a pending interrupt:
644 * ICP State: Reject_Current
646 * We can remove EE from the current processor, the update
647 * transaction will set it again if needed
649 icp_rm_clr_vcpu_irq(icp
->vcpu
);
652 old_state
= new_state
= READ_ONCE(icp
->state
);
655 new_state
.cppr
= cppr
;
657 if (cppr
<= new_state
.pending_pri
) {
658 reject
= new_state
.xisr
;
660 new_state
.pending_pri
= 0xff;
663 } while (!icp_rm_try_update(icp
, old_state
, new_state
));
666 * Check for rejects. They are handled by doing a new delivery
667 * attempt (see comments in icp_rm_deliver_irq).
669 if (reject
&& reject
!= XICS_IPI
) {
671 icp_rm_deliver_irq(xics
, icp
, reject
, false);
674 return check_too_hard(xics
, icp
);
677 static int ics_rm_eoi(struct kvm_vcpu
*vcpu
, u32 irq
)
679 struct kvmppc_xics
*xics
= vcpu
->kvm
->arch
.xics
;
680 struct kvmppc_icp
*icp
= vcpu
->arch
.icp
;
681 struct kvmppc_ics
*ics
;
682 struct ics_irq_state
*state
;
687 * ICS EOI handling: For LSI, if P bit is still set, we need to
690 * For MSI, we move Q bit into P (and clear Q). If it is set,
694 ics
= kvmppc_xics_find_ics(xics
, irq
, &src
);
698 state
= &ics
->irq_state
[src
];
701 pq_new
= state
->pq_state
;
704 pq_old
= state
->pq_state
;
705 pq_new
= pq_old
>> 1;
706 } while (cmpxchg(&state
->pq_state
, pq_old
, pq_new
) != pq_old
);
708 if (pq_new
& PQ_PRESENTED
)
709 icp_rm_deliver_irq(xics
, NULL
, irq
, false);
711 if (!hlist_empty(&vcpu
->kvm
->irq_ack_notifier_list
)) {
712 icp
->rm_action
|= XICS_RM_NOTIFY_EOI
;
713 icp
->rm_eoied_irq
= irq
;
716 if (state
->host_irq
) {
717 ++vcpu
->stat
.pthru_all
;
718 if (state
->intr_cpu
!= -1) {
719 int pcpu
= raw_smp_processor_id();
721 pcpu
= cpu_first_thread_sibling(pcpu
);
722 ++vcpu
->stat
.pthru_host
;
723 if (state
->intr_cpu
!= pcpu
) {
724 ++vcpu
->stat
.pthru_bad_aff
;
725 xics_opal_set_server(state
->host_irq
, pcpu
);
727 state
->intr_cpu
= -1;
732 return check_too_hard(xics
, icp
);
735 int xics_rm_h_eoi(struct kvm_vcpu
*vcpu
, unsigned long xirr
)
737 struct kvmppc_xics
*xics
= vcpu
->kvm
->arch
.xics
;
738 struct kvmppc_icp
*icp
= vcpu
->arch
.icp
;
739 u32 irq
= xirr
& 0x00ffffff;
741 if (!xics
|| !xics
->real_mode
)
747 * Note: If EOI is incorrectly used by SW to lower the CPPR
748 * value (ie more favored), we do not check for rejection of
749 * a pending interrupt, this is a SW error and PAPR specifies
750 * that we don't have to deal with it.
752 * The sending of an EOI to the ICS is handled after the
755 * ICP State: Down_CPPR which we handle
756 * in a separate function as it's shared with H_CPPR.
758 icp_rm_down_cppr(xics
, icp
, xirr
>> 24);
760 /* IPIs have no EOI */
762 return check_too_hard(xics
, icp
);
764 return ics_rm_eoi(vcpu
, irq
);
767 unsigned long eoi_rc
;
769 static void icp_eoi(struct irq_chip
*c
, u32 hwirq
, __be32 xirr
, bool *again
)
771 void __iomem
*xics_phys
;
774 if (kvmhv_on_pseries()) {
775 unsigned long retbuf
[PLPAR_HCALL_BUFSIZE
];
778 plpar_hcall_raw(H_EOI
, retbuf
, hwirq
);
782 rc
= pnv_opal_pci_msi_eoi(c
, hwirq
);
790 xics_phys
= local_paca
->kvm_hstate
.xics_phys
;
792 __raw_rm_writel(xirr
, xics_phys
+ XICS_XIRR
);
794 rc
= opal_int_eoi(be32_to_cpu(xirr
));
799 static int xics_opal_set_server(unsigned int hw_irq
, int server_cpu
)
801 unsigned int mangle_cpu
= get_hard_smp_processor_id(server_cpu
) << 2;
803 return opal_set_xive(hw_irq
, mangle_cpu
, DEFAULT_PRIORITY
);
807 * Increment a per-CPU 32-bit unsigned integer variable.
808 * Safe to call in real-mode. Handles vmalloc'ed addresses
810 * ToDo: Make this work for any integral type
813 static inline void this_cpu_inc_rm(unsigned int __percpu
*addr
)
817 int cpu
= smp_processor_id();
819 raddr
= per_cpu_ptr(addr
, cpu
);
820 l
= (unsigned long)raddr
;
822 if (get_region_id(l
) == VMALLOC_REGION_ID
) {
823 l
= vmalloc_to_phys(raddr
);
824 raddr
= (unsigned int *)l
;
830 * We don't try to update the flags in the irq_desc 'istate' field in
831 * here as would happen in the normal IRQ handling path for several reasons:
832 * - state flags represent internal IRQ state and are not expected to be
833 * updated outside the IRQ subsystem
834 * - more importantly, these are useful for edge triggered interrupts,
835 * IRQ probing, etc., but we are only handling MSI/MSIx interrupts here
836 * and these states shouldn't apply to us.
838 * However, we do update irq_stats - we somewhat duplicate the code in
839 * kstat_incr_irqs_this_cpu() for this since this function is defined
840 * in irq/internal.h which we don't want to include here.
841 * The only difference is that desc->kstat_irqs is an allocated per CPU
842 * variable and could have been vmalloc'ed, so we can't directly
843 * call __this_cpu_inc() on it. The kstat structure is a static
844 * per CPU variable and it should be accessible by real-mode KVM.
847 static void kvmppc_rm_handle_irq_desc(struct irq_desc
*desc
)
849 this_cpu_inc_rm(desc
->kstat_irqs
);
850 __this_cpu_inc(kstat
.irqs_sum
);
853 long kvmppc_deliver_irq_passthru(struct kvm_vcpu
*vcpu
,
855 struct kvmppc_irq_map
*irq_map
,
856 struct kvmppc_passthru_irqmap
*pimap
,
859 struct kvmppc_xics
*xics
;
860 struct kvmppc_icp
*icp
;
861 struct kvmppc_ics
*ics
;
862 struct ics_irq_state
*state
;
867 irq
= irq_map
->v_hwirq
;
868 xics
= vcpu
->kvm
->arch
.xics
;
869 icp
= vcpu
->arch
.icp
;
871 kvmppc_rm_handle_irq_desc(irq_map
->desc
);
873 ics
= kvmppc_xics_find_ics(xics
, irq
, &src
);
877 state
= &ics
->irq_state
[src
];
879 /* only MSIs register bypass producers, so it must be MSI here */
881 pq_old
= state
->pq_state
;
882 pq_new
= ((pq_old
<< 1) & 3) | PQ_PRESENTED
;
883 } while (cmpxchg(&state
->pq_state
, pq_old
, pq_new
) != pq_old
);
885 /* Test P=1, Q=0, this is the only case where we present */
886 if (pq_new
== PQ_PRESENTED
)
887 icp_rm_deliver_irq(xics
, icp
, irq
, false);
889 /* EOI the interrupt */
890 icp_eoi(irq_desc_get_chip(irq_map
->desc
), irq_map
->r_hwirq
, xirr
,
893 if (check_too_hard(xics
, icp
) == H_TOO_HARD
)
899 /* --- Non-real mode XICS-related built-in routines --- */
902 * Host Operations poked by RM KVM
904 static void rm_host_ipi_action(int action
, void *data
)
907 case XICS_RM_KICK_VCPU
:
908 kvmppc_host_rm_ops_hv
->vcpu_kick(data
);
911 WARN(1, "Unexpected rm_action=%d data=%p\n", action
, data
);
917 void kvmppc_xics_ipi_action(void)
920 unsigned int cpu
= smp_processor_id();
921 struct kvmppc_host_rm_core
*rm_corep
;
923 core
= cpu
>> threads_shift
;
924 rm_corep
= &kvmppc_host_rm_ops_hv
->rm_core
[core
];
926 if (rm_corep
->rm_data
) {
927 rm_host_ipi_action(rm_corep
->rm_state
.rm_action
,
929 /* Order these stores against the real mode KVM */
930 rm_corep
->rm_data
= NULL
;
932 rm_corep
->rm_state
.rm_action
= 0;