2 * arch/sh/math-emu/math.c
4 * Copyright (C) 2006 Takashi YOSHII <takasi-y@ops.dti.ne.jp>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <linux/types.h>
13 #include <linux/sched/signal.h>
14 #include <linux/signal.h>
15 #include <linux/perf_event.h>
17 #include <linux/uaccess.h>
18 #include <asm/processor.h>
22 #include <math-emu/soft-fp.h>
23 #include <math-emu/single.h>
24 #include <math-emu/double.h>
26 #define FPUL (fregs->fpul)
27 #define FPSCR (fregs->fpscr)
28 #define FPSCR_RM (FPSCR&3)
29 #define FPSCR_DN ((FPSCR>>18)&1)
30 #define FPSCR_PR ((FPSCR>>19)&1)
31 #define FPSCR_SZ ((FPSCR>>20)&1)
32 #define FPSCR_FR ((FPSCR>>21)&1)
33 #define FPSCR_MASK 0x003fffffUL
35 #define BANK(n) (n^(FPSCR_FR?16:0))
36 #define FR ((unsigned long*)(fregs->fp_regs))
37 #define FR0 (FR[BANK(0)])
38 #define FRn (FR[BANK(n)])
39 #define FRm (FR[BANK(m)])
40 #define DR ((unsigned long long*)(fregs->fp_regs))
41 #define DRn (DR[BANK(n)/2])
42 #define DRm (DR[BANK(m)/2])
44 #define XREG(n) (n^16)
45 #define XFn (FR[BANK(XREG(n))])
46 #define XFm (FR[BANK(XREG(m))])
47 #define XDn (DR[BANK(XREG(n))/2])
48 #define XDm (DR[BANK(XREG(m))/2])
50 #define R0 (regs->regs[0])
51 #define Rn (regs->regs[n])
52 #define Rm (regs->regs[m])
54 #define WRITE(d,a) ({if(put_user(d, (typeof (d)*)a)) return -EFAULT;})
55 #define READ(d,a) ({if(get_user(d, (typeof (d)*)a)) return -EFAULT;})
57 #define PACK_S(r,f) FP_PACK_SP(&r,f)
58 #define UNPACK_S(f,r) FP_UNPACK_SP(f,&r)
60 {u32 t[2]; FP_PACK_DP(t,f); ((u32*)&r)[0]=t[1]; ((u32*)&r)[1]=t[0];}
61 #define UNPACK_D(f,r) \
62 {u32 t[2]; t[0]=((u32*)&r)[1]; t[1]=((u32*)&r)[0]; FP_UNPACK_DP(f,t);}
64 // 2 args instructions.
65 #define BOTH_PRmn(op,x) \
66 FP_DECL_EX; if(FPSCR_PR) op(D,x,DRm,DRn); else op(S,x,FRm,FRn);
68 #define CMP_X(SZ,R,M,N) do{ \
69 FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
70 UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
71 FP_CMP_##SZ(R, Fn, Fm, 2); }while(0)
72 #define EQ_X(SZ,R,M,N) do{ \
73 FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); \
74 UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
75 FP_CMP_EQ_##SZ(R, Fn, Fm); }while(0)
76 #define CMP(OP) ({ int r; BOTH_PRmn(OP##_X,r); r; })
79 fcmp_gt(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
90 fcmp_eq(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
92 if (CMP(CMP
/*EQ*/) == 0)
99 #define ARITH_X(SZ,OP,M,N) do{ \
100 FP_DECL_##SZ(Fm); FP_DECL_##SZ(Fn); FP_DECL_##SZ(Fr); \
101 UNPACK_##SZ(Fm, M); UNPACK_##SZ(Fn, N); \
102 FP_##OP##_##SZ(Fr, Fn, Fm); \
103 PACK_##SZ(N, Fr); }while(0)
106 fadd(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
108 BOTH_PRmn(ARITH_X
, ADD
);
113 fsub(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
115 BOTH_PRmn(ARITH_X
, SUB
);
120 fmul(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
122 BOTH_PRmn(ARITH_X
, MUL
);
127 fdiv(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
129 BOTH_PRmn(ARITH_X
, DIV
);
134 fmac(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
145 FP_MUL_S(Ft
, Fm
, F0
);
146 FP_ADD_S(Fr
, Fn
, Ft
);
151 // to process fmov's extension (odd n for DR access XD).
152 #define FMOV_EXT(x) if(x&1) x+=16-1
155 fmov_idx_reg(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
160 READ(FRn
, Rm
+ R0
+ 4);
171 fmov_mem_reg(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
187 fmov_inc_reg(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
205 fmov_reg_idx(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
210 WRITE(FRm
, Rn
+ R0
+ 4);
221 fmov_reg_mem(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
237 fmov_reg_dec(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
255 fmov_reg_reg(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
,
270 fnop_mn(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int m
, int n
)
275 // 1 arg instructions.
276 #define NOTYETn(i) static int i(struct sh_fpu_soft_struct *fregs, int n) \
277 { printk( #i " not yet done.\n"); return 0; }
285 #define EMU_FLOAT_X(SZ,N) do { \
287 FP_FROM_INT_##SZ(Fn, FPUL, 32, int); \
288 PACK_##SZ(N, Fn); }while(0)
289 static int ffloat(struct sh_fpu_soft_struct
*fregs
, int n
)
301 #define EMU_FTRC_X(SZ,N) do { \
303 UNPACK_##SZ(Fn, N); \
304 FP_TO_INT_##SZ(FPUL, Fn, 32, 1); }while(0)
305 static int ftrc(struct sh_fpu_soft_struct
*fregs
, int n
)
317 static int fcnvsd(struct sh_fpu_soft_struct
*fregs
, int n
)
323 FP_CONV(D
, S
, 2, 1, Fr
, Fn
);
328 static int fcnvds(struct sh_fpu_soft_struct
*fregs
, int n
)
334 FP_CONV(S
, D
, 1, 2, Fr
, Fn
);
339 static int fxchg(struct sh_fpu_soft_struct
*fregs
, int flag
)
345 static int fsts(struct sh_fpu_soft_struct
*fregs
, int n
)
351 static int flds(struct sh_fpu_soft_struct
*fregs
, int n
)
357 static int fneg(struct sh_fpu_soft_struct
*fregs
, int n
)
359 FRn
^= (1 << (_FP_W_TYPE_SIZE
- 1));
363 static int fabs(struct sh_fpu_soft_struct
*fregs
, int n
)
365 FRn
&= ~(1 << (_FP_W_TYPE_SIZE
- 1));
369 static int fld0(struct sh_fpu_soft_struct
*fregs
, int n
)
375 static int fld1(struct sh_fpu_soft_struct
*fregs
, int n
)
377 FRn
= (_FP_EXPBIAS_S
<< (_FP_FRACBITS_S
- 1));
381 static int fnop_n(struct sh_fpu_soft_struct
*fregs
, int n
)
386 /// Instruction decoders.
388 static int id_fxfd(struct sh_fpu_soft_struct
*, int);
389 static int id_fnxd(struct sh_fpu_soft_struct
*, struct pt_regs
*, int, int);
391 static int (*fnxd
[])(struct sh_fpu_soft_struct
*, int) = {
392 fsts
, flds
, ffloat
, ftrc
, fneg
, fabs
, fsqrt
, fsrra
,
393 fld0
, fld1
, fcnvsd
, fcnvds
, fnop_n
, fnop_n
, fipr
, id_fxfd
396 static int (*fnmx
[])(struct sh_fpu_soft_struct
*, struct pt_regs
*, int, int) = {
397 fadd
, fsub
, fmul
, fdiv
, fcmp_eq
, fcmp_gt
, fmov_idx_reg
, fmov_reg_idx
,
398 fmov_mem_reg
, fmov_inc_reg
, fmov_reg_mem
, fmov_reg_dec
,
399 fmov_reg_reg
, id_fnxd
, fmac
, fnop_mn
};
401 static int id_fxfd(struct sh_fpu_soft_struct
*fregs
, int x
)
403 const int flag
[] = { FPSCR_SZ
, FPSCR_PR
, FPSCR_FR
, 0 };
406 fxchg(fregs
, flag
[x
>> 2]);
418 id_fnxd(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, int x
, int n
)
420 return (fnxd
[x
])(fregs
, n
);
424 id_fnmx(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, u16 code
)
426 int n
= (code
>> 8) & 0xf, m
= (code
>> 4) & 0xf, x
= code
& 0xf;
427 return (fnmx
[x
])(fregs
, regs
, m
, n
);
431 id_sys(struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
, u16 code
)
433 int n
= ((code
>> 8) & 0xf);
434 unsigned long *reg
= (code
& 0x0010) ? &FPUL
: &FPSCR
;
436 switch (code
& 0xf0ff) {
462 static int fpu_emulate(u16 code
, struct sh_fpu_soft_struct
*fregs
, struct pt_regs
*regs
)
464 if ((code
& 0xf000) == 0xf000)
465 return id_fnmx(fregs
, regs
, code
);
467 return id_sys(fregs
, regs
, code
);
471 * denormal_to_double - Given denormalized float number,
474 * @fpu: Pointer to sh_fpu_soft structure
475 * @n: Index to FP register
477 static void denormal_to_double(struct sh_fpu_soft_struct
*fpu
, int n
)
479 unsigned long du
, dl
;
480 unsigned long x
= fpu
->fpul
;
481 int exp
= 1023 - 126;
483 if (x
!= 0 && (x
& 0x7f800000) == 0) {
484 du
= (x
& 0x80000000);
485 while ((x
& 0x00800000) == 0) {
490 du
|= (exp
<< 20) | (x
>> 3);
493 fpu
->fp_regs
[n
] = du
;
494 fpu
->fp_regs
[n
+1] = dl
;
499 * ieee_fpe_handler - Handle denormalized number exception
501 * @regs: Pointer to register structure
503 * Returns 1 when it's handled (should not cause exception).
505 static int ieee_fpe_handler(struct pt_regs
*regs
)
507 unsigned short insn
= *(unsigned short *)regs
->pc
;
508 unsigned short finsn
;
509 unsigned long nextpc
;
517 (nib
[0] == 0x4 && nib
[2] == 0x0 && nib
[3] == 0xb)) /* bsr & jsr */
518 regs
->pr
= regs
->pc
+ 4;
520 if (nib
[0] == 0xa || nib
[0] == 0xb) { /* bra & bsr */
521 nextpc
= regs
->pc
+ 4 + ((short) ((insn
& 0xfff) << 4) >> 3);
522 finsn
= *(unsigned short *) (regs
->pc
+ 2);
523 } else if (nib
[0] == 0x8 && nib
[1] == 0xd) { /* bt/s */
525 nextpc
= regs
->pc
+ 4 + ((char) (insn
& 0xff) << 1);
527 nextpc
= regs
->pc
+ 4;
528 finsn
= *(unsigned short *) (regs
->pc
+ 2);
529 } else if (nib
[0] == 0x8 && nib
[1] == 0xf) { /* bf/s */
531 nextpc
= regs
->pc
+ 4;
533 nextpc
= regs
->pc
+ 4 + ((char) (insn
& 0xff) << 1);
534 finsn
= *(unsigned short *) (regs
->pc
+ 2);
535 } else if (nib
[0] == 0x4 && nib
[3] == 0xb &&
536 (nib
[2] == 0x0 || nib
[2] == 0x2)) { /* jmp & jsr */
537 nextpc
= regs
->regs
[nib
[1]];
538 finsn
= *(unsigned short *) (regs
->pc
+ 2);
539 } else if (nib
[0] == 0x0 && nib
[3] == 0x3 &&
540 (nib
[2] == 0x0 || nib
[2] == 0x2)) { /* braf & bsrf */
541 nextpc
= regs
->pc
+ 4 + regs
->regs
[nib
[1]];
542 finsn
= *(unsigned short *) (regs
->pc
+ 2);
543 } else if (insn
== 0x000b) { /* rts */
545 finsn
= *(unsigned short *) (regs
->pc
+ 2);
547 nextpc
= regs
->pc
+ 2;
551 if ((finsn
& 0xf1ff) == 0xf0ad) { /* fcnvsd */
552 struct task_struct
*tsk
= current
;
554 if ((tsk
->thread
.xstate
->softfpu
.fpscr
& (1 << 17))) {
556 denormal_to_double (&tsk
->thread
.xstate
->softfpu
,
558 tsk
->thread
.xstate
->softfpu
.fpscr
&=
559 ~(FPSCR_CAUSE_MASK
| FPSCR_FLAG_MASK
);
560 task_thread_info(tsk
)->status
|= TS_USEDFPU
;
562 force_sig_fault(SIGFPE
, FPE_FLTINV
,
563 (void __user
*)regs
->pc
);
574 * fpu_init - Initialize FPU registers
575 * @fpu: Pointer to software emulated FPU registers.
577 static void fpu_init(struct sh_fpu_soft_struct
*fpu
)
581 fpu
->fpscr
= FPSCR_INIT
;
584 for (i
= 0; i
< 16; i
++) {
591 * do_fpu_inst - Handle reserved instructions for FPU emulation
592 * @inst: instruction code.
593 * @regs: registers on stack.
595 int do_fpu_inst(unsigned short inst
, struct pt_regs
*regs
)
597 struct task_struct
*tsk
= current
;
598 struct sh_fpu_soft_struct
*fpu
= &(tsk
->thread
.xstate
->softfpu
);
600 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, regs
, 0);
602 if (!(task_thread_info(tsk
)->status
& TS_USEDFPU
)) {
603 /* initialize once. */
605 task_thread_info(tsk
)->status
|= TS_USEDFPU
;
608 return fpu_emulate(inst
, fpu
, regs
);