arch/x86/kvm/mmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_MMU_H
   3 #define __KVM_X86_MMU_H
   4
   5 #include <linux/kvm_host.h>
   6 #include "kvm_cache_regs.h"
   7
   8 #define PT64_PT_BITS 9
   9 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
  10 #define PT32_PT_BITS 10
  11 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
  12
  13 #define PT_WRITABLE_SHIFT 1
  14 #define PT_USER_SHIFT 2
  15
  16 #define PT_PRESENT_MASK (1ULL << 0)
  17 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
  18 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
  19 #define PT_PWT_MASK (1ULL << 3)
  20 #define PT_PCD_MASK (1ULL << 4)
  21 #define PT_ACCESSED_SHIFT 5
  22 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
  23 #define PT_DIRTY_SHIFT 6
  24 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
  25 #define PT_PAGE_SIZE_SHIFT 7
  26 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
  27 #define PT_PAT_MASK (1ULL << 7)
  28 #define PT_GLOBAL_MASK (1ULL << 8)
  29 #define PT64_NX_SHIFT 63
  30 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
  31
  32 #define PT_PAT_SHIFT 7
  33 #define PT_DIR_PAT_SHIFT 12
  34 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
  35
  36 #define PT32_DIR_PSE36_SIZE 4
  37 #define PT32_DIR_PSE36_SHIFT 13
  38 #define PT32_DIR_PSE36_MASK \
  39         (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
  40
  41 #define PT64_ROOT_5LEVEL 5
  42 #define PT64_ROOT_4LEVEL 4
  43 #define PT32_ROOT_LEVEL 2
  44 #define PT32E_ROOT_LEVEL 3
  45
  46 static inline u64 rsvd_bits(int s, int e)
  47 {
  48         if (e < s)
  49                 return 0;
  50
  51         return ((1ULL << (e - s + 1)) - 1) << s;
  52 }
  53
  54 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value, u64 access_mask);
  55
  56 void
  57 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
  58
  59 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots);
  60 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
  61 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
  62                              bool accessed_dirty, gpa_t new_eptp);
  63 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
  64 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
  65                                 u64 fault_address, char *insn, int insn_len);
  66
  67 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
  68 {
  69         if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
  70                 return kvm->arch.n_max_mmu_pages -
  71                         kvm->arch.n_used_mmu_pages;
  72
  73         return 0;
  74 }
  75
  76 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
  77 {
  78         if (likely(vcpu->arch.mmu->root_hpa != INVALID_PAGE))
  79                 return 0;
  80
  81         return kvm_mmu_load(vcpu);
  82 }
  83
  84 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
  85 {
  86         BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
  87
  88         return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
  89                ? cr3 & X86_CR3_PCID_MASK
  90                : 0;
  91 }
  92
  93 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
  94 {
  95         return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
  96 }
  97
  98 static inline void kvm_mmu_load_cr3(struct kvm_vcpu *vcpu)
  99 {
 100         if (VALID_PAGE(vcpu->arch.mmu->root_hpa))
 101                 vcpu->arch.mmu->set_cr3(vcpu, vcpu->arch.mmu->root_hpa |
 102                                               kvm_get_active_pcid(vcpu));
 103 }
 104
 105 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
 106                        bool prefault);
 107
 108 static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
 109                                         u32 err, bool prefault)
 110 {
 111 #ifdef CONFIG_RETPOLINE
 112         if (likely(vcpu->arch.mmu->page_fault == kvm_tdp_page_fault))
 113                 return kvm_tdp_page_fault(vcpu, cr2_or_gpa, err, prefault);
 114 #endif
 115         return vcpu->arch.mmu->page_fault(vcpu, cr2_or_gpa, err, prefault);
 116 }
 117
 118 /*
 119  * Currently, we have two sorts of write-protection, a) the first one
 120  * write-protects guest page to sync the guest modification, b) another one is
 121  * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
 122  * between these two sorts are:
 123  * 1) the first case clears SPTE_MMU_WRITEABLE bit.
 124  * 2) the first case requires flushing tlb immediately avoiding corrupting
 125  *    shadow page table between all vcpus so it should be in the protection of
 126  *    mmu-lock. And the another case does not need to flush tlb until returning
 127  *    the dirty bitmap to userspace since it only write-protects the page
 128  *    logged in the bitmap, that means the page in the dirty bitmap is not
 129  *    missed, so it can flush tlb out of mmu-lock.
 130  *
 131  * So, there is the problem: the first case can meet the corrupted tlb caused
 132  * by another case which write-protects pages but without flush tlb
 133  * immediately. In order to making the first case be aware this problem we let
 134  * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
 135  * is set, it works since another case never touches SPTE_MMU_WRITEABLE bit.
 136  *
 137  * Anyway, whenever a spte is updated (only permission and status bits are
 138  * changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes
 139  * readonly, if that happens, we need to flush tlb. Fortunately,
 140  * mmu_spte_update() has already handled it perfectly.
 141  *
 142  * The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK:
 143  * - if we want to see if it has writable tlb entry or if the spte can be
 144  *   writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most
 145  *   case, otherwise
 146  * - if we fix page fault on the spte or do write-protection by dirty logging,
 147  *   check PT_WRITABLE_MASK.
 148  *
 149  * TODO: introduce APIs to split these two cases.
 150  */
 151 static inline int is_writable_pte(unsigned long pte)
 152 {
 153         return pte & PT_WRITABLE_MASK;
 154 }
 155
 156 static inline bool is_write_protection(struct kvm_vcpu *vcpu)
 157 {
 158         return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
 159 }
 160
 161 /*
 162  * Check if a given access (described through the I/D, W/R and U/S bits of a
 163  * page fault error code pfec) causes a permission fault with the given PTE
 164  * access rights (in ACC_* format).
 165  *
 166  * Return zero if the access does not fault; return the page fault error code
 167  * if the access faults.
 168  */
 169 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 170                                   unsigned pte_access, unsigned pte_pkey,
 171                                   unsigned pfec)
 172 {
 173         int cpl = kvm_x86_ops->get_cpl(vcpu);
 174         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
 175
 176         /*
 177          * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
 178          *
 179          * If CPL = 3, SMAP applies to all supervisor-mode data accesses
 180          * (these are implicit supervisor accesses) regardless of the value
 181          * of EFLAGS.AC.
 182          *
 183          * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
 184          * the result in X86_EFLAGS_AC. We then insert it in place of
 185          * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
 186          * but it will be one in index if SMAP checks are being overridden.
 187          * It is important to keep this branchless.
 188          */
 189         unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
 190         int index = (pfec >> 1) +
 191                     (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
 192         bool fault = (mmu->permissions[index] >> pte_access) & 1;
 193         u32 errcode = PFERR_PRESENT_MASK;
 194
 195         WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
 196         if (unlikely(mmu->pkru_mask)) {
 197                 u32 pkru_bits, offset;
 198
 199                 /*
 200                 * PKRU defines 32 bits, there are 16 domains and 2
 201                 * attribute bits per domain in pkru.  pte_pkey is the
 202                 * index of the protection domain, so pte_pkey * 2 is
 203                 * is the index of the first bit for the domain.
 204                 */
 205                 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
 206
 207                 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
 208                 offset = (pfec & ~1) +
 209                         ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
 210
 211                 pkru_bits &= mmu->pkru_mask >> offset;
 212                 errcode |= -pkru_bits & PFERR_PK_MASK;
 213                 fault |= (pkru_bits != 0);
 214         }
 215
 216         return -(u32)fault & errcode;
 217 }
 218
 219 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
 220
 221 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
 222 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
 223 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
 224                                     struct kvm_memory_slot *slot, u64 gfn);
 225 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
 226
 227 int kvm_mmu_post_init_vm(struct kvm *kvm);
 228 void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
 229
 230 #endif