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arm64: dts: Revert "specify console via command line"
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-xiic.c
blob90c1c362394d099e7af64276e507999bdb49a692
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
6 *
7 * This code was implemented by Mocean Laboratories AB when porting linux
8 * to the automotive development board Russellville. The copyright holder
9 * as seen in the header is Intel corporation.
10 * Mocean Laboratories forked off the GNU/Linux platform work into a
11 * separate company called Pelagicore AB, which committed the code to the
12 * kernel.
13 */
14
15 /* Supports:
16 * Xilinx IIC
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/wait.h>
27 #include <linux/platform_data/i2c-xiic.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/of.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33
34 #define DRIVER_NAME "xiic-i2c"
35
36 enum xilinx_i2c_state {
37 STATE_DONE,
38 STATE_ERROR,
39 STATE_START
40 };
41
42 enum xiic_endian {
43 LITTLE,
44 BIG
45 };
46
47 /**
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
49 * @dev: Pointer to device structure
50 * @base: Memory base of the HW registers
51 * @wait: Wait queue for callers
52 * @adap: Kernel adapter representation
53 * @tx_msg: Messages from above to be sent
54 * @lock: Mutual exclusion
55 * @tx_pos: Current pos in TX message
56 * @nmsgs: Number of messages in tx_msg
57 * @state: See STATE_
58 * @rx_msg: Current RX message
59 * @rx_pos: Position within current RX message
60 * @endianness: big/little-endian byte order
61 * @clk: Pointer to AXI4-lite input clock
62 */
63 struct xiic_i2c {
64 struct device *dev;
65 void __iomem *base;
66 wait_queue_head_t wait;
67 struct i2c_adapter adap;
68 struct i2c_msg *tx_msg;
69 struct mutex lock;
70 unsigned int tx_pos;
71 unsigned int nmsgs;
72 enum xilinx_i2c_state state;
73 struct i2c_msg *rx_msg;
74 int rx_pos;
75 enum xiic_endian endianness;
76 struct clk *clk;
77 };
78
79
80 #define XIIC_MSB_OFFSET 0
81 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
82
83 /*
84 * Register offsets in bytes from RegisterBase. Three is added to the
85 * base offset to access LSB (IBM style) of the word
86 */
87 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
88 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
89 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
90 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
91 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
92 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
93 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
94 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
95 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
96 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
97
98 /* Control Register masks */
99 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
100 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
101 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
102 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
103 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
104 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
105 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
106
107 /* Status Register masks */
108 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
109 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
110 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
111 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
112 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
113 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
114 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
115 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
116
117 /* Interrupt Status Register masks Interrupt occurs when... */
118 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
119 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
120 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
121 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
122 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
123 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
124 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
125 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
126
127 /* The following constants specify the depth of the FIFOs */
128 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
129 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
130
131 /* The following constants specify groups of interrupts that are typically
132 * enabled or disables at the same time
133 */
134 #define XIIC_TX_INTERRUPTS \
135 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
136
137 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
138
139 /*
140 * Tx Fifo upper bit masks.
141 */
142 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
143 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
144
145 /*
146 * The following constants define the register offsets for the Interrupt
147 * registers. There are some holes in the memory map for reserved addresses
148 * to allow other registers to be added and still match the memory map of the
149 * interrupt controller registers
150 */
151 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
152 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
153 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
154 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
155
156 #define XIIC_RESET_MASK 0xAUL
157
158 #define XIIC_PM_TIMEOUT 1000 /* ms */
159 /* timeout waiting for the controller to respond */
160 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
161 /*
162 * The following constant is used for the device global interrupt enable
163 * register, to enable all interrupts for the device, this is the only bit
164 * in the register
165 */
166 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
167
168 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
169 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
170
171 static int xiic_start_xfer(struct xiic_i2c *i2c);
172 static void __xiic_start_xfer(struct xiic_i2c *i2c);
173
174 /*
175 * For the register read and write functions, a little-endian and big-endian
176 * version are necessary. Endianness is detected during the probe function.
177 * Only the least significant byte [doublet] of the register are ever
178 * accessed. This requires an offset of 3 [2] from the base address for
179 * big-endian systems.
180 */
181
182 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
183 {
184 if (i2c->endianness == LITTLE)
185 iowrite8(value, i2c->base + reg);
186 else
187 iowrite8(value, i2c->base + reg + 3);
188 }
189
190 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
191 {
192 u8 ret;
193
194 if (i2c->endianness == LITTLE)
195 ret = ioread8(i2c->base + reg);
196 else
197 ret = ioread8(i2c->base + reg + 3);
198 return ret;
199 }
200
201 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
202 {
203 if (i2c->endianness == LITTLE)
204 iowrite16(value, i2c->base + reg);
205 else
206 iowrite16be(value, i2c->base + reg + 2);
207 }
208
209 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
210 {
211 if (i2c->endianness == LITTLE)
212 iowrite32(value, i2c->base + reg);
213 else
214 iowrite32be(value, i2c->base + reg);
215 }
216
217 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
218 {
219 u32 ret;
220
221 if (i2c->endianness == LITTLE)
222 ret = ioread32(i2c->base + reg);
223 else
224 ret = ioread32be(i2c->base + reg);
225 return ret;
226 }
227
228 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
229 {
230 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
231 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
232 }
233
234 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
235 {
236 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
237 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
238 }
239
240 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
241 {
242 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
243 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
244 }
245
246 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
247 {
248 xiic_irq_clr(i2c, mask);
249 xiic_irq_en(i2c, mask);
250 }
251
252 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
253 {
254 u8 sr;
255 unsigned long timeout;
256
257 timeout = jiffies + XIIC_I2C_TIMEOUT;
258 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
259 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
260 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
261 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
262 if (time_after(jiffies, timeout)) {
263 dev_err(i2c->dev, "Failed to clear rx fifo\n");
264 return -ETIMEDOUT;
265 }
266 }
267
268 return 0;
269 }
270
271 static int xiic_reinit(struct xiic_i2c *i2c)
272 {
273 int ret;
274
275 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
276
277 /* Set receive Fifo depth to maximum (zero based). */
278 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
279
280 /* Reset Tx Fifo. */
281 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
282
283 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
284 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
285
286 /* make sure RX fifo is empty */
287 ret = xiic_clear_rx_fifo(i2c);
288 if (ret)
289 return ret;
290
291 /* Enable interrupts */
292 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
293
294 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
295
296 return 0;
297 }
298
299 static void xiic_deinit(struct xiic_i2c *i2c)
300 {
301 u8 cr;
302
303 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
304
305 /* Disable IIC Device. */
306 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
307 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
308 }
309
310 static void xiic_read_rx(struct xiic_i2c *i2c)
311 {
312 u8 bytes_in_fifo;
313 int i;
314
315 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
316
317 dev_dbg(i2c->adap.dev.parent,
318 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
319 __func__, bytes_in_fifo, xiic_rx_space(i2c),
320 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
321 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
322
323 if (bytes_in_fifo > xiic_rx_space(i2c))
324 bytes_in_fifo = xiic_rx_space(i2c);
325
326 for (i = 0; i < bytes_in_fifo; i++)
327 i2c->rx_msg->buf[i2c->rx_pos++] =
328 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
329
330 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
331 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
332 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
333 }
334
335 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
336 {
337 /* return the actual space left in the FIFO */
338 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
339 }
340
341 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
342 {
343 u8 fifo_space = xiic_tx_fifo_space(i2c);
344 int len = xiic_tx_space(i2c);
345
346 len = (len > fifo_space) ? fifo_space : len;
347
348 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
349 __func__, len, fifo_space);
350
351 while (len--) {
352 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
353 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
354 /* last message in transfer -> STOP */
355 data |= XIIC_TX_DYN_STOP_MASK;
356 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
357 }
358 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
359 }
360 }
361
362 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
363 {
364 i2c->tx_msg = NULL;
365 i2c->rx_msg = NULL;
366 i2c->nmsgs = 0;
367 i2c->state = code;
368 wake_up(&i2c->wait);
369 }
370
371 static irqreturn_t xiic_process(int irq, void *dev_id)
372 {
373 struct xiic_i2c *i2c = dev_id;
374 u32 pend, isr, ier;
375 u32 clr = 0;
376
377 /* Get the interrupt Status from the IPIF. There is no clearing of
378 * interrupts in the IPIF. Interrupts must be cleared at the source.
379 * To find which interrupts are pending; AND interrupts pending with
380 * interrupts masked.
381 */
382 mutex_lock(&i2c->lock);
383 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
384 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
385 pend = isr & ier;
386
387 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
388 __func__, ier, isr, pend);
389 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
390 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
391 i2c->tx_msg, i2c->nmsgs);
392
393
394 /* Service requesting interrupt */
395 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
396 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
397 !(pend & XIIC_INTR_RX_FULL_MASK))) {
398 /* bus arbritration lost, or...
399 * Transmit error _OR_ RX completed
400 * if this happens when RX_FULL is not set
401 * this is probably a TX error
402 */
403
404 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
405
406 /* dynamic mode seem to suffer from problems if we just flushes
407 * fifos and the next message is a TX with len 0 (only addr)
408 * reset the IP instead of just flush fifos
409 */
410 xiic_reinit(i2c);
411
412 if (i2c->rx_msg)
413 xiic_wakeup(i2c, STATE_ERROR);
414 if (i2c->tx_msg)
415 xiic_wakeup(i2c, STATE_ERROR);
416 }
417 if (pend & XIIC_INTR_RX_FULL_MASK) {
418 /* Receive register/FIFO is full */
419
420 clr |= XIIC_INTR_RX_FULL_MASK;
421 if (!i2c->rx_msg) {
422 dev_dbg(i2c->adap.dev.parent,
423 "%s unexpected RX IRQ\n", __func__);
424 xiic_clear_rx_fifo(i2c);
425 goto out;
426 }
427
428 xiic_read_rx(i2c);
429 if (xiic_rx_space(i2c) == 0) {
430 /* this is the last part of the message */
431 i2c->rx_msg = NULL;
432
433 /* also clear TX error if there (RX complete) */
434 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
435
436 dev_dbg(i2c->adap.dev.parent,
437 "%s end of message, nmsgs: %d\n",
438 __func__, i2c->nmsgs);
439
440 /* send next message if this wasn't the last,
441 * otherwise the transfer will be finialise when
442 * receiving the bus not busy interrupt
443 */
444 if (i2c->nmsgs > 1) {
445 i2c->nmsgs--;
446 i2c->tx_msg++;
447 dev_dbg(i2c->adap.dev.parent,
448 "%s will start next...\n", __func__);
449
450 __xiic_start_xfer(i2c);
451 }
452 }
453 }
454 if (pend & XIIC_INTR_BNB_MASK) {
455 /* IIC bus has transitioned to not busy */
456 clr |= XIIC_INTR_BNB_MASK;
457
458 /* The bus is not busy, disable BusNotBusy interrupt */
459 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
460
461 if (!i2c->tx_msg)
462 goto out;
463
464 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
465 xiic_tx_space(i2c) == 0)
466 xiic_wakeup(i2c, STATE_DONE);
467 else
468 xiic_wakeup(i2c, STATE_ERROR);
469 }
470 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
471 /* Transmit register/FIFO is empty or ½ empty */
472
473 clr |= (pend &
474 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
475
476 if (!i2c->tx_msg) {
477 dev_dbg(i2c->adap.dev.parent,
478 "%s unexpected TX IRQ\n", __func__);
479 goto out;
480 }
481
482 xiic_fill_tx_fifo(i2c);
483
484 /* current message sent and there is space in the fifo */
485 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
486 dev_dbg(i2c->adap.dev.parent,
487 "%s end of message sent, nmsgs: %d\n",
488 __func__, i2c->nmsgs);
489 if (i2c->nmsgs > 1) {
490 i2c->nmsgs--;
491 i2c->tx_msg++;
492 __xiic_start_xfer(i2c);
493 } else {
494 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
495
496 dev_dbg(i2c->adap.dev.parent,
497 "%s Got TX IRQ but no more to do...\n",
498 __func__);
499 }
500 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
501 /* current frame is sent and is last,
502 * make sure to disable tx half
503 */
504 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
505 }
506 out:
507 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
508
509 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
510 mutex_unlock(&i2c->lock);
511 return IRQ_HANDLED;
512 }
513
514 static int xiic_bus_busy(struct xiic_i2c *i2c)
515 {
516 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
517
518 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
519 }
520
521 static int xiic_busy(struct xiic_i2c *i2c)
522 {
523 int tries = 3;
524 int err;
525
526 if (i2c->tx_msg)
527 return -EBUSY;
528
529 /* for instance if previous transfer was terminated due to TX error
530 * it might be that the bus is on it's way to become available
531 * give it at most 3 ms to wake
532 */
533 err = xiic_bus_busy(i2c);
534 while (err && tries--) {
535 msleep(1);
536 err = xiic_bus_busy(i2c);
537 }
538
539 return err;
540 }
541
542 static void xiic_start_recv(struct xiic_i2c *i2c)
543 {
544 u8 rx_watermark;
545 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
546 unsigned long flags;
547
548 /* Clear and enable Rx full interrupt. */
549 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
550
551 /* we want to get all but last byte, because the TX_ERROR IRQ is used
552 * to inidicate error ACK on the address, and negative ack on the last
553 * received byte, so to not mix them receive all but last.
554 * In the case where there is only one byte to receive
555 * we can check if ERROR and RX full is set at the same time
556 */
557 rx_watermark = msg->len;
558 if (rx_watermark > IIC_RX_FIFO_DEPTH)
559 rx_watermark = IIC_RX_FIFO_DEPTH;
560 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
561
562 local_irq_save(flags);
563 if (!(msg->flags & I2C_M_NOSTART))
564 /* write the address */
565 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
566 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK);
567
568 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
569
570 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
571 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
572 local_irq_restore(flags);
573
574 if (i2c->nmsgs == 1)
575 /* very last, enable bus not busy as well */
576 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
577
578 /* the message is tx:ed */
579 i2c->tx_pos = msg->len;
580 }
581
582 static void xiic_start_send(struct xiic_i2c *i2c)
583 {
584 struct i2c_msg *msg = i2c->tx_msg;
585
586 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
587
588 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
589 __func__, msg, msg->len);
590 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
591 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
592 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
593
594 if (!(msg->flags & I2C_M_NOSTART)) {
595 /* write the address */
596 u16 data = i2c_8bit_addr_from_msg(msg) |
597 XIIC_TX_DYN_START_MASK;
598 if ((i2c->nmsgs == 1) && msg->len == 0)
599 /* no data and last message -> add STOP */
600 data |= XIIC_TX_DYN_STOP_MASK;
601
602 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
603 }
604
605 xiic_fill_tx_fifo(i2c);
606
607 /* Clear any pending Tx empty, Tx Error and then enable them. */
608 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
609 XIIC_INTR_BNB_MASK);
610 }
611
612 static irqreturn_t xiic_isr(int irq, void *dev_id)
613 {
614 struct xiic_i2c *i2c = dev_id;
615 u32 pend, isr, ier;
616 irqreturn_t ret = IRQ_NONE;
617 /* Do not processes a devices interrupts if the device has no
618 * interrupts pending
619 */
620
621 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
622
623 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
624 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
625 pend = isr & ier;
626 if (pend)
627 ret = IRQ_WAKE_THREAD;
628
629 return ret;
630 }
631
632 static void __xiic_start_xfer(struct xiic_i2c *i2c)
633 {
634 int first = 1;
635 int fifo_space = xiic_tx_fifo_space(i2c);
636 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
637 __func__, i2c->tx_msg, fifo_space);
638
639 if (!i2c->tx_msg)
640 return;
641
642 i2c->rx_pos = 0;
643 i2c->tx_pos = 0;
644 i2c->state = STATE_START;
645 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
646 if (!first) {
647 i2c->nmsgs--;
648 i2c->tx_msg++;
649 i2c->tx_pos = 0;
650 } else
651 first = 0;
652
653 if (i2c->tx_msg->flags & I2C_M_RD) {
654 /* we dont date putting several reads in the FIFO */
655 xiic_start_recv(i2c);
656 return;
657 } else {
658 xiic_start_send(i2c);
659 if (xiic_tx_space(i2c) != 0) {
660 /* the message could not be completely sent */
661 break;
662 }
663 }
664
665 fifo_space = xiic_tx_fifo_space(i2c);
666 }
667
668 /* there are more messages or the current one could not be completely
669 * put into the FIFO, also enable the half empty interrupt
670 */
671 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
672 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
673
674 }
675
676 static int xiic_start_xfer(struct xiic_i2c *i2c)
677 {
678 int ret;
679 mutex_lock(&i2c->lock);
680
681 ret = xiic_reinit(i2c);
682 if (!ret)
683 __xiic_start_xfer(i2c);
684
685 mutex_unlock(&i2c->lock);
686
687 return ret;
688 }
689
690 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
691 {
692 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
693 int err;
694
695 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
696 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
697
698 err = pm_runtime_get_sync(i2c->dev);
699 if (err < 0)
700 return err;
701
702 err = xiic_busy(i2c);
703 if (err)
704 goto out;
705
706 i2c->tx_msg = msgs;
707 i2c->nmsgs = num;
708
709 err = xiic_start_xfer(i2c);
710 if (err < 0) {
711 dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
712 goto out;
713 }
714
715 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
716 (i2c->state == STATE_DONE), HZ)) {
717 err = (i2c->state == STATE_DONE) ? num : -EIO;
718 goto out;
719 } else {
720 i2c->tx_msg = NULL;
721 i2c->rx_msg = NULL;
722 i2c->nmsgs = 0;
723 err = -ETIMEDOUT;
724 goto out;
725 }
726 out:
727 pm_runtime_mark_last_busy(i2c->dev);
728 pm_runtime_put_autosuspend(i2c->dev);
729 return err;
730 }
731
732 static u32 xiic_func(struct i2c_adapter *adap)
733 {
734 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
735 }
736
737 static const struct i2c_algorithm xiic_algorithm = {
738 .master_xfer = xiic_xfer,
739 .functionality = xiic_func,
740 };
741
742 static const struct i2c_adapter_quirks xiic_quirks = {
743 .max_read_len = 255,
744 };
745
746 static const struct i2c_adapter xiic_adapter = {
747 .owner = THIS_MODULE,
748 .name = DRIVER_NAME,
749 .class = I2C_CLASS_DEPRECATED,
750 .algo = &xiic_algorithm,
751 .quirks = &xiic_quirks,
752 };
753
754
755 static int xiic_i2c_probe(struct platform_device *pdev)
756 {
757 struct xiic_i2c *i2c;
758 struct xiic_i2c_platform_data *pdata;
759 struct resource *res;
760 int ret, irq;
761 u8 i;
762 u32 sr;
763
764 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
765 if (!i2c)
766 return -ENOMEM;
767
768 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769 i2c->base = devm_ioremap_resource(&pdev->dev, res);
770 if (IS_ERR(i2c->base))
771 return PTR_ERR(i2c->base);
772
773 irq = platform_get_irq(pdev, 0);
774 if (irq < 0)
775 return irq;
776
777 pdata = dev_get_platdata(&pdev->dev);
778
779 /* hook up driver to tree */
780 platform_set_drvdata(pdev, i2c);
781 i2c->adap = xiic_adapter;
782 i2c_set_adapdata(&i2c->adap, i2c);
783 i2c->adap.dev.parent = &pdev->dev;
784 i2c->adap.dev.of_node = pdev->dev.of_node;
785
786 mutex_init(&i2c->lock);
787 init_waitqueue_head(&i2c->wait);
788
789 i2c->clk = devm_clk_get(&pdev->dev, NULL);
790 if (IS_ERR(i2c->clk)) {
791 if (PTR_ERR(i2c->clk) != -EPROBE_DEFER)
792 dev_err(&pdev->dev, "input clock not found.\n");
793 return PTR_ERR(i2c->clk);
794 }
795 ret = clk_prepare_enable(i2c->clk);
796 if (ret) {
797 dev_err(&pdev->dev, "Unable to enable clock.\n");
798 return ret;
799 }
800 i2c->dev = &pdev->dev;
801 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
802 pm_runtime_use_autosuspend(i2c->dev);
803 pm_runtime_set_active(i2c->dev);
804 pm_runtime_enable(i2c->dev);
805 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
806 xiic_process, IRQF_ONESHOT,
807 pdev->name, i2c);
808
809 if (ret < 0) {
810 dev_err(&pdev->dev, "Cannot claim IRQ\n");
811 goto err_clk_dis;
812 }
813
814 /*
815 * Detect endianness
816 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
817 * set, assume that the endianness was wrong and swap.
818 */
819 i2c->endianness = LITTLE;
820 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
821 /* Reset is cleared in xiic_reinit */
822 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
823 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
824 i2c->endianness = BIG;
825
826 ret = xiic_reinit(i2c);
827 if (ret < 0) {
828 dev_err(&pdev->dev, "Cannot xiic_reinit\n");
829 goto err_clk_dis;
830 }
831
832 /* add i2c adapter to i2c tree */
833 ret = i2c_add_adapter(&i2c->adap);
834 if (ret) {
835 xiic_deinit(i2c);
836 goto err_clk_dis;
837 }
838
839 if (pdata) {
840 /* add in known devices to the bus */
841 for (i = 0; i < pdata->num_devices; i++)
842 i2c_new_client_device(&i2c->adap, pdata->devices + i);
843 }
844
845 return 0;
846
847 err_clk_dis:
848 pm_runtime_set_suspended(&pdev->dev);
849 pm_runtime_disable(&pdev->dev);
850 clk_disable_unprepare(i2c->clk);
851 return ret;
852 }
853
854 static int xiic_i2c_remove(struct platform_device *pdev)
855 {
856 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
857 int ret;
858
859 /* remove adapter & data */
860 i2c_del_adapter(&i2c->adap);
861
862 ret = pm_runtime_get_sync(i2c->dev);
863 if (ret < 0)
864 return ret;
865
866 xiic_deinit(i2c);
867 pm_runtime_put_sync(i2c->dev);
868 clk_disable_unprepare(i2c->clk);
869 pm_runtime_disable(&pdev->dev);
870 pm_runtime_set_suspended(&pdev->dev);
871 pm_runtime_dont_use_autosuspend(&pdev->dev);
872
873 return 0;
874 }
875
876 #if defined(CONFIG_OF)
877 static const struct of_device_id xiic_of_match[] = {
878 { .compatible = "xlnx,xps-iic-2.00.a", },
879 {},
880 };
881 MODULE_DEVICE_TABLE(of, xiic_of_match);
882 #endif
883
884 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
885 {
886 struct xiic_i2c *i2c = dev_get_drvdata(dev);
887
888 clk_disable(i2c->clk);
889
890 return 0;
891 }
892
893 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
894 {
895 struct xiic_i2c *i2c = dev_get_drvdata(dev);
896 int ret;
897
898 ret = clk_enable(i2c->clk);
899 if (ret) {
900 dev_err(dev, "Cannot enable clock.\n");
901 return ret;
902 }
903
904 return 0;
905 }
906
907 static const struct dev_pm_ops xiic_dev_pm_ops = {
908 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
909 xiic_i2c_runtime_resume, NULL)
910 };
911 static struct platform_driver xiic_i2c_driver = {
912 .probe = xiic_i2c_probe,
913 .remove = xiic_i2c_remove,
914 .driver = {
915 .name = DRIVER_NAME,
916 .of_match_table = of_match_ptr(xiic_of_match),
917 .pm = &xiic_dev_pm_ops,
918 },
919 };
920
921 module_platform_driver(xiic_i2c_driver);
922
923 MODULE_AUTHOR("info@mocean-labs.com");
924 MODULE_DESCRIPTION("Xilinx I2C bus driver");
925 MODULE_LICENSE("GPL v2");
926 MODULE_ALIAS("platform:"DRIVER_NAME);
Linux with added FPC-III support