arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22
  23 / {
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         sysram@02020000 {
  35                 compatible = "mmio-sram";
  36                 reg = <0x02020000 0x40000>;
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges = <0 0x02020000 0x40000>;
  40
  41                 smp-sysram@0 {
  42                         compatible = "samsung,exynos4210-sysram";
  43                         reg = <0x0 0x1000>;
  44                 };
  45
  46                 smp-sysram@2f000 {
  47                         compatible = "samsung,exynos4210-sysram-ns";
  48                         reg = <0x2f000 0x1000>;
  49                 };
  50         };
  51
  52         pd_isp: isp-power-domain@10023CA0 {
  53                 compatible = "samsung,exynos4210-pd";
  54                 reg = <0x10023CA0 0x20>;
  55                 #power-domain-cells = <0>;
  56         };
  57
  58         clock: clock-controller@10030000 {
  59                 compatible = "samsung,exynos4412-clock";
  60                 reg = <0x10030000 0x20000>;
  61                 #clock-cells = <1>;
  62         };
  63
  64         mct@10050000 {
  65                 compatible = "samsung,exynos4412-mct";
  66                 reg = <0x10050000 0x800>;
  67                 interrupt-parent = <&mct_map>;
  68                 interrupts = <0>, <1>, <2>, <3>, <4>;
  69                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  70                 clock-names = "fin_pll", "mct";
  71
  72                 mct_map: mct-map {
  73                         #interrupt-cells = <1>;
  74                         #address-cells = <0>;
  75                         #size-cells = <0>;
  76                         interrupt-map = <0 &gic 0 57 0>,
  77                                         <1 &combiner 12 5>,
  78                                         <2 &combiner 12 6>,
  79                                         <3 &combiner 12 7>,
  80                                         <4 &gic 1 12 0>;
  81                 };
  82         };
  83
  84         combiner: interrupt-controller@10440000 {
  85                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  86                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  87                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  88                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  89                              <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
  90         };
  91
  92         pinctrl_0: pinctrl@11400000 {
  93                 compatible = "samsung,exynos4x12-pinctrl";
  94                 reg = <0x11400000 0x1000>;
  95                 interrupts = <0 47 0>;
  96         };
  97
  98         pinctrl_1: pinctrl@11000000 {
  99                 compatible = "samsung,exynos4x12-pinctrl";
 100                 reg = <0x11000000 0x1000>;
 101                 interrupts = <0 46 0>;
 102
 103                 wakup_eint: wakeup-interrupt-controller {
 104                         compatible = "samsung,exynos4210-wakeup-eint";
 105                         interrupt-parent = <&gic>;
 106                         interrupts = <0 32 0>;
 107                 };
 108         };
 109
 110         adc: adc@126C0000 {
 111                 compatible = "samsung,exynos-adc-v1";
 112                 reg = <0x126C0000 0x100>;
 113                 interrupt-parent = <&combiner>;
 114                 interrupts = <10 3>;
 115                 clocks = <&clock CLK_TSADC>;
 116                 clock-names = "adc";
 117                 #io-channel-cells = <1>;
 118                 io-channel-ranges;
 119                 samsung,syscon-phandle = <&pmu_system_controller>;
 120                 status = "disabled";
 121         };
 122
 123         pinctrl_2: pinctrl@03860000 {
 124                 compatible = "samsung,exynos4x12-pinctrl";
 125                 reg = <0x03860000 0x1000>;
 126                 interrupt-parent = <&combiner>;
 127                 interrupts = <10 0>;
 128         };
 129
 130         pinctrl_3: pinctrl@106E0000 {
 131                 compatible = "samsung,exynos4x12-pinctrl";
 132                 reg = <0x106E0000 0x1000>;
 133                 interrupts = <0 72 0>;
 134         };
 135
 136         pmu_system_controller: system-controller@10020000 {
 137                 compatible = "samsung,exynos4212-pmu", "syscon";
 138                 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 139                                 "clkout4", "clkout8", "clkout9";
 140                 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 141                         <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 142                         <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
 143                         <&clock CLK_XUSBXTI>;
 144                 #clock-cells = <1>;
 145         };
 146
 147         g2d@10800000 {
 148                 compatible = "samsung,exynos4212-g2d";
 149                 reg = <0x10800000 0x1000>;
 150                 interrupts = <0 89 0>;
 151                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 152                 clock-names = "sclk_fimg2d", "fimg2d";
 153                 status = "disabled";
 154         };
 155
 156         camera {
 157                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 158                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 159                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 160
 161                 fimc_0: fimc@11800000 {
 162                         compatible = "samsung,exynos4212-fimc";
 163                         samsung,pix-limits = <4224 8192 1920 4224>;
 164                         samsung,mainscaler-ext;
 165                         samsung,isp-wb;
 166                         samsung,cam-if;
 167                 };
 168
 169                 fimc_1: fimc@11810000 {
 170                         compatible = "samsung,exynos4212-fimc";
 171                         samsung,pix-limits = <4224 8192 1920 4224>;
 172                         samsung,mainscaler-ext;
 173                         samsung,isp-wb;
 174                         samsung,cam-if;
 175                 };
 176
 177                 fimc_2: fimc@11820000 {
 178                         compatible = "samsung,exynos4212-fimc";
 179                         samsung,pix-limits = <4224 8192 1920 4224>;
 180                         samsung,mainscaler-ext;
 181                         samsung,isp-wb;
 182                         samsung,lcd-wb;
 183                         samsung,cam-if;
 184                 };
 185
 186                 fimc_3: fimc@11830000 {
 187                         compatible = "samsung,exynos4212-fimc";
 188                         samsung,pix-limits = <1920 8192 1366 1920>;
 189                         samsung,rotators = <0>;
 190                         samsung,mainscaler-ext;
 191                         samsung,isp-wb;
 192                         samsung,lcd-wb;
 193                 };
 194
 195                 fimc_lite_0: fimc-lite@12390000 {
 196                         compatible = "samsung,exynos4212-fimc-lite";
 197                         reg = <0x12390000 0x1000>;
 198                         interrupts = <0 105 0>;
 199                         power-domains = <&pd_isp>;
 200                         clocks = <&clock CLK_FIMC_LITE0>;
 201                         clock-names = "flite";
 202                         status = "disabled";
 203                 };
 204
 205                 fimc_lite_1: fimc-lite@123A0000 {
 206                         compatible = "samsung,exynos4212-fimc-lite";
 207                         reg = <0x123A0000 0x1000>;
 208                         interrupts = <0 106 0>;
 209                         power-domains = <&pd_isp>;
 210                         clocks = <&clock CLK_FIMC_LITE1>;
 211                         clock-names = "flite";
 212                         status = "disabled";
 213                 };
 214
 215                 fimc_is: fimc-is@12000000 {
 216                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
 217                         reg = <0x12000000 0x260000>;
 218                         interrupts = <0 90 0>, <0 95 0>;
 219                         power-domains = <&pd_isp>;
 220                         clocks = <&clock CLK_FIMC_LITE0>,
 221                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 222                                  <&clock CLK_PPMUISPMX>,
 223                                  <&clock CLK_MOUT_MPLL_USER_T>,
 224                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 225                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 226                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
 227                                  <&clock CLK_DIV_MCUISP0>,
 228                                  <&clock CLK_DIV_MCUISP1>,
 229                                  <&clock CLK_SCLK_UART_ISP>,
 230                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 231                                  <&clock CLK_ACLK400_MCUISP>,
 232                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 233                         clock-names = "lite0", "lite1", "ppmuispx",
 234                                       "ppmuispmx", "mpll", "isp",
 235                                       "drc", "fd", "mcuisp",
 236                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 237                                       "mcuispdiv1", "uart", "aclk200",
 238                                       "div_aclk200", "aclk400mcuisp",
 239                                       "div_aclk400mcuisp";
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                         ranges;
 243                         status = "disabled";
 244
 245                         pmu {
 246                                 reg = <0x10020000 0x3000>;
 247                         };
 248
 249                         i2c1_isp: i2c-isp@12140000 {
 250                                 compatible = "samsung,exynos4212-i2c-isp";
 251                                 reg = <0x12140000 0x100>;
 252                                 clocks = <&clock CLK_I2C1_ISP>;
 253                                 clock-names = "i2c_isp";
 254                                 #address-cells = <1>;
 255                                 #size-cells = <0>;
 256                         };
 257                 };
 258         };
 259
 260         mshc_0: mmc@12550000 {
 261                 compatible = "samsung,exynos4412-dw-mshc";
 262                 reg = <0x12550000 0x1000>;
 263                 interrupts = <0 77 0>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 fifo-depth = <0x80>;
 267                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 268                 clock-names = "biu", "ciu";
 269                 status = "disabled";
 270         };
 271
 272         exynos-usbphy@125B0000 {
 273                 compatible = "samsung,exynos4x12-usb2-phy";
 274                 samsung,sysreg-phandle = <&sys_reg>;
 275         };
 276
 277         tmu@100C0000 {
 278                 compatible = "samsung,exynos4412-tmu";
 279                 interrupt-parent = <&combiner>;
 280                 interrupts = <2 4>;
 281                 reg = <0x100C0000 0x100>;
 282                 clocks = <&clock 383>;
 283                 clock-names = "tmu_apbif";
 284                 status = "disabled";
 285         };
 286 };