2 * rtrap.S: Preparing for return from trap on Sparc V9.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
14 #include <asm/visasm.h>
15 #include <asm/processor.h>
17 #define RTRAP_PSTATE (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18 #define RTRAP_PSTATE_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
19 #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
21 #ifdef CONFIG_CONTEXT_TRACKING
22 # define SCHEDULE_USER schedule_user
24 # define SCHEDULE_USER schedule
31 wrpr %g0, RTRAP_PSTATE, %pstate
32 ba,pt %xcc, __handle_preemption_continue
33 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
35 __handle_user_windows:
36 call fault_in_user_windows
37 wrpr %g0, RTRAP_PSTATE, %pstate
38 ba,pt %xcc, __handle_preemption_continue
39 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
43 andcc %l5, FPRS_FEF, %g0
44 sethi %hi(TSTATE_PEF), %o0
45 be,a,pn %icc, __handle_userfpu_continue
47 ba,a,pt %xcc, __handle_userfpu_continue
51 add %sp, PTREGS_OFF, %o0
54 wrpr %g0, RTRAP_PSTATE, %pstate
55 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
57 /* Signal delivery can modify pt_regs tstate, so we must
60 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
61 sethi %hi(0xf << 20), %l4
63 ba,pt %xcc, __handle_preemption_continue
66 /* When returning from a NMI (%pil==15) interrupt we want to
67 * avoid running softirqs, doing IRQ tracing, preempting, etc.
70 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
71 sethi %hi(0xf << 20), %l4
75 ba,pt %xcc, rtrap_no_irq_enable
77 /* Do not actually set the %pil here. We will do that
78 * below after we clear PSTATE_IE in the %pstate register.
79 * If we re-enable interrupts here, we can recurse down
80 * the hardirq stack potentially endlessly, causing a
85 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
88 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
89 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
91 sethi %hi(0xf << 20), %l4
95 #ifdef CONFIG_TRACE_IRQFLAGS
96 brnz,pn %l4, rtrap_no_irq_enable
98 call trace_hardirqs_on
100 /* Do not actually set the %pil here. We will do that
101 * below after we clear PSTATE_IE in the %pstate register.
102 * If we re-enable interrupts here, we can recurse down
103 * the hardirq stack potentially endlessly, causing a
106 * It is tempting to put this test and trace_hardirqs_on
107 * call at the 'rt_continue' label, but that will not work
108 * as that path hits unconditionally and we do not want to
109 * execute this in NMI return paths, for example.
113 andcc %l1, TSTATE_PRIV, %l3
114 bne,pn %icc, to_kernel
117 /* We must hold IRQs off and atomically test schedule+signal
118 * state, then hold them off all the way back to userspace.
119 * If we are returning to kernel, none of this matters. Note
120 * that we are disabling interrupts via PSTATE_IE, not using
123 * If we do not do this, there is a window where we would do
124 * the tests, later the signal/resched event arrives but we do
125 * not process it since we are still in kernel mode. It would
126 * take until the next local IRQ before the signal/resched
127 * event would be handled.
129 * This also means that if we have to deal with user
130 * windows, we have to redo all of these sched+signal checks
131 * with IRQs disabled.
133 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
135 __handle_preemption_continue:
136 ldx [%g6 + TI_FLAGS], %l0
137 sethi %hi(_TIF_USER_WORK_MASK), %o0
138 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
140 sethi %hi(TSTATE_PEF), %o0
141 be,pt %xcc, user_nowork
143 andcc %l0, _TIF_NEED_RESCHED, %g0
144 bne,pn %xcc, __handle_preemption
145 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
146 bne,pn %xcc, __handle_signal
147 ldub [%g6 + TI_WSAVED], %o2
148 brnz,pn %o2, __handle_user_windows
150 sethi %hi(TSTATE_PEF), %o0
153 /* This fpdepth clear is necessary for non-syscall rtraps only */
155 bne,pn %xcc, __handle_userfpu
156 stb %g0, [%g6 + TI_FPDEPTH]
157 __handle_userfpu_continue:
159 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
160 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
162 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
163 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
164 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
168 /* Must do this before thread reg is clobbered below. */
169 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
171 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
172 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
174 /* Normal globals are restored, go to trap globals. */
175 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
177 .section .sun4v_2insn_patch, "ax"
179 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
185 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
186 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
188 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
189 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
190 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
191 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
192 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
193 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
194 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
195 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
197 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
201 andn %l1, TSTATE_SYSCALL, %l1
202 wrpr %l1, %g0, %tstate
206 brnz,pn %l3, kern_rtt
207 mov PRIMARY_CONTEXT, %l7
209 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
210 .section .sun4v_1insn_patch, "ax"
212 ldxa [%l7 + %l7] ASI_MMU, %l0
215 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
216 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
219 661: stxa %l0, [%l7] ASI_DMMU
220 .section .sun4v_1insn_patch, "ax"
222 stxa %l0, [%l7] ASI_MMU
225 sethi %hi(KERNBASE), %l7
231 wrpr %l2, %g0, %canrestore
232 wrpr %l1, %g0, %wstate
233 brnz,pt %l2, user_rtt_restore
234 wrpr %g0, %g0, %otherwin
236 ldx [%g6 + TI_FLAGS], %g3
237 wr %g0, ASI_AIUP, %asi
239 andcc %g3, _TIF_32BIT, %g0
241 bne,pt %xcc, user_rtt_fill_32bit
243 ba,a,pt %xcc, user_rtt_fill_64bit
252 wrpr %g2, 0x0, %wstate
254 /* We know %canrestore and %otherwin are both zero. */
256 sethi %hi(sparc64_kern_pri_context), %g2
257 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
258 mov PRIMARY_CONTEXT, %g1
260 661: stxa %g2, [%g1] ASI_DMMU
261 .section .sun4v_1insn_patch, "ax"
263 stxa %g2, [%g1] ASI_MMU
266 sethi %hi(KERNBASE), %g1
269 or %g4, FAULT_CODE_WINFIXUP, %g4
270 stb %g4, [%g6 + TI_FAULT_CODE]
271 stx %g5, [%g6 + TI_FAULT_ADDR]
277 .section .sun4v_1insn_patch, "ax"
282 wrpr %g0, RTRAP_PSTATE, %pstate
285 ldx [%g6 + TI_TASK], %g4
286 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
287 call do_sparc64_fault
288 add %sp, PTREGS_OFF, %o0
292 user_rtt_pre_restore:
298 rdpr %canrestore, %g1
299 wrpr %g1, 0x0, %cleanwin
303 kern_rtt: rdpr %canrestore, %g1
304 brz,pn %g1, kern_rtt_fill
307 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
312 #ifdef CONFIG_PREEMPT
313 ldsw [%g6 + TI_PRE_COUNT], %l5
314 brnz %l5, kern_fpucheck
315 ldx [%g6 + TI_FLAGS], %l5
316 andcc %l5, _TIF_NEED_RESCHED, %g0
317 be,pt %xcc, kern_fpucheck
320 bne,pn %xcc, kern_fpucheck
322 call preempt_schedule_irq
326 kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
327 brz,pt %l5, rt_continue
329 add %g6, TI_FPSAVED, %l6
330 ldub [%l6 + %o0], %l2
334 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
336 and %l2, FPRS_DL, %l6
337 andcc %l2, FPRS_FEF, %g0
342 wr %g1, FPRS_FEF, %fprs
344 add %g6, TI_XFSR, %o1
346 add %g6, TI_FPREGS, %o3
348 add %g6, TI_FPREGS+0x40, %o4
351 ldda [%o3 + %o2] ASI_BLK_P, %f0
352 ldda [%o4 + %o2] ASI_BLK_P, %f16
354 1: andcc %l2, FPRS_DU, %g0
359 ldda [%o3 + %o2] ASI_BLK_P, %f32
360 ldda [%o4 + %o2] ASI_BLK_P, %f48
362 ldx [%o1 + %o5], %fsr
363 2: stb %l5, [%g6 + TI_FPDEPTH]
364 ba,pt %xcc, rt_continue
366 5: wr %g0, FPRS_FEF, %fprs
369 add %g6, TI_FPREGS+0x80, %o3
370 add %g6, TI_FPREGS+0xc0, %o4
372 ldda [%o3 + %o2] ASI_BLK_P, %f32
373 ldda [%o4 + %o2] ASI_BLK_P, %f48
375 wr %g0, FPRS_DU, %fprs
376 ba,pt %xcc, rt_continue
377 stb %l5, [%g6 + TI_FPDEPTH]