?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
irqchip: Fix dependencies for archs w/o HAS_IOMEM
[linux/fpc-iii.git] / arch / x86 / kernel / cpu / perf_event_intel.c
bloba667078a51807bb5bd1ca2e5d5c4ff205e9dd42b
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/nmi.h>
16
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
19 #include <asm/apic.h>
20
21 #include "perf_event.h"
22
23 /*
24 * Intel PerfMon, used on Core and later.
25 */
26 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
27 {
28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
36 };
37
38 static struct event_constraint intel_core_event_constraints[] __read_mostly =
39 {
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
46 EVENT_CONSTRAINT_END
47 };
48
49 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
50 {
51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
64 EVENT_CONSTRAINT_END
65 };
66
67 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
68 {
69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
80 EVENT_CONSTRAINT_END
81 };
82
83 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
84 {
85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
88 EVENT_EXTRA_END
89 };
90
91 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
92 {
93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
100 EVENT_CONSTRAINT_END
101 };
102
103 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
104 {
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
117
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
122
123 EVENT_CONSTRAINT_END
124 };
125
126 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
127 {
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
141
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
146
147 EVENT_CONSTRAINT_END
148 };
149
150 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
151 {
152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
156 EVENT_EXTRA_END
157 };
158
159 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
160 {
161 EVENT_CONSTRAINT_END
162 };
163
164 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
165 {
166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
169 EVENT_CONSTRAINT_END
170 };
171
172 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
173 {
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
177 EVENT_CONSTRAINT_END
178 };
179
180 struct event_constraint intel_skl_event_constraints[] = {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
185 EVENT_CONSTRAINT_END
186 };
187
188 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
189 INTEL_UEVENT_EXTRA_REG(0x01b7,
190 MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x02b7,
192 MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
193 EVENT_EXTRA_END
194 };
195
196 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
197 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
198 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
199 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
200 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
201 EVENT_EXTRA_END
202 };
203
204 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
205 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
206 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
207 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
208 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
209 EVENT_EXTRA_END
210 };
211
212 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
213 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
214 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
215 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
216 /*
217 * Note the low 8 bits eventsel code is not a continuous field, containing
218 * some #GPing bits. These are masked out.
219 */
220 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
221 EVENT_EXTRA_END
222 };
223
224 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
225 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
226 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
227
228 struct attribute *nhm_events_attrs[] = {
229 EVENT_PTR(mem_ld_nhm),
230 NULL,
231 };
232
233 struct attribute *snb_events_attrs[] = {
234 EVENT_PTR(mem_ld_snb),
235 EVENT_PTR(mem_st_snb),
236 NULL,
237 };
238
239 static struct event_constraint intel_hsw_event_constraints[] = {
240 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
241 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
242 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
243 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
244 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
245 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
246 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
247 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
248 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
249 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
250 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
251 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
252
253 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
254 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
255 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
256 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
257
258 EVENT_CONSTRAINT_END
259 };
260
261 struct event_constraint intel_bdw_event_constraints[] = {
262 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
263 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
264 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
265 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
266 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
267 EVENT_CONSTRAINT_END
268 };
269
270 static u64 intel_pmu_event_map(int hw_event)
271 {
272 return intel_perfmon_event_map[hw_event];
273 }
274
275 /*
276 * Notes on the events:
277 * - data reads do not include code reads (comparable to earlier tables)
278 * - data counts include speculative execution (except L1 write, dtlb, bpu)
279 * - remote node access includes remote memory, remote cache, remote mmio.
280 * - prefetches are not included in the counts.
281 * - icache miss does not include decoded icache
282 */
283
284 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
285 #define SKL_DEMAND_RFO BIT_ULL(1)
286 #define SKL_ANY_RESPONSE BIT_ULL(16)
287 #define SKL_SUPPLIER_NONE BIT_ULL(17)
288 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
289 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
290 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
291 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
292 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
293 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
294 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
295 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
296 #define SKL_SPL_HIT BIT_ULL(30)
297 #define SKL_SNOOP_NONE BIT_ULL(31)
298 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
299 #define SKL_SNOOP_MISS BIT_ULL(33)
300 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
301 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
302 #define SKL_SNOOP_HITM BIT_ULL(36)
303 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
304 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
305 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
306 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
307 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
308 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
309 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
310 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
311 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
312 SKL_SNOOP_HITM|SKL_SPL_HIT)
313 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
314 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
315 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
316 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
317 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
318
319 static __initconst const u64 skl_hw_cache_event_ids
320 [PERF_COUNT_HW_CACHE_MAX]
321 [PERF_COUNT_HW_CACHE_OP_MAX]
322 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
323 {
324 [ C(L1D ) ] = {
325 [ C(OP_READ) ] = {
326 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
327 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
328 },
329 [ C(OP_WRITE) ] = {
330 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
331 [ C(RESULT_MISS) ] = 0x0,
332 },
333 [ C(OP_PREFETCH) ] = {
334 [ C(RESULT_ACCESS) ] = 0x0,
335 [ C(RESULT_MISS) ] = 0x0,
336 },
337 },
338 [ C(L1I ) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = 0x0,
341 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
342 },
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = -1,
345 [ C(RESULT_MISS) ] = -1,
346 },
347 [ C(OP_PREFETCH) ] = {
348 [ C(RESULT_ACCESS) ] = 0x0,
349 [ C(RESULT_MISS) ] = 0x0,
350 },
351 },
352 [ C(LL ) ] = {
353 [ C(OP_READ) ] = {
354 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
355 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
356 },
357 [ C(OP_WRITE) ] = {
358 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
359 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
360 },
361 [ C(OP_PREFETCH) ] = {
362 [ C(RESULT_ACCESS) ] = 0x0,
363 [ C(RESULT_MISS) ] = 0x0,
364 },
365 },
366 [ C(DTLB) ] = {
367 [ C(OP_READ) ] = {
368 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
369 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
370 },
371 [ C(OP_WRITE) ] = {
372 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
373 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
374 },
375 [ C(OP_PREFETCH) ] = {
376 [ C(RESULT_ACCESS) ] = 0x0,
377 [ C(RESULT_MISS) ] = 0x0,
378 },
379 },
380 [ C(ITLB) ] = {
381 [ C(OP_READ) ] = {
382 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
383 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
384 },
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = -1,
387 [ C(RESULT_MISS) ] = -1,
388 },
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = -1,
391 [ C(RESULT_MISS) ] = -1,
392 },
393 },
394 [ C(BPU ) ] = {
395 [ C(OP_READ) ] = {
396 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
397 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
398 },
399 [ C(OP_WRITE) ] = {
400 [ C(RESULT_ACCESS) ] = -1,
401 [ C(RESULT_MISS) ] = -1,
402 },
403 [ C(OP_PREFETCH) ] = {
404 [ C(RESULT_ACCESS) ] = -1,
405 [ C(RESULT_MISS) ] = -1,
406 },
407 },
408 [ C(NODE) ] = {
409 [ C(OP_READ) ] = {
410 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
411 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
412 },
413 [ C(OP_WRITE) ] = {
414 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
415 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
416 },
417 [ C(OP_PREFETCH) ] = {
418 [ C(RESULT_ACCESS) ] = 0x0,
419 [ C(RESULT_MISS) ] = 0x0,
420 },
421 },
422 };
423
424 static __initconst const u64 skl_hw_cache_extra_regs
425 [PERF_COUNT_HW_CACHE_MAX]
426 [PERF_COUNT_HW_CACHE_OP_MAX]
427 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
428 {
429 [ C(LL ) ] = {
430 [ C(OP_READ) ] = {
431 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
432 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
433 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
434 SKL_L3_MISS|SKL_ANY_SNOOP|
435 SKL_SUPPLIER_NONE,
436 },
437 [ C(OP_WRITE) ] = {
438 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
439 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
440 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
441 SKL_L3_MISS|SKL_ANY_SNOOP|
442 SKL_SUPPLIER_NONE,
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
447 },
448 },
449 [ C(NODE) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
452 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
453 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
454 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
455 },
456 [ C(OP_WRITE) ] = {
457 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
458 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
459 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
460 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
461 },
462 [ C(OP_PREFETCH) ] = {
463 [ C(RESULT_ACCESS) ] = 0x0,
464 [ C(RESULT_MISS) ] = 0x0,
465 },
466 },
467 };
468
469 #define SNB_DMND_DATA_RD (1ULL << 0)
470 #define SNB_DMND_RFO (1ULL << 1)
471 #define SNB_DMND_IFETCH (1ULL << 2)
472 #define SNB_DMND_WB (1ULL << 3)
473 #define SNB_PF_DATA_RD (1ULL << 4)
474 #define SNB_PF_RFO (1ULL << 5)
475 #define SNB_PF_IFETCH (1ULL << 6)
476 #define SNB_LLC_DATA_RD (1ULL << 7)
477 #define SNB_LLC_RFO (1ULL << 8)
478 #define SNB_LLC_IFETCH (1ULL << 9)
479 #define SNB_BUS_LOCKS (1ULL << 10)
480 #define SNB_STRM_ST (1ULL << 11)
481 #define SNB_OTHER (1ULL << 15)
482 #define SNB_RESP_ANY (1ULL << 16)
483 #define SNB_NO_SUPP (1ULL << 17)
484 #define SNB_LLC_HITM (1ULL << 18)
485 #define SNB_LLC_HITE (1ULL << 19)
486 #define SNB_LLC_HITS (1ULL << 20)
487 #define SNB_LLC_HITF (1ULL << 21)
488 #define SNB_LOCAL (1ULL << 22)
489 #define SNB_REMOTE (0xffULL << 23)
490 #define SNB_SNP_NONE (1ULL << 31)
491 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
492 #define SNB_SNP_MISS (1ULL << 33)
493 #define SNB_NO_FWD (1ULL << 34)
494 #define SNB_SNP_FWD (1ULL << 35)
495 #define SNB_HITM (1ULL << 36)
496 #define SNB_NON_DRAM (1ULL << 37)
497
498 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
499 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
500 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
501
502 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
503 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
504 SNB_HITM)
505
506 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
507 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
508
509 #define SNB_L3_ACCESS SNB_RESP_ANY
510 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
511
512 static __initconst const u64 snb_hw_cache_extra_regs
513 [PERF_COUNT_HW_CACHE_MAX]
514 [PERF_COUNT_HW_CACHE_OP_MAX]
515 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
516 {
517 [ C(LL ) ] = {
518 [ C(OP_READ) ] = {
519 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
520 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
521 },
522 [ C(OP_WRITE) ] = {
523 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
524 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
525 },
526 [ C(OP_PREFETCH) ] = {
527 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
528 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
529 },
530 },
531 [ C(NODE) ] = {
532 [ C(OP_READ) ] = {
533 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
534 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
535 },
536 [ C(OP_WRITE) ] = {
537 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
538 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
539 },
540 [ C(OP_PREFETCH) ] = {
541 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
542 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
543 },
544 },
545 };
546
547 static __initconst const u64 snb_hw_cache_event_ids
548 [PERF_COUNT_HW_CACHE_MAX]
549 [PERF_COUNT_HW_CACHE_OP_MAX]
550 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
551 {
552 [ C(L1D) ] = {
553 [ C(OP_READ) ] = {
554 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
555 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
556 },
557 [ C(OP_WRITE) ] = {
558 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
559 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
560 },
561 [ C(OP_PREFETCH) ] = {
562 [ C(RESULT_ACCESS) ] = 0x0,
563 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
564 },
565 },
566 [ C(L1I ) ] = {
567 [ C(OP_READ) ] = {
568 [ C(RESULT_ACCESS) ] = 0x0,
569 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
570 },
571 [ C(OP_WRITE) ] = {
572 [ C(RESULT_ACCESS) ] = -1,
573 [ C(RESULT_MISS) ] = -1,
574 },
575 [ C(OP_PREFETCH) ] = {
576 [ C(RESULT_ACCESS) ] = 0x0,
577 [ C(RESULT_MISS) ] = 0x0,
578 },
579 },
580 [ C(LL ) ] = {
581 [ C(OP_READ) ] = {
582 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
583 [ C(RESULT_ACCESS) ] = 0x01b7,
584 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
585 [ C(RESULT_MISS) ] = 0x01b7,
586 },
587 [ C(OP_WRITE) ] = {
588 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
589 [ C(RESULT_ACCESS) ] = 0x01b7,
590 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
591 [ C(RESULT_MISS) ] = 0x01b7,
592 },
593 [ C(OP_PREFETCH) ] = {
594 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
595 [ C(RESULT_ACCESS) ] = 0x01b7,
596 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
597 [ C(RESULT_MISS) ] = 0x01b7,
598 },
599 },
600 [ C(DTLB) ] = {
601 [ C(OP_READ) ] = {
602 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
603 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
604 },
605 [ C(OP_WRITE) ] = {
606 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
607 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
608 },
609 [ C(OP_PREFETCH) ] = {
610 [ C(RESULT_ACCESS) ] = 0x0,
611 [ C(RESULT_MISS) ] = 0x0,
612 },
613 },
614 [ C(ITLB) ] = {
615 [ C(OP_READ) ] = {
616 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
617 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
618 },
619 [ C(OP_WRITE) ] = {
620 [ C(RESULT_ACCESS) ] = -1,
621 [ C(RESULT_MISS) ] = -1,
622 },
623 [ C(OP_PREFETCH) ] = {
624 [ C(RESULT_ACCESS) ] = -1,
625 [ C(RESULT_MISS) ] = -1,
626 },
627 },
628 [ C(BPU ) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
631 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
632 },
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = -1,
635 [ C(RESULT_MISS) ] = -1,
636 },
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = -1,
639 [ C(RESULT_MISS) ] = -1,
640 },
641 },
642 [ C(NODE) ] = {
643 [ C(OP_READ) ] = {
644 [ C(RESULT_ACCESS) ] = 0x01b7,
645 [ C(RESULT_MISS) ] = 0x01b7,
646 },
647 [ C(OP_WRITE) ] = {
648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 [ C(RESULT_MISS) ] = 0x01b7,
650 },
651 [ C(OP_PREFETCH) ] = {
652 [ C(RESULT_ACCESS) ] = 0x01b7,
653 [ C(RESULT_MISS) ] = 0x01b7,
654 },
655 },
656
657 };
658
659 /*
660 * Notes on the events:
661 * - data reads do not include code reads (comparable to earlier tables)
662 * - data counts include speculative execution (except L1 write, dtlb, bpu)
663 * - remote node access includes remote memory, remote cache, remote mmio.
664 * - prefetches are not included in the counts because they are not
665 * reliably counted.
666 */
667
668 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
669 #define HSW_DEMAND_RFO BIT_ULL(1)
670 #define HSW_ANY_RESPONSE BIT_ULL(16)
671 #define HSW_SUPPLIER_NONE BIT_ULL(17)
672 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
673 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
674 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
675 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
676 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
677 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
678 HSW_L3_MISS_REMOTE_HOP2P)
679 #define HSW_SNOOP_NONE BIT_ULL(31)
680 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
681 #define HSW_SNOOP_MISS BIT_ULL(33)
682 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
683 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
684 #define HSW_SNOOP_HITM BIT_ULL(36)
685 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
686 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
687 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
688 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
689 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
690 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
691 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
692 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
693 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
694 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
695 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
696
697 #define BDW_L3_MISS_LOCAL BIT(26)
698 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
699 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
700 HSW_L3_MISS_REMOTE_HOP2P)
701
702
703 static __initconst const u64 hsw_hw_cache_event_ids
704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707 {
708 [ C(L1D ) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
711 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
715 [ C(RESULT_MISS) ] = 0x0,
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x0,
719 [ C(RESULT_MISS) ] = 0x0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0,
725 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0x0,
733 [ C(RESULT_MISS) ] = 0x0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
739 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
743 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0x0,
747 [ C(RESULT_MISS) ] = 0x0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
753 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
757 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0x0,
761 [ C(RESULT_MISS) ] = 0x0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
767 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
781 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792 [ C(NODE) ] = {
793 [ C(OP_READ) ] = {
794 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
795 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
796 },
797 [ C(OP_WRITE) ] = {
798 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
799 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
800 },
801 [ C(OP_PREFETCH) ] = {
802 [ C(RESULT_ACCESS) ] = 0x0,
803 [ C(RESULT_MISS) ] = 0x0,
804 },
805 },
806 };
807
808 static __initconst const u64 hsw_hw_cache_extra_regs
809 [PERF_COUNT_HW_CACHE_MAX]
810 [PERF_COUNT_HW_CACHE_OP_MAX]
811 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
812 {
813 [ C(LL ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
816 HSW_LLC_ACCESS,
817 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
818 HSW_L3_MISS|HSW_ANY_SNOOP,
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
822 HSW_LLC_ACCESS,
823 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
824 HSW_L3_MISS|HSW_ANY_SNOOP,
825 },
826 [ C(OP_PREFETCH) ] = {
827 [ C(RESULT_ACCESS) ] = 0x0,
828 [ C(RESULT_MISS) ] = 0x0,
829 },
830 },
831 [ C(NODE) ] = {
832 [ C(OP_READ) ] = {
833 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
834 HSW_L3_MISS_LOCAL_DRAM|
835 HSW_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
837 HSW_L3_MISS_REMOTE|
838 HSW_SNOOP_DRAM,
839 },
840 [ C(OP_WRITE) ] = {
841 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
842 HSW_L3_MISS_LOCAL_DRAM|
843 HSW_SNOOP_DRAM,
844 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
845 HSW_L3_MISS_REMOTE|
846 HSW_SNOOP_DRAM,
847 },
848 [ C(OP_PREFETCH) ] = {
849 [ C(RESULT_ACCESS) ] = 0x0,
850 [ C(RESULT_MISS) ] = 0x0,
851 },
852 },
853 };
854
855 static __initconst const u64 westmere_hw_cache_event_ids
856 [PERF_COUNT_HW_CACHE_MAX]
857 [PERF_COUNT_HW_CACHE_OP_MAX]
858 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
859 {
860 [ C(L1D) ] = {
861 [ C(OP_READ) ] = {
862 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
863 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
864 },
865 [ C(OP_WRITE) ] = {
866 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
867 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
868 },
869 [ C(OP_PREFETCH) ] = {
870 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
871 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
872 },
873 },
874 [ C(L1I ) ] = {
875 [ C(OP_READ) ] = {
876 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
877 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
878 },
879 [ C(OP_WRITE) ] = {
880 [ C(RESULT_ACCESS) ] = -1,
881 [ C(RESULT_MISS) ] = -1,
882 },
883 [ C(OP_PREFETCH) ] = {
884 [ C(RESULT_ACCESS) ] = 0x0,
885 [ C(RESULT_MISS) ] = 0x0,
886 },
887 },
888 [ C(LL ) ] = {
889 [ C(OP_READ) ] = {
890 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
891 [ C(RESULT_ACCESS) ] = 0x01b7,
892 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
893 [ C(RESULT_MISS) ] = 0x01b7,
894 },
895 /*
896 * Use RFO, not WRITEBACK, because a write miss would typically occur
897 * on RFO.
898 */
899 [ C(OP_WRITE) ] = {
900 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
901 [ C(RESULT_ACCESS) ] = 0x01b7,
902 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
903 [ C(RESULT_MISS) ] = 0x01b7,
904 },
905 [ C(OP_PREFETCH) ] = {
906 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
907 [ C(RESULT_ACCESS) ] = 0x01b7,
908 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
909 [ C(RESULT_MISS) ] = 0x01b7,
910 },
911 },
912 [ C(DTLB) ] = {
913 [ C(OP_READ) ] = {
914 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
915 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
916 },
917 [ C(OP_WRITE) ] = {
918 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
919 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
920 },
921 [ C(OP_PREFETCH) ] = {
922 [ C(RESULT_ACCESS) ] = 0x0,
923 [ C(RESULT_MISS) ] = 0x0,
924 },
925 },
926 [ C(ITLB) ] = {
927 [ C(OP_READ) ] = {
928 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
929 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
930 },
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = -1,
933 [ C(RESULT_MISS) ] = -1,
934 },
935 [ C(OP_PREFETCH) ] = {
936 [ C(RESULT_ACCESS) ] = -1,
937 [ C(RESULT_MISS) ] = -1,
938 },
939 },
940 [ C(BPU ) ] = {
941 [ C(OP_READ) ] = {
942 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
943 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
944 },
945 [ C(OP_WRITE) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = -1,
951 [ C(RESULT_MISS) ] = -1,
952 },
953 },
954 [ C(NODE) ] = {
955 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 [ C(RESULT_MISS) ] = 0x01b7,
958 },
959 [ C(OP_WRITE) ] = {
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 [ C(RESULT_MISS) ] = 0x01b7,
962 },
963 [ C(OP_PREFETCH) ] = {
964 [ C(RESULT_ACCESS) ] = 0x01b7,
965 [ C(RESULT_MISS) ] = 0x01b7,
966 },
967 },
968 };
969
970 /*
971 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
972 * See IA32 SDM Vol 3B 30.6.1.3
973 */
974
975 #define NHM_DMND_DATA_RD (1 << 0)
976 #define NHM_DMND_RFO (1 << 1)
977 #define NHM_DMND_IFETCH (1 << 2)
978 #define NHM_DMND_WB (1 << 3)
979 #define NHM_PF_DATA_RD (1 << 4)
980 #define NHM_PF_DATA_RFO (1 << 5)
981 #define NHM_PF_IFETCH (1 << 6)
982 #define NHM_OFFCORE_OTHER (1 << 7)
983 #define NHM_UNCORE_HIT (1 << 8)
984 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
985 #define NHM_OTHER_CORE_HITM (1 << 10)
986 /* reserved */
987 #define NHM_REMOTE_CACHE_FWD (1 << 12)
988 #define NHM_REMOTE_DRAM (1 << 13)
989 #define NHM_LOCAL_DRAM (1 << 14)
990 #define NHM_NON_DRAM (1 << 15)
991
992 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
993 #define NHM_REMOTE (NHM_REMOTE_DRAM)
994
995 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
996 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
997 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
998
999 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1000 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1001 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1002
1003 static __initconst const u64 nehalem_hw_cache_extra_regs
1004 [PERF_COUNT_HW_CACHE_MAX]
1005 [PERF_COUNT_HW_CACHE_OP_MAX]
1006 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1007 {
1008 [ C(LL ) ] = {
1009 [ C(OP_READ) ] = {
1010 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1011 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1012 },
1013 [ C(OP_WRITE) ] = {
1014 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1015 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1016 },
1017 [ C(OP_PREFETCH) ] = {
1018 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1019 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1020 },
1021 },
1022 [ C(NODE) ] = {
1023 [ C(OP_READ) ] = {
1024 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1025 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1026 },
1027 [ C(OP_WRITE) ] = {
1028 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1029 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1030 },
1031 [ C(OP_PREFETCH) ] = {
1032 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1033 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1034 },
1035 },
1036 };
1037
1038 static __initconst const u64 nehalem_hw_cache_event_ids
1039 [PERF_COUNT_HW_CACHE_MAX]
1040 [PERF_COUNT_HW_CACHE_OP_MAX]
1041 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1042 {
1043 [ C(L1D) ] = {
1044 [ C(OP_READ) ] = {
1045 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1046 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1047 },
1048 [ C(OP_WRITE) ] = {
1049 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1050 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1051 },
1052 [ C(OP_PREFETCH) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1054 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1055 },
1056 },
1057 [ C(L1I ) ] = {
1058 [ C(OP_READ) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1060 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1061 },
1062 [ C(OP_WRITE) ] = {
1063 [ C(RESULT_ACCESS) ] = -1,
1064 [ C(RESULT_MISS) ] = -1,
1065 },
1066 [ C(OP_PREFETCH) ] = {
1067 [ C(RESULT_ACCESS) ] = 0x0,
1068 [ C(RESULT_MISS) ] = 0x0,
1069 },
1070 },
1071 [ C(LL ) ] = {
1072 [ C(OP_READ) ] = {
1073 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1074 [ C(RESULT_ACCESS) ] = 0x01b7,
1075 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1076 [ C(RESULT_MISS) ] = 0x01b7,
1077 },
1078 /*
1079 * Use RFO, not WRITEBACK, because a write miss would typically occur
1080 * on RFO.
1081 */
1082 [ C(OP_WRITE) ] = {
1083 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1084 [ C(RESULT_ACCESS) ] = 0x01b7,
1085 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1086 [ C(RESULT_MISS) ] = 0x01b7,
1087 },
1088 [ C(OP_PREFETCH) ] = {
1089 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1090 [ C(RESULT_ACCESS) ] = 0x01b7,
1091 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1092 [ C(RESULT_MISS) ] = 0x01b7,
1093 },
1094 },
1095 [ C(DTLB) ] = {
1096 [ C(OP_READ) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1098 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1099 },
1100 [ C(OP_WRITE) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1102 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1103 },
1104 [ C(OP_PREFETCH) ] = {
1105 [ C(RESULT_ACCESS) ] = 0x0,
1106 [ C(RESULT_MISS) ] = 0x0,
1107 },
1108 },
1109 [ C(ITLB) ] = {
1110 [ C(OP_READ) ] = {
1111 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1112 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1113 },
1114 [ C(OP_WRITE) ] = {
1115 [ C(RESULT_ACCESS) ] = -1,
1116 [ C(RESULT_MISS) ] = -1,
1117 },
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = -1,
1120 [ C(RESULT_MISS) ] = -1,
1121 },
1122 },
1123 [ C(BPU ) ] = {
1124 [ C(OP_READ) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1126 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1127 },
1128 [ C(OP_WRITE) ] = {
1129 [ C(RESULT_ACCESS) ] = -1,
1130 [ C(RESULT_MISS) ] = -1,
1131 },
1132 [ C(OP_PREFETCH) ] = {
1133 [ C(RESULT_ACCESS) ] = -1,
1134 [ C(RESULT_MISS) ] = -1,
1135 },
1136 },
1137 [ C(NODE) ] = {
1138 [ C(OP_READ) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 [ C(RESULT_MISS) ] = 0x01b7,
1141 },
1142 [ C(OP_WRITE) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x01b7,
1144 [ C(RESULT_MISS) ] = 0x01b7,
1145 },
1146 [ C(OP_PREFETCH) ] = {
1147 [ C(RESULT_ACCESS) ] = 0x01b7,
1148 [ C(RESULT_MISS) ] = 0x01b7,
1149 },
1150 },
1151 };
1152
1153 static __initconst const u64 core2_hw_cache_event_ids
1154 [PERF_COUNT_HW_CACHE_MAX]
1155 [PERF_COUNT_HW_CACHE_OP_MAX]
1156 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1157 {
1158 [ C(L1D) ] = {
1159 [ C(OP_READ) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1161 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1162 },
1163 [ C(OP_WRITE) ] = {
1164 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1165 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1166 },
1167 [ C(OP_PREFETCH) ] = {
1168 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1169 [ C(RESULT_MISS) ] = 0,
1170 },
1171 },
1172 [ C(L1I ) ] = {
1173 [ C(OP_READ) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1175 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1176 },
1177 [ C(OP_WRITE) ] = {
1178 [ C(RESULT_ACCESS) ] = -1,
1179 [ C(RESULT_MISS) ] = -1,
1180 },
1181 [ C(OP_PREFETCH) ] = {
1182 [ C(RESULT_ACCESS) ] = 0,
1183 [ C(RESULT_MISS) ] = 0,
1184 },
1185 },
1186 [ C(LL ) ] = {
1187 [ C(OP_READ) ] = {
1188 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1189 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1190 },
1191 [ C(OP_WRITE) ] = {
1192 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1193 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1194 },
1195 [ C(OP_PREFETCH) ] = {
1196 [ C(RESULT_ACCESS) ] = 0,
1197 [ C(RESULT_MISS) ] = 0,
1198 },
1199 },
1200 [ C(DTLB) ] = {
1201 [ C(OP_READ) ] = {
1202 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1203 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1204 },
1205 [ C(OP_WRITE) ] = {
1206 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1207 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1208 },
1209 [ C(OP_PREFETCH) ] = {
1210 [ C(RESULT_ACCESS) ] = 0,
1211 [ C(RESULT_MISS) ] = 0,
1212 },
1213 },
1214 [ C(ITLB) ] = {
1215 [ C(OP_READ) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1217 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1218 },
1219 [ C(OP_WRITE) ] = {
1220 [ C(RESULT_ACCESS) ] = -1,
1221 [ C(RESULT_MISS) ] = -1,
1222 },
1223 [ C(OP_PREFETCH) ] = {
1224 [ C(RESULT_ACCESS) ] = -1,
1225 [ C(RESULT_MISS) ] = -1,
1226 },
1227 },
1228 [ C(BPU ) ] = {
1229 [ C(OP_READ) ] = {
1230 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1231 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1232 },
1233 [ C(OP_WRITE) ] = {
1234 [ C(RESULT_ACCESS) ] = -1,
1235 [ C(RESULT_MISS) ] = -1,
1236 },
1237 [ C(OP_PREFETCH) ] = {
1238 [ C(RESULT_ACCESS) ] = -1,
1239 [ C(RESULT_MISS) ] = -1,
1240 },
1241 },
1242 };
1243
1244 static __initconst const u64 atom_hw_cache_event_ids
1245 [PERF_COUNT_HW_CACHE_MAX]
1246 [PERF_COUNT_HW_CACHE_OP_MAX]
1247 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1248 {
1249 [ C(L1D) ] = {
1250 [ C(OP_READ) ] = {
1251 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1252 [ C(RESULT_MISS) ] = 0,
1253 },
1254 [ C(OP_WRITE) ] = {
1255 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1256 [ C(RESULT_MISS) ] = 0,
1257 },
1258 [ C(OP_PREFETCH) ] = {
1259 [ C(RESULT_ACCESS) ] = 0x0,
1260 [ C(RESULT_MISS) ] = 0,
1261 },
1262 },
1263 [ C(L1I ) ] = {
1264 [ C(OP_READ) ] = {
1265 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1266 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1267 },
1268 [ C(OP_WRITE) ] = {
1269 [ C(RESULT_ACCESS) ] = -1,
1270 [ C(RESULT_MISS) ] = -1,
1271 },
1272 [ C(OP_PREFETCH) ] = {
1273 [ C(RESULT_ACCESS) ] = 0,
1274 [ C(RESULT_MISS) ] = 0,
1275 },
1276 },
1277 [ C(LL ) ] = {
1278 [ C(OP_READ) ] = {
1279 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1280 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1281 },
1282 [ C(OP_WRITE) ] = {
1283 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1284 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1285 },
1286 [ C(OP_PREFETCH) ] = {
1287 [ C(RESULT_ACCESS) ] = 0,
1288 [ C(RESULT_MISS) ] = 0,
1289 },
1290 },
1291 [ C(DTLB) ] = {
1292 [ C(OP_READ) ] = {
1293 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1294 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1295 },
1296 [ C(OP_WRITE) ] = {
1297 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1298 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1299 },
1300 [ C(OP_PREFETCH) ] = {
1301 [ C(RESULT_ACCESS) ] = 0,
1302 [ C(RESULT_MISS) ] = 0,
1303 },
1304 },
1305 [ C(ITLB) ] = {
1306 [ C(OP_READ) ] = {
1307 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1308 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1309 },
1310 [ C(OP_WRITE) ] = {
1311 [ C(RESULT_ACCESS) ] = -1,
1312 [ C(RESULT_MISS) ] = -1,
1313 },
1314 [ C(OP_PREFETCH) ] = {
1315 [ C(RESULT_ACCESS) ] = -1,
1316 [ C(RESULT_MISS) ] = -1,
1317 },
1318 },
1319 [ C(BPU ) ] = {
1320 [ C(OP_READ) ] = {
1321 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1322 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1323 },
1324 [ C(OP_WRITE) ] = {
1325 [ C(RESULT_ACCESS) ] = -1,
1326 [ C(RESULT_MISS) ] = -1,
1327 },
1328 [ C(OP_PREFETCH) ] = {
1329 [ C(RESULT_ACCESS) ] = -1,
1330 [ C(RESULT_MISS) ] = -1,
1331 },
1332 },
1333 };
1334
1335 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1336 {
1337 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1338 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1339 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1340 EVENT_EXTRA_END
1341 };
1342
1343 #define SLM_DMND_READ SNB_DMND_DATA_RD
1344 #define SLM_DMND_WRITE SNB_DMND_RFO
1345 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1346
1347 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1348 #define SLM_LLC_ACCESS SNB_RESP_ANY
1349 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1350
1351 static __initconst const u64 slm_hw_cache_extra_regs
1352 [PERF_COUNT_HW_CACHE_MAX]
1353 [PERF_COUNT_HW_CACHE_OP_MAX]
1354 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1355 {
1356 [ C(LL ) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1359 [ C(RESULT_MISS) ] = 0,
1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1363 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1367 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1368 },
1369 },
1370 };
1371
1372 static __initconst const u64 slm_hw_cache_event_ids
1373 [PERF_COUNT_HW_CACHE_MAX]
1374 [PERF_COUNT_HW_CACHE_OP_MAX]
1375 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1376 {
1377 [ C(L1D) ] = {
1378 [ C(OP_READ) ] = {
1379 [ C(RESULT_ACCESS) ] = 0,
1380 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1381 },
1382 [ C(OP_WRITE) ] = {
1383 [ C(RESULT_ACCESS) ] = 0,
1384 [ C(RESULT_MISS) ] = 0,
1385 },
1386 [ C(OP_PREFETCH) ] = {
1387 [ C(RESULT_ACCESS) ] = 0,
1388 [ C(RESULT_MISS) ] = 0,
1389 },
1390 },
1391 [ C(L1I ) ] = {
1392 [ C(OP_READ) ] = {
1393 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1394 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1395 },
1396 [ C(OP_WRITE) ] = {
1397 [ C(RESULT_ACCESS) ] = -1,
1398 [ C(RESULT_MISS) ] = -1,
1399 },
1400 [ C(OP_PREFETCH) ] = {
1401 [ C(RESULT_ACCESS) ] = 0,
1402 [ C(RESULT_MISS) ] = 0,
1403 },
1404 },
1405 [ C(LL ) ] = {
1406 [ C(OP_READ) ] = {
1407 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1408 [ C(RESULT_ACCESS) ] = 0x01b7,
1409 [ C(RESULT_MISS) ] = 0,
1410 },
1411 [ C(OP_WRITE) ] = {
1412 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1413 [ C(RESULT_ACCESS) ] = 0x01b7,
1414 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1415 [ C(RESULT_MISS) ] = 0x01b7,
1416 },
1417 [ C(OP_PREFETCH) ] = {
1418 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1419 [ C(RESULT_ACCESS) ] = 0x01b7,
1420 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1421 [ C(RESULT_MISS) ] = 0x01b7,
1422 },
1423 },
1424 [ C(DTLB) ] = {
1425 [ C(OP_READ) ] = {
1426 [ C(RESULT_ACCESS) ] = 0,
1427 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1428 },
1429 [ C(OP_WRITE) ] = {
1430 [ C(RESULT_ACCESS) ] = 0,
1431 [ C(RESULT_MISS) ] = 0,
1432 },
1433 [ C(OP_PREFETCH) ] = {
1434 [ C(RESULT_ACCESS) ] = 0,
1435 [ C(RESULT_MISS) ] = 0,
1436 },
1437 },
1438 [ C(ITLB) ] = {
1439 [ C(OP_READ) ] = {
1440 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1441 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1442 },
1443 [ C(OP_WRITE) ] = {
1444 [ C(RESULT_ACCESS) ] = -1,
1445 [ C(RESULT_MISS) ] = -1,
1446 },
1447 [ C(OP_PREFETCH) ] = {
1448 [ C(RESULT_ACCESS) ] = -1,
1449 [ C(RESULT_MISS) ] = -1,
1450 },
1451 },
1452 [ C(BPU ) ] = {
1453 [ C(OP_READ) ] = {
1454 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1455 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1456 },
1457 [ C(OP_WRITE) ] = {
1458 [ C(RESULT_ACCESS) ] = -1,
1459 [ C(RESULT_MISS) ] = -1,
1460 },
1461 [ C(OP_PREFETCH) ] = {
1462 [ C(RESULT_ACCESS) ] = -1,
1463 [ C(RESULT_MISS) ] = -1,
1464 },
1465 },
1466 };
1467
1468 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1469 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1470 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1471 #define KNL_MCDRAM_FAR BIT_ULL(22)
1472 #define KNL_DDR_LOCAL BIT_ULL(23)
1473 #define KNL_DDR_FAR BIT_ULL(24)
1474 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1475 KNL_DDR_LOCAL | KNL_DDR_FAR)
1476 #define KNL_L2_READ SLM_DMND_READ
1477 #define KNL_L2_WRITE SLM_DMND_WRITE
1478 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1479 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1480 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1481 KNL_DRAM_ANY | SNB_SNP_ANY | \
1482 SNB_NON_DRAM)
1483
1484 static __initconst const u64 knl_hw_cache_extra_regs
1485 [PERF_COUNT_HW_CACHE_MAX]
1486 [PERF_COUNT_HW_CACHE_OP_MAX]
1487 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1488 [C(LL)] = {
1489 [C(OP_READ)] = {
1490 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1491 [C(RESULT_MISS)] = 0,
1492 },
1493 [C(OP_WRITE)] = {
1494 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1495 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1496 },
1497 [C(OP_PREFETCH)] = {
1498 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1499 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1500 },
1501 },
1502 };
1503
1504 /*
1505 * Use from PMIs where the LBRs are already disabled.
1506 */
1507 static void __intel_pmu_disable_all(void)
1508 {
1509 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1510
1511 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1512
1513 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1514 intel_pmu_disable_bts();
1515 else
1516 intel_bts_disable_local();
1517
1518 intel_pmu_pebs_disable_all();
1519 }
1520
1521 static void intel_pmu_disable_all(void)
1522 {
1523 __intel_pmu_disable_all();
1524 intel_pmu_lbr_disable_all();
1525 }
1526
1527 static void __intel_pmu_enable_all(int added, bool pmi)
1528 {
1529 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1530
1531 intel_pmu_pebs_enable_all();
1532 intel_pmu_lbr_enable_all(pmi);
1533 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1534 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1535
1536 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1537 struct perf_event *event =
1538 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1539
1540 if (WARN_ON_ONCE(!event))
1541 return;
1542
1543 intel_pmu_enable_bts(event->hw.config);
1544 } else
1545 intel_bts_enable_local();
1546 }
1547
1548 static void intel_pmu_enable_all(int added)
1549 {
1550 __intel_pmu_enable_all(added, false);
1551 }
1552
1553 /*
1554 * Workaround for:
1555 * Intel Errata AAK100 (model 26)
1556 * Intel Errata AAP53 (model 30)
1557 * Intel Errata BD53 (model 44)
1558 *
1559 * The official story:
1560 * These chips need to be 'reset' when adding counters by programming the
1561 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1562 * in sequence on the same PMC or on different PMCs.
1563 *
1564 * In practise it appears some of these events do in fact count, and
1565 * we need to programm all 4 events.
1566 */
1567 static void intel_pmu_nhm_workaround(void)
1568 {
1569 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1570 static const unsigned long nhm_magic[4] = {
1571 0x4300B5,
1572 0x4300D2,
1573 0x4300B1,
1574 0x4300B1
1575 };
1576 struct perf_event *event;
1577 int i;
1578
1579 /*
1580 * The Errata requires below steps:
1581 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1582 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1583 * the corresponding PMCx;
1584 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1585 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1586 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1587 */
1588
1589 /*
1590 * The real steps we choose are a little different from above.
1591 * A) To reduce MSR operations, we don't run step 1) as they
1592 * are already cleared before this function is called;
1593 * B) Call x86_perf_event_update to save PMCx before configuring
1594 * PERFEVTSELx with magic number;
1595 * C) With step 5), we do clear only when the PERFEVTSELx is
1596 * not used currently.
1597 * D) Call x86_perf_event_set_period to restore PMCx;
1598 */
1599
1600 /* We always operate 4 pairs of PERF Counters */
1601 for (i = 0; i < 4; i++) {
1602 event = cpuc->events[i];
1603 if (event)
1604 x86_perf_event_update(event);
1605 }
1606
1607 for (i = 0; i < 4; i++) {
1608 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1609 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1610 }
1611
1612 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1613 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1614
1615 for (i = 0; i < 4; i++) {
1616 event = cpuc->events[i];
1617
1618 if (event) {
1619 x86_perf_event_set_period(event);
1620 __x86_pmu_enable_event(&event->hw,
1621 ARCH_PERFMON_EVENTSEL_ENABLE);
1622 } else
1623 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1624 }
1625 }
1626
1627 static void intel_pmu_nhm_enable_all(int added)
1628 {
1629 if (added)
1630 intel_pmu_nhm_workaround();
1631 intel_pmu_enable_all(added);
1632 }
1633
1634 static inline u64 intel_pmu_get_status(void)
1635 {
1636 u64 status;
1637
1638 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1639
1640 return status;
1641 }
1642
1643 static inline void intel_pmu_ack_status(u64 ack)
1644 {
1645 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1646 }
1647
1648 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1649 {
1650 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1651 u64 ctrl_val, mask;
1652
1653 mask = 0xfULL << (idx * 4);
1654
1655 rdmsrl(hwc->config_base, ctrl_val);
1656 ctrl_val &= ~mask;
1657 wrmsrl(hwc->config_base, ctrl_val);
1658 }
1659
1660 static inline bool event_is_checkpointed(struct perf_event *event)
1661 {
1662 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1663 }
1664
1665 static void intel_pmu_disable_event(struct perf_event *event)
1666 {
1667 struct hw_perf_event *hwc = &event->hw;
1668 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1669
1670 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1671 intel_pmu_disable_bts();
1672 intel_pmu_drain_bts_buffer();
1673 return;
1674 }
1675
1676 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1677 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1678 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1679
1680 /*
1681 * must disable before any actual event
1682 * because any event may be combined with LBR
1683 */
1684 if (needs_branch_stack(event))
1685 intel_pmu_lbr_disable(event);
1686
1687 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1688 intel_pmu_disable_fixed(hwc);
1689 return;
1690 }
1691
1692 x86_pmu_disable_event(event);
1693
1694 if (unlikely(event->attr.precise_ip))
1695 intel_pmu_pebs_disable(event);
1696 }
1697
1698 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1699 {
1700 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1701 u64 ctrl_val, bits, mask;
1702
1703 /*
1704 * Enable IRQ generation (0x8),
1705 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1706 * if requested:
1707 */
1708 bits = 0x8ULL;
1709 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1710 bits |= 0x2;
1711 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1712 bits |= 0x1;
1713
1714 /*
1715 * ANY bit is supported in v3 and up
1716 */
1717 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1718 bits |= 0x4;
1719
1720 bits <<= (idx * 4);
1721 mask = 0xfULL << (idx * 4);
1722
1723 rdmsrl(hwc->config_base, ctrl_val);
1724 ctrl_val &= ~mask;
1725 ctrl_val |= bits;
1726 wrmsrl(hwc->config_base, ctrl_val);
1727 }
1728
1729 static void intel_pmu_enable_event(struct perf_event *event)
1730 {
1731 struct hw_perf_event *hwc = &event->hw;
1732 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1733
1734 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1735 if (!__this_cpu_read(cpu_hw_events.enabled))
1736 return;
1737
1738 intel_pmu_enable_bts(hwc->config);
1739 return;
1740 }
1741 /*
1742 * must enabled before any actual event
1743 * because any event may be combined with LBR
1744 */
1745 if (needs_branch_stack(event))
1746 intel_pmu_lbr_enable(event);
1747
1748 if (event->attr.exclude_host)
1749 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1750 if (event->attr.exclude_guest)
1751 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1752
1753 if (unlikely(event_is_checkpointed(event)))
1754 cpuc->intel_cp_status |= (1ull << hwc->idx);
1755
1756 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1757 intel_pmu_enable_fixed(hwc);
1758 return;
1759 }
1760
1761 if (unlikely(event->attr.precise_ip))
1762 intel_pmu_pebs_enable(event);
1763
1764 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1765 }
1766
1767 /*
1768 * Save and restart an expired event. Called by NMI contexts,
1769 * so it has to be careful about preempting normal event ops:
1770 */
1771 int intel_pmu_save_and_restart(struct perf_event *event)
1772 {
1773 x86_perf_event_update(event);
1774 /*
1775 * For a checkpointed counter always reset back to 0. This
1776 * avoids a situation where the counter overflows, aborts the
1777 * transaction and is then set back to shortly before the
1778 * overflow, and overflows and aborts again.
1779 */
1780 if (unlikely(event_is_checkpointed(event))) {
1781 /* No race with NMIs because the counter should not be armed */
1782 wrmsrl(event->hw.event_base, 0);
1783 local64_set(&event->hw.prev_count, 0);
1784 }
1785 return x86_perf_event_set_period(event);
1786 }
1787
1788 static void intel_pmu_reset(void)
1789 {
1790 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1791 unsigned long flags;
1792 int idx;
1793
1794 if (!x86_pmu.num_counters)
1795 return;
1796
1797 local_irq_save(flags);
1798
1799 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1800
1801 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1802 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1803 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
1804 }
1805 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1806 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1807
1808 if (ds)
1809 ds->bts_index = ds->bts_buffer_base;
1810
1811 /* Ack all overflows and disable fixed counters */
1812 if (x86_pmu.version >= 2) {
1813 intel_pmu_ack_status(intel_pmu_get_status());
1814 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1815 }
1816
1817 /* Reset LBRs and LBR freezing */
1818 if (x86_pmu.lbr_nr) {
1819 update_debugctlmsr(get_debugctlmsr() &
1820 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1821 }
1822
1823 local_irq_restore(flags);
1824 }
1825
1826 /*
1827 * This handler is triggered by the local APIC, so the APIC IRQ handling
1828 * rules apply:
1829 */
1830 static int intel_pmu_handle_irq(struct pt_regs *regs)
1831 {
1832 struct perf_sample_data data;
1833 struct cpu_hw_events *cpuc;
1834 int bit, loops;
1835 u64 status;
1836 int handled;
1837
1838 cpuc = this_cpu_ptr(&cpu_hw_events);
1839
1840 /*
1841 * No known reason to not always do late ACK,
1842 * but just in case do it opt-in.
1843 */
1844 if (!x86_pmu.late_ack)
1845 apic_write(APIC_LVTPC, APIC_DM_NMI);
1846 __intel_pmu_disable_all();
1847 handled = intel_pmu_drain_bts_buffer();
1848 handled += intel_bts_interrupt();
1849 status = intel_pmu_get_status();
1850 if (!status)
1851 goto done;
1852
1853 loops = 0;
1854 again:
1855 intel_pmu_lbr_read();
1856 intel_pmu_ack_status(status);
1857 if (++loops > 100) {
1858 static bool warned = false;
1859 if (!warned) {
1860 WARN(1, "perfevents: irq loop stuck!\n");
1861 perf_event_print_debug();
1862 warned = true;
1863 }
1864 intel_pmu_reset();
1865 goto done;
1866 }
1867
1868 inc_irq_stat(apic_perf_irqs);
1869
1870
1871 /*
1872 * Ignore a range of extra bits in status that do not indicate
1873 * overflow by themselves.
1874 */
1875 status &= ~(GLOBAL_STATUS_COND_CHG |
1876 GLOBAL_STATUS_ASIF |
1877 GLOBAL_STATUS_LBRS_FROZEN);
1878 if (!status)
1879 goto done;
1880
1881 /*
1882 * PEBS overflow sets bit 62 in the global status register
1883 */
1884 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1885 handled++;
1886 x86_pmu.drain_pebs(regs);
1887 }
1888
1889 /*
1890 * Intel PT
1891 */
1892 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1893 handled++;
1894 intel_pt_interrupt();
1895 }
1896
1897 /*
1898 * Checkpointed counters can lead to 'spurious' PMIs because the
1899 * rollback caused by the PMI will have cleared the overflow status
1900 * bit. Therefore always force probe these counters.
1901 */
1902 status |= cpuc->intel_cp_status;
1903
1904 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1905 struct perf_event *event = cpuc->events[bit];
1906
1907 handled++;
1908
1909 if (!test_bit(bit, cpuc->active_mask))
1910 continue;
1911
1912 if (!intel_pmu_save_and_restart(event))
1913 continue;
1914
1915 perf_sample_data_init(&data, 0, event->hw.last_period);
1916
1917 if (has_branch_stack(event))
1918 data.br_stack = &cpuc->lbr_stack;
1919
1920 if (perf_event_overflow(event, &data, regs))
1921 x86_pmu_stop(event, 0);
1922 }
1923
1924 /*
1925 * Repeat if there is more work to be done:
1926 */
1927 status = intel_pmu_get_status();
1928 if (status)
1929 goto again;
1930
1931 done:
1932 __intel_pmu_enable_all(0, true);
1933 /*
1934 * Only unmask the NMI after the overflow counters
1935 * have been reset. This avoids spurious NMIs on
1936 * Haswell CPUs.
1937 */
1938 if (x86_pmu.late_ack)
1939 apic_write(APIC_LVTPC, APIC_DM_NMI);
1940 return handled;
1941 }
1942
1943 static struct event_constraint *
1944 intel_bts_constraints(struct perf_event *event)
1945 {
1946 struct hw_perf_event *hwc = &event->hw;
1947 unsigned int hw_event, bts_event;
1948
1949 if (event->attr.freq)
1950 return NULL;
1951
1952 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1953 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1954
1955 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1956 return &bts_constraint;
1957
1958 return NULL;
1959 }
1960
1961 static int intel_alt_er(int idx, u64 config)
1962 {
1963 int alt_idx;
1964 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
1965 return idx;
1966
1967 if (idx == EXTRA_REG_RSP_0)
1968 alt_idx = EXTRA_REG_RSP_1;
1969
1970 if (idx == EXTRA_REG_RSP_1)
1971 alt_idx = EXTRA_REG_RSP_0;
1972
1973 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
1974 return idx;
1975
1976 return alt_idx;
1977 }
1978
1979 static void intel_fixup_er(struct perf_event *event, int idx)
1980 {
1981 event->hw.extra_reg.idx = idx;
1982
1983 if (idx == EXTRA_REG_RSP_0) {
1984 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1985 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1986 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1987 } else if (idx == EXTRA_REG_RSP_1) {
1988 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1989 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1990 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1991 }
1992 }
1993
1994 /*
1995 * manage allocation of shared extra msr for certain events
1996 *
1997 * sharing can be:
1998 * per-cpu: to be shared between the various events on a single PMU
1999 * per-core: per-cpu + shared by HT threads
2000 */
2001 static struct event_constraint *
2002 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2003 struct perf_event *event,
2004 struct hw_perf_event_extra *reg)
2005 {
2006 struct event_constraint *c = &emptyconstraint;
2007 struct er_account *era;
2008 unsigned long flags;
2009 int idx = reg->idx;
2010
2011 /*
2012 * reg->alloc can be set due to existing state, so for fake cpuc we
2013 * need to ignore this, otherwise we might fail to allocate proper fake
2014 * state for this extra reg constraint. Also see the comment below.
2015 */
2016 if (reg->alloc && !cpuc->is_fake)
2017 return NULL; /* call x86_get_event_constraint() */
2018
2019 again:
2020 era = &cpuc->shared_regs->regs[idx];
2021 /*
2022 * we use spin_lock_irqsave() to avoid lockdep issues when
2023 * passing a fake cpuc
2024 */
2025 raw_spin_lock_irqsave(&era->lock, flags);
2026
2027 if (!atomic_read(&era->ref) || era->config == reg->config) {
2028
2029 /*
2030 * If its a fake cpuc -- as per validate_{group,event}() we
2031 * shouldn't touch event state and we can avoid doing so
2032 * since both will only call get_event_constraints() once
2033 * on each event, this avoids the need for reg->alloc.
2034 *
2035 * Not doing the ER fixup will only result in era->reg being
2036 * wrong, but since we won't actually try and program hardware
2037 * this isn't a problem either.
2038 */
2039 if (!cpuc->is_fake) {
2040 if (idx != reg->idx)
2041 intel_fixup_er(event, idx);
2042
2043 /*
2044 * x86_schedule_events() can call get_event_constraints()
2045 * multiple times on events in the case of incremental
2046 * scheduling(). reg->alloc ensures we only do the ER
2047 * allocation once.
2048 */
2049 reg->alloc = 1;
2050 }
2051
2052 /* lock in msr value */
2053 era->config = reg->config;
2054 era->reg = reg->reg;
2055
2056 /* one more user */
2057 atomic_inc(&era->ref);
2058
2059 /*
2060 * need to call x86_get_event_constraint()
2061 * to check if associated event has constraints
2062 */
2063 c = NULL;
2064 } else {
2065 idx = intel_alt_er(idx, reg->config);
2066 if (idx != reg->idx) {
2067 raw_spin_unlock_irqrestore(&era->lock, flags);
2068 goto again;
2069 }
2070 }
2071 raw_spin_unlock_irqrestore(&era->lock, flags);
2072
2073 return c;
2074 }
2075
2076 static void
2077 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2078 struct hw_perf_event_extra *reg)
2079 {
2080 struct er_account *era;
2081
2082 /*
2083 * Only put constraint if extra reg was actually allocated. Also takes
2084 * care of event which do not use an extra shared reg.
2085 *
2086 * Also, if this is a fake cpuc we shouldn't touch any event state
2087 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2088 * either since it'll be thrown out.
2089 */
2090 if (!reg->alloc || cpuc->is_fake)
2091 return;
2092
2093 era = &cpuc->shared_regs->regs[reg->idx];
2094
2095 /* one fewer user */
2096 atomic_dec(&era->ref);
2097
2098 /* allocate again next time */
2099 reg->alloc = 0;
2100 }
2101
2102 static struct event_constraint *
2103 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2104 struct perf_event *event)
2105 {
2106 struct event_constraint *c = NULL, *d;
2107 struct hw_perf_event_extra *xreg, *breg;
2108
2109 xreg = &event->hw.extra_reg;
2110 if (xreg->idx != EXTRA_REG_NONE) {
2111 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2112 if (c == &emptyconstraint)
2113 return c;
2114 }
2115 breg = &event->hw.branch_reg;
2116 if (breg->idx != EXTRA_REG_NONE) {
2117 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2118 if (d == &emptyconstraint) {
2119 __intel_shared_reg_put_constraints(cpuc, xreg);
2120 c = d;
2121 }
2122 }
2123 return c;
2124 }
2125
2126 struct event_constraint *
2127 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2128 struct perf_event *event)
2129 {
2130 struct event_constraint *c;
2131
2132 if (x86_pmu.event_constraints) {
2133 for_each_event_constraint(c, x86_pmu.event_constraints) {
2134 if ((event->hw.config & c->cmask) == c->code) {
2135 event->hw.flags |= c->flags;
2136 return c;
2137 }
2138 }
2139 }
2140
2141 return &unconstrained;
2142 }
2143
2144 static struct event_constraint *
2145 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2146 struct perf_event *event)
2147 {
2148 struct event_constraint *c;
2149
2150 c = intel_bts_constraints(event);
2151 if (c)
2152 return c;
2153
2154 c = intel_shared_regs_constraints(cpuc, event);
2155 if (c)
2156 return c;
2157
2158 c = intel_pebs_constraints(event);
2159 if (c)
2160 return c;
2161
2162 return x86_get_event_constraints(cpuc, idx, event);
2163 }
2164
2165 static void
2166 intel_start_scheduling(struct cpu_hw_events *cpuc)
2167 {
2168 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2169 struct intel_excl_states *xl;
2170 int tid = cpuc->excl_thread_id;
2171
2172 /*
2173 * nothing needed if in group validation mode
2174 */
2175 if (cpuc->is_fake || !is_ht_workaround_enabled())
2176 return;
2177
2178 /*
2179 * no exclusion needed
2180 */
2181 if (WARN_ON_ONCE(!excl_cntrs))
2182 return;
2183
2184 xl = &excl_cntrs->states[tid];
2185
2186 xl->sched_started = true;
2187 /*
2188 * lock shared state until we are done scheduling
2189 * in stop_event_scheduling()
2190 * makes scheduling appear as a transaction
2191 */
2192 raw_spin_lock(&excl_cntrs->lock);
2193 }
2194
2195 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2196 {
2197 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2198 struct event_constraint *c = cpuc->event_constraint[idx];
2199 struct intel_excl_states *xl;
2200 int tid = cpuc->excl_thread_id;
2201
2202 if (cpuc->is_fake || !is_ht_workaround_enabled())
2203 return;
2204
2205 if (WARN_ON_ONCE(!excl_cntrs))
2206 return;
2207
2208 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2209 return;
2210
2211 xl = &excl_cntrs->states[tid];
2212
2213 lockdep_assert_held(&excl_cntrs->lock);
2214
2215 if (c->flags & PERF_X86_EVENT_EXCL)
2216 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2217 else
2218 xl->state[cntr] = INTEL_EXCL_SHARED;
2219 }
2220
2221 static void
2222 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2223 {
2224 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2225 struct intel_excl_states *xl;
2226 int tid = cpuc->excl_thread_id;
2227
2228 /*
2229 * nothing needed if in group validation mode
2230 */
2231 if (cpuc->is_fake || !is_ht_workaround_enabled())
2232 return;
2233 /*
2234 * no exclusion needed
2235 */
2236 if (WARN_ON_ONCE(!excl_cntrs))
2237 return;
2238
2239 xl = &excl_cntrs->states[tid];
2240
2241 xl->sched_started = false;
2242 /*
2243 * release shared state lock (acquired in intel_start_scheduling())
2244 */
2245 raw_spin_unlock(&excl_cntrs->lock);
2246 }
2247
2248 static struct event_constraint *
2249 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2250 int idx, struct event_constraint *c)
2251 {
2252 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2253 struct intel_excl_states *xlo;
2254 int tid = cpuc->excl_thread_id;
2255 int is_excl, i;
2256
2257 /*
2258 * validating a group does not require
2259 * enforcing cross-thread exclusion
2260 */
2261 if (cpuc->is_fake || !is_ht_workaround_enabled())
2262 return c;
2263
2264 /*
2265 * no exclusion needed
2266 */
2267 if (WARN_ON_ONCE(!excl_cntrs))
2268 return c;
2269
2270 /*
2271 * because we modify the constraint, we need
2272 * to make a copy. Static constraints come
2273 * from static const tables.
2274 *
2275 * only needed when constraint has not yet
2276 * been cloned (marked dynamic)
2277 */
2278 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2279 struct event_constraint *cx;
2280
2281 /*
2282 * grab pre-allocated constraint entry
2283 */
2284 cx = &cpuc->constraint_list[idx];
2285
2286 /*
2287 * initialize dynamic constraint
2288 * with static constraint
2289 */
2290 *cx = *c;
2291
2292 /*
2293 * mark constraint as dynamic, so we
2294 * can free it later on
2295 */
2296 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2297 c = cx;
2298 }
2299
2300 /*
2301 * From here on, the constraint is dynamic.
2302 * Either it was just allocated above, or it
2303 * was allocated during a earlier invocation
2304 * of this function
2305 */
2306
2307 /*
2308 * state of sibling HT
2309 */
2310 xlo = &excl_cntrs->states[tid ^ 1];
2311
2312 /*
2313 * event requires exclusive counter access
2314 * across HT threads
2315 */
2316 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2317 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2318 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2319 if (!cpuc->n_excl++)
2320 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2321 }
2322
2323 /*
2324 * Modify static constraint with current dynamic
2325 * state of thread
2326 *
2327 * EXCLUSIVE: sibling counter measuring exclusive event
2328 * SHARED : sibling counter measuring non-exclusive event
2329 * UNUSED : sibling counter unused
2330 */
2331 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2332 /*
2333 * exclusive event in sibling counter
2334 * our corresponding counter cannot be used
2335 * regardless of our event
2336 */
2337 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2338 __clear_bit(i, c->idxmsk);
2339 /*
2340 * if measuring an exclusive event, sibling
2341 * measuring non-exclusive, then counter cannot
2342 * be used
2343 */
2344 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2345 __clear_bit(i, c->idxmsk);
2346 }
2347
2348 /*
2349 * recompute actual bit weight for scheduling algorithm
2350 */
2351 c->weight = hweight64(c->idxmsk64);
2352
2353 /*
2354 * if we return an empty mask, then switch
2355 * back to static empty constraint to avoid
2356 * the cost of freeing later on
2357 */
2358 if (c->weight == 0)
2359 c = &emptyconstraint;
2360
2361 return c;
2362 }
2363
2364 static struct event_constraint *
2365 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2366 struct perf_event *event)
2367 {
2368 struct event_constraint *c1 = NULL;
2369 struct event_constraint *c2;
2370
2371 if (idx >= 0) /* fake does < 0 */
2372 c1 = cpuc->event_constraint[idx];
2373
2374 /*
2375 * first time only
2376 * - static constraint: no change across incremental scheduling calls
2377 * - dynamic constraint: handled by intel_get_excl_constraints()
2378 */
2379 c2 = __intel_get_event_constraints(cpuc, idx, event);
2380 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2381 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2382 c1->weight = c2->weight;
2383 c2 = c1;
2384 }
2385
2386 if (cpuc->excl_cntrs)
2387 return intel_get_excl_constraints(cpuc, event, idx, c2);
2388
2389 return c2;
2390 }
2391
2392 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2393 struct perf_event *event)
2394 {
2395 struct hw_perf_event *hwc = &event->hw;
2396 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2397 int tid = cpuc->excl_thread_id;
2398 struct intel_excl_states *xl;
2399
2400 /*
2401 * nothing needed if in group validation mode
2402 */
2403 if (cpuc->is_fake)
2404 return;
2405
2406 if (WARN_ON_ONCE(!excl_cntrs))
2407 return;
2408
2409 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2410 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2411 if (!--cpuc->n_excl)
2412 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2413 }
2414
2415 /*
2416 * If event was actually assigned, then mark the counter state as
2417 * unused now.
2418 */
2419 if (hwc->idx >= 0) {
2420 xl = &excl_cntrs->states[tid];
2421
2422 /*
2423 * put_constraint may be called from x86_schedule_events()
2424 * which already has the lock held so here make locking
2425 * conditional.
2426 */
2427 if (!xl->sched_started)
2428 raw_spin_lock(&excl_cntrs->lock);
2429
2430 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2431
2432 if (!xl->sched_started)
2433 raw_spin_unlock(&excl_cntrs->lock);
2434 }
2435 }
2436
2437 static void
2438 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2439 struct perf_event *event)
2440 {
2441 struct hw_perf_event_extra *reg;
2442
2443 reg = &event->hw.extra_reg;
2444 if (reg->idx != EXTRA_REG_NONE)
2445 __intel_shared_reg_put_constraints(cpuc, reg);
2446
2447 reg = &event->hw.branch_reg;
2448 if (reg->idx != EXTRA_REG_NONE)
2449 __intel_shared_reg_put_constraints(cpuc, reg);
2450 }
2451
2452 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2453 struct perf_event *event)
2454 {
2455 intel_put_shared_regs_event_constraints(cpuc, event);
2456
2457 /*
2458 * is PMU has exclusive counter restrictions, then
2459 * all events are subject to and must call the
2460 * put_excl_constraints() routine
2461 */
2462 if (cpuc->excl_cntrs)
2463 intel_put_excl_constraints(cpuc, event);
2464 }
2465
2466 static void intel_pebs_aliases_core2(struct perf_event *event)
2467 {
2468 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2469 /*
2470 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2471 * (0x003c) so that we can use it with PEBS.
2472 *
2473 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2474 * PEBS capable. However we can use INST_RETIRED.ANY_P
2475 * (0x00c0), which is a PEBS capable event, to get the same
2476 * count.
2477 *
2478 * INST_RETIRED.ANY_P counts the number of cycles that retires
2479 * CNTMASK instructions. By setting CNTMASK to a value (16)
2480 * larger than the maximum number of instructions that can be
2481 * retired per cycle (4) and then inverting the condition, we
2482 * count all cycles that retire 16 or less instructions, which
2483 * is every cycle.
2484 *
2485 * Thereby we gain a PEBS capable cycle counter.
2486 */
2487 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2488
2489 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2490 event->hw.config = alt_config;
2491 }
2492 }
2493
2494 static void intel_pebs_aliases_snb(struct perf_event *event)
2495 {
2496 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2497 /*
2498 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2499 * (0x003c) so that we can use it with PEBS.
2500 *
2501 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2502 * PEBS capable. However we can use UOPS_RETIRED.ALL
2503 * (0x01c2), which is a PEBS capable event, to get the same
2504 * count.
2505 *
2506 * UOPS_RETIRED.ALL counts the number of cycles that retires
2507 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2508 * larger than the maximum number of micro-ops that can be
2509 * retired per cycle (4) and then inverting the condition, we
2510 * count all cycles that retire 16 or less micro-ops, which
2511 * is every cycle.
2512 *
2513 * Thereby we gain a PEBS capable cycle counter.
2514 */
2515 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2516
2517 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2518 event->hw.config = alt_config;
2519 }
2520 }
2521
2522 static void intel_pebs_aliases_precdist(struct perf_event *event)
2523 {
2524 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2525 /*
2526 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2527 * (0x003c) so that we can use it with PEBS.
2528 *
2529 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2530 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2531 * (0x01c0), which is a PEBS capable event, to get the same
2532 * count.
2533 *
2534 * The PREC_DIST event has special support to minimize sample
2535 * shadowing effects. One drawback is that it can be
2536 * only programmed on counter 1, but that seems like an
2537 * acceptable trade off.
2538 */
2539 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2540
2541 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2542 event->hw.config = alt_config;
2543 }
2544 }
2545
2546 static void intel_pebs_aliases_ivb(struct perf_event *event)
2547 {
2548 if (event->attr.precise_ip < 3)
2549 return intel_pebs_aliases_snb(event);
2550 return intel_pebs_aliases_precdist(event);
2551 }
2552
2553 static void intel_pebs_aliases_skl(struct perf_event *event)
2554 {
2555 if (event->attr.precise_ip < 3)
2556 return intel_pebs_aliases_core2(event);
2557 return intel_pebs_aliases_precdist(event);
2558 }
2559
2560 static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2561 {
2562 unsigned long flags = x86_pmu.free_running_flags;
2563
2564 if (event->attr.use_clockid)
2565 flags &= ~PERF_SAMPLE_TIME;
2566 return flags;
2567 }
2568
2569 static int intel_pmu_hw_config(struct perf_event *event)
2570 {
2571 int ret = x86_pmu_hw_config(event);
2572
2573 if (ret)
2574 return ret;
2575
2576 if (event->attr.precise_ip) {
2577 if (!event->attr.freq) {
2578 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2579 if (!(event->attr.sample_type &
2580 ~intel_pmu_free_running_flags(event)))
2581 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2582 }
2583 if (x86_pmu.pebs_aliases)
2584 x86_pmu.pebs_aliases(event);
2585 }
2586
2587 if (needs_branch_stack(event)) {
2588 ret = intel_pmu_setup_lbr_filter(event);
2589 if (ret)
2590 return ret;
2591
2592 /*
2593 * BTS is set up earlier in this path, so don't account twice
2594 */
2595 if (!intel_pmu_has_bts(event)) {
2596 /* disallow lbr if conflicting events are present */
2597 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2598 return -EBUSY;
2599
2600 event->destroy = hw_perf_lbr_event_destroy;
2601 }
2602 }
2603
2604 if (event->attr.type != PERF_TYPE_RAW)
2605 return 0;
2606
2607 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2608 return 0;
2609
2610 if (x86_pmu.version < 3)
2611 return -EINVAL;
2612
2613 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2614 return -EACCES;
2615
2616 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2617
2618 return 0;
2619 }
2620
2621 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2622 {
2623 if (x86_pmu.guest_get_msrs)
2624 return x86_pmu.guest_get_msrs(nr);
2625 *nr = 0;
2626 return NULL;
2627 }
2628 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2629
2630 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2631 {
2632 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2633 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2634
2635 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2636 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2637 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2638 /*
2639 * If PMU counter has PEBS enabled it is not enough to disable counter
2640 * on a guest entry since PEBS memory write can overshoot guest entry
2641 * and corrupt guest memory. Disabling PEBS solves the problem.
2642 */
2643 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2644 arr[1].host = cpuc->pebs_enabled;
2645 arr[1].guest = 0;
2646
2647 *nr = 2;
2648 return arr;
2649 }
2650
2651 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2652 {
2653 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2654 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2655 int idx;
2656
2657 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2658 struct perf_event *event = cpuc->events[idx];
2659
2660 arr[idx].msr = x86_pmu_config_addr(idx);
2661 arr[idx].host = arr[idx].guest = 0;
2662
2663 if (!test_bit(idx, cpuc->active_mask))
2664 continue;
2665
2666 arr[idx].host = arr[idx].guest =
2667 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2668
2669 if (event->attr.exclude_host)
2670 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2671 else if (event->attr.exclude_guest)
2672 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2673 }
2674
2675 *nr = x86_pmu.num_counters;
2676 return arr;
2677 }
2678
2679 static void core_pmu_enable_event(struct perf_event *event)
2680 {
2681 if (!event->attr.exclude_host)
2682 x86_pmu_enable_event(event);
2683 }
2684
2685 static void core_pmu_enable_all(int added)
2686 {
2687 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2688 int idx;
2689
2690 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2691 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2692
2693 if (!test_bit(idx, cpuc->active_mask) ||
2694 cpuc->events[idx]->attr.exclude_host)
2695 continue;
2696
2697 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2698 }
2699 }
2700
2701 static int hsw_hw_config(struct perf_event *event)
2702 {
2703 int ret = intel_pmu_hw_config(event);
2704
2705 if (ret)
2706 return ret;
2707 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2708 return 0;
2709 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2710
2711 /*
2712 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2713 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2714 * this combination.
2715 */
2716 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2717 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2718 event->attr.precise_ip > 0))
2719 return -EOPNOTSUPP;
2720
2721 if (event_is_checkpointed(event)) {
2722 /*
2723 * Sampling of checkpointed events can cause situations where
2724 * the CPU constantly aborts because of a overflow, which is
2725 * then checkpointed back and ignored. Forbid checkpointing
2726 * for sampling.
2727 *
2728 * But still allow a long sampling period, so that perf stat
2729 * from KVM works.
2730 */
2731 if (event->attr.sample_period > 0 &&
2732 event->attr.sample_period < 0x7fffffff)
2733 return -EOPNOTSUPP;
2734 }
2735 return 0;
2736 }
2737
2738 static struct event_constraint counter2_constraint =
2739 EVENT_CONSTRAINT(0, 0x4, 0);
2740
2741 static struct event_constraint *
2742 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2743 struct perf_event *event)
2744 {
2745 struct event_constraint *c;
2746
2747 c = intel_get_event_constraints(cpuc, idx, event);
2748
2749 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2750 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2751 if (c->idxmsk64 & (1U << 2))
2752 return &counter2_constraint;
2753 return &emptyconstraint;
2754 }
2755
2756 return c;
2757 }
2758
2759 /*
2760 * Broadwell:
2761 *
2762 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2763 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2764 * the two to enforce a minimum period of 128 (the smallest value that has bits
2765 * 0-5 cleared and >= 100).
2766 *
2767 * Because of how the code in x86_perf_event_set_period() works, the truncation
2768 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2769 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2770 *
2771 * Therefore the effective (average) period matches the requested period,
2772 * despite coarser hardware granularity.
2773 */
2774 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2775 {
2776 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2777 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2778 if (left < 128)
2779 left = 128;
2780 left &= ~0x3fu;
2781 }
2782 return left;
2783 }
2784
2785 PMU_FORMAT_ATTR(event, "config:0-7" );
2786 PMU_FORMAT_ATTR(umask, "config:8-15" );
2787 PMU_FORMAT_ATTR(edge, "config:18" );
2788 PMU_FORMAT_ATTR(pc, "config:19" );
2789 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2790 PMU_FORMAT_ATTR(inv, "config:23" );
2791 PMU_FORMAT_ATTR(cmask, "config:24-31" );
2792 PMU_FORMAT_ATTR(in_tx, "config:32");
2793 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
2794
2795 static struct attribute *intel_arch_formats_attr[] = {
2796 &format_attr_event.attr,
2797 &format_attr_umask.attr,
2798 &format_attr_edge.attr,
2799 &format_attr_pc.attr,
2800 &format_attr_inv.attr,
2801 &format_attr_cmask.attr,
2802 NULL,
2803 };
2804
2805 ssize_t intel_event_sysfs_show(char *page, u64 config)
2806 {
2807 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2808
2809 return x86_event_sysfs_show(page, config, event);
2810 }
2811
2812 struct intel_shared_regs *allocate_shared_regs(int cpu)
2813 {
2814 struct intel_shared_regs *regs;
2815 int i;
2816
2817 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2818 GFP_KERNEL, cpu_to_node(cpu));
2819 if (regs) {
2820 /*
2821 * initialize the locks to keep lockdep happy
2822 */
2823 for (i = 0; i < EXTRA_REG_MAX; i++)
2824 raw_spin_lock_init(&regs->regs[i].lock);
2825
2826 regs->core_id = -1;
2827 }
2828 return regs;
2829 }
2830
2831 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2832 {
2833 struct intel_excl_cntrs *c;
2834
2835 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2836 GFP_KERNEL, cpu_to_node(cpu));
2837 if (c) {
2838 raw_spin_lock_init(&c->lock);
2839 c->core_id = -1;
2840 }
2841 return c;
2842 }
2843
2844 static int intel_pmu_cpu_prepare(int cpu)
2845 {
2846 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2847
2848 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2849 cpuc->shared_regs = allocate_shared_regs(cpu);
2850 if (!cpuc->shared_regs)
2851 goto err;
2852 }
2853
2854 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2855 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2856
2857 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2858 if (!cpuc->constraint_list)
2859 goto err_shared_regs;
2860
2861 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2862 if (!cpuc->excl_cntrs)
2863 goto err_constraint_list;
2864
2865 cpuc->excl_thread_id = 0;
2866 }
2867
2868 return NOTIFY_OK;
2869
2870 err_constraint_list:
2871 kfree(cpuc->constraint_list);
2872 cpuc->constraint_list = NULL;
2873
2874 err_shared_regs:
2875 kfree(cpuc->shared_regs);
2876 cpuc->shared_regs = NULL;
2877
2878 err:
2879 return NOTIFY_BAD;
2880 }
2881
2882 static void intel_pmu_cpu_starting(int cpu)
2883 {
2884 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2885 int core_id = topology_core_id(cpu);
2886 int i;
2887
2888 init_debug_store_on_cpu(cpu);
2889 /*
2890 * Deal with CPUs that don't clear their LBRs on power-up.
2891 */
2892 intel_pmu_lbr_reset();
2893
2894 cpuc->lbr_sel = NULL;
2895
2896 if (!cpuc->shared_regs)
2897 return;
2898
2899 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
2900 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2901
2902 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
2903 struct intel_shared_regs *pc;
2904
2905 pc = per_cpu(cpu_hw_events, i).shared_regs;
2906 if (pc && pc->core_id == core_id) {
2907 *onln = cpuc->shared_regs;
2908 cpuc->shared_regs = pc;
2909 break;
2910 }
2911 }
2912 cpuc->shared_regs->core_id = core_id;
2913 cpuc->shared_regs->refcnt++;
2914 }
2915
2916 if (x86_pmu.lbr_sel_map)
2917 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2918
2919 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2920 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
2921 struct intel_excl_cntrs *c;
2922
2923 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2924 if (c && c->core_id == core_id) {
2925 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2926 cpuc->excl_cntrs = c;
2927 cpuc->excl_thread_id = 1;
2928 break;
2929 }
2930 }
2931 cpuc->excl_cntrs->core_id = core_id;
2932 cpuc->excl_cntrs->refcnt++;
2933 }
2934 }
2935
2936 static void free_excl_cntrs(int cpu)
2937 {
2938 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2939 struct intel_excl_cntrs *c;
2940
2941 c = cpuc->excl_cntrs;
2942 if (c) {
2943 if (c->core_id == -1 || --c->refcnt == 0)
2944 kfree(c);
2945 cpuc->excl_cntrs = NULL;
2946 kfree(cpuc->constraint_list);
2947 cpuc->constraint_list = NULL;
2948 }
2949 }
2950
2951 static void intel_pmu_cpu_dying(int cpu)
2952 {
2953 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2954 struct intel_shared_regs *pc;
2955
2956 pc = cpuc->shared_regs;
2957 if (pc) {
2958 if (pc->core_id == -1 || --pc->refcnt == 0)
2959 kfree(pc);
2960 cpuc->shared_regs = NULL;
2961 }
2962
2963 free_excl_cntrs(cpu);
2964
2965 fini_debug_store_on_cpu(cpu);
2966 }
2967
2968 static void intel_pmu_sched_task(struct perf_event_context *ctx,
2969 bool sched_in)
2970 {
2971 if (x86_pmu.pebs_active)
2972 intel_pmu_pebs_sched_task(ctx, sched_in);
2973 if (x86_pmu.lbr_nr)
2974 intel_pmu_lbr_sched_task(ctx, sched_in);
2975 }
2976
2977 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2978
2979 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2980
2981 PMU_FORMAT_ATTR(frontend, "config1:0-23");
2982
2983 static struct attribute *intel_arch3_formats_attr[] = {
2984 &format_attr_event.attr,
2985 &format_attr_umask.attr,
2986 &format_attr_edge.attr,
2987 &format_attr_pc.attr,
2988 &format_attr_any.attr,
2989 &format_attr_inv.attr,
2990 &format_attr_cmask.attr,
2991 &format_attr_in_tx.attr,
2992 &format_attr_in_tx_cp.attr,
2993
2994 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2995 &format_attr_ldlat.attr, /* PEBS load latency */
2996 NULL,
2997 };
2998
2999 static struct attribute *skl_format_attr[] = {
3000 &format_attr_frontend.attr,
3001 NULL,
3002 };
3003
3004 static __initconst const struct x86_pmu core_pmu = {
3005 .name = "core",
3006 .handle_irq = x86_pmu_handle_irq,
3007 .disable_all = x86_pmu_disable_all,
3008 .enable_all = core_pmu_enable_all,
3009 .enable = core_pmu_enable_event,
3010 .disable = x86_pmu_disable_event,
3011 .hw_config = x86_pmu_hw_config,
3012 .schedule_events = x86_schedule_events,
3013 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3014 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3015 .event_map = intel_pmu_event_map,
3016 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3017 .apic = 1,
3018 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3019
3020 /*
3021 * Intel PMCs cannot be accessed sanely above 32-bit width,
3022 * so we install an artificial 1<<31 period regardless of
3023 * the generic event period:
3024 */
3025 .max_period = (1ULL<<31) - 1,
3026 .get_event_constraints = intel_get_event_constraints,
3027 .put_event_constraints = intel_put_event_constraints,
3028 .event_constraints = intel_core_event_constraints,
3029 .guest_get_msrs = core_guest_get_msrs,
3030 .format_attrs = intel_arch_formats_attr,
3031 .events_sysfs_show = intel_event_sysfs_show,
3032
3033 /*
3034 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3035 * together with PMU version 1 and thus be using core_pmu with
3036 * shared_regs. We need following callbacks here to allocate
3037 * it properly.
3038 */
3039 .cpu_prepare = intel_pmu_cpu_prepare,
3040 .cpu_starting = intel_pmu_cpu_starting,
3041 .cpu_dying = intel_pmu_cpu_dying,
3042 };
3043
3044 static __initconst const struct x86_pmu intel_pmu = {
3045 .name = "Intel",
3046 .handle_irq = intel_pmu_handle_irq,
3047 .disable_all = intel_pmu_disable_all,
3048 .enable_all = intel_pmu_enable_all,
3049 .enable = intel_pmu_enable_event,
3050 .disable = intel_pmu_disable_event,
3051 .hw_config = intel_pmu_hw_config,
3052 .schedule_events = x86_schedule_events,
3053 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3054 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3055 .event_map = intel_pmu_event_map,
3056 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3057 .apic = 1,
3058 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3059 /*
3060 * Intel PMCs cannot be accessed sanely above 32 bit width,
3061 * so we install an artificial 1<<31 period regardless of
3062 * the generic event period:
3063 */
3064 .max_period = (1ULL << 31) - 1,
3065 .get_event_constraints = intel_get_event_constraints,
3066 .put_event_constraints = intel_put_event_constraints,
3067 .pebs_aliases = intel_pebs_aliases_core2,
3068
3069 .format_attrs = intel_arch3_formats_attr,
3070 .events_sysfs_show = intel_event_sysfs_show,
3071
3072 .cpu_prepare = intel_pmu_cpu_prepare,
3073 .cpu_starting = intel_pmu_cpu_starting,
3074 .cpu_dying = intel_pmu_cpu_dying,
3075 .guest_get_msrs = intel_guest_get_msrs,
3076 .sched_task = intel_pmu_sched_task,
3077 };
3078
3079 static __init void intel_clovertown_quirk(void)
3080 {
3081 /*
3082 * PEBS is unreliable due to:
3083 *
3084 * AJ67 - PEBS may experience CPL leaks
3085 * AJ68 - PEBS PMI may be delayed by one event
3086 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3087 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3088 *
3089 * AJ67 could be worked around by restricting the OS/USR flags.
3090 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3091 *
3092 * AJ106 could possibly be worked around by not allowing LBR
3093 * usage from PEBS, including the fixup.
3094 * AJ68 could possibly be worked around by always programming
3095 * a pebs_event_reset[0] value and coping with the lost events.
3096 *
3097 * But taken together it might just make sense to not enable PEBS on
3098 * these chips.
3099 */
3100 pr_warn("PEBS disabled due to CPU errata\n");
3101 x86_pmu.pebs = 0;
3102 x86_pmu.pebs_constraints = NULL;
3103 }
3104
3105 static int intel_snb_pebs_broken(int cpu)
3106 {
3107 u32 rev = UINT_MAX; /* default to broken for unknown models */
3108
3109 switch (cpu_data(cpu).x86_model) {
3110 case 42: /* SNB */
3111 rev = 0x28;
3112 break;
3113
3114 case 45: /* SNB-EP */
3115 switch (cpu_data(cpu).x86_mask) {
3116 case 6: rev = 0x618; break;
3117 case 7: rev = 0x70c; break;
3118 }
3119 }
3120
3121 return (cpu_data(cpu).microcode < rev);
3122 }
3123
3124 static void intel_snb_check_microcode(void)
3125 {
3126 int pebs_broken = 0;
3127 int cpu;
3128
3129 get_online_cpus();
3130 for_each_online_cpu(cpu) {
3131 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3132 break;
3133 }
3134 put_online_cpus();
3135
3136 if (pebs_broken == x86_pmu.pebs_broken)
3137 return;
3138
3139 /*
3140 * Serialized by the microcode lock..
3141 */
3142 if (x86_pmu.pebs_broken) {
3143 pr_info("PEBS enabled due to microcode update\n");
3144 x86_pmu.pebs_broken = 0;
3145 } else {
3146 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3147 x86_pmu.pebs_broken = 1;
3148 }
3149 }
3150
3151 /*
3152 * Under certain circumstances, access certain MSR may cause #GP.
3153 * The function tests if the input MSR can be safely accessed.
3154 */
3155 static bool check_msr(unsigned long msr, u64 mask)
3156 {
3157 u64 val_old, val_new, val_tmp;
3158
3159 /*
3160 * Read the current value, change it and read it back to see if it
3161 * matches, this is needed to detect certain hardware emulators
3162 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3163 */
3164 if (rdmsrl_safe(msr, &val_old))
3165 return false;
3166
3167 /*
3168 * Only change the bits which can be updated by wrmsrl.
3169 */
3170 val_tmp = val_old ^ mask;
3171 if (wrmsrl_safe(msr, val_tmp) ||
3172 rdmsrl_safe(msr, &val_new))
3173 return false;
3174
3175 if (val_new != val_tmp)
3176 return false;
3177
3178 /* Here it's sure that the MSR can be safely accessed.
3179 * Restore the old value and return.
3180 */
3181 wrmsrl(msr, val_old);
3182
3183 return true;
3184 }
3185
3186 static __init void intel_sandybridge_quirk(void)
3187 {
3188 x86_pmu.check_microcode = intel_snb_check_microcode;
3189 intel_snb_check_microcode();
3190 }
3191
3192 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3193 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3194 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3195 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3196 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3197 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3198 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3199 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3200 };
3201
3202 static __init void intel_arch_events_quirk(void)
3203 {
3204 int bit;
3205
3206 /* disable event that reported as not presend by cpuid */
3207 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3208 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3209 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3210 intel_arch_events_map[bit].name);
3211 }
3212 }
3213
3214 static __init void intel_nehalem_quirk(void)
3215 {
3216 union cpuid10_ebx ebx;
3217
3218 ebx.full = x86_pmu.events_maskl;
3219 if (ebx.split.no_branch_misses_retired) {
3220 /*
3221 * Erratum AAJ80 detected, we work it around by using
3222 * the BR_MISP_EXEC.ANY event. This will over-count
3223 * branch-misses, but it's still much better than the
3224 * architectural event which is often completely bogus:
3225 */
3226 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3227 ebx.split.no_branch_misses_retired = 0;
3228 x86_pmu.events_maskl = ebx.full;
3229 pr_info("CPU erratum AAJ80 worked around\n");
3230 }
3231 }
3232
3233 /*
3234 * enable software workaround for errata:
3235 * SNB: BJ122
3236 * IVB: BV98
3237 * HSW: HSD29
3238 *
3239 * Only needed when HT is enabled. However detecting
3240 * if HT is enabled is difficult (model specific). So instead,
3241 * we enable the workaround in the early boot, and verify if
3242 * it is needed in a later initcall phase once we have valid
3243 * topology information to check if HT is actually enabled
3244 */
3245 static __init void intel_ht_bug(void)
3246 {
3247 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3248
3249 x86_pmu.start_scheduling = intel_start_scheduling;
3250 x86_pmu.commit_scheduling = intel_commit_scheduling;
3251 x86_pmu.stop_scheduling = intel_stop_scheduling;
3252 }
3253
3254 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3255 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
3256
3257 /* Haswell special events */
3258 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3259 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3260 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3261 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3262 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3263 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3264 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3265 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3266 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3267 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3268 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3269 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
3270
3271 static struct attribute *hsw_events_attrs[] = {
3272 EVENT_PTR(tx_start),
3273 EVENT_PTR(tx_commit),
3274 EVENT_PTR(tx_abort),
3275 EVENT_PTR(tx_capacity),
3276 EVENT_PTR(tx_conflict),
3277 EVENT_PTR(el_start),
3278 EVENT_PTR(el_commit),
3279 EVENT_PTR(el_abort),
3280 EVENT_PTR(el_capacity),
3281 EVENT_PTR(el_conflict),
3282 EVENT_PTR(cycles_t),
3283 EVENT_PTR(cycles_ct),
3284 EVENT_PTR(mem_ld_hsw),
3285 EVENT_PTR(mem_st_hsw),
3286 NULL
3287 };
3288
3289 __init int intel_pmu_init(void)
3290 {
3291 union cpuid10_edx edx;
3292 union cpuid10_eax eax;
3293 union cpuid10_ebx ebx;
3294 struct event_constraint *c;
3295 unsigned int unused;
3296 struct extra_reg *er;
3297 int version, i;
3298
3299 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
3300 switch (boot_cpu_data.x86) {
3301 case 0x6:
3302 return p6_pmu_init();
3303 case 0xb:
3304 return knc_pmu_init();
3305 case 0xf:
3306 return p4_pmu_init();
3307 }
3308 return -ENODEV;
3309 }
3310
3311 /*
3312 * Check whether the Architectural PerfMon supports
3313 * Branch Misses Retired hw_event or not.
3314 */
3315 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3316 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
3317 return -ENODEV;
3318
3319 version = eax.split.version_id;
3320 if (version < 2)
3321 x86_pmu = core_pmu;
3322 else
3323 x86_pmu = intel_pmu;
3324
3325 x86_pmu.version = version;
3326 x86_pmu.num_counters = eax.split.num_counters;
3327 x86_pmu.cntval_bits = eax.split.bit_width;
3328 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
3329
3330 x86_pmu.events_maskl = ebx.full;
3331 x86_pmu.events_mask_len = eax.split.mask_length;
3332
3333 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3334
3335 /*
3336 * Quirk: v2 perfmon does not report fixed-purpose events, so
3337 * assume at least 3 events:
3338 */
3339 if (version > 1)
3340 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
3341
3342 if (boot_cpu_has(X86_FEATURE_PDCM)) {
3343 u64 capabilities;
3344
3345 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3346 x86_pmu.intel_cap.capabilities = capabilities;
3347 }
3348
3349 intel_ds_init();
3350
3351 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3352
3353 /*
3354 * Install the hw-cache-events table:
3355 */
3356 switch (boot_cpu_data.x86_model) {
3357 case 14: /* 65nm Core "Yonah" */
3358 pr_cont("Core events, ");
3359 break;
3360
3361 case 15: /* 65nm Core2 "Merom" */
3362 x86_add_quirk(intel_clovertown_quirk);
3363 case 22: /* 65nm Core2 "Merom-L" */
3364 case 23: /* 45nm Core2 "Penryn" */
3365 case 29: /* 45nm Core2 "Dunnington (MP) */
3366 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3367 sizeof(hw_cache_event_ids));
3368
3369 intel_pmu_lbr_init_core();
3370
3371 x86_pmu.event_constraints = intel_core2_event_constraints;
3372 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3373 pr_cont("Core2 events, ");
3374 break;
3375
3376 case 30: /* 45nm Nehalem */
3377 case 26: /* 45nm Nehalem-EP */
3378 case 46: /* 45nm Nehalem-EX */
3379 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3380 sizeof(hw_cache_event_ids));
3381 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3382 sizeof(hw_cache_extra_regs));
3383
3384 intel_pmu_lbr_init_nhm();
3385
3386 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3387 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3388 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3389 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3390
3391 x86_pmu.cpu_events = nhm_events_attrs;
3392
3393 /* UOPS_ISSUED.STALLED_CYCLES */
3394 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3395 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3396 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3397 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3398 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3399
3400 x86_add_quirk(intel_nehalem_quirk);
3401
3402 pr_cont("Nehalem events, ");
3403 break;
3404
3405 case 28: /* 45nm Atom "Pineview" */
3406 case 38: /* 45nm Atom "Lincroft" */
3407 case 39: /* 32nm Atom "Penwell" */
3408 case 53: /* 32nm Atom "Cloverview" */
3409 case 54: /* 32nm Atom "Cedarview" */
3410 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3411 sizeof(hw_cache_event_ids));
3412
3413 intel_pmu_lbr_init_atom();
3414
3415 x86_pmu.event_constraints = intel_gen_event_constraints;
3416 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3417 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
3418 pr_cont("Atom events, ");
3419 break;
3420
3421 case 55: /* 22nm Atom "Silvermont" */
3422 case 76: /* 14nm Atom "Airmont" */
3423 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
3424 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3425 sizeof(hw_cache_event_ids));
3426 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3427 sizeof(hw_cache_extra_regs));
3428
3429 intel_pmu_lbr_init_atom();
3430
3431 x86_pmu.event_constraints = intel_slm_event_constraints;
3432 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3433 x86_pmu.extra_regs = intel_slm_extra_regs;
3434 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3435 pr_cont("Silvermont events, ");
3436 break;
3437
3438 case 37: /* 32nm Westmere */
3439 case 44: /* 32nm Westmere-EP */
3440 case 47: /* 32nm Westmere-EX */
3441 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3442 sizeof(hw_cache_event_ids));
3443 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3444 sizeof(hw_cache_extra_regs));
3445
3446 intel_pmu_lbr_init_nhm();
3447
3448 x86_pmu.event_constraints = intel_westmere_event_constraints;
3449 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3450 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3451 x86_pmu.extra_regs = intel_westmere_extra_regs;
3452 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3453
3454 x86_pmu.cpu_events = nhm_events_attrs;
3455
3456 /* UOPS_ISSUED.STALLED_CYCLES */
3457 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3458 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3459 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3460 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3461 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3462
3463 pr_cont("Westmere events, ");
3464 break;
3465
3466 case 42: /* 32nm SandyBridge */
3467 case 45: /* 32nm SandyBridge-E/EN/EP */
3468 x86_add_quirk(intel_sandybridge_quirk);
3469 x86_add_quirk(intel_ht_bug);
3470 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3471 sizeof(hw_cache_event_ids));
3472 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3473 sizeof(hw_cache_extra_regs));
3474
3475 intel_pmu_lbr_init_snb();
3476
3477 x86_pmu.event_constraints = intel_snb_event_constraints;
3478 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3479 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3480 if (boot_cpu_data.x86_model == 45)
3481 x86_pmu.extra_regs = intel_snbep_extra_regs;
3482 else
3483 x86_pmu.extra_regs = intel_snb_extra_regs;
3484
3485
3486 /* all extra regs are per-cpu when HT is on */
3487 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3488 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3489
3490 x86_pmu.cpu_events = snb_events_attrs;
3491
3492 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3493 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3494 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3495 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3496 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3497 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3498
3499 pr_cont("SandyBridge events, ");
3500 break;
3501
3502 case 58: /* 22nm IvyBridge */
3503 case 62: /* 22nm IvyBridge-EP/EX */
3504 x86_add_quirk(intel_ht_bug);
3505 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3506 sizeof(hw_cache_event_ids));
3507 /* dTLB-load-misses on IVB is different than SNB */
3508 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3509
3510 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3511 sizeof(hw_cache_extra_regs));
3512
3513 intel_pmu_lbr_init_snb();
3514
3515 x86_pmu.event_constraints = intel_ivb_event_constraints;
3516 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3517 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3518 x86_pmu.pebs_prec_dist = true;
3519 if (boot_cpu_data.x86_model == 62)
3520 x86_pmu.extra_regs = intel_snbep_extra_regs;
3521 else
3522 x86_pmu.extra_regs = intel_snb_extra_regs;
3523 /* all extra regs are per-cpu when HT is on */
3524 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3525 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3526
3527 x86_pmu.cpu_events = snb_events_attrs;
3528
3529 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3530 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3531 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3532
3533 pr_cont("IvyBridge events, ");
3534 break;
3535
3536
3537 case 60: /* 22nm Haswell Core */
3538 case 63: /* 22nm Haswell Server */
3539 case 69: /* 22nm Haswell ULT */
3540 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
3541 x86_add_quirk(intel_ht_bug);
3542 x86_pmu.late_ack = true;
3543 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3544 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3545
3546 intel_pmu_lbr_init_hsw();
3547
3548 x86_pmu.event_constraints = intel_hsw_event_constraints;
3549 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3550 x86_pmu.extra_regs = intel_snbep_extra_regs;
3551 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3552 x86_pmu.pebs_prec_dist = true;
3553 /* all extra regs are per-cpu when HT is on */
3554 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3555 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3556
3557 x86_pmu.hw_config = hsw_hw_config;
3558 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3559 x86_pmu.cpu_events = hsw_events_attrs;
3560 x86_pmu.lbr_double_abort = true;
3561 pr_cont("Haswell events, ");
3562 break;
3563
3564 case 61: /* 14nm Broadwell Core-M */
3565 case 86: /* 14nm Broadwell Xeon D */
3566 case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3567 case 79: /* 14nm Broadwell Server */
3568 x86_pmu.late_ack = true;
3569 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3570 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3571
3572 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3573 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3574 BDW_L3_MISS|HSW_SNOOP_DRAM;
3575 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3576 HSW_SNOOP_DRAM;
3577 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3578 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3579 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3580 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3581
3582 intel_pmu_lbr_init_hsw();
3583
3584 x86_pmu.event_constraints = intel_bdw_event_constraints;
3585 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3586 x86_pmu.extra_regs = intel_snbep_extra_regs;
3587 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3588 x86_pmu.pebs_prec_dist = true;
3589 /* all extra regs are per-cpu when HT is on */
3590 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3591 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3592
3593 x86_pmu.hw_config = hsw_hw_config;
3594 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3595 x86_pmu.cpu_events = hsw_events_attrs;
3596 x86_pmu.limit_period = bdw_limit_period;
3597 pr_cont("Broadwell events, ");
3598 break;
3599
3600 case 87: /* Knights Landing Xeon Phi */
3601 memcpy(hw_cache_event_ids,
3602 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3603 memcpy(hw_cache_extra_regs,
3604 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3605 intel_pmu_lbr_init_knl();
3606
3607 x86_pmu.event_constraints = intel_slm_event_constraints;
3608 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3609 x86_pmu.extra_regs = intel_knl_extra_regs;
3610
3611 /* all extra regs are per-cpu when HT is on */
3612 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3613 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3614
3615 pr_cont("Knights Landing events, ");
3616 break;
3617
3618 case 78: /* 14nm Skylake Mobile */
3619 case 94: /* 14nm Skylake Desktop */
3620 x86_pmu.late_ack = true;
3621 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3622 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3623 intel_pmu_lbr_init_skl();
3624
3625 x86_pmu.event_constraints = intel_skl_event_constraints;
3626 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3627 x86_pmu.extra_regs = intel_skl_extra_regs;
3628 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3629 x86_pmu.pebs_prec_dist = true;
3630 /* all extra regs are per-cpu when HT is on */
3631 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3632 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3633
3634 x86_pmu.hw_config = hsw_hw_config;
3635 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3636 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3637 skl_format_attr);
3638 WARN_ON(!x86_pmu.format_attrs);
3639 x86_pmu.cpu_events = hsw_events_attrs;
3640 pr_cont("Skylake events, ");
3641 break;
3642
3643 default:
3644 switch (x86_pmu.version) {
3645 case 1:
3646 x86_pmu.event_constraints = intel_v1_event_constraints;
3647 pr_cont("generic architected perfmon v1, ");
3648 break;
3649 default:
3650 /*
3651 * default constraints for v2 and up
3652 */
3653 x86_pmu.event_constraints = intel_gen_event_constraints;
3654 pr_cont("generic architected perfmon, ");
3655 break;
3656 }
3657 }
3658
3659 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3660 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3661 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3662 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3663 }
3664 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3665
3666 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3667 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3668 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3669 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3670 }
3671
3672 x86_pmu.intel_ctrl |=
3673 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3674
3675 if (x86_pmu.event_constraints) {
3676 /*
3677 * event on fixed counter2 (REF_CYCLES) only works on this
3678 * counter, so do not extend mask to generic counters
3679 */
3680 for_each_event_constraint(c, x86_pmu.event_constraints) {
3681 if (c->cmask == FIXED_EVENT_FLAGS
3682 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3683 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3684 }
3685 c->idxmsk64 &=
3686 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3687 c->weight = hweight64(c->idxmsk64);
3688 }
3689 }
3690
3691 /*
3692 * Access LBR MSR may cause #GP under certain circumstances.
3693 * E.g. KVM doesn't support LBR MSR
3694 * Check all LBT MSR here.
3695 * Disable LBR access if any LBR MSRs can not be accessed.
3696 */
3697 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3698 x86_pmu.lbr_nr = 0;
3699 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3700 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3701 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3702 x86_pmu.lbr_nr = 0;
3703 }
3704
3705 /*
3706 * Access extra MSR may cause #GP under certain circumstances.
3707 * E.g. KVM doesn't support offcore event
3708 * Check all extra_regs here.
3709 */
3710 if (x86_pmu.extra_regs) {
3711 for (er = x86_pmu.extra_regs; er->msr; er++) {
3712 er->extra_msr_access = check_msr(er->msr, 0x11UL);
3713 /* Disable LBR select mapping */
3714 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3715 x86_pmu.lbr_sel_map = NULL;
3716 }
3717 }
3718
3719 /* Support full width counters using alternative MSR range */
3720 if (x86_pmu.intel_cap.full_width_write) {
3721 x86_pmu.max_period = x86_pmu.cntval_mask;
3722 x86_pmu.perfctr = MSR_IA32_PMC0;
3723 pr_cont("full-width counters, ");
3724 }
3725
3726 return 0;
3727 }
3728
3729 /*
3730 * HT bug: phase 2 init
3731 * Called once we have valid topology information to check
3732 * whether or not HT is enabled
3733 * If HT is off, then we disable the workaround
3734 */
3735 static __init int fixup_ht_bug(void)
3736 {
3737 int cpu = smp_processor_id();
3738 int w, c;
3739 /*
3740 * problem not present on this CPU model, nothing to do
3741 */
3742 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3743 return 0;
3744
3745 w = cpumask_weight(topology_sibling_cpumask(cpu));
3746 if (w > 1) {
3747 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3748 return 0;
3749 }
3750
3751 if (lockup_detector_suspend() != 0) {
3752 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3753 return 0;
3754 }
3755
3756 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3757
3758 x86_pmu.start_scheduling = NULL;
3759 x86_pmu.commit_scheduling = NULL;
3760 x86_pmu.stop_scheduling = NULL;
3761
3762 lockup_detector_resume();
3763
3764 get_online_cpus();
3765
3766 for_each_online_cpu(c) {
3767 free_excl_cntrs(c);
3768 }
3769
3770 put_online_cpus();
3771 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3772 return 0;
3773 }
3774 subsys_initcall(fixup_ht_bug)
Linux with added FPC-III support