irqchip: Fix dependencies for archs w/o HAS_IOMEM
[linux/fpc-iii.git] / arch / xtensa / platforms / xtfpga / setup.c
blobe9f65f79cf2ea0bff6393313385bbebf500db9a3
1 /*
3 * arch/xtensa/platform/xtavnet/setup.c
5 * ...
7 * Authors: Chris Zankel <chris@zankel.net>
8 * Joe Taylor <joe@tensilica.com>
10 * Copyright 2001 - 2006 Tensilica Inc.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/errno.h>
22 #include <linux/reboot.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/console.h>
27 #include <linux/delay.h>
28 #include <linux/of.h>
30 #include <asm/timex.h>
31 #include <asm/processor.h>
32 #include <asm/platform.h>
33 #include <asm/bootparam.h>
34 #include <platform/lcd.h>
35 #include <platform/hardware.h>
37 void platform_halt(void)
39 lcd_disp_at_pos(" HALT ", 0);
40 local_irq_disable();
41 while (1)
42 cpu_relax();
45 void platform_power_off(void)
47 lcd_disp_at_pos("POWEROFF", 0);
48 local_irq_disable();
49 while (1)
50 cpu_relax();
53 void platform_restart(void)
55 /* Flush and reset the mmu, simulate a processor reset, and
56 * jump to the reset vector. */
59 __asm__ __volatile__ ("movi a2, 15\n\t"
60 "wsr a2, icountlevel\n\t"
61 "movi a2, 0\n\t"
62 "wsr a2, icount\n\t"
63 #if XCHAL_NUM_IBREAK > 0
64 "wsr a2, ibreakenable\n\t"
65 #endif
66 #if XCHAL_HAVE_LOOPS
67 "wsr a2, lcount\n\t"
68 #endif
69 "movi a2, 0x1f\n\t"
70 "wsr a2, ps\n\t"
71 "isync\n\t"
72 "jx %0\n\t"
74 : "a" (XCHAL_RESET_VECTOR_VADDR)
75 : "a2"
78 /* control never gets here */
81 void __init platform_setup(char **cmdline)
85 #ifdef CONFIG_OF
87 static void __init update_clock_frequency(struct device_node *node)
89 struct property *newfreq;
90 u32 freq;
92 if (!of_property_read_u32(node, "clock-frequency", &freq) && freq != 0)
93 return;
95 newfreq = kzalloc(sizeof(*newfreq) + sizeof(u32), GFP_KERNEL);
96 if (!newfreq)
97 return;
98 newfreq->value = newfreq + 1;
99 newfreq->length = sizeof(freq);
100 newfreq->name = kstrdup("clock-frequency", GFP_KERNEL);
101 if (!newfreq->name) {
102 kfree(newfreq);
103 return;
106 *(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR);
107 of_update_property(node, newfreq);
110 #define MAC_LEN 6
111 static void __init update_local_mac(struct device_node *node)
113 struct property *newmac;
114 const u8* macaddr;
115 int prop_len;
117 macaddr = of_get_property(node, "local-mac-address", &prop_len);
118 if (macaddr == NULL || prop_len != MAC_LEN)
119 return;
121 newmac = kzalloc(sizeof(*newmac) + MAC_LEN, GFP_KERNEL);
122 if (newmac == NULL)
123 return;
125 newmac->value = newmac + 1;
126 newmac->length = MAC_LEN;
127 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
128 if (newmac->name == NULL) {
129 kfree(newmac);
130 return;
133 memcpy(newmac->value, macaddr, MAC_LEN);
134 ((u8*)newmac->value)[5] = (*(u32*)DIP_SWITCHES_VADDR) & 0x3f;
135 of_update_property(node, newmac);
138 static int __init machine_setup(void)
140 struct device_node *clock;
141 struct device_node *eth = NULL;
143 for_each_node_by_name(clock, "main-oscillator")
144 update_clock_frequency(clock);
146 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
147 update_local_mac(eth);
148 return 0;
150 arch_initcall(machine_setup);
152 #endif
154 /* early initialization */
156 void __init platform_init(bp_tag_t *first)
160 /* Heartbeat. */
162 void platform_heartbeat(void)
166 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
168 void __init platform_calibrate_ccount(void)
170 long clk_freq = 0;
171 #ifdef CONFIG_OF
172 struct device_node *cpu =
173 of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu");
174 if (cpu) {
175 u32 freq;
176 update_clock_frequency(cpu);
177 if (!of_property_read_u32(cpu, "clock-frequency", &freq))
178 clk_freq = freq;
180 #endif
181 if (!clk_freq)
182 clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
184 ccount_freq = clk_freq;
187 #endif
189 #ifndef CONFIG_OF
191 #include <linux/serial_8250.h>
192 #include <linux/if.h>
193 #include <net/ethoc.h>
194 #include <linux/usb/c67x00.h>
196 /*----------------------------------------------------------------------------
197 * Ethernet -- OpenCores Ethernet MAC (ethoc driver)
200 static struct resource ethoc_res[] = {
201 [0] = { /* register space */
202 .start = OETH_REGS_PADDR,
203 .end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
204 .flags = IORESOURCE_MEM,
206 [1] = { /* buffer space */
207 .start = OETH_SRAMBUFF_PADDR,
208 .end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1,
209 .flags = IORESOURCE_MEM,
211 [2] = { /* IRQ number */
212 .start = OETH_IRQ,
213 .end = OETH_IRQ,
214 .flags = IORESOURCE_IRQ,
218 static struct ethoc_platform_data ethoc_pdata = {
220 * The MAC address for these boards is 00:50:c2:13:6f:xx.
221 * The last byte (here as zero) is read from the DIP switches on the
222 * board.
224 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
225 .phy_id = -1,
228 static struct platform_device ethoc_device = {
229 .name = "ethoc",
230 .id = -1,
231 .num_resources = ARRAY_SIZE(ethoc_res),
232 .resource = ethoc_res,
233 .dev = {
234 .platform_data = &ethoc_pdata,
238 /*----------------------------------------------------------------------------
239 * USB Host/Device -- Cypress CY7C67300
242 static struct resource c67x00_res[] = {
243 [0] = { /* register space */
244 .start = C67X00_PADDR,
245 .end = C67X00_PADDR + C67X00_SIZE - 1,
246 .flags = IORESOURCE_MEM,
248 [1] = { /* IRQ number */
249 .start = C67X00_IRQ,
250 .end = C67X00_IRQ,
251 .flags = IORESOURCE_IRQ,
255 static struct c67x00_platform_data c67x00_pdata = {
256 .sie_config = C67X00_SIE1_HOST | C67X00_SIE2_UNUSED,
257 .hpi_regstep = 4,
260 static struct platform_device c67x00_device = {
261 .name = "c67x00",
262 .id = -1,
263 .num_resources = ARRAY_SIZE(c67x00_res),
264 .resource = c67x00_res,
265 .dev = {
266 .platform_data = &c67x00_pdata,
270 /*----------------------------------------------------------------------------
271 * UART
274 static struct resource serial_resource = {
275 .start = DUART16552_PADDR,
276 .end = DUART16552_PADDR + 0x1f,
277 .flags = IORESOURCE_MEM,
280 static struct plat_serial8250_port serial_platform_data[] = {
281 [0] = {
282 .mapbase = DUART16552_PADDR,
283 .irq = DUART16552_INTNUM,
284 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
285 UPF_IOREMAP,
286 .iotype = UPIO_MEM32,
287 .regshift = 2,
288 .uartclk = 0, /* set in xtavnet_init() */
290 { },
293 static struct platform_device xtavnet_uart = {
294 .name = "serial8250",
295 .id = PLAT8250_DEV_PLATFORM,
296 .dev = {
297 .platform_data = serial_platform_data,
299 .num_resources = 1,
300 .resource = &serial_resource,
303 /* platform devices */
304 static struct platform_device *platform_devices[] __initdata = {
305 &ethoc_device,
306 &c67x00_device,
307 &xtavnet_uart,
311 static int __init xtavnet_init(void)
313 /* Ethernet MAC address. */
314 ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR;
316 /* Clock rate varies among FPGA bitstreams; board specific FPGA register
317 * reports the actual clock rate.
319 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
322 /* register platform devices */
323 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
325 /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user
326 * knows whether they set it correctly on the DIP switches.
328 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
329 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;
331 return 0;
335 * Register to be done during do_initcalls().
337 arch_initcall(xtavnet_init);
339 #endif /* CONFIG_OF */