8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
13 default 2 if ARCH_REALVIEW
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
29 select IRQ_DOMAIN_HIERARCHY
33 select PCI_MSI_IRQ_DOMAIN
35 config HISILICON_IRQ_MBIGEN
36 bool "Support mbigen interrupt controller"
38 depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
40 Enable the mbigen interrupt controller used on
46 select IRQ_DOMAIN_HIERARCHY
47 select GENERIC_IRQ_CHIP
52 select MULTI_IRQ_HANDLER
56 default 4 if ARCH_S5PV210
60 The maximum number of VICs available in the system, for
65 select GENERIC_IRQ_CHIP
67 select MULTI_IRQ_HANDLER
72 select GENERIC_IRQ_CHIP
74 select MULTI_IRQ_HANDLER
83 select GENERIC_IRQ_CHIP
88 select GENERIC_IRQ_CHIP
93 select GENERIC_IRQ_CHIP
98 select GENERIC_IRQ_CHIP
103 select GENERIC_IRQ_CHIP
108 select GENERIC_IRQ_CHIP
111 config CLPS711X_IRQCHIP
113 depends on ARCH_CLPS711X
115 select MULTI_IRQ_HANDLER
125 select GENERIC_IRQ_CHIP
131 select MULTI_IRQ_HANDLER
133 config RENESAS_INTC_IRQPIN
139 select GENERIC_IRQ_CHIP
147 Enables SysCfg Controlled IRQs on STi based platforms.
152 select GENERIC_IRQ_CHIP
155 tristate "TS-4800 IRQ controller"
159 Support for the TS-4800 FPGA IRQ controller
161 config VERSATILE_FPGA_IRQ
165 config VERSATILE_FPGA_IRQ_NR
168 depends on VERSATILE_FPGA_IRQ
177 Support for a CROSSBAR ip that precedes the main interrupt controller.
178 The primary irqchip invokes the crossbar's callback which inturn allocates
179 a free irq and configures the IP. Thus the peripheral interrupts are
180 routed to one of the free irqchip interrupt lines.
183 tristate "Keystone 2 IRQ controller IP"
184 depends on ARCH_KEYSTONE
186 Support for Texas Instruments Keystone 2 IRQ controller IP which
187 is part of the Keystone 2 IPC mechanism
195 depends on MACH_INGENIC
198 config RENESAS_H8300H_INTC
202 config RENESAS_H8S_INTC
210 Enables the wakeup IRQs for IMX platforms with GPCv2 block
213 def_bool y if MACH_ASM9260 || ARCH_MXS