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irqchip: Fix dependencies for archs w/o HAS_IOMEM
[linux/fpc-iii.git] / sound / soc / codecs / rt5677.c
blob69d987a9935c9f91311db09b1a2cfb7cd5a2c609
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/regmap.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/firmware.h>
23 #include <linux/property.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31
32 #include "rl6231.h"
33 #include "rt5677.h"
34 #include "rt5677-spi.h"
35
36 #define RT5677_DEVICE_ID 0x6327
37
38 #define RT5677_PR_RANGE_BASE (0xff + 1)
39 #define RT5677_PR_SPACING 0x100
40
41 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
42
43 static const struct regmap_range_cfg rt5677_ranges[] = {
44 {
45 .name = "PR",
46 .range_min = RT5677_PR_BASE,
47 .range_max = RT5677_PR_BASE + 0xfd,
48 .selector_reg = RT5677_PRIV_INDEX,
49 .selector_mask = 0xff,
50 .selector_shift = 0x0,
51 .window_start = RT5677_PRIV_DATA,
52 .window_len = 0x1,
53 },
54 };
55
56 static const struct reg_sequence init_list[] = {
57 {RT5677_ASRC_12, 0x0018},
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
64 {RT5677_PR_BASE + 0x15, 0x0490},
65 {RT5677_PR_BASE + 0x38, 0x0f71},
66 {RT5677_PR_BASE + 0x39, 0x0f71},
67 };
68 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
69
70 static const struct reg_default rt5677_reg[] = {
71 {RT5677_RESET , 0x0000},
72 {RT5677_LOUT1 , 0xa800},
73 {RT5677_IN1 , 0x0000},
74 {RT5677_MICBIAS , 0x0000},
75 {RT5677_SLIMBUS_PARAM , 0x0000},
76 {RT5677_SLIMBUS_RX , 0x0000},
77 {RT5677_SLIMBUS_CTRL , 0x0000},
78 {RT5677_SIDETONE_CTRL , 0x000b},
79 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
80 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
81 {RT5677_DAC4_DIG_VOL , 0xafaf},
82 {RT5677_DAC3_DIG_VOL , 0xafaf},
83 {RT5677_DAC1_DIG_VOL , 0xafaf},
84 {RT5677_DAC2_DIG_VOL , 0xafaf},
85 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
86 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO1_2_ADC_BST , 0x0000},
89 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_ADC_BST_CTRL2 , 0x0000},
91 {RT5677_STO3_4_ADC_BST , 0x0000},
92 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_MIXER , 0xd4c0},
95 {RT5677_STO3_ADC_MIXER , 0xd4c0},
96 {RT5677_STO2_ADC_MIXER , 0xd4c0},
97 {RT5677_STO1_ADC_MIXER , 0xd4c0},
98 {RT5677_MONO_ADC_MIXER , 0xd4d1},
99 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
100 {RT5677_STO1_DAC_MIXER , 0xaaaa},
101 {RT5677_MONO_DAC_MIXER , 0xaaaa},
102 {RT5677_DD1_MIXER , 0xaaaa},
103 {RT5677_DD2_MIXER , 0xaaaa},
104 {RT5677_IF3_DATA , 0x0000},
105 {RT5677_IF4_DATA , 0x0000},
106 {RT5677_PDM_OUT_CTRL , 0x8888},
107 {RT5677_PDM_DATA_CTRL1 , 0x0000},
108 {RT5677_PDM_DATA_CTRL2 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
115 {RT5677_TDM1_CTRL1 , 0x0300},
116 {RT5677_TDM1_CTRL2 , 0x0000},
117 {RT5677_TDM1_CTRL3 , 0x4000},
118 {RT5677_TDM1_CTRL4 , 0x0123},
119 {RT5677_TDM1_CTRL5 , 0x4567},
120 {RT5677_TDM2_CTRL1 , 0x0300},
121 {RT5677_TDM2_CTRL2 , 0x0000},
122 {RT5677_TDM2_CTRL3 , 0x4000},
123 {RT5677_TDM2_CTRL4 , 0x0123},
124 {RT5677_TDM2_CTRL5 , 0x4567},
125 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
126 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
133 {RT5677_DMIC_CTRL1 , 0x1505},
134 {RT5677_DMIC_CTRL2 , 0x0055},
135 {RT5677_HAP_GENE_CTRL1 , 0x0111},
136 {RT5677_HAP_GENE_CTRL2 , 0x0064},
137 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
142 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
143 {RT5677_HAP_GENE_CTRL9 , 0xf000},
144 {RT5677_HAP_GENE_CTRL10 , 0x0000},
145 {RT5677_PWR_DIG1 , 0x0000},
146 {RT5677_PWR_DIG2 , 0x0000},
147 {RT5677_PWR_ANLG1 , 0x0055},
148 {RT5677_PWR_ANLG2 , 0x0000},
149 {RT5677_PWR_DSP1 , 0x0001},
150 {RT5677_PWR_DSP_ST , 0x0000},
151 {RT5677_PWR_DSP2 , 0x0000},
152 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
153 {RT5677_PRIV_INDEX , 0x0000},
154 {RT5677_PRIV_DATA , 0x0000},
155 {RT5677_I2S4_SDP , 0x8000},
156 {RT5677_I2S1_SDP , 0x8000},
157 {RT5677_I2S2_SDP , 0x8000},
158 {RT5677_I2S3_SDP , 0x8000},
159 {RT5677_CLK_TREE_CTRL1 , 0x1111},
160 {RT5677_CLK_TREE_CTRL2 , 0x1111},
161 {RT5677_CLK_TREE_CTRL3 , 0x0000},
162 {RT5677_PLL1_CTRL1 , 0x0000},
163 {RT5677_PLL1_CTRL2 , 0x0000},
164 {RT5677_PLL2_CTRL1 , 0x0c60},
165 {RT5677_PLL2_CTRL2 , 0x2000},
166 {RT5677_GLB_CLK1 , 0x0000},
167 {RT5677_GLB_CLK2 , 0x0000},
168 {RT5677_ASRC_1 , 0x0000},
169 {RT5677_ASRC_2 , 0x0000},
170 {RT5677_ASRC_3 , 0x0000},
171 {RT5677_ASRC_4 , 0x0000},
172 {RT5677_ASRC_5 , 0x0000},
173 {RT5677_ASRC_6 , 0x0000},
174 {RT5677_ASRC_7 , 0x0000},
175 {RT5677_ASRC_8 , 0x0000},
176 {RT5677_ASRC_9 , 0x0000},
177 {RT5677_ASRC_10 , 0x0000},
178 {RT5677_ASRC_11 , 0x0000},
179 {RT5677_ASRC_12 , 0x0018},
180 {RT5677_ASRC_13 , 0x0000},
181 {RT5677_ASRC_14 , 0x0000},
182 {RT5677_ASRC_15 , 0x0000},
183 {RT5677_ASRC_16 , 0x0000},
184 {RT5677_ASRC_17 , 0x0000},
185 {RT5677_ASRC_18 , 0x0000},
186 {RT5677_ASRC_19 , 0x0000},
187 {RT5677_ASRC_20 , 0x0000},
188 {RT5677_ASRC_21 , 0x000c},
189 {RT5677_ASRC_22 , 0x0000},
190 {RT5677_ASRC_23 , 0x0000},
191 {RT5677_VAD_CTRL1 , 0x2184},
192 {RT5677_VAD_CTRL2 , 0x010a},
193 {RT5677_VAD_CTRL3 , 0x0aea},
194 {RT5677_VAD_CTRL4 , 0x000c},
195 {RT5677_VAD_CTRL5 , 0x0000},
196 {RT5677_DSP_INB_CTRL1 , 0x0000},
197 {RT5677_DSP_INB_CTRL2 , 0x0000},
198 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
199 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
203 {RT5677_ADC_EQ_CTRL1 , 0x6000},
204 {RT5677_ADC_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL1 , 0xc000},
206 {RT5677_EQ_CTRL2 , 0x0000},
207 {RT5677_EQ_CTRL3 , 0x0000},
208 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
209 {RT5677_JD_CTRL1 , 0x0000},
210 {RT5677_JD_CTRL2 , 0x0000},
211 {RT5677_JD_CTRL3 , 0x0000},
212 {RT5677_IRQ_CTRL1 , 0x0000},
213 {RT5677_IRQ_CTRL2 , 0x0000},
214 {RT5677_GPIO_ST , 0x0000},
215 {RT5677_GPIO_CTRL1 , 0x0000},
216 {RT5677_GPIO_CTRL2 , 0x0000},
217 {RT5677_GPIO_CTRL3 , 0x0000},
218 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
219 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
227 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
228 {RT5677_MB_DRC_CTRL1 , 0x0f20},
229 {RT5677_DRC1_CTRL1 , 0x001f},
230 {RT5677_DRC1_CTRL2 , 0x020c},
231 {RT5677_DRC1_CTRL3 , 0x1f00},
232 {RT5677_DRC1_CTRL4 , 0x0000},
233 {RT5677_DRC1_CTRL5 , 0x0000},
234 {RT5677_DRC1_CTRL6 , 0x0029},
235 {RT5677_DRC2_CTRL1 , 0x001f},
236 {RT5677_DRC2_CTRL2 , 0x020c},
237 {RT5677_DRC2_CTRL3 , 0x1f00},
238 {RT5677_DRC2_CTRL4 , 0x0000},
239 {RT5677_DRC2_CTRL5 , 0x0000},
240 {RT5677_DRC2_CTRL6 , 0x0029},
241 {RT5677_DRC1_HL_CTRL1 , 0x8000},
242 {RT5677_DRC1_HL_CTRL2 , 0x0200},
243 {RT5677_DRC2_HL_CTRL1 , 0x8000},
244 {RT5677_DRC2_HL_CTRL2 , 0x0200},
245 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
258 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
259 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
261 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
262 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
263 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
265 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
266 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
267 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
268 {RT5677_DIG_MISC , 0x0000},
269 {RT5677_GEN_CTRL1 , 0x0000},
270 {RT5677_GEN_CTRL2 , 0x0000},
271 {RT5677_VENDOR_ID , 0x0000},
272 {RT5677_VENDOR_ID1 , 0x10ec},
273 {RT5677_VENDOR_ID2 , 0x6327},
274 };
275
276 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
277 {
278 int i;
279
280 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
281 if (reg >= rt5677_ranges[i].range_min &&
282 reg <= rt5677_ranges[i].range_max) {
283 return true;
284 }
285 }
286
287 switch (reg) {
288 case RT5677_RESET:
289 case RT5677_SLIMBUS_PARAM:
290 case RT5677_PDM_DATA_CTRL1:
291 case RT5677_PDM_DATA_CTRL2:
292 case RT5677_PDM1_DATA_CTRL4:
293 case RT5677_PDM2_DATA_CTRL4:
294 case RT5677_I2C_MASTER_CTRL1:
295 case RT5677_I2C_MASTER_CTRL7:
296 case RT5677_I2C_MASTER_CTRL8:
297 case RT5677_HAP_GENE_CTRL2:
298 case RT5677_PWR_DSP_ST:
299 case RT5677_PRIV_DATA:
300 case RT5677_PLL1_CTRL2:
301 case RT5677_PLL2_CTRL2:
302 case RT5677_ASRC_22:
303 case RT5677_ASRC_23:
304 case RT5677_VAD_CTRL5:
305 case RT5677_ADC_EQ_CTRL1:
306 case RT5677_EQ_CTRL1:
307 case RT5677_IRQ_CTRL1:
308 case RT5677_IRQ_CTRL2:
309 case RT5677_GPIO_ST:
310 case RT5677_DSP_INB1_SRC_CTRL4:
311 case RT5677_DSP_INB2_SRC_CTRL4:
312 case RT5677_DSP_INB3_SRC_CTRL4:
313 case RT5677_DSP_OUTB1_SRC_CTRL4:
314 case RT5677_DSP_OUTB2_SRC_CTRL4:
315 case RT5677_VENDOR_ID:
316 case RT5677_VENDOR_ID1:
317 case RT5677_VENDOR_ID2:
318 return true;
319 default:
320 return false;
321 }
322 }
323
324 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
325 {
326 int i;
327
328 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
329 if (reg >= rt5677_ranges[i].range_min &&
330 reg <= rt5677_ranges[i].range_max) {
331 return true;
332 }
333 }
334
335 switch (reg) {
336 case RT5677_RESET:
337 case RT5677_LOUT1:
338 case RT5677_IN1:
339 case RT5677_MICBIAS:
340 case RT5677_SLIMBUS_PARAM:
341 case RT5677_SLIMBUS_RX:
342 case RT5677_SLIMBUS_CTRL:
343 case RT5677_SIDETONE_CTRL:
344 case RT5677_ANA_DAC1_2_3_SRC:
345 case RT5677_IF_DSP_DAC3_4_MIXER:
346 case RT5677_DAC4_DIG_VOL:
347 case RT5677_DAC3_DIG_VOL:
348 case RT5677_DAC1_DIG_VOL:
349 case RT5677_DAC2_DIG_VOL:
350 case RT5677_IF_DSP_DAC2_MIXER:
351 case RT5677_STO1_ADC_DIG_VOL:
352 case RT5677_MONO_ADC_DIG_VOL:
353 case RT5677_STO1_2_ADC_BST:
354 case RT5677_STO2_ADC_DIG_VOL:
355 case RT5677_ADC_BST_CTRL2:
356 case RT5677_STO3_4_ADC_BST:
357 case RT5677_STO3_ADC_DIG_VOL:
358 case RT5677_STO4_ADC_DIG_VOL:
359 case RT5677_STO4_ADC_MIXER:
360 case RT5677_STO3_ADC_MIXER:
361 case RT5677_STO2_ADC_MIXER:
362 case RT5677_STO1_ADC_MIXER:
363 case RT5677_MONO_ADC_MIXER:
364 case RT5677_ADC_IF_DSP_DAC1_MIXER:
365 case RT5677_STO1_DAC_MIXER:
366 case RT5677_MONO_DAC_MIXER:
367 case RT5677_DD1_MIXER:
368 case RT5677_DD2_MIXER:
369 case RT5677_IF3_DATA:
370 case RT5677_IF4_DATA:
371 case RT5677_PDM_OUT_CTRL:
372 case RT5677_PDM_DATA_CTRL1:
373 case RT5677_PDM_DATA_CTRL2:
374 case RT5677_PDM1_DATA_CTRL2:
375 case RT5677_PDM1_DATA_CTRL3:
376 case RT5677_PDM1_DATA_CTRL4:
377 case RT5677_PDM2_DATA_CTRL2:
378 case RT5677_PDM2_DATA_CTRL3:
379 case RT5677_PDM2_DATA_CTRL4:
380 case RT5677_TDM1_CTRL1:
381 case RT5677_TDM1_CTRL2:
382 case RT5677_TDM1_CTRL3:
383 case RT5677_TDM1_CTRL4:
384 case RT5677_TDM1_CTRL5:
385 case RT5677_TDM2_CTRL1:
386 case RT5677_TDM2_CTRL2:
387 case RT5677_TDM2_CTRL3:
388 case RT5677_TDM2_CTRL4:
389 case RT5677_TDM2_CTRL5:
390 case RT5677_I2C_MASTER_CTRL1:
391 case RT5677_I2C_MASTER_CTRL2:
392 case RT5677_I2C_MASTER_CTRL3:
393 case RT5677_I2C_MASTER_CTRL4:
394 case RT5677_I2C_MASTER_CTRL5:
395 case RT5677_I2C_MASTER_CTRL6:
396 case RT5677_I2C_MASTER_CTRL7:
397 case RT5677_I2C_MASTER_CTRL8:
398 case RT5677_DMIC_CTRL1:
399 case RT5677_DMIC_CTRL2:
400 case RT5677_HAP_GENE_CTRL1:
401 case RT5677_HAP_GENE_CTRL2:
402 case RT5677_HAP_GENE_CTRL3:
403 case RT5677_HAP_GENE_CTRL4:
404 case RT5677_HAP_GENE_CTRL5:
405 case RT5677_HAP_GENE_CTRL6:
406 case RT5677_HAP_GENE_CTRL7:
407 case RT5677_HAP_GENE_CTRL8:
408 case RT5677_HAP_GENE_CTRL9:
409 case RT5677_HAP_GENE_CTRL10:
410 case RT5677_PWR_DIG1:
411 case RT5677_PWR_DIG2:
412 case RT5677_PWR_ANLG1:
413 case RT5677_PWR_ANLG2:
414 case RT5677_PWR_DSP1:
415 case RT5677_PWR_DSP_ST:
416 case RT5677_PWR_DSP2:
417 case RT5677_ADC_DAC_HPF_CTRL1:
418 case RT5677_PRIV_INDEX:
419 case RT5677_PRIV_DATA:
420 case RT5677_I2S4_SDP:
421 case RT5677_I2S1_SDP:
422 case RT5677_I2S2_SDP:
423 case RT5677_I2S3_SDP:
424 case RT5677_CLK_TREE_CTRL1:
425 case RT5677_CLK_TREE_CTRL2:
426 case RT5677_CLK_TREE_CTRL3:
427 case RT5677_PLL1_CTRL1:
428 case RT5677_PLL1_CTRL2:
429 case RT5677_PLL2_CTRL1:
430 case RT5677_PLL2_CTRL2:
431 case RT5677_GLB_CLK1:
432 case RT5677_GLB_CLK2:
433 case RT5677_ASRC_1:
434 case RT5677_ASRC_2:
435 case RT5677_ASRC_3:
436 case RT5677_ASRC_4:
437 case RT5677_ASRC_5:
438 case RT5677_ASRC_6:
439 case RT5677_ASRC_7:
440 case RT5677_ASRC_8:
441 case RT5677_ASRC_9:
442 case RT5677_ASRC_10:
443 case RT5677_ASRC_11:
444 case RT5677_ASRC_12:
445 case RT5677_ASRC_13:
446 case RT5677_ASRC_14:
447 case RT5677_ASRC_15:
448 case RT5677_ASRC_16:
449 case RT5677_ASRC_17:
450 case RT5677_ASRC_18:
451 case RT5677_ASRC_19:
452 case RT5677_ASRC_20:
453 case RT5677_ASRC_21:
454 case RT5677_ASRC_22:
455 case RT5677_ASRC_23:
456 case RT5677_VAD_CTRL1:
457 case RT5677_VAD_CTRL2:
458 case RT5677_VAD_CTRL3:
459 case RT5677_VAD_CTRL4:
460 case RT5677_VAD_CTRL5:
461 case RT5677_DSP_INB_CTRL1:
462 case RT5677_DSP_INB_CTRL2:
463 case RT5677_DSP_IN_OUTB_CTRL:
464 case RT5677_DSP_OUTB0_1_DIG_VOL:
465 case RT5677_DSP_OUTB2_3_DIG_VOL:
466 case RT5677_DSP_OUTB4_5_DIG_VOL:
467 case RT5677_DSP_OUTB6_7_DIG_VOL:
468 case RT5677_ADC_EQ_CTRL1:
469 case RT5677_ADC_EQ_CTRL2:
470 case RT5677_EQ_CTRL1:
471 case RT5677_EQ_CTRL2:
472 case RT5677_EQ_CTRL3:
473 case RT5677_SOFT_VOL_ZERO_CROSS1:
474 case RT5677_JD_CTRL1:
475 case RT5677_JD_CTRL2:
476 case RT5677_JD_CTRL3:
477 case RT5677_IRQ_CTRL1:
478 case RT5677_IRQ_CTRL2:
479 case RT5677_GPIO_ST:
480 case RT5677_GPIO_CTRL1:
481 case RT5677_GPIO_CTRL2:
482 case RT5677_GPIO_CTRL3:
483 case RT5677_STO1_ADC_HI_FILTER1:
484 case RT5677_STO1_ADC_HI_FILTER2:
485 case RT5677_MONO_ADC_HI_FILTER1:
486 case RT5677_MONO_ADC_HI_FILTER2:
487 case RT5677_STO2_ADC_HI_FILTER1:
488 case RT5677_STO2_ADC_HI_FILTER2:
489 case RT5677_STO3_ADC_HI_FILTER1:
490 case RT5677_STO3_ADC_HI_FILTER2:
491 case RT5677_STO4_ADC_HI_FILTER1:
492 case RT5677_STO4_ADC_HI_FILTER2:
493 case RT5677_MB_DRC_CTRL1:
494 case RT5677_DRC1_CTRL1:
495 case RT5677_DRC1_CTRL2:
496 case RT5677_DRC1_CTRL3:
497 case RT5677_DRC1_CTRL4:
498 case RT5677_DRC1_CTRL5:
499 case RT5677_DRC1_CTRL6:
500 case RT5677_DRC2_CTRL1:
501 case RT5677_DRC2_CTRL2:
502 case RT5677_DRC2_CTRL3:
503 case RT5677_DRC2_CTRL4:
504 case RT5677_DRC2_CTRL5:
505 case RT5677_DRC2_CTRL6:
506 case RT5677_DRC1_HL_CTRL1:
507 case RT5677_DRC1_HL_CTRL2:
508 case RT5677_DRC2_HL_CTRL1:
509 case RT5677_DRC2_HL_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL1:
511 case RT5677_DSP_INB1_SRC_CTRL2:
512 case RT5677_DSP_INB1_SRC_CTRL3:
513 case RT5677_DSP_INB1_SRC_CTRL4:
514 case RT5677_DSP_INB2_SRC_CTRL1:
515 case RT5677_DSP_INB2_SRC_CTRL2:
516 case RT5677_DSP_INB2_SRC_CTRL3:
517 case RT5677_DSP_INB2_SRC_CTRL4:
518 case RT5677_DSP_INB3_SRC_CTRL1:
519 case RT5677_DSP_INB3_SRC_CTRL2:
520 case RT5677_DSP_INB3_SRC_CTRL3:
521 case RT5677_DSP_INB3_SRC_CTRL4:
522 case RT5677_DSP_OUTB1_SRC_CTRL1:
523 case RT5677_DSP_OUTB1_SRC_CTRL2:
524 case RT5677_DSP_OUTB1_SRC_CTRL3:
525 case RT5677_DSP_OUTB1_SRC_CTRL4:
526 case RT5677_DSP_OUTB2_SRC_CTRL1:
527 case RT5677_DSP_OUTB2_SRC_CTRL2:
528 case RT5677_DSP_OUTB2_SRC_CTRL3:
529 case RT5677_DSP_OUTB2_SRC_CTRL4:
530 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
531 case RT5677_DSP_OUTB_45_MIXER_CTRL:
532 case RT5677_DSP_OUTB_67_MIXER_CTRL:
533 case RT5677_DIG_MISC:
534 case RT5677_GEN_CTRL1:
535 case RT5677_GEN_CTRL2:
536 case RT5677_VENDOR_ID:
537 case RT5677_VENDOR_ID1:
538 case RT5677_VENDOR_ID2:
539 return true;
540 default:
541 return false;
542 }
543 }
544
545 /**
546 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
547 * @rt5677: Private Data.
548 * @addr: Address index.
549 * @value: Address data.
550 *
551 *
552 * Returns 0 for success or negative error code.
553 */
554 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
555 unsigned int addr, unsigned int value, unsigned int opcode)
556 {
557 struct snd_soc_codec *codec = rt5677->codec;
558 int ret;
559
560 mutex_lock(&rt5677->dsp_cmd_lock);
561
562 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563 addr >> 16);
564 if (ret < 0) {
565 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
566 goto err;
567 }
568
569 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
570 addr & 0xffff);
571 if (ret < 0) {
572 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
573 goto err;
574 }
575
576 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
577 value >> 16);
578 if (ret < 0) {
579 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
580 goto err;
581 }
582
583 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
584 value & 0xffff);
585 if (ret < 0) {
586 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
587 goto err;
588 }
589
590 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591 opcode);
592 if (ret < 0) {
593 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
594 goto err;
595 }
596
597 err:
598 mutex_unlock(&rt5677->dsp_cmd_lock);
599
600 return ret;
601 }
602
603 /**
604 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
605 * rt5677: Private Data.
606 * @addr: Address index.
607 * @value: Address data.
608 *
609 *
610 * Returns 0 for success or negative error code.
611 */
612 static int rt5677_dsp_mode_i2c_read_addr(
613 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
614 {
615 struct snd_soc_codec *codec = rt5677->codec;
616 int ret;
617 unsigned int msb, lsb;
618
619 mutex_lock(&rt5677->dsp_cmd_lock);
620
621 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622 addr >> 16);
623 if (ret < 0) {
624 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
625 goto err;
626 }
627
628 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
629 addr & 0xffff);
630 if (ret < 0) {
631 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
632 goto err;
633 }
634
635 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636 0x0002);
637 if (ret < 0) {
638 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
639 goto err;
640 }
641
642 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
644 *value = (msb << 16) | lsb;
645
646 err:
647 mutex_unlock(&rt5677->dsp_cmd_lock);
648
649 return ret;
650 }
651
652 /**
653 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
654 * rt5677: Private Data.
655 * @reg: Register index.
656 * @value: Register data.
657 *
658 *
659 * Returns 0 for success or negative error code.
660 */
661 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
662 unsigned int reg, unsigned int value)
663 {
664 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
665 value, 0x0001);
666 }
667
668 /**
669 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
670 * @codec: SoC audio codec device.
671 * @reg: Register index.
672 * @value: Register data.
673 *
674 *
675 * Returns 0 for success or negative error code.
676 */
677 static int rt5677_dsp_mode_i2c_read(
678 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
679 {
680 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
681 value);
682
683 *value &= 0xffff;
684
685 return ret;
686 }
687
688 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
689 {
690 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
691
692 if (on) {
693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
694 rt5677->is_dsp_mode = true;
695 } else {
696 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
697 rt5677->is_dsp_mode = false;
698 }
699 }
700
701 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
702 {
703 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
704 static bool activity;
705 int ret;
706
707 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
708 return -ENXIO;
709
710 if (on && !activity) {
711 activity = true;
712
713 regcache_cache_only(rt5677->regmap, false);
714 regcache_cache_bypass(rt5677->regmap, true);
715
716 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
717 regmap_update_bits(rt5677->regmap,
718 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
720 RT5677_LDO1_SEL_MASK, 0x0);
721 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
722 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
723 switch (rt5677->type) {
724 case RT5677:
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
726 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
727 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
728 RT5677_PLL2_PR_SRC_MASK |
729 RT5677_DSP_CLK_SRC_MASK,
730 RT5677_PLL2_PR_SRC_MCLK2 |
731 RT5677_DSP_CLK_SRC_BYPASS);
732 break;
733 case RT5676:
734 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
735 RT5677_DSP_CLK_SRC_MASK,
736 RT5677_DSP_CLK_SRC_BYPASS);
737 break;
738 default:
739 break;
740 }
741 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
742 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
743 rt5677_set_dsp_mode(codec, true);
744
745 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
746 codec->dev);
747 if (ret == 0) {
748 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
749 release_firmware(rt5677->fw1);
750 }
751
752 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
753 codec->dev);
754 if (ret == 0) {
755 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
756 release_firmware(rt5677->fw2);
757 }
758
759 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
760
761 regcache_cache_bypass(rt5677->regmap, false);
762 regcache_cache_only(rt5677->regmap, true);
763 } else if (!on && activity) {
764 activity = false;
765
766 regcache_cache_only(rt5677->regmap, false);
767 regcache_cache_bypass(rt5677->regmap, true);
768
769 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
770 rt5677_set_dsp_mode(codec, false);
771 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
772
773 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
774
775 regcache_cache_bypass(rt5677->regmap, false);
776 regcache_mark_dirty(rt5677->regmap);
777 regcache_sync(rt5677->regmap);
778 }
779
780 return 0;
781 }
782
783 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
784 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
786 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
787 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
788 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
789
790 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
791 static const DECLARE_TLV_DB_RANGE(bst_tlv,
792 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
793 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
794 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
795 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
796 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
797 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
798 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
799 );
800
801 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
802 struct snd_ctl_elem_value *ucontrol)
803 {
804 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
805 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
806
807 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
808
809 return 0;
810 }
811
812 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
813 struct snd_ctl_elem_value *ucontrol)
814 {
815 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
816 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
817 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
818
819 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
820
821 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
822 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
823
824 return 0;
825 }
826
827 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
828 /* OUTPUT Control */
829 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
830 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
831 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
832 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
833 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
834 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
835
836 /* DAC Digital Volume */
837 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
839 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
841 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
842 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
843 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
844 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
845
846 /* IN1/IN2 Control */
847 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
848 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
849
850 /* ADC Digital Volume Control */
851 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
858 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
860 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
861
862 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
863 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
864 adc_vol_tlv),
865 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
866 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
867 adc_vol_tlv),
868 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
869 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
870 adc_vol_tlv),
871 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
872 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
873 adc_vol_tlv),
874 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
875 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
876 adc_vol_tlv),
877
878 /* Sidetone Control */
879 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
880 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
881
882 /* ADC Boost Volume Control */
883 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
884 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
885 adc_bst_tlv),
886 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
887 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
888 adc_bst_tlv),
889 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
890 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
891 adc_bst_tlv),
892 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
893 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
894 adc_bst_tlv),
895 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
896 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
897 adc_bst_tlv),
898
899 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
900 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
901 };
902
903 /**
904 * set_dmic_clk - Set parameter of dmic.
905 *
906 * @w: DAPM widget.
907 * @kcontrol: The kcontrol of this widget.
908 * @event: Event id.
909 *
910 * Choose dmic clock between 1MHz and 3MHz.
911 * It is better for clock to approximate 3MHz.
912 */
913 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
914 struct snd_kcontrol *kcontrol, int event)
915 {
916 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
917 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
918 int idx, rate;
919
920 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
921 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
922 idx = rl6231_calc_dmic_clk(rate);
923 if (idx < 0)
924 dev_err(codec->dev, "Failed to set DMIC clock\n");
925 else
926 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
927 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
928 return idx;
929 }
930
931 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
932 struct snd_soc_dapm_widget *sink)
933 {
934 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
935 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
936 unsigned int val;
937
938 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
939 val &= RT5677_SCLK_SRC_MASK;
940 if (val == RT5677_SCLK_SRC_PLL1)
941 return 1;
942 else
943 return 0;
944 }
945
946 static int is_using_asrc(struct snd_soc_dapm_widget *source,
947 struct snd_soc_dapm_widget *sink)
948 {
949 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
950 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
951 unsigned int reg, shift, val;
952
953 if (source->reg == RT5677_ASRC_1) {
954 switch (source->shift) {
955 case 12:
956 reg = RT5677_ASRC_4;
957 shift = 0;
958 break;
959 case 13:
960 reg = RT5677_ASRC_4;
961 shift = 4;
962 break;
963 case 14:
964 reg = RT5677_ASRC_4;
965 shift = 8;
966 break;
967 case 15:
968 reg = RT5677_ASRC_4;
969 shift = 12;
970 break;
971 default:
972 return 0;
973 }
974 } else {
975 switch (source->shift) {
976 case 0:
977 reg = RT5677_ASRC_6;
978 shift = 8;
979 break;
980 case 1:
981 reg = RT5677_ASRC_6;
982 shift = 12;
983 break;
984 case 2:
985 reg = RT5677_ASRC_5;
986 shift = 0;
987 break;
988 case 3:
989 reg = RT5677_ASRC_5;
990 shift = 4;
991 break;
992 case 4:
993 reg = RT5677_ASRC_5;
994 shift = 8;
995 break;
996 case 5:
997 reg = RT5677_ASRC_5;
998 shift = 12;
999 break;
1000 case 12:
1001 reg = RT5677_ASRC_3;
1002 shift = 0;
1003 break;
1004 case 13:
1005 reg = RT5677_ASRC_3;
1006 shift = 4;
1007 break;
1008 case 14:
1009 reg = RT5677_ASRC_3;
1010 shift = 12;
1011 break;
1012 default:
1013 return 0;
1014 }
1015 }
1016
1017 regmap_read(rt5677->regmap, reg, &val);
1018 val = (val >> shift) & 0xf;
1019
1020 switch (val) {
1021 case 1 ... 6:
1022 return 1;
1023 default:
1024 return 0;
1025 }
1026
1027 }
1028
1029 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1030 struct snd_soc_dapm_widget *sink)
1031 {
1032 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1033 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1034
1035 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1036 return 1;
1037
1038 return 0;
1039 }
1040
1041 /**
1042 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1043 * @codec: SoC audio codec device.
1044 * @filter_mask: mask of filters.
1045 * @clk_src: clock source
1046 *
1047 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1048 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1049 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1050 * ASRC function will track i2s clock and generate a corresponding system clock
1051 * for codec. This function provides an API to select the clock source for a
1052 * set of filters specified by the mask. And the codec driver will turn on ASRC
1053 * for these filters if ASRC is selected as their clock source.
1054 */
1055 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1056 unsigned int filter_mask, unsigned int clk_src)
1057 {
1058 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1059 unsigned int asrc3_mask = 0, asrc3_value = 0;
1060 unsigned int asrc4_mask = 0, asrc4_value = 0;
1061 unsigned int asrc5_mask = 0, asrc5_value = 0;
1062 unsigned int asrc6_mask = 0, asrc6_value = 0;
1063 unsigned int asrc7_mask = 0, asrc7_value = 0;
1064 unsigned int asrc8_mask = 0, asrc8_value = 0;
1065
1066 switch (clk_src) {
1067 case RT5677_CLK_SEL_SYS:
1068 case RT5677_CLK_SEL_I2S1_ASRC:
1069 case RT5677_CLK_SEL_I2S2_ASRC:
1070 case RT5677_CLK_SEL_I2S3_ASRC:
1071 case RT5677_CLK_SEL_I2S4_ASRC:
1072 case RT5677_CLK_SEL_I2S5_ASRC:
1073 case RT5677_CLK_SEL_I2S6_ASRC:
1074 case RT5677_CLK_SEL_SYS2:
1075 case RT5677_CLK_SEL_SYS3:
1076 case RT5677_CLK_SEL_SYS4:
1077 case RT5677_CLK_SEL_SYS5:
1078 case RT5677_CLK_SEL_SYS6:
1079 case RT5677_CLK_SEL_SYS7:
1080 break;
1081
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 /* ASRC 3 */
1087 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1088 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1089 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1090 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1091 }
1092
1093 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1094 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1095 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1096 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1097 }
1098
1099 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1100 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1101 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1102 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1103 }
1104
1105 if (asrc3_mask)
1106 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1107 asrc3_value);
1108
1109 /* ASRC 4 */
1110 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1111 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1112 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1113 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1114 }
1115
1116 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1117 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1118 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1119 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1120 }
1121
1122 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1123 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1124 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1125 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1126 }
1127
1128 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1129 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1130 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1131 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1132 }
1133
1134 if (asrc4_mask)
1135 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1136 asrc4_value);
1137
1138 /* ASRC 5 */
1139 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1140 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1141 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1142 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1143 }
1144
1145 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1146 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1147 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1148 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1149 }
1150
1151 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1152 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1153 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1154 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1155 }
1156
1157 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1158 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1159 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1160 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1161 }
1162
1163 if (asrc5_mask)
1164 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1165 asrc5_value);
1166
1167 /* ASRC 6 */
1168 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1169 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1170 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1171 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1172 }
1173
1174 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1175 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1176 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1177 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1178 }
1179
1180 if (asrc6_mask)
1181 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1182 asrc6_value);
1183
1184 /* ASRC 7 */
1185 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1186 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1187 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1188 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1189 }
1190
1191 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1192 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1193 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1194 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1195 }
1196
1197 if (asrc7_mask)
1198 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1199 asrc7_value);
1200
1201 /* ASRC 8 */
1202 if (filter_mask & RT5677_I2S1_SOURCE) {
1203 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1204 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1205 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1206 }
1207
1208 if (filter_mask & RT5677_I2S2_SOURCE) {
1209 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1210 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1211 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1212 }
1213
1214 if (filter_mask & RT5677_I2S3_SOURCE) {
1215 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1216 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1217 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1218 }
1219
1220 if (filter_mask & RT5677_I2S4_SOURCE) {
1221 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1222 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1223 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1224 }
1225
1226 if (asrc8_mask)
1227 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1228 asrc8_value);
1229
1230 return 0;
1231 }
1232 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1233
1234 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1235 struct snd_soc_dapm_widget *sink)
1236 {
1237 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1238 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1239 unsigned int asrc_setting;
1240
1241 switch (source->shift) {
1242 case 11:
1243 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1244 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1245 RT5677_AD_STO1_CLK_SEL_SFT;
1246 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1247 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1248 return 1;
1249 break;
1250
1251 case 10:
1252 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1253 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1254 RT5677_AD_STO2_CLK_SEL_SFT;
1255 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1256 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1257 return 1;
1258 break;
1259
1260 case 9:
1261 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1262 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1263 RT5677_AD_STO3_CLK_SEL_SFT;
1264 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1265 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1266 return 1;
1267 break;
1268
1269 case 8:
1270 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1271 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1272 RT5677_AD_STO4_CLK_SEL_SFT;
1273 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1274 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1275 return 1;
1276 break;
1277
1278 case 7:
1279 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1280 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1281 RT5677_AD_MONOL_CLK_SEL_SFT;
1282 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1283 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1284 return 1;
1285 break;
1286
1287 case 6:
1288 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1289 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1290 RT5677_AD_MONOR_CLK_SEL_SFT;
1291 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1292 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1293 return 1;
1294 break;
1295
1296 default:
1297 break;
1298 }
1299
1300 return 0;
1301 }
1302
1303 /* Digital Mixer */
1304 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1305 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1306 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1307 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1308 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1309 };
1310
1311 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1312 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1313 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1314 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1315 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1316 };
1317
1318 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1319 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1320 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1321 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1322 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1323 };
1324
1325 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1326 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1327 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1328 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1329 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1330 };
1331
1332 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1333 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1334 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1335 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1336 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1337 };
1338
1339 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1340 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1341 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1342 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1343 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1344 };
1345
1346 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1347 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1348 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1349 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1350 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1351 };
1352
1353 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1354 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1355 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1356 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1357 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1358 };
1359
1360 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1361 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1362 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1363 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1364 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1365 };
1366
1367 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1368 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1369 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1370 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1371 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1372 };
1373
1374 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1375 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1376 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1377 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1378 RT5677_M_DAC1_L_SFT, 1, 1),
1379 };
1380
1381 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1382 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1383 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1384 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1385 RT5677_M_DAC1_R_SFT, 1, 1),
1386 };
1387
1388 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1389 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1390 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1391 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1392 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1393 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1394 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1395 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1396 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1397 };
1398
1399 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1400 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1401 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1402 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1403 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1404 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1405 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1406 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1407 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1408 };
1409
1410 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1411 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1412 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1413 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1414 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1415 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1416 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1417 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1418 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1419 };
1420
1421 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1422 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1423 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1424 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1425 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1426 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1427 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1428 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1429 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1430 };
1431
1432 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1433 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1434 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1435 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1436 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1437 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1438 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1439 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1440 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1441 };
1442
1443 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1444 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1445 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1446 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1447 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1448 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1449 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1450 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1451 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1452 };
1453
1454 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1455 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1456 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1457 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1458 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1459 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1460 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1461 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1462 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1463 };
1464
1465 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1466 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1467 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1468 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1469 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1470 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1471 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1472 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1473 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1474 };
1475
1476 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1477 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1478 RT5677_DSP_IB_01_H_SFT, 1, 1),
1479 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1480 RT5677_DSP_IB_23_H_SFT, 1, 1),
1481 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482 RT5677_DSP_IB_45_H_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484 RT5677_DSP_IB_6_H_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486 RT5677_DSP_IB_7_H_SFT, 1, 1),
1487 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488 RT5677_DSP_IB_8_H_SFT, 1, 1),
1489 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1490 RT5677_DSP_IB_9_H_SFT, 1, 1),
1491 };
1492
1493 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1494 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1495 RT5677_DSP_IB_01_L_SFT, 1, 1),
1496 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1497 RT5677_DSP_IB_23_L_SFT, 1, 1),
1498 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1499 RT5677_DSP_IB_45_L_SFT, 1, 1),
1500 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1501 RT5677_DSP_IB_6_L_SFT, 1, 1),
1502 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1503 RT5677_DSP_IB_7_L_SFT, 1, 1),
1504 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1505 RT5677_DSP_IB_8_L_SFT, 1, 1),
1506 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1507 RT5677_DSP_IB_9_L_SFT, 1, 1),
1508 };
1509
1510 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1511 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1512 RT5677_DSP_IB_01_H_SFT, 1, 1),
1513 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1514 RT5677_DSP_IB_23_H_SFT, 1, 1),
1515 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516 RT5677_DSP_IB_45_H_SFT, 1, 1),
1517 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518 RT5677_DSP_IB_6_H_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520 RT5677_DSP_IB_7_H_SFT, 1, 1),
1521 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522 RT5677_DSP_IB_8_H_SFT, 1, 1),
1523 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1524 RT5677_DSP_IB_9_H_SFT, 1, 1),
1525 };
1526
1527 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1528 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1529 RT5677_DSP_IB_01_L_SFT, 1, 1),
1530 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1531 RT5677_DSP_IB_23_L_SFT, 1, 1),
1532 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1533 RT5677_DSP_IB_45_L_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1535 RT5677_DSP_IB_6_L_SFT, 1, 1),
1536 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1537 RT5677_DSP_IB_7_L_SFT, 1, 1),
1538 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1539 RT5677_DSP_IB_8_L_SFT, 1, 1),
1540 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1541 RT5677_DSP_IB_9_L_SFT, 1, 1),
1542 };
1543
1544 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1545 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1546 RT5677_DSP_IB_01_H_SFT, 1, 1),
1547 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1548 RT5677_DSP_IB_23_H_SFT, 1, 1),
1549 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550 RT5677_DSP_IB_45_H_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552 RT5677_DSP_IB_6_H_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554 RT5677_DSP_IB_7_H_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556 RT5677_DSP_IB_8_H_SFT, 1, 1),
1557 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1558 RT5677_DSP_IB_9_H_SFT, 1, 1),
1559 };
1560
1561 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1562 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1563 RT5677_DSP_IB_01_L_SFT, 1, 1),
1564 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1565 RT5677_DSP_IB_23_L_SFT, 1, 1),
1566 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1567 RT5677_DSP_IB_45_L_SFT, 1, 1),
1568 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1569 RT5677_DSP_IB_6_L_SFT, 1, 1),
1570 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1571 RT5677_DSP_IB_7_L_SFT, 1, 1),
1572 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1573 RT5677_DSP_IB_8_L_SFT, 1, 1),
1574 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1575 RT5677_DSP_IB_9_L_SFT, 1, 1),
1576 };
1577
1578
1579 /* Mux */
1580 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1581 static const char * const rt5677_dac1_src[] = {
1582 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1583 "OB 01"
1584 };
1585
1586 static SOC_ENUM_SINGLE_DECL(
1587 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1588 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1589
1590 static const struct snd_kcontrol_new rt5677_dac1_mux =
1591 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1592
1593 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1594 static const char * const rt5677_adda1_src[] = {
1595 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1596 };
1597
1598 static SOC_ENUM_SINGLE_DECL(
1599 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1600 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1601
1602 static const struct snd_kcontrol_new rt5677_adda1_mux =
1603 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1604
1605
1606 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1607 static const char * const rt5677_dac2l_src[] = {
1608 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1609 "OB 2",
1610 };
1611
1612 static SOC_ENUM_SINGLE_DECL(
1613 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1614 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1615
1616 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1617 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1618
1619 static const char * const rt5677_dac2r_src[] = {
1620 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1621 "OB 3", "Haptic Generator", "VAD ADC"
1622 };
1623
1624 static SOC_ENUM_SINGLE_DECL(
1625 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1626 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1627
1628 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1629 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1630
1631 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1632 static const char * const rt5677_dac3l_src[] = {
1633 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1634 "SLB DAC 4", "OB 4"
1635 };
1636
1637 static SOC_ENUM_SINGLE_DECL(
1638 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1639 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1640
1641 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1642 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1643
1644 static const char * const rt5677_dac3r_src[] = {
1645 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1646 "SLB DAC 5", "OB 5"
1647 };
1648
1649 static SOC_ENUM_SINGLE_DECL(
1650 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1651 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1652
1653 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1654 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1655
1656 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1657 static const char * const rt5677_dac4l_src[] = {
1658 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1659 "SLB DAC 6", "OB 6"
1660 };
1661
1662 static SOC_ENUM_SINGLE_DECL(
1663 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1664 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1665
1666 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1667 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1668
1669 static const char * const rt5677_dac4r_src[] = {
1670 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1671 "SLB DAC 7", "OB 7"
1672 };
1673
1674 static SOC_ENUM_SINGLE_DECL(
1675 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1676 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1677
1678 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1679 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1680
1681 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1682 static const char * const rt5677_iob_bypass_src[] = {
1683 "Bypass", "Pass SRC"
1684 };
1685
1686 static SOC_ENUM_SINGLE_DECL(
1687 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1688 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1689
1690 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1691 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1692
1693 static SOC_ENUM_SINGLE_DECL(
1694 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1695 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1696
1697 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1698 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1699
1700 static SOC_ENUM_SINGLE_DECL(
1701 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1702 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1703
1704 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1705 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1706
1707 static SOC_ENUM_SINGLE_DECL(
1708 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1709 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1710
1711 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1712 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1713
1714 static SOC_ENUM_SINGLE_DECL(
1715 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1716 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1717
1718 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1719 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1720
1721 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1722 static const char * const rt5677_stereo_adc2_src[] = {
1723 "DD MIX1", "DMIC", "Stereo DAC MIX"
1724 };
1725
1726 static SOC_ENUM_SINGLE_DECL(
1727 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1728 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1729
1730 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1731 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1732
1733 static SOC_ENUM_SINGLE_DECL(
1734 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1735 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1736
1737 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1738 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1739
1740 static SOC_ENUM_SINGLE_DECL(
1741 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1742 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1743
1744 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1745 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1746
1747 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1748 static const char * const rt5677_dmic_src[] = {
1749 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1750 };
1751
1752 static SOC_ENUM_SINGLE_DECL(
1753 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1754 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1755
1756 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1757 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1758
1759 static SOC_ENUM_SINGLE_DECL(
1760 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1761 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1762
1763 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1764 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1765
1766 static SOC_ENUM_SINGLE_DECL(
1767 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1768 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1769
1770 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1771 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1772
1773 static SOC_ENUM_SINGLE_DECL(
1774 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1775 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1776
1777 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1778 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1779
1780 static SOC_ENUM_SINGLE_DECL(
1781 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1782 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1783
1784 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1785 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1786
1787 static SOC_ENUM_SINGLE_DECL(
1788 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1789 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1790
1791 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1792 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1793
1794 /* Stereo2 ADC Source */ /* MX-26 [0] */
1795 static const char * const rt5677_stereo2_adc_lr_src[] = {
1796 "L", "LR"
1797 };
1798
1799 static SOC_ENUM_SINGLE_DECL(
1800 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1801 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1802
1803 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1804 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1805
1806 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1807 static const char * const rt5677_stereo_adc1_src[] = {
1808 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1809 };
1810
1811 static SOC_ENUM_SINGLE_DECL(
1812 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1813 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1814
1815 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1816 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1817
1818 static SOC_ENUM_SINGLE_DECL(
1819 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1820 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1821
1822 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1823 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1824
1825 static SOC_ENUM_SINGLE_DECL(
1826 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1827 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1828
1829 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1830 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1831
1832 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1833 static const char * const rt5677_mono_adc2_l_src[] = {
1834 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1835 };
1836
1837 static SOC_ENUM_SINGLE_DECL(
1838 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1839 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1840
1841 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1842 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1843
1844 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1845 static const char * const rt5677_mono_adc1_l_src[] = {
1846 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1847 };
1848
1849 static SOC_ENUM_SINGLE_DECL(
1850 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1851 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1852
1853 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1854 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1855
1856 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1857 static const char * const rt5677_mono_adc2_r_src[] = {
1858 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1859 };
1860
1861 static SOC_ENUM_SINGLE_DECL(
1862 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1863 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1864
1865 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1866 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1867
1868 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1869 static const char * const rt5677_mono_adc1_r_src[] = {
1870 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1871 };
1872
1873 static SOC_ENUM_SINGLE_DECL(
1874 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1875 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1876
1877 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1878 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1879
1880 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1881 static const char * const rt5677_stereo4_adc2_src[] = {
1882 "DD MIX1", "DMIC", "DD MIX2"
1883 };
1884
1885 static SOC_ENUM_SINGLE_DECL(
1886 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1887 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1888
1889 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1890 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1891
1892
1893 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1894 static const char * const rt5677_stereo4_adc1_src[] = {
1895 "DD MIX1", "ADC1/2", "DD MIX2"
1896 };
1897
1898 static SOC_ENUM_SINGLE_DECL(
1899 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1900 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1901
1902 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1903 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1904
1905 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1906 static const char * const rt5677_inbound01_src[] = {
1907 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1908 "VAD ADC/DAC1 FS"
1909 };
1910
1911 static SOC_ENUM_SINGLE_DECL(
1912 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1913 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1914
1915 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1916 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1917
1918 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1919 static const char * const rt5677_inbound23_src[] = {
1920 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1921 "DAC1 FS", "IF4 DAC"
1922 };
1923
1924 static SOC_ENUM_SINGLE_DECL(
1925 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1926 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1927
1928 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1929 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1930
1931 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1932 static const char * const rt5677_inbound45_src[] = {
1933 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1934 "IF3 DAC"
1935 };
1936
1937 static SOC_ENUM_SINGLE_DECL(
1938 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1939 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1940
1941 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1942 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1943
1944 /* InBound6 Source */ /* MX-A3 [2:0] */
1945 static const char * const rt5677_inbound6_src[] = {
1946 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1947 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1948 };
1949
1950 static SOC_ENUM_SINGLE_DECL(
1951 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1952 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1953
1954 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1955 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1956
1957 /* InBound7 Source */ /* MX-A4 [14:12] */
1958 static const char * const rt5677_inbound7_src[] = {
1959 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1960 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1961 };
1962
1963 static SOC_ENUM_SINGLE_DECL(
1964 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1965 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1966
1967 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1968 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1969
1970 /* InBound8 Source */ /* MX-A4 [10:8] */
1971 static const char * const rt5677_inbound8_src[] = {
1972 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1973 "MONO ADC MIX L", "DACL1 FS"
1974 };
1975
1976 static SOC_ENUM_SINGLE_DECL(
1977 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1978 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1979
1980 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1981 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1982
1983 /* InBound9 Source */ /* MX-A4 [6:4] */
1984 static const char * const rt5677_inbound9_src[] = {
1985 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1986 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1987 };
1988
1989 static SOC_ENUM_SINGLE_DECL(
1990 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1991 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1992
1993 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1994 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1995
1996 /* VAD Source */ /* MX-9F [6:4] */
1997 static const char * const rt5677_vad_src[] = {
1998 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1999 "STO3 ADC MIX L"
2000 };
2001
2002 static SOC_ENUM_SINGLE_DECL(
2003 rt5677_vad_enum, RT5677_VAD_CTRL4,
2004 RT5677_VAD_SRC_SFT, rt5677_vad_src);
2005
2006 static const struct snd_kcontrol_new rt5677_vad_src_mux =
2007 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2008
2009 /* Sidetone Source */ /* MX-13 [11:9] */
2010 static const char * const rt5677_sidetone_src[] = {
2011 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2012 };
2013
2014 static SOC_ENUM_SINGLE_DECL(
2015 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2016 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2017
2018 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2019 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2020
2021 /* DAC1/2 Source */ /* MX-15 [1:0] */
2022 static const char * const rt5677_dac12_src[] = {
2023 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2024 };
2025
2026 static SOC_ENUM_SINGLE_DECL(
2027 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2028 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2029
2030 static const struct snd_kcontrol_new rt5677_dac12_mux =
2031 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2032
2033 /* DAC3 Source */ /* MX-15 [5:4] */
2034 static const char * const rt5677_dac3_src[] = {
2035 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2036 };
2037
2038 static SOC_ENUM_SINGLE_DECL(
2039 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2040 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2041
2042 static const struct snd_kcontrol_new rt5677_dac3_mux =
2043 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2044
2045 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2046 static const char * const rt5677_pdm_src[] = {
2047 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2048 };
2049
2050 static SOC_ENUM_SINGLE_DECL(
2051 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2052 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2053
2054 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2055 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2056
2057 static SOC_ENUM_SINGLE_DECL(
2058 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2059 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2060
2061 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2062 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2063
2064 static SOC_ENUM_SINGLE_DECL(
2065 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2066 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2067
2068 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2069 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2070
2071 static SOC_ENUM_SINGLE_DECL(
2072 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2073 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2074
2075 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2076 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2077
2078 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2079 static const char * const rt5677_if12_adc1_src[] = {
2080 "STO1 ADC MIX", "OB01", "VAD ADC"
2081 };
2082
2083 static SOC_ENUM_SINGLE_DECL(
2084 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2085 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2086
2087 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2088 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2089
2090 static SOC_ENUM_SINGLE_DECL(
2091 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2092 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2093
2094 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2095 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2096
2097 static SOC_ENUM_SINGLE_DECL(
2098 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2099 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2100
2101 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2102 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2103
2104 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2105 static const char * const rt5677_if12_adc2_src[] = {
2106 "STO2 ADC MIX", "OB23"
2107 };
2108
2109 static SOC_ENUM_SINGLE_DECL(
2110 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2111 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2112
2113 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2114 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2115
2116 static SOC_ENUM_SINGLE_DECL(
2117 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2118 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2119
2120 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2121 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2122
2123 static SOC_ENUM_SINGLE_DECL(
2124 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2125 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2126
2127 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2128 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2129
2130 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2131 static const char * const rt5677_if12_adc3_src[] = {
2132 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2133 };
2134
2135 static SOC_ENUM_SINGLE_DECL(
2136 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2137 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2138
2139 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2140 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2141
2142 static SOC_ENUM_SINGLE_DECL(
2143 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2144 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2145
2146 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2147 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2148
2149 static SOC_ENUM_SINGLE_DECL(
2150 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2151 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2152
2153 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2154 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2155
2156 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2157 static const char * const rt5677_if12_adc4_src[] = {
2158 "STO4 ADC MIX", "OB67", "OB01"
2159 };
2160
2161 static SOC_ENUM_SINGLE_DECL(
2162 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2163 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2164
2165 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2166 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2167
2168 static SOC_ENUM_SINGLE_DECL(
2169 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2170 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2171
2172 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2173 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2174
2175 static SOC_ENUM_SINGLE_DECL(
2176 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2177 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2178
2179 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2180 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2181
2182 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2183 static const char * const rt5677_if34_adc_src[] = {
2184 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2185 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2186 };
2187
2188 static SOC_ENUM_SINGLE_DECL(
2189 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2190 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2191
2192 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2193 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2194
2195 static SOC_ENUM_SINGLE_DECL(
2196 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2197 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2198
2199 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2200 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2201
2202 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2203 static const char * const rt5677_if12_adc_swap_src[] = {
2204 "L/R", "R/L", "L/L", "R/R"
2205 };
2206
2207 static SOC_ENUM_SINGLE_DECL(
2208 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2209 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2210
2211 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2212 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2213
2214 static SOC_ENUM_SINGLE_DECL(
2215 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2216 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2217
2218 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2219 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2220
2221 static SOC_ENUM_SINGLE_DECL(
2222 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2223 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2224
2225 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2226 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2227
2228 static SOC_ENUM_SINGLE_DECL(
2229 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2230 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2231
2232 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2233 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2234
2235 static SOC_ENUM_SINGLE_DECL(
2236 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2237 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2238
2239 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2240 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2241
2242 static SOC_ENUM_SINGLE_DECL(
2243 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2244 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2245
2246 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2247 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2248
2249 static SOC_ENUM_SINGLE_DECL(
2250 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2251 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2252
2253 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2254 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2255
2256 static SOC_ENUM_SINGLE_DECL(
2257 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2258 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2259
2260 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2261 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2262
2263 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2264 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2265 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2266 "3/1/2/4", "3/4/1/2"
2267 };
2268
2269 static SOC_ENUM_SINGLE_DECL(
2270 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2271 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2272
2273 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2274 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2275
2276 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2277 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2278 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2279 "2/3/1/4", "3/4/1/2"
2280 };
2281
2282 static SOC_ENUM_SINGLE_DECL(
2283 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2284 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2285
2286 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2287 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2288
2289 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2290 MX-3F[14:12][10:8][6:4][2:0]
2291 MX-43[14:12][10:8][6:4][2:0]
2292 MX-44[14:12][10:8][6:4][2:0] */
2293 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2294 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2295 };
2296
2297 static SOC_ENUM_SINGLE_DECL(
2298 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2299 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2300
2301 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2302 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2303
2304 static SOC_ENUM_SINGLE_DECL(
2305 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2306 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2307
2308 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2309 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2310
2311 static SOC_ENUM_SINGLE_DECL(
2312 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2313 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2314
2315 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2316 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2317
2318 static SOC_ENUM_SINGLE_DECL(
2319 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2320 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2321
2322 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2323 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2324
2325 static SOC_ENUM_SINGLE_DECL(
2326 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2327 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2328
2329 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2330 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2331
2332 static SOC_ENUM_SINGLE_DECL(
2333 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2334 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2335
2336 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2337 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2338
2339 static SOC_ENUM_SINGLE_DECL(
2340 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2341 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2342
2343 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2344 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2345
2346 static SOC_ENUM_SINGLE_DECL(
2347 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2348 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2349
2350 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2351 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2352
2353 static SOC_ENUM_SINGLE_DECL(
2354 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2355 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2356
2357 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2358 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2359
2360 static SOC_ENUM_SINGLE_DECL(
2361 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2362 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2363
2364 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2365 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2366
2367 static SOC_ENUM_SINGLE_DECL(
2368 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2369 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2370
2371 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2372 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2373
2374 static SOC_ENUM_SINGLE_DECL(
2375 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2376 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2377
2378 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2379 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2380
2381 static SOC_ENUM_SINGLE_DECL(
2382 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2383 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2384
2385 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2386 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2387
2388 static SOC_ENUM_SINGLE_DECL(
2389 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2390 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2391
2392 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2393 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2394
2395 static SOC_ENUM_SINGLE_DECL(
2396 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2397 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2398
2399 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2400 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2401
2402 static SOC_ENUM_SINGLE_DECL(
2403 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2404 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2405
2406 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2407 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2408
2409 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2410 struct snd_kcontrol *kcontrol, int event)
2411 {
2412 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2413 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2414
2415 switch (event) {
2416 case SND_SOC_DAPM_POST_PMU:
2417 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2418 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2419 break;
2420
2421 case SND_SOC_DAPM_PRE_PMD:
2422 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2423 RT5677_PWR_BST1_P, 0);
2424 break;
2425
2426 default:
2427 return 0;
2428 }
2429
2430 return 0;
2431 }
2432
2433 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2434 struct snd_kcontrol *kcontrol, int event)
2435 {
2436 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2437 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2438
2439 switch (event) {
2440 case SND_SOC_DAPM_POST_PMU:
2441 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2442 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2443 break;
2444
2445 case SND_SOC_DAPM_PRE_PMD:
2446 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2447 RT5677_PWR_BST2_P, 0);
2448 break;
2449
2450 default:
2451 return 0;
2452 }
2453
2454 return 0;
2455 }
2456
2457 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2458 struct snd_kcontrol *kcontrol, int event)
2459 {
2460 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2461 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2462
2463 switch (event) {
2464 case SND_SOC_DAPM_PRE_PMU:
2465 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2466 break;
2467
2468 case SND_SOC_DAPM_POST_PMU:
2469 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2470 break;
2471
2472 default:
2473 return 0;
2474 }
2475
2476 return 0;
2477 }
2478
2479 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2480 struct snd_kcontrol *kcontrol, int event)
2481 {
2482 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2483 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2484
2485 switch (event) {
2486 case SND_SOC_DAPM_PRE_PMU:
2487 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2488 break;
2489
2490 case SND_SOC_DAPM_POST_PMU:
2491 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2492 break;
2493
2494 default:
2495 return 0;
2496 }
2497
2498 return 0;
2499 }
2500
2501 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2502 struct snd_kcontrol *kcontrol, int event)
2503 {
2504 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2505 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2506
2507 switch (event) {
2508 case SND_SOC_DAPM_POST_PMU:
2509 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2510 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2511 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2512 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2513 break;
2514
2515 case SND_SOC_DAPM_PRE_PMD:
2516 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2517 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2518 RT5677_PWR_CLK_MB, 0);
2519 break;
2520
2521 default:
2522 return 0;
2523 }
2524
2525 return 0;
2526 }
2527
2528 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2529 struct snd_kcontrol *kcontrol, int event)
2530 {
2531 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2532 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2533 unsigned int value;
2534
2535 switch (event) {
2536 case SND_SOC_DAPM_PRE_PMU:
2537 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2538 if (value & RT5677_IF1_ADC_CTRL_MASK)
2539 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2540 RT5677_IF1_ADC_MODE_MASK,
2541 RT5677_IF1_ADC_MODE_TDM);
2542 break;
2543
2544 default:
2545 return 0;
2546 }
2547
2548 return 0;
2549 }
2550
2551 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2552 struct snd_kcontrol *kcontrol, int event)
2553 {
2554 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2555 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2556 unsigned int value;
2557
2558 switch (event) {
2559 case SND_SOC_DAPM_PRE_PMU:
2560 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2561 if (value & RT5677_IF2_ADC_CTRL_MASK)
2562 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2563 RT5677_IF2_ADC_MODE_MASK,
2564 RT5677_IF2_ADC_MODE_TDM);
2565 break;
2566
2567 default:
2568 return 0;
2569 }
2570
2571 return 0;
2572 }
2573
2574 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2575 struct snd_kcontrol *kcontrol, int event)
2576 {
2577 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2578 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2579
2580 switch (event) {
2581 case SND_SOC_DAPM_POST_PMU:
2582 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2583 !rt5677->is_vref_slow) {
2584 mdelay(20);
2585 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2586 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2587 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2588 rt5677->is_vref_slow = true;
2589 }
2590 break;
2591
2592 default:
2593 return 0;
2594 }
2595
2596 return 0;
2597 }
2598
2599 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2600 struct snd_kcontrol *kcontrol, int event)
2601 {
2602 switch (event) {
2603 case SND_SOC_DAPM_POST_PMU:
2604 msleep(50);
2605 break;
2606
2607 default:
2608 return 0;
2609 }
2610
2611 return 0;
2612 }
2613
2614 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2615 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2616 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2617 SND_SOC_DAPM_POST_PMU),
2618 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2619 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2620 SND_SOC_DAPM_POST_PMU),
2621
2622 /* ASRC */
2623 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2624 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2625 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2626 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2627 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2628 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2629 0),
2630 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2631 0),
2632 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2633 0),
2634 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2635 0),
2636 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2637 0),
2638 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2639 0),
2640 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2641 0),
2642 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2643 0),
2644 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2645 0),
2646 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2647 0),
2648 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2649 0),
2650 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2651 0),
2652 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2653 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2654 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2655 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2656 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2657 0),
2658 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2659 0),
2660
2661 /* Input Side */
2662 /* micbias */
2663 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2664 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2665 SND_SOC_DAPM_POST_PMU),
2666
2667 /* Input Lines */
2668 SND_SOC_DAPM_INPUT("DMIC L1"),
2669 SND_SOC_DAPM_INPUT("DMIC R1"),
2670 SND_SOC_DAPM_INPUT("DMIC L2"),
2671 SND_SOC_DAPM_INPUT("DMIC R2"),
2672 SND_SOC_DAPM_INPUT("DMIC L3"),
2673 SND_SOC_DAPM_INPUT("DMIC R3"),
2674 SND_SOC_DAPM_INPUT("DMIC L4"),
2675 SND_SOC_DAPM_INPUT("DMIC R4"),
2676
2677 SND_SOC_DAPM_INPUT("IN1P"),
2678 SND_SOC_DAPM_INPUT("IN1N"),
2679 SND_SOC_DAPM_INPUT("IN2P"),
2680 SND_SOC_DAPM_INPUT("IN2N"),
2681
2682 SND_SOC_DAPM_INPUT("Haptic Generator"),
2683
2684 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2685 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2686 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2687 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2688
2689 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2690 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2691 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2692 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2694 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2695 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2696 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2697
2698 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2699 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2700
2701 /* Boost */
2702 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2703 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2704 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2705 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2706 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2707 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2708
2709 /* ADCs */
2710 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2711 0, 0),
2712 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2713 0, 0),
2714 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2715
2716 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2717 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2718 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2719 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2720 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2721 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2722 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2723 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2724
2725 /* ADC Mux */
2726 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto1_dmic_mux),
2728 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto1_adc1_mux),
2730 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto1_adc2_mux),
2732 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_sto2_dmic_mux),
2734 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sto2_adc1_mux),
2736 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_sto2_adc2_mux),
2738 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_sto2_adc_lr_mux),
2740 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_sto3_dmic_mux),
2742 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_sto3_adc1_mux),
2744 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_sto3_adc2_mux),
2746 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_sto4_dmic_mux),
2748 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2749 &rt5677_sto4_adc1_mux),
2750 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2751 &rt5677_sto4_adc2_mux),
2752 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2753 &rt5677_mono_dmic_l_mux),
2754 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2755 &rt5677_mono_dmic_r_mux),
2756 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2757 &rt5677_mono_adc2_l_mux),
2758 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2759 &rt5677_mono_adc1_l_mux),
2760 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2761 &rt5677_mono_adc1_r_mux),
2762 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2763 &rt5677_mono_adc2_r_mux),
2764
2765 /* ADC Mixer */
2766 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2767 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2768 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2769 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2770 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2771 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2772 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2773 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2774 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2775 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2776 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2777 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2778 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2779 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2780 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2781 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2782 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2783 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2784 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2785 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2786 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2787 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2788 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2789 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2790 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2791 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2792 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2793 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2794 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2795 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2796 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2797 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2798
2799 /* ADC PGA */
2800 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2803 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2804 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2805 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2806 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2807 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2808 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2810 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2811 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2812 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2813 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2814 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2815 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2816
2817 /* DSP */
2818 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ib9_src_mux),
2820 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ib8_src_mux),
2822 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_ib7_src_mux),
2824 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_ib6_src_mux),
2826 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5677_ib45_src_mux),
2828 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5677_ib23_src_mux),
2830 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2831 &rt5677_ib01_src_mux),
2832 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2833 &rt5677_ib45_bypass_src_mux),
2834 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2835 &rt5677_ib23_bypass_src_mux),
2836 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2837 &rt5677_ib01_bypass_src_mux),
2838 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2839 &rt5677_ob23_bypass_src_mux),
2840 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2841 &rt5677_ob01_bypass_src_mux),
2842
2843 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2845
2846 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2852
2853 /* Digital Interface */
2854 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2855 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2872
2873 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2874 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2891
2892 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2893 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2895 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2900
2901 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2902 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2909
2910 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2911 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2914 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2915 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2916 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2917 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2918 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2919 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2920 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2923 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2924 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2925 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2926 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2927 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2928
2929 /* Digital Interface Select */
2930 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5677_if1_adc1_mux),
2932 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5677_if1_adc2_mux),
2934 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5677_if1_adc3_mux),
2936 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5677_if1_adc4_mux),
2938 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5677_if1_adc1_swap_mux),
2940 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5677_if1_adc2_swap_mux),
2942 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5677_if1_adc3_swap_mux),
2944 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5677_if1_adc4_swap_mux),
2946 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2948 SND_SOC_DAPM_PRE_PMU),
2949 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_if2_adc1_mux),
2951 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5677_if2_adc2_mux),
2953 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5677_if2_adc3_mux),
2955 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5677_if2_adc4_mux),
2957 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5677_if2_adc1_swap_mux),
2959 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5677_if2_adc2_swap_mux),
2961 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_if2_adc3_swap_mux),
2963 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5677_if2_adc4_swap_mux),
2965 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2967 SND_SOC_DAPM_PRE_PMU),
2968 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5677_if3_adc_mux),
2970 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5677_if4_adc_mux),
2972 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5677_slb_adc1_mux),
2974 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5677_slb_adc2_mux),
2976 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5677_slb_adc3_mux),
2978 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5677_slb_adc4_mux),
2980
2981 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5677_if1_dac0_tdm_sel_mux),
2983 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5677_if1_dac1_tdm_sel_mux),
2985 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5677_if1_dac2_tdm_sel_mux),
2987 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5677_if1_dac3_tdm_sel_mux),
2989 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5677_if1_dac4_tdm_sel_mux),
2991 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5677_if1_dac5_tdm_sel_mux),
2993 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5677_if1_dac6_tdm_sel_mux),
2995 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5677_if1_dac7_tdm_sel_mux),
2997
2998 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5677_if2_dac0_tdm_sel_mux),
3000 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
3001 &rt5677_if2_dac1_tdm_sel_mux),
3002 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
3003 &rt5677_if2_dac2_tdm_sel_mux),
3004 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
3005 &rt5677_if2_dac3_tdm_sel_mux),
3006 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
3007 &rt5677_if2_dac4_tdm_sel_mux),
3008 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
3009 &rt5677_if2_dac5_tdm_sel_mux),
3010 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
3011 &rt5677_if2_dac6_tdm_sel_mux),
3012 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3013 &rt5677_if2_dac7_tdm_sel_mux),
3014
3015 /* Audio Interface */
3016 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3017 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3018 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3019 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3020 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3021 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3022 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3023 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3024 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3025 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3026
3027 /* Sidetone Mux */
3028 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3029 &rt5677_sidetone_mux),
3030 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3031 RT5677_ST_EN_SFT, 0, NULL, 0),
3032
3033 /* VAD Mux*/
3034 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3035 &rt5677_vad_src_mux),
3036
3037 /* Tensilica DSP */
3038 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3039 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3040 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3041 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3042 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3043 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3044 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3045 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3046 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3047 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3048 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3049 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3050 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3051
3052 /* Output Side */
3053 /* DAC mixer before sound effect */
3054 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3055 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3056 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3057 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3058 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3059
3060 /* DAC Mux */
3061 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3062 &rt5677_dac1_mux),
3063 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3064 &rt5677_adda1_mux),
3065 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3066 &rt5677_dac12_mux),
3067 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3068 &rt5677_dac3_mux),
3069
3070 /* DAC2 channel Mux */
3071 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3072 &rt5677_dac2_l_mux),
3073 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3074 &rt5677_dac2_r_mux),
3075
3076 /* DAC3 channel Mux */
3077 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3078 &rt5677_dac3_l_mux),
3079 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3080 &rt5677_dac3_r_mux),
3081
3082 /* DAC4 channel Mux */
3083 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3084 &rt5677_dac4_l_mux),
3085 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3086 &rt5677_dac4_r_mux),
3087
3088 /* DAC Mixer */
3089 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3090 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3091 SND_SOC_DAPM_POST_PMU),
3092 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3093 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3094 SND_SOC_DAPM_POST_PMU),
3095 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3096 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3097 SND_SOC_DAPM_POST_PMU),
3098 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3099 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3100 SND_SOC_DAPM_POST_PMU),
3101 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3102 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3103 SND_SOC_DAPM_POST_PMU),
3104 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3105 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3106 SND_SOC_DAPM_POST_PMU),
3107 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3108 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3109 SND_SOC_DAPM_POST_PMU),
3110
3111 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3112 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3113 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3114 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3115 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3116 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3117 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3118 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3119 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3120 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3121 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3122 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3123 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3124 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3125 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3126 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3127 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3128 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3129 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3130 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3131
3132 /* DACs */
3133 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3134 RT5677_PWR_DAC1_BIT, 0),
3135 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3136 RT5677_PWR_DAC2_BIT, 0),
3137 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3138 RT5677_PWR_DAC3_BIT, 0),
3139
3140 /* PDM */
3141 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3142 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3143 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3144 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3145
3146 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3147 1, &rt5677_pdm1_l_mux),
3148 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3149 1, &rt5677_pdm1_r_mux),
3150 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3151 1, &rt5677_pdm2_l_mux),
3152 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3153 1, &rt5677_pdm2_r_mux),
3154
3155 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3156 0, NULL, 0),
3157 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3158 0, NULL, 0),
3159 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3160 0, NULL, 0),
3161
3162 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3163 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3164 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3165 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3166 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3167 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3168
3169 /* Output Lines */
3170 SND_SOC_DAPM_OUTPUT("LOUT1"),
3171 SND_SOC_DAPM_OUTPUT("LOUT2"),
3172 SND_SOC_DAPM_OUTPUT("LOUT3"),
3173 SND_SOC_DAPM_OUTPUT("PDM1L"),
3174 SND_SOC_DAPM_OUTPUT("PDM1R"),
3175 SND_SOC_DAPM_OUTPUT("PDM2L"),
3176 SND_SOC_DAPM_OUTPUT("PDM2R"),
3177
3178 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3179 };
3180
3181 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3182 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3183 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3184 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3185 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3186 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3187 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3188 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3189 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3190 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3191 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3192
3193 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3194 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3195 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3196 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3197 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3198 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3199 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3200 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3201 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3202 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3203 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3204 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3205 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3206
3207 { "DMIC1", NULL, "DMIC L1" },
3208 { "DMIC1", NULL, "DMIC R1" },
3209 { "DMIC2", NULL, "DMIC L2" },
3210 { "DMIC2", NULL, "DMIC R2" },
3211 { "DMIC3", NULL, "DMIC L3" },
3212 { "DMIC3", NULL, "DMIC R3" },
3213 { "DMIC4", NULL, "DMIC L4" },
3214 { "DMIC4", NULL, "DMIC R4" },
3215
3216 { "DMIC L1", NULL, "DMIC CLK" },
3217 { "DMIC R1", NULL, "DMIC CLK" },
3218 { "DMIC L2", NULL, "DMIC CLK" },
3219 { "DMIC R2", NULL, "DMIC CLK" },
3220 { "DMIC L3", NULL, "DMIC CLK" },
3221 { "DMIC R3", NULL, "DMIC CLK" },
3222 { "DMIC L4", NULL, "DMIC CLK" },
3223 { "DMIC R4", NULL, "DMIC CLK" },
3224
3225 { "DMIC L1", NULL, "DMIC1 power" },
3226 { "DMIC R1", NULL, "DMIC1 power" },
3227 { "DMIC L3", NULL, "DMIC3 power" },
3228 { "DMIC R3", NULL, "DMIC3 power" },
3229 { "DMIC L4", NULL, "DMIC4 power" },
3230 { "DMIC R4", NULL, "DMIC4 power" },
3231
3232 { "BST1", NULL, "IN1P" },
3233 { "BST1", NULL, "IN1N" },
3234 { "BST2", NULL, "IN2P" },
3235 { "BST2", NULL, "IN2N" },
3236
3237 { "IN1P", NULL, "MICBIAS1" },
3238 { "IN1N", NULL, "MICBIAS1" },
3239 { "IN2P", NULL, "MICBIAS1" },
3240 { "IN2N", NULL, "MICBIAS1" },
3241
3242 { "ADC 1", NULL, "BST1" },
3243 { "ADC 1", NULL, "ADC 1 power" },
3244 { "ADC 1", NULL, "ADC1 clock" },
3245 { "ADC 2", NULL, "BST2" },
3246 { "ADC 2", NULL, "ADC 2 power" },
3247 { "ADC 2", NULL, "ADC2 clock" },
3248
3249 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3250 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3251 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3252 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3253
3254 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3255 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3256 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3257 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3258
3259 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3260 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3261 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3262 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3263
3264 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3265 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3266 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3267 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3268
3269 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3270 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3271 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3272 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3273
3274 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3275 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3276 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3277 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3278
3279 { "ADC 1_2", NULL, "ADC 1" },
3280 { "ADC 1_2", NULL, "ADC 2" },
3281
3282 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3283 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3284 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3285
3286 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3287 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3288 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3289
3290 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3291 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3292 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3293
3294 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3295 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3296 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3297
3298 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3299 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3300 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3301
3302 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3303 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3304 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3305
3306 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3307 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3308 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3309
3310 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3311 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3312 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3313
3314 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3315 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3316 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3317
3318 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3319 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3320 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3321
3322 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3323 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3324 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3325
3326 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3327 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3328 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3329
3330 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3331 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3332 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3333 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3334
3335 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3336 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3337 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3338 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3339 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3340
3341 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3342 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3343
3344 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3345 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3346 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3347 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3348
3349 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3350 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3351
3352 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3353 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3354
3355 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3356 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3357 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3358 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3359 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3360
3361 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3362 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3363
3364 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3365 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3366 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3367 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3368
3369 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3370 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3371 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3372 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3373 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3374
3375 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3376 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3377
3378 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3379 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3380 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3381 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3382
3383 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3384 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3385 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3386 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3387 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3388
3389 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3390 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3391
3392 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3393 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3394 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3395 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3396
3397 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3398 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3399 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3400 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3401
3402 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3403 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3404
3405 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3406 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3407 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3408 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3409 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3410
3411 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3412 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3413 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3414
3415 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3416 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3417
3418 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3419 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3420 { "IF1 ADC3 Mux", "OB45", "OB45" },
3421
3422 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3423 { "IF1 ADC4 Mux", "OB67", "OB67" },
3424 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3425
3426 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3427 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3428 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3429 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3430
3431 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3432 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3433 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3434 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3435
3436 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3437 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3438 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3439 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3440
3441 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3442 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3443 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3444 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3445
3446 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3447 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3448 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3449 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3450
3451 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3452 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3453 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3454 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3455 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3456 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3457 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3458 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3459
3460 { "AIF1TX", NULL, "I2S1" },
3461 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3462
3463 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3464 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3465 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3466
3467 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3468 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3469
3470 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3471 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3472 { "IF2 ADC3 Mux", "OB45", "OB45" },
3473
3474 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3475 { "IF2 ADC4 Mux", "OB67", "OB67" },
3476 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3477
3478 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3479 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3480 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3481 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3482
3483 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3484 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3485 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3486 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3487
3488 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3489 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3490 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3491 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3492
3493 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3494 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3495 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3496 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3497
3498 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3499 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3500 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3501 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3502
3503 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3504 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3505 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3506 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3507 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3508 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3509 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3510 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3511
3512 { "AIF2TX", NULL, "I2S2" },
3513 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3514
3515 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3516 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3517 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3518 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3519 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3520 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3521 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3522 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3523
3524 { "AIF3TX", NULL, "I2S3" },
3525 { "AIF3TX", NULL, "IF3 ADC Mux" },
3526
3527 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3528 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3529 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3530 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3531 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3532 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3533 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3534 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3535
3536 { "AIF4TX", NULL, "I2S4" },
3537 { "AIF4TX", NULL, "IF4 ADC Mux" },
3538
3539 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3540 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3541 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3542
3543 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3544 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3545
3546 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3547 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3548 { "SLB ADC3 Mux", "OB45", "OB45" },
3549
3550 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3551 { "SLB ADC4 Mux", "OB67", "OB67" },
3552 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3553
3554 { "SLBTX", NULL, "SLB" },
3555 { "SLBTX", NULL, "SLB ADC1 Mux" },
3556 { "SLBTX", NULL, "SLB ADC2 Mux" },
3557 { "SLBTX", NULL, "SLB ADC3 Mux" },
3558 { "SLBTX", NULL, "SLB ADC4 Mux" },
3559
3560 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3561 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3562 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3563 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3564 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3565
3566 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3567 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3568
3569 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3570 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3571 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3572 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3573 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3574 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3575
3576 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3577 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3578
3579 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3580 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3581 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3582 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3583 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3584
3585 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3586 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3587
3588 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3589 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3590 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3591 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3592 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3593 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3594 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3595 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3596
3597 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3598 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3599 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3600 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3601 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3602 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3603 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3604 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3605
3606 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3607 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3608 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3609 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3610 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3611 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3612
3613 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3614 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3615 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3616 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3617 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3618 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3619 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3620
3621 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3622 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3623 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3624 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3625 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3626 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3627 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3628
3629 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3630 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3631 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3632 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3633 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3634 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3635 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3636
3637 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3638 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3639 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3640 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3641 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3642 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3643 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3644
3645 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3646 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3647 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3648 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3649 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3650 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3651 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3652
3653 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3654 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3655 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3656 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3657 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3658 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3659 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3660
3661 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3662 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3663 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3664 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3665 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3666 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3667 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3668
3669 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3670 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3671 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3672 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3673
3674 { "OutBound2", NULL, "OB23 Bypass Mux" },
3675 { "OutBound3", NULL, "OB23 Bypass Mux" },
3676 { "OutBound4", NULL, "OB4 MIX" },
3677 { "OutBound5", NULL, "OB5 MIX" },
3678 { "OutBound6", NULL, "OB6 MIX" },
3679 { "OutBound7", NULL, "OB7 MIX" },
3680
3681 { "OB45", NULL, "OutBound4" },
3682 { "OB45", NULL, "OutBound5" },
3683 { "OB67", NULL, "OutBound6" },
3684 { "OB67", NULL, "OutBound7" },
3685
3686 { "IF1 DAC0", NULL, "AIF1RX" },
3687 { "IF1 DAC1", NULL, "AIF1RX" },
3688 { "IF1 DAC2", NULL, "AIF1RX" },
3689 { "IF1 DAC3", NULL, "AIF1RX" },
3690 { "IF1 DAC4", NULL, "AIF1RX" },
3691 { "IF1 DAC5", NULL, "AIF1RX" },
3692 { "IF1 DAC6", NULL, "AIF1RX" },
3693 { "IF1 DAC7", NULL, "AIF1RX" },
3694 { "IF1 DAC0", NULL, "I2S1" },
3695 { "IF1 DAC1", NULL, "I2S1" },
3696 { "IF1 DAC2", NULL, "I2S1" },
3697 { "IF1 DAC3", NULL, "I2S1" },
3698 { "IF1 DAC4", NULL, "I2S1" },
3699 { "IF1 DAC5", NULL, "I2S1" },
3700 { "IF1 DAC6", NULL, "I2S1" },
3701 { "IF1 DAC7", NULL, "I2S1" },
3702
3703 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3704 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3705 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3706 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3707 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3708 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3709 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3710 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3711
3712 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3713 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3714 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3715 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3716 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3717 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3718 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3719 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3720
3721 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3722 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3723 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3724 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3725 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3726 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3727 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3728 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3729
3730 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3731 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3732 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3733 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3734 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3735 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3736 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3737 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3738
3739 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3740 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3741 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3742 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3743 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3744 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3745 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3746 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3747
3748 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3749 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3750 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3751 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3752 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3753 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3754 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3755 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3756
3757 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3758 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3759 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3760 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3761 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3762 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3763 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3764 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3765
3766 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3767 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3768 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3769 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3770 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3771 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3772 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3773 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3774
3775 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3776 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3777 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3778 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3779 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3780 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3781 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3782 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3783
3784 { "IF2 DAC0", NULL, "AIF2RX" },
3785 { "IF2 DAC1", NULL, "AIF2RX" },
3786 { "IF2 DAC2", NULL, "AIF2RX" },
3787 { "IF2 DAC3", NULL, "AIF2RX" },
3788 { "IF2 DAC4", NULL, "AIF2RX" },
3789 { "IF2 DAC5", NULL, "AIF2RX" },
3790 { "IF2 DAC6", NULL, "AIF2RX" },
3791 { "IF2 DAC7", NULL, "AIF2RX" },
3792 { "IF2 DAC0", NULL, "I2S2" },
3793 { "IF2 DAC1", NULL, "I2S2" },
3794 { "IF2 DAC2", NULL, "I2S2" },
3795 { "IF2 DAC3", NULL, "I2S2" },
3796 { "IF2 DAC4", NULL, "I2S2" },
3797 { "IF2 DAC5", NULL, "I2S2" },
3798 { "IF2 DAC6", NULL, "I2S2" },
3799 { "IF2 DAC7", NULL, "I2S2" },
3800
3801 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3802 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3803 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3804 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3805 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3806 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3807 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3808 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3809
3810 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3811 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3812 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3813 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3814 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3815 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3816 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3817 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3818
3819 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3820 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3821 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3822 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3823 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3824 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3825 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3826 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3827
3828 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3829 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3830 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3831 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3832 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3833 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3834 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3835 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3836
3837 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3838 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3839 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3840 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3841 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3842 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3843 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3844 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3845
3846 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3847 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3848 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3849 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3850 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3851 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3852 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3853 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3854
3855 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3856 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3857 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3858 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3859 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3860 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3861 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3862 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3863
3864 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3865 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3866 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3867 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3868 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3869 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3870 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3871 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3872
3873 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3874 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3875 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3876 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3877 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3878 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3879 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3880 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3881
3882 { "IF3 DAC", NULL, "AIF3RX" },
3883 { "IF3 DAC", NULL, "I2S3" },
3884
3885 { "IF4 DAC", NULL, "AIF4RX" },
3886 { "IF4 DAC", NULL, "I2S4" },
3887
3888 { "IF3 DAC L", NULL, "IF3 DAC" },
3889 { "IF3 DAC R", NULL, "IF3 DAC" },
3890
3891 { "IF4 DAC L", NULL, "IF4 DAC" },
3892 { "IF4 DAC R", NULL, "IF4 DAC" },
3893
3894 { "SLB DAC0", NULL, "SLBRX" },
3895 { "SLB DAC1", NULL, "SLBRX" },
3896 { "SLB DAC2", NULL, "SLBRX" },
3897 { "SLB DAC3", NULL, "SLBRX" },
3898 { "SLB DAC4", NULL, "SLBRX" },
3899 { "SLB DAC5", NULL, "SLBRX" },
3900 { "SLB DAC6", NULL, "SLBRX" },
3901 { "SLB DAC7", NULL, "SLBRX" },
3902 { "SLB DAC0", NULL, "SLB" },
3903 { "SLB DAC1", NULL, "SLB" },
3904 { "SLB DAC2", NULL, "SLB" },
3905 { "SLB DAC3", NULL, "SLB" },
3906 { "SLB DAC4", NULL, "SLB" },
3907 { "SLB DAC5", NULL, "SLB" },
3908 { "SLB DAC6", NULL, "SLB" },
3909 { "SLB DAC7", NULL, "SLB" },
3910
3911 { "SLB DAC01", NULL, "SLB DAC0" },
3912 { "SLB DAC01", NULL, "SLB DAC1" },
3913 { "SLB DAC23", NULL, "SLB DAC2" },
3914 { "SLB DAC23", NULL, "SLB DAC3" },
3915 { "SLB DAC45", NULL, "SLB DAC4" },
3916 { "SLB DAC45", NULL, "SLB DAC5" },
3917 { "SLB DAC67", NULL, "SLB DAC6" },
3918 { "SLB DAC67", NULL, "SLB DAC7" },
3919
3920 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3921 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3922 { "ADDA1 Mux", "OB 67", "OB67" },
3923
3924 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3925 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3926 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3927 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3928 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3929 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3930
3931 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3932 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3933 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3934 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3935
3936 { "DAC1 FS", NULL, "DAC1 MIXL" },
3937 { "DAC1 FS", NULL, "DAC1 MIXR" },
3938
3939 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3940 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3941 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3942 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3943 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3944 { "DAC2 L Mux", "OB 2", "OutBound2" },
3945
3946 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3947 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3948 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3949 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3950 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3951 { "DAC2 R Mux", "OB 3", "OutBound3" },
3952 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3953 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3954
3955 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3956 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3957 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3958 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3959 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3960 { "DAC3 L Mux", "OB 4", "OutBound4" },
3961
3962 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3963 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3964 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3965 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3966 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3967 { "DAC3 R Mux", "OB 5", "OutBound5" },
3968
3969 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3970 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3971 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3972 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3973 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3974 { "DAC4 L Mux", "OB 6", "OutBound6" },
3975
3976 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3977 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3978 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3979 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3980 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3981 { "DAC4 R Mux", "OB 7", "OutBound7" },
3982
3983 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3984 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3985 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3986 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3987 { "Sidetone Mux", "ADC1", "ADC 1" },
3988 { "Sidetone Mux", "ADC2", "ADC 2" },
3989 { "Sidetone Mux", NULL, "Sidetone Power" },
3990
3991 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3992 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3993 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3994 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3995 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3996 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3997 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3998 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3999 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
4000 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
4001 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
4002
4003 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
4004 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
4005 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
4006 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
4007 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
4008 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4009 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
4010 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
4011 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
4012 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
4013 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
4014 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4015
4016 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4017 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4018 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4019 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4020 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4021 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4022 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4023 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4024 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4025 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4026 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4027 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4028
4029 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4030 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4031 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4032 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4033 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4034 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4035 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4036 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4037 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4038 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4039 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4040 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4041
4042 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4043 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4044 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4045 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4046 { "DD1 MIX", NULL, "DD1 MIXL" },
4047 { "DD1 MIX", NULL, "DD1 MIXR" },
4048 { "DD2 MIX", NULL, "DD2 MIXL" },
4049 { "DD2 MIX", NULL, "DD2 MIXR" },
4050
4051 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4052 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4053 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4054 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4055
4056 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4057 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4058 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4059 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4060
4061 { "DAC 1", NULL, "DAC12 SRC Mux" },
4062 { "DAC 2", NULL, "DAC12 SRC Mux" },
4063 { "DAC 3", NULL, "DAC3 SRC Mux" },
4064
4065 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4066 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4067 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4068 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4069 { "PDM1 L Mux", NULL, "PDM1 Power" },
4070 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4071 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4072 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4073 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4074 { "PDM1 R Mux", NULL, "PDM1 Power" },
4075 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4076 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4077 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4078 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4079 { "PDM2 L Mux", NULL, "PDM2 Power" },
4080 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4081 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4082 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4083 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4084 { "PDM2 R Mux", NULL, "PDM2 Power" },
4085
4086 { "LOUT1 amp", NULL, "DAC 1" },
4087 { "LOUT2 amp", NULL, "DAC 2" },
4088 { "LOUT3 amp", NULL, "DAC 3" },
4089
4090 { "LOUT1 vref", NULL, "LOUT1 amp" },
4091 { "LOUT2 vref", NULL, "LOUT2 amp" },
4092 { "LOUT3 vref", NULL, "LOUT3 amp" },
4093
4094 { "LOUT1", NULL, "LOUT1 vref" },
4095 { "LOUT2", NULL, "LOUT2 vref" },
4096 { "LOUT3", NULL, "LOUT3 vref" },
4097
4098 { "PDM1L", NULL, "PDM1 L Mux" },
4099 { "PDM1R", NULL, "PDM1 R Mux" },
4100 { "PDM2L", NULL, "PDM2 L Mux" },
4101 { "PDM2R", NULL, "PDM2 R Mux" },
4102 };
4103
4104 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4105 { "DMIC L2", NULL, "DMIC1 power" },
4106 { "DMIC R2", NULL, "DMIC1 power" },
4107 };
4108
4109 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4110 { "DMIC L2", NULL, "DMIC2 power" },
4111 { "DMIC R2", NULL, "DMIC2 power" },
4112 };
4113
4114 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4115 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4116 {
4117 struct snd_soc_codec *codec = dai->codec;
4118 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4119 unsigned int val_len = 0, val_clk, mask_clk;
4120 int pre_div, bclk_ms, frame_size;
4121
4122 rt5677->lrck[dai->id] = params_rate(params);
4123 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4124 if (pre_div < 0) {
4125 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4126 rt5677->sysclk, rt5677->lrck[dai->id]);
4127 return -EINVAL;
4128 }
4129 frame_size = snd_soc_params_to_frame_size(params);
4130 if (frame_size < 0) {
4131 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4132 return -EINVAL;
4133 }
4134 bclk_ms = frame_size > 32;
4135 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4136
4137 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4138 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4139 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4140 bclk_ms, pre_div, dai->id);
4141
4142 switch (params_width(params)) {
4143 case 16:
4144 break;
4145 case 20:
4146 val_len |= RT5677_I2S_DL_20;
4147 break;
4148 case 24:
4149 val_len |= RT5677_I2S_DL_24;
4150 break;
4151 case 8:
4152 val_len |= RT5677_I2S_DL_8;
4153 break;
4154 default:
4155 return -EINVAL;
4156 }
4157
4158 switch (dai->id) {
4159 case RT5677_AIF1:
4160 mask_clk = RT5677_I2S_PD1_MASK;
4161 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4162 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4163 RT5677_I2S_DL_MASK, val_len);
4164 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4165 mask_clk, val_clk);
4166 break;
4167 case RT5677_AIF2:
4168 mask_clk = RT5677_I2S_PD2_MASK;
4169 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4170 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4171 RT5677_I2S_DL_MASK, val_len);
4172 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4173 mask_clk, val_clk);
4174 break;
4175 case RT5677_AIF3:
4176 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4177 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4178 pre_div << RT5677_I2S_PD3_SFT;
4179 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4180 RT5677_I2S_DL_MASK, val_len);
4181 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4182 mask_clk, val_clk);
4183 break;
4184 case RT5677_AIF4:
4185 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4186 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4187 pre_div << RT5677_I2S_PD4_SFT;
4188 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4189 RT5677_I2S_DL_MASK, val_len);
4190 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4191 mask_clk, val_clk);
4192 break;
4193 default:
4194 break;
4195 }
4196
4197 return 0;
4198 }
4199
4200 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4201 {
4202 struct snd_soc_codec *codec = dai->codec;
4203 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4204 unsigned int reg_val = 0;
4205
4206 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4207 case SND_SOC_DAIFMT_CBM_CFM:
4208 rt5677->master[dai->id] = 1;
4209 break;
4210 case SND_SOC_DAIFMT_CBS_CFS:
4211 reg_val |= RT5677_I2S_MS_S;
4212 rt5677->master[dai->id] = 0;
4213 break;
4214 default:
4215 return -EINVAL;
4216 }
4217
4218 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4219 case SND_SOC_DAIFMT_NB_NF:
4220 break;
4221 case SND_SOC_DAIFMT_IB_NF:
4222 reg_val |= RT5677_I2S_BP_INV;
4223 break;
4224 default:
4225 return -EINVAL;
4226 }
4227
4228 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4229 case SND_SOC_DAIFMT_I2S:
4230 break;
4231 case SND_SOC_DAIFMT_LEFT_J:
4232 reg_val |= RT5677_I2S_DF_LEFT;
4233 break;
4234 case SND_SOC_DAIFMT_DSP_A:
4235 reg_val |= RT5677_I2S_DF_PCM_A;
4236 break;
4237 case SND_SOC_DAIFMT_DSP_B:
4238 reg_val |= RT5677_I2S_DF_PCM_B;
4239 break;
4240 default:
4241 return -EINVAL;
4242 }
4243
4244 switch (dai->id) {
4245 case RT5677_AIF1:
4246 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4247 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4248 RT5677_I2S_DF_MASK, reg_val);
4249 break;
4250 case RT5677_AIF2:
4251 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4252 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4253 RT5677_I2S_DF_MASK, reg_val);
4254 break;
4255 case RT5677_AIF3:
4256 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4257 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4258 RT5677_I2S_DF_MASK, reg_val);
4259 break;
4260 case RT5677_AIF4:
4261 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4262 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4263 RT5677_I2S_DF_MASK, reg_val);
4264 break;
4265 default:
4266 break;
4267 }
4268
4269
4270 return 0;
4271 }
4272
4273 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4274 int clk_id, unsigned int freq, int dir)
4275 {
4276 struct snd_soc_codec *codec = dai->codec;
4277 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4278 unsigned int reg_val = 0;
4279
4280 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4281 return 0;
4282
4283 switch (clk_id) {
4284 case RT5677_SCLK_S_MCLK:
4285 reg_val |= RT5677_SCLK_SRC_MCLK;
4286 break;
4287 case RT5677_SCLK_S_PLL1:
4288 reg_val |= RT5677_SCLK_SRC_PLL1;
4289 break;
4290 case RT5677_SCLK_S_RCCLK:
4291 reg_val |= RT5677_SCLK_SRC_RCCLK;
4292 break;
4293 default:
4294 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4295 return -EINVAL;
4296 }
4297 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4298 RT5677_SCLK_SRC_MASK, reg_val);
4299 rt5677->sysclk = freq;
4300 rt5677->sysclk_src = clk_id;
4301
4302 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4303
4304 return 0;
4305 }
4306
4307 /**
4308 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4309 * @freq_in: external clock provided to codec.
4310 * @freq_out: target clock which codec works on.
4311 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4312 *
4313 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4314 *
4315 * Returns 0 for success or negative error code.
4316 */
4317 static int rt5677_pll_calc(const unsigned int freq_in,
4318 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4319 {
4320 if (RT5677_PLL_INP_MIN > freq_in)
4321 return -EINVAL;
4322
4323 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4324 }
4325
4326 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4327 unsigned int freq_in, unsigned int freq_out)
4328 {
4329 struct snd_soc_codec *codec = dai->codec;
4330 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4331 struct rl6231_pll_code pll_code;
4332 int ret;
4333
4334 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4335 freq_out == rt5677->pll_out)
4336 return 0;
4337
4338 if (!freq_in || !freq_out) {
4339 dev_dbg(codec->dev, "PLL disabled\n");
4340
4341 rt5677->pll_in = 0;
4342 rt5677->pll_out = 0;
4343 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4344 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4345 return 0;
4346 }
4347
4348 switch (source) {
4349 case RT5677_PLL1_S_MCLK:
4350 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4351 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4352 break;
4353 case RT5677_PLL1_S_BCLK1:
4354 case RT5677_PLL1_S_BCLK2:
4355 case RT5677_PLL1_S_BCLK3:
4356 case RT5677_PLL1_S_BCLK4:
4357 switch (dai->id) {
4358 case RT5677_AIF1:
4359 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4360 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4361 break;
4362 case RT5677_AIF2:
4363 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4364 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4365 break;
4366 case RT5677_AIF3:
4367 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4368 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4369 break;
4370 case RT5677_AIF4:
4371 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4372 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4373 break;
4374 default:
4375 break;
4376 }
4377 break;
4378 default:
4379 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4380 return -EINVAL;
4381 }
4382
4383 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4384 if (ret < 0) {
4385 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4386 return ret;
4387 }
4388
4389 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4390 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4391 pll_code.n_code, pll_code.k_code);
4392
4393 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4394 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4395 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4396 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4397 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4398
4399 rt5677->pll_in = freq_in;
4400 rt5677->pll_out = freq_out;
4401 rt5677->pll_src = source;
4402
4403 return 0;
4404 }
4405
4406 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4407 unsigned int rx_mask, int slots, int slot_width)
4408 {
4409 struct snd_soc_codec *codec = dai->codec;
4410 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4411 unsigned int val = 0, slot_width_25 = 0;
4412
4413 if (rx_mask || tx_mask)
4414 val |= (1 << 12);
4415
4416 switch (slots) {
4417 case 4:
4418 val |= (1 << 10);
4419 break;
4420 case 6:
4421 val |= (2 << 10);
4422 break;
4423 case 8:
4424 val |= (3 << 10);
4425 break;
4426 case 2:
4427 default:
4428 break;
4429 }
4430
4431 switch (slot_width) {
4432 case 20:
4433 val |= (1 << 8);
4434 break;
4435 case 25:
4436 slot_width_25 = 0x8080;
4437 case 24:
4438 val |= (2 << 8);
4439 break;
4440 case 32:
4441 val |= (3 << 8);
4442 break;
4443 case 16:
4444 default:
4445 break;
4446 }
4447
4448 switch (dai->id) {
4449 case RT5677_AIF1:
4450 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4451 val);
4452 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4453 slot_width_25);
4454 break;
4455 case RT5677_AIF2:
4456 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4457 val);
4458 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4459 slot_width_25);
4460 break;
4461 default:
4462 break;
4463 }
4464
4465 return 0;
4466 }
4467
4468 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4469 enum snd_soc_bias_level level)
4470 {
4471 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4472
4473 switch (level) {
4474 case SND_SOC_BIAS_ON:
4475 break;
4476
4477 case SND_SOC_BIAS_PREPARE:
4478 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4479 rt5677_set_dsp_vad(codec, false);
4480
4481 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4482 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4483 0x0055);
4484 regmap_update_bits(rt5677->regmap,
4485 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4486 0x0f00, 0x0f00);
4487 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4488 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4489 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4490 RT5677_PWR_BG | RT5677_PWR_VREF2,
4491 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4492 RT5677_PWR_BG | RT5677_PWR_VREF2);
4493 rt5677->is_vref_slow = false;
4494 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4495 RT5677_PWR_CORE, RT5677_PWR_CORE);
4496 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4497 0x1, 0x1);
4498 }
4499 break;
4500
4501 case SND_SOC_BIAS_STANDBY:
4502 break;
4503
4504 case SND_SOC_BIAS_OFF:
4505 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4506 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4507 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4508 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4509 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4510 regmap_update_bits(rt5677->regmap,
4511 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4512
4513 if (rt5677->dsp_vad_en)
4514 rt5677_set_dsp_vad(codec, true);
4515 break;
4516
4517 default:
4518 break;
4519 }
4520
4521 return 0;
4522 }
4523
4524 #ifdef CONFIG_GPIOLIB
4525 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4526 {
4527 return container_of(chip, struct rt5677_priv, gpio_chip);
4528 }
4529
4530 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4531 {
4532 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4533
4534 switch (offset) {
4535 case RT5677_GPIO1 ... RT5677_GPIO5:
4536 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4537 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4538 break;
4539
4540 case RT5677_GPIO6:
4541 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4542 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4543 break;
4544
4545 default:
4546 break;
4547 }
4548 }
4549
4550 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4551 unsigned offset, int value)
4552 {
4553 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4554
4555 switch (offset) {
4556 case RT5677_GPIO1 ... RT5677_GPIO5:
4557 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4558 0x3 << (offset * 3 + 1),
4559 (0x2 | !!value) << (offset * 3 + 1));
4560 break;
4561
4562 case RT5677_GPIO6:
4563 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4564 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4565 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4566 break;
4567
4568 default:
4569 break;
4570 }
4571
4572 return 0;
4573 }
4574
4575 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4576 {
4577 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4578 int value, ret;
4579
4580 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4581 if (ret < 0)
4582 return ret;
4583
4584 return (value & (0x1 << offset)) >> offset;
4585 }
4586
4587 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4588 {
4589 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4590
4591 switch (offset) {
4592 case RT5677_GPIO1 ... RT5677_GPIO5:
4593 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4594 0x1 << (offset * 3 + 2), 0x0);
4595 break;
4596
4597 case RT5677_GPIO6:
4598 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4599 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4600 break;
4601
4602 default:
4603 break;
4604 }
4605
4606 return 0;
4607 }
4608
4609 /** Configures the gpio as
4610 * 0 - floating
4611 * 1 - pull down
4612 * 2 - pull up
4613 */
4614 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4615 int value)
4616 {
4617 int shift;
4618
4619 switch (offset) {
4620 case RT5677_GPIO1 ... RT5677_GPIO2:
4621 shift = 2 * (1 - offset);
4622 regmap_update_bits(rt5677->regmap,
4623 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4624 0x3 << shift,
4625 (value & 0x3) << shift);
4626 break;
4627
4628 case RT5677_GPIO3 ... RT5677_GPIO6:
4629 shift = 2 * (9 - offset);
4630 regmap_update_bits(rt5677->regmap,
4631 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4632 0x3 << shift,
4633 (value & 0x3) << shift);
4634 break;
4635
4636 default:
4637 break;
4638 }
4639 }
4640
4641 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4642 {
4643 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4644 struct regmap_irq_chip_data *data = rt5677->irq_data;
4645 int irq;
4646
4647 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4648 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4649 (rt5677->pdata.jd1_gpio == 2 &&
4650 offset == RT5677_GPIO2) ||
4651 (rt5677->pdata.jd1_gpio == 3 &&
4652 offset == RT5677_GPIO3)) {
4653 irq = RT5677_IRQ_JD1;
4654 } else {
4655 return -ENXIO;
4656 }
4657 }
4658
4659 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4660 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4661 (rt5677->pdata.jd2_gpio == 2 &&
4662 offset == RT5677_GPIO5) ||
4663 (rt5677->pdata.jd2_gpio == 3 &&
4664 offset == RT5677_GPIO6)) {
4665 irq = RT5677_IRQ_JD2;
4666 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4667 offset == RT5677_GPIO4) ||
4668 (rt5677->pdata.jd3_gpio == 2 &&
4669 offset == RT5677_GPIO5) ||
4670 (rt5677->pdata.jd3_gpio == 3 &&
4671 offset == RT5677_GPIO6)) {
4672 irq = RT5677_IRQ_JD3;
4673 } else {
4674 return -ENXIO;
4675 }
4676 }
4677
4678 return regmap_irq_get_virq(data, irq);
4679 }
4680
4681 static struct gpio_chip rt5677_template_chip = {
4682 .label = "rt5677",
4683 .owner = THIS_MODULE,
4684 .direction_output = rt5677_gpio_direction_out,
4685 .set = rt5677_gpio_set,
4686 .direction_input = rt5677_gpio_direction_in,
4687 .get = rt5677_gpio_get,
4688 .to_irq = rt5677_to_irq,
4689 .can_sleep = 1,
4690 };
4691
4692 static void rt5677_init_gpio(struct i2c_client *i2c)
4693 {
4694 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4695 int ret;
4696
4697 rt5677->gpio_chip = rt5677_template_chip;
4698 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4699 rt5677->gpio_chip.dev = &i2c->dev;
4700 rt5677->gpio_chip.base = -1;
4701
4702 ret = gpiochip_add(&rt5677->gpio_chip);
4703 if (ret != 0)
4704 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4705 }
4706
4707 static void rt5677_free_gpio(struct i2c_client *i2c)
4708 {
4709 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4710
4711 gpiochip_remove(&rt5677->gpio_chip);
4712 }
4713 #else
4714 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4715 int value)
4716 {
4717 }
4718
4719 static void rt5677_init_gpio(struct i2c_client *i2c)
4720 {
4721 }
4722
4723 static void rt5677_free_gpio(struct i2c_client *i2c)
4724 {
4725 }
4726 #endif
4727
4728 static int rt5677_probe(struct snd_soc_codec *codec)
4729 {
4730 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4731 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4732 int i;
4733
4734 rt5677->codec = codec;
4735
4736 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4737 snd_soc_dapm_add_routes(dapm,
4738 rt5677_dmic2_clk_2,
4739 ARRAY_SIZE(rt5677_dmic2_clk_2));
4740 } else { /*use dmic1 clock by default*/
4741 snd_soc_dapm_add_routes(dapm,
4742 rt5677_dmic2_clk_1,
4743 ARRAY_SIZE(rt5677_dmic2_clk_1));
4744 }
4745
4746 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4747
4748 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4749 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4750
4751 for (i = 0; i < RT5677_GPIO_NUM; i++)
4752 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4753
4754 if (rt5677->irq_data) {
4755 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4756 0x8000);
4757 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4758 0x0008);
4759
4760 if (rt5677->pdata.jd1_gpio)
4761 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4762 RT5677_SEL_GPIO_JD1_MASK,
4763 rt5677->pdata.jd1_gpio <<
4764 RT5677_SEL_GPIO_JD1_SFT);
4765
4766 if (rt5677->pdata.jd2_gpio)
4767 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4768 RT5677_SEL_GPIO_JD2_MASK,
4769 rt5677->pdata.jd2_gpio <<
4770 RT5677_SEL_GPIO_JD2_SFT);
4771
4772 if (rt5677->pdata.jd3_gpio)
4773 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4774 RT5677_SEL_GPIO_JD3_MASK,
4775 rt5677->pdata.jd3_gpio <<
4776 RT5677_SEL_GPIO_JD3_SFT);
4777 }
4778
4779 mutex_init(&rt5677->dsp_cmd_lock);
4780 mutex_init(&rt5677->dsp_pri_lock);
4781
4782 return 0;
4783 }
4784
4785 static int rt5677_remove(struct snd_soc_codec *codec)
4786 {
4787 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4788
4789 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4790 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4791 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4792
4793 return 0;
4794 }
4795
4796 #ifdef CONFIG_PM
4797 static int rt5677_suspend(struct snd_soc_codec *codec)
4798 {
4799 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4800
4801 if (!rt5677->dsp_vad_en) {
4802 regcache_cache_only(rt5677->regmap, true);
4803 regcache_mark_dirty(rt5677->regmap);
4804
4805 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4806 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4807 }
4808
4809 return 0;
4810 }
4811
4812 static int rt5677_resume(struct snd_soc_codec *codec)
4813 {
4814 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4815
4816 if (!rt5677->dsp_vad_en) {
4817 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4818 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4819 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4820 msleep(10);
4821
4822 regcache_cache_only(rt5677->regmap, false);
4823 regcache_sync(rt5677->regmap);
4824 }
4825
4826 return 0;
4827 }
4828 #else
4829 #define rt5677_suspend NULL
4830 #define rt5677_resume NULL
4831 #endif
4832
4833 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4834 {
4835 struct i2c_client *client = context;
4836 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4837
4838 if (rt5677->is_dsp_mode) {
4839 if (reg > 0xff) {
4840 mutex_lock(&rt5677->dsp_pri_lock);
4841 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4842 reg & 0xff);
4843 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4844 mutex_unlock(&rt5677->dsp_pri_lock);
4845 } else {
4846 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4847 }
4848 } else {
4849 regmap_read(rt5677->regmap_physical, reg, val);
4850 }
4851
4852 return 0;
4853 }
4854
4855 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4856 {
4857 struct i2c_client *client = context;
4858 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4859
4860 if (rt5677->is_dsp_mode) {
4861 if (reg > 0xff) {
4862 mutex_lock(&rt5677->dsp_pri_lock);
4863 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4864 reg & 0xff);
4865 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4866 val);
4867 mutex_unlock(&rt5677->dsp_pri_lock);
4868 } else {
4869 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4870 }
4871 } else {
4872 regmap_write(rt5677->regmap_physical, reg, val);
4873 }
4874
4875 return 0;
4876 }
4877
4878 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4879 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4880 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4881
4882 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4883 .hw_params = rt5677_hw_params,
4884 .set_fmt = rt5677_set_dai_fmt,
4885 .set_sysclk = rt5677_set_dai_sysclk,
4886 .set_pll = rt5677_set_dai_pll,
4887 .set_tdm_slot = rt5677_set_tdm_slot,
4888 };
4889
4890 static struct snd_soc_dai_driver rt5677_dai[] = {
4891 {
4892 .name = "rt5677-aif1",
4893 .id = RT5677_AIF1,
4894 .playback = {
4895 .stream_name = "AIF1 Playback",
4896 .channels_min = 1,
4897 .channels_max = 2,
4898 .rates = RT5677_STEREO_RATES,
4899 .formats = RT5677_FORMATS,
4900 },
4901 .capture = {
4902 .stream_name = "AIF1 Capture",
4903 .channels_min = 1,
4904 .channels_max = 2,
4905 .rates = RT5677_STEREO_RATES,
4906 .formats = RT5677_FORMATS,
4907 },
4908 .ops = &rt5677_aif_dai_ops,
4909 },
4910 {
4911 .name = "rt5677-aif2",
4912 .id = RT5677_AIF2,
4913 .playback = {
4914 .stream_name = "AIF2 Playback",
4915 .channels_min = 1,
4916 .channels_max = 2,
4917 .rates = RT5677_STEREO_RATES,
4918 .formats = RT5677_FORMATS,
4919 },
4920 .capture = {
4921 .stream_name = "AIF2 Capture",
4922 .channels_min = 1,
4923 .channels_max = 2,
4924 .rates = RT5677_STEREO_RATES,
4925 .formats = RT5677_FORMATS,
4926 },
4927 .ops = &rt5677_aif_dai_ops,
4928 },
4929 {
4930 .name = "rt5677-aif3",
4931 .id = RT5677_AIF3,
4932 .playback = {
4933 .stream_name = "AIF3 Playback",
4934 .channels_min = 1,
4935 .channels_max = 2,
4936 .rates = RT5677_STEREO_RATES,
4937 .formats = RT5677_FORMATS,
4938 },
4939 .capture = {
4940 .stream_name = "AIF3 Capture",
4941 .channels_min = 1,
4942 .channels_max = 2,
4943 .rates = RT5677_STEREO_RATES,
4944 .formats = RT5677_FORMATS,
4945 },
4946 .ops = &rt5677_aif_dai_ops,
4947 },
4948 {
4949 .name = "rt5677-aif4",
4950 .id = RT5677_AIF4,
4951 .playback = {
4952 .stream_name = "AIF4 Playback",
4953 .channels_min = 1,
4954 .channels_max = 2,
4955 .rates = RT5677_STEREO_RATES,
4956 .formats = RT5677_FORMATS,
4957 },
4958 .capture = {
4959 .stream_name = "AIF4 Capture",
4960 .channels_min = 1,
4961 .channels_max = 2,
4962 .rates = RT5677_STEREO_RATES,
4963 .formats = RT5677_FORMATS,
4964 },
4965 .ops = &rt5677_aif_dai_ops,
4966 },
4967 {
4968 .name = "rt5677-slimbus",
4969 .id = RT5677_AIF5,
4970 .playback = {
4971 .stream_name = "SLIMBus Playback",
4972 .channels_min = 1,
4973 .channels_max = 2,
4974 .rates = RT5677_STEREO_RATES,
4975 .formats = RT5677_FORMATS,
4976 },
4977 .capture = {
4978 .stream_name = "SLIMBus Capture",
4979 .channels_min = 1,
4980 .channels_max = 2,
4981 .rates = RT5677_STEREO_RATES,
4982 .formats = RT5677_FORMATS,
4983 },
4984 .ops = &rt5677_aif_dai_ops,
4985 },
4986 };
4987
4988 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4989 .probe = rt5677_probe,
4990 .remove = rt5677_remove,
4991 .suspend = rt5677_suspend,
4992 .resume = rt5677_resume,
4993 .set_bias_level = rt5677_set_bias_level,
4994 .idle_bias_off = true,
4995 .controls = rt5677_snd_controls,
4996 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4997 .dapm_widgets = rt5677_dapm_widgets,
4998 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4999 .dapm_routes = rt5677_dapm_routes,
5000 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
5001 };
5002
5003 static const struct regmap_config rt5677_regmap_physical = {
5004 .name = "physical",
5005 .reg_bits = 8,
5006 .val_bits = 16,
5007
5008 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5009 RT5677_PR_SPACING),
5010 .readable_reg = rt5677_readable_register,
5011
5012 .cache_type = REGCACHE_NONE,
5013 .ranges = rt5677_ranges,
5014 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5015 };
5016
5017 static const struct regmap_config rt5677_regmap = {
5018 .reg_bits = 8,
5019 .val_bits = 16,
5020
5021 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5022 RT5677_PR_SPACING),
5023
5024 .volatile_reg = rt5677_volatile_register,
5025 .readable_reg = rt5677_readable_register,
5026 .reg_read = rt5677_read,
5027 .reg_write = rt5677_write,
5028
5029 .cache_type = REGCACHE_RBTREE,
5030 .reg_defaults = rt5677_reg,
5031 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5032 .ranges = rt5677_ranges,
5033 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5034 };
5035
5036 static const struct i2c_device_id rt5677_i2c_id[] = {
5037 { "rt5677", RT5677 },
5038 { "rt5676", RT5676 },
5039 { }
5040 };
5041 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5042
5043 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5044 struct device *dev)
5045 {
5046 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5047 "realtek,in1-differential");
5048 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5049 "realtek,in2-differential");
5050 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5051 "realtek,lout1-differential");
5052 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5053 "realtek,lout2-differential");
5054 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5055 "realtek,lout3-differential");
5056
5057 device_property_read_u8_array(dev, "realtek,gpio-config",
5058 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5059
5060 device_property_read_u32(dev, "realtek,jd1-gpio",
5061 &rt5677->pdata.jd1_gpio);
5062 device_property_read_u32(dev, "realtek,jd2-gpio",
5063 &rt5677->pdata.jd2_gpio);
5064 device_property_read_u32(dev, "realtek,jd3-gpio",
5065 &rt5677->pdata.jd3_gpio);
5066 }
5067
5068 static struct regmap_irq rt5677_irqs[] = {
5069 [RT5677_IRQ_JD1] = {
5070 .reg_offset = 0,
5071 .mask = RT5677_EN_IRQ_GPIO_JD1,
5072 },
5073 [RT5677_IRQ_JD2] = {
5074 .reg_offset = 0,
5075 .mask = RT5677_EN_IRQ_GPIO_JD2,
5076 },
5077 [RT5677_IRQ_JD3] = {
5078 .reg_offset = 0,
5079 .mask = RT5677_EN_IRQ_GPIO_JD3,
5080 },
5081 };
5082
5083 static struct regmap_irq_chip rt5677_irq_chip = {
5084 .name = "rt5677",
5085 .irqs = rt5677_irqs,
5086 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5087
5088 .num_regs = 1,
5089 .status_base = RT5677_IRQ_CTRL1,
5090 .mask_base = RT5677_IRQ_CTRL1,
5091 .mask_invert = 1,
5092 };
5093
5094 static int rt5677_init_irq(struct i2c_client *i2c)
5095 {
5096 int ret;
5097 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5098
5099 if (!rt5677->pdata.jd1_gpio &&
5100 !rt5677->pdata.jd2_gpio &&
5101 !rt5677->pdata.jd3_gpio)
5102 return 0;
5103
5104 if (!i2c->irq) {
5105 dev_err(&i2c->dev, "No interrupt specified\n");
5106 return -EINVAL;
5107 }
5108
5109 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5110 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5111 &rt5677_irq_chip, &rt5677->irq_data);
5112
5113 if (ret != 0) {
5114 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5115 return ret;
5116 }
5117
5118 return 0;
5119 }
5120
5121 static void rt5677_free_irq(struct i2c_client *i2c)
5122 {
5123 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5124
5125 if (rt5677->irq_data)
5126 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5127 }
5128
5129 static int rt5677_i2c_probe(struct i2c_client *i2c,
5130 const struct i2c_device_id *id)
5131 {
5132 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5133 struct rt5677_priv *rt5677;
5134 int ret;
5135 unsigned int val;
5136
5137 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5138 GFP_KERNEL);
5139 if (rt5677 == NULL)
5140 return -ENOMEM;
5141
5142 i2c_set_clientdata(i2c, rt5677);
5143
5144 rt5677->type = id->driver_data;
5145
5146 if (pdata)
5147 rt5677->pdata = *pdata;
5148 else
5149 rt5677_read_device_properties(rt5677, &i2c->dev);
5150
5151 /* pow-ldo2 and reset are optional. The codec pins may be statically
5152 * connected on the board without gpios. If the gpio device property
5153 * isn't specified, devm_gpiod_get_optional returns NULL.
5154 */
5155 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5156 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5157 if (IS_ERR(rt5677->pow_ldo2)) {
5158 ret = PTR_ERR(rt5677->pow_ldo2);
5159 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5160 return ret;
5161 }
5162 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5163 "realtek,reset", GPIOD_OUT_HIGH);
5164 if (IS_ERR(rt5677->reset_pin)) {
5165 ret = PTR_ERR(rt5677->reset_pin);
5166 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5167 return ret;
5168 }
5169
5170 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5171 /* Wait a while until I2C bus becomes available. The datasheet
5172 * does not specify the exact we should wait but startup
5173 * sequence mentiones at least a few milliseconds.
5174 */
5175 msleep(10);
5176 }
5177
5178 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5179 &rt5677_regmap_physical);
5180 if (IS_ERR(rt5677->regmap_physical)) {
5181 ret = PTR_ERR(rt5677->regmap_physical);
5182 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5183 ret);
5184 return ret;
5185 }
5186
5187 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5188 if (IS_ERR(rt5677->regmap)) {
5189 ret = PTR_ERR(rt5677->regmap);
5190 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5191 ret);
5192 return ret;
5193 }
5194
5195 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5196 if (val != RT5677_DEVICE_ID) {
5197 dev_err(&i2c->dev,
5198 "Device with ID register %#x is not rt5677\n", val);
5199 return -ENODEV;
5200 }
5201
5202 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5203
5204 ret = regmap_register_patch(rt5677->regmap, init_list,
5205 ARRAY_SIZE(init_list));
5206 if (ret != 0)
5207 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5208
5209 if (rt5677->pdata.in1_diff)
5210 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5211 RT5677_IN_DF1, RT5677_IN_DF1);
5212
5213 if (rt5677->pdata.in2_diff)
5214 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5215 RT5677_IN_DF2, RT5677_IN_DF2);
5216
5217 if (rt5677->pdata.lout1_diff)
5218 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5219 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5220
5221 if (rt5677->pdata.lout2_diff)
5222 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5223 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5224
5225 if (rt5677->pdata.lout3_diff)
5226 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5227 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5228
5229 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5230 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5231 RT5677_GPIO5_FUNC_MASK,
5232 RT5677_GPIO5_FUNC_DMIC);
5233 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5234 RT5677_GPIO5_DIR_MASK,
5235 RT5677_GPIO5_DIR_OUT);
5236 }
5237
5238 if (rt5677->pdata.micbias1_vdd_3v3)
5239 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5240 RT5677_MICBIAS1_CTRL_VDD_MASK,
5241 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5242
5243 rt5677_init_gpio(i2c);
5244 rt5677_init_irq(i2c);
5245
5246 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5247 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5248 }
5249
5250 static int rt5677_i2c_remove(struct i2c_client *i2c)
5251 {
5252 snd_soc_unregister_codec(&i2c->dev);
5253 rt5677_free_irq(i2c);
5254 rt5677_free_gpio(i2c);
5255
5256 return 0;
5257 }
5258
5259 static struct i2c_driver rt5677_i2c_driver = {
5260 .driver = {
5261 .name = "rt5677",
5262 },
5263 .probe = rt5677_i2c_probe,
5264 .remove = rt5677_i2c_remove,
5265 .id_table = rt5677_i2c_id,
5266 };
5267 module_i2c_driver(rt5677_i2c_driver);
5268
5269 MODULE_DESCRIPTION("ASoC RT5677 driver");
5270 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5271 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support