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irqchip: Fix dependencies for archs w/o HAS_IOMEM
[linux/fpc-iii.git] / sound / soc / dwc / designware_i2s.c
blob6e6a70c5c2bdba8349e4652e53a672c7fb40d74e
1 /*
2 * ALSA SoC Synopsys I2S Audio Layer
3 *
4 * sound/soc/dwc/designware_i2s.c
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Rajeev Kumar <rajeevkumar.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <sound/designware_i2s.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/dmaengine_pcm.h>
26
27 /* common register for all channel */
28 #define IER 0x000
29 #define IRER 0x004
30 #define ITER 0x008
31 #define CER 0x00C
32 #define CCR 0x010
33 #define RXFFR 0x014
34 #define TXFFR 0x018
35
36 /* I2STxRxRegisters for all channels */
37 #define LRBR_LTHR(x) (0x40 * x + 0x020)
38 #define RRBR_RTHR(x) (0x40 * x + 0x024)
39 #define RER(x) (0x40 * x + 0x028)
40 #define TER(x) (0x40 * x + 0x02C)
41 #define RCR(x) (0x40 * x + 0x030)
42 #define TCR(x) (0x40 * x + 0x034)
43 #define ISR(x) (0x40 * x + 0x038)
44 #define IMR(x) (0x40 * x + 0x03C)
45 #define ROR(x) (0x40 * x + 0x040)
46 #define TOR(x) (0x40 * x + 0x044)
47 #define RFCR(x) (0x40 * x + 0x048)
48 #define TFCR(x) (0x40 * x + 0x04C)
49 #define RFF(x) (0x40 * x + 0x050)
50 #define TFF(x) (0x40 * x + 0x054)
51
52 /* I2SCOMPRegisters */
53 #define I2S_COMP_PARAM_2 0x01F0
54 #define I2S_COMP_PARAM_1 0x01F4
55 #define I2S_COMP_VERSION 0x01F8
56 #define I2S_COMP_TYPE 0x01FC
57
58 /*
59 * Component parameter register fields - define the I2S block's
60 * configuration.
61 */
62 #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)
63 #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)
64 #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)
65 #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)
66 #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)
67 #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)
68 #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
69 #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
70 #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4)
71 #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)
72 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
73
74 #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)
75 #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)
76 #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)
77 #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)
78
79 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
80 #define COMP_MAX_WORDSIZE (1 << 3)
81 #define COMP_MAX_DATA_WIDTH (1 << 2)
82
83 #define MAX_CHANNEL_NUM 8
84 #define MIN_CHANNEL_NUM 2
85
86 union dw_i2s_snd_dma_data {
87 struct i2s_dma_data pd;
88 struct snd_dmaengine_dai_dma_data dt;
89 };
90
91 struct dw_i2s_dev {
92 void __iomem *i2s_base;
93 struct clk *clk;
94 int active;
95 unsigned int capability;
96 struct device *dev;
97
98 /* data related to DMA transfers b/w i2s and DMAC */
99 union dw_i2s_snd_dma_data play_dma_data;
100 union dw_i2s_snd_dma_data capture_dma_data;
101 struct i2s_clk_config_data config;
102 int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
103 };
104
105 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
106 {
107 writel(val, io_base + reg);
108 }
109
110 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
111 {
112 return readl(io_base + reg);
113 }
114
115 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
116 {
117 u32 i = 0;
118
119 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
120 for (i = 0; i < 4; i++)
121 i2s_write_reg(dev->i2s_base, TER(i), 0);
122 } else {
123 for (i = 0; i < 4; i++)
124 i2s_write_reg(dev->i2s_base, RER(i), 0);
125 }
126 }
127
128 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
129 {
130 u32 i = 0;
131
132 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
133 for (i = 0; i < 4; i++)
134 i2s_read_reg(dev->i2s_base, TOR(i));
135 } else {
136 for (i = 0; i < 4; i++)
137 i2s_read_reg(dev->i2s_base, ROR(i));
138 }
139 }
140
141 static void i2s_start(struct dw_i2s_dev *dev,
142 struct snd_pcm_substream *substream)
143 {
144 u32 i, irq;
145 i2s_write_reg(dev->i2s_base, IER, 1);
146
147 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
148 for (i = 0; i < 4; i++) {
149 irq = i2s_read_reg(dev->i2s_base, IMR(i));
150 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
151 }
152 i2s_write_reg(dev->i2s_base, ITER, 1);
153 } else {
154 for (i = 0; i < 4; i++) {
155 irq = i2s_read_reg(dev->i2s_base, IMR(i));
156 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
157 }
158 i2s_write_reg(dev->i2s_base, IRER, 1);
159 }
160
161 i2s_write_reg(dev->i2s_base, CER, 1);
162 }
163
164 static void i2s_stop(struct dw_i2s_dev *dev,
165 struct snd_pcm_substream *substream)
166 {
167 u32 i = 0, irq;
168
169 i2s_clear_irqs(dev, substream->stream);
170 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
171 i2s_write_reg(dev->i2s_base, ITER, 0);
172
173 for (i = 0; i < 4; i++) {
174 irq = i2s_read_reg(dev->i2s_base, IMR(i));
175 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
176 }
177 } else {
178 i2s_write_reg(dev->i2s_base, IRER, 0);
179
180 for (i = 0; i < 4; i++) {
181 irq = i2s_read_reg(dev->i2s_base, IMR(i));
182 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
183 }
184 }
185
186 if (!dev->active) {
187 i2s_write_reg(dev->i2s_base, CER, 0);
188 i2s_write_reg(dev->i2s_base, IER, 0);
189 }
190 }
191
192 static int dw_i2s_startup(struct snd_pcm_substream *substream,
193 struct snd_soc_dai *cpu_dai)
194 {
195 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
196 union dw_i2s_snd_dma_data *dma_data = NULL;
197
198 if (!(dev->capability & DWC_I2S_RECORD) &&
199 (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
200 return -EINVAL;
201
202 if (!(dev->capability & DWC_I2S_PLAY) &&
203 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
204 return -EINVAL;
205
206 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
207 dma_data = &dev->play_dma_data;
208 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
209 dma_data = &dev->capture_dma_data;
210
211 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
212
213 return 0;
214 }
215
216 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
217 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
218 {
219 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
220 struct i2s_clk_config_data *config = &dev->config;
221 u32 ccr, xfer_resolution, ch_reg, irq;
222 int ret;
223
224 switch (params_format(params)) {
225 case SNDRV_PCM_FORMAT_S16_LE:
226 config->data_width = 16;
227 ccr = 0x00;
228 xfer_resolution = 0x02;
229 break;
230
231 case SNDRV_PCM_FORMAT_S24_LE:
232 config->data_width = 24;
233 ccr = 0x08;
234 xfer_resolution = 0x04;
235 break;
236
237 case SNDRV_PCM_FORMAT_S32_LE:
238 config->data_width = 32;
239 ccr = 0x10;
240 xfer_resolution = 0x05;
241 break;
242
243 default:
244 dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
245 return -EINVAL;
246 }
247
248 config->chan_nr = params_channels(params);
249
250 switch (config->chan_nr) {
251 case EIGHT_CHANNEL_SUPPORT:
252 case SIX_CHANNEL_SUPPORT:
253 case FOUR_CHANNEL_SUPPORT:
254 case TWO_CHANNEL_SUPPORT:
255 break;
256 default:
257 dev_err(dev->dev, "channel not supported\n");
258 return -EINVAL;
259 }
260
261 i2s_disable_channels(dev, substream->stream);
262
263 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
264 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
265 i2s_write_reg(dev->i2s_base, TCR(ch_reg),
266 xfer_resolution);
267 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
268 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
269 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
270 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
271 } else {
272 i2s_write_reg(dev->i2s_base, RCR(ch_reg),
273 xfer_resolution);
274 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
275 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
276 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
277 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
278 }
279 }
280
281 i2s_write_reg(dev->i2s_base, CCR, ccr);
282
283 config->sample_rate = params_rate(params);
284
285 if (dev->capability & DW_I2S_MASTER) {
286 if (dev->i2s_clk_cfg) {
287 ret = dev->i2s_clk_cfg(config);
288 if (ret < 0) {
289 dev_err(dev->dev, "runtime audio clk config fail\n");
290 return ret;
291 }
292 } else {
293 u32 bitclk = config->sample_rate *
294 config->data_width * 2;
295
296 ret = clk_set_rate(dev->clk, bitclk);
297 if (ret) {
298 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
299 ret);
300 return ret;
301 }
302 }
303 }
304 return 0;
305 }
306
307 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
308 struct snd_soc_dai *dai)
309 {
310 snd_soc_dai_set_dma_data(dai, substream, NULL);
311 }
312
313 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
314 struct snd_soc_dai *dai)
315 {
316 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
317
318 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
319 i2s_write_reg(dev->i2s_base, TXFFR, 1);
320 else
321 i2s_write_reg(dev->i2s_base, RXFFR, 1);
322
323 return 0;
324 }
325
326 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
327 int cmd, struct snd_soc_dai *dai)
328 {
329 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
330 int ret = 0;
331
332 switch (cmd) {
333 case SNDRV_PCM_TRIGGER_START:
334 case SNDRV_PCM_TRIGGER_RESUME:
335 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
336 dev->active++;
337 i2s_start(dev, substream);
338 break;
339
340 case SNDRV_PCM_TRIGGER_STOP:
341 case SNDRV_PCM_TRIGGER_SUSPEND:
342 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
343 dev->active--;
344 i2s_stop(dev, substream);
345 break;
346 default:
347 ret = -EINVAL;
348 break;
349 }
350 return ret;
351 }
352
353 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
354 {
355 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
356 int ret = 0;
357
358 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
359 case SND_SOC_DAIFMT_CBM_CFM:
360 if (dev->capability & DW_I2S_SLAVE)
361 ret = 0;
362 else
363 ret = -EINVAL;
364 break;
365 case SND_SOC_DAIFMT_CBS_CFS:
366 if (dev->capability & DW_I2S_MASTER)
367 ret = 0;
368 else
369 ret = -EINVAL;
370 break;
371 case SND_SOC_DAIFMT_CBM_CFS:
372 case SND_SOC_DAIFMT_CBS_CFM:
373 ret = -EINVAL;
374 break;
375 default:
376 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
377 ret = -EINVAL;
378 break;
379 }
380 return ret;
381 }
382
383 static struct snd_soc_dai_ops dw_i2s_dai_ops = {
384 .startup = dw_i2s_startup,
385 .shutdown = dw_i2s_shutdown,
386 .hw_params = dw_i2s_hw_params,
387 .prepare = dw_i2s_prepare,
388 .trigger = dw_i2s_trigger,
389 .set_fmt = dw_i2s_set_fmt,
390 };
391
392 static const struct snd_soc_component_driver dw_i2s_component = {
393 .name = "dw-i2s",
394 };
395
396 #ifdef CONFIG_PM
397
398 static int dw_i2s_suspend(struct snd_soc_dai *dai)
399 {
400 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
401
402 if (dev->capability & DW_I2S_MASTER)
403 clk_disable(dev->clk);
404 return 0;
405 }
406
407 static int dw_i2s_resume(struct snd_soc_dai *dai)
408 {
409 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
410
411 if (dev->capability & DW_I2S_MASTER)
412 clk_enable(dev->clk);
413 return 0;
414 }
415
416 #else
417 #define dw_i2s_suspend NULL
418 #define dw_i2s_resume NULL
419 #endif
420
421 /*
422 * The following tables allow a direct lookup of various parameters
423 * defined in the I2S block's configuration in terms of sound system
424 * parameters. Each table is sized to the number of entries possible
425 * according to the number of configuration bits describing an I2S
426 * block parameter.
427 */
428
429 /* Maximum bit resolution of a channel - not uniformly spaced */
430 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
431 12, 16, 20, 24, 32, 0, 0, 0
432 };
433
434 /* Width of (DMA) bus */
435 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
436 DMA_SLAVE_BUSWIDTH_1_BYTE,
437 DMA_SLAVE_BUSWIDTH_2_BYTES,
438 DMA_SLAVE_BUSWIDTH_4_BYTES,
439 DMA_SLAVE_BUSWIDTH_UNDEFINED
440 };
441
442 /* PCM format to support channel resolution */
443 static const u32 formats[COMP_MAX_WORDSIZE] = {
444 SNDRV_PCM_FMTBIT_S16_LE,
445 SNDRV_PCM_FMTBIT_S16_LE,
446 SNDRV_PCM_FMTBIT_S24_LE,
447 SNDRV_PCM_FMTBIT_S24_LE,
448 SNDRV_PCM_FMTBIT_S32_LE,
449 0,
450 0,
451 0
452 };
453
454 static int dw_configure_dai(struct dw_i2s_dev *dev,
455 struct snd_soc_dai_driver *dw_i2s_dai,
456 unsigned int rates)
457 {
458 /*
459 * Read component parameter registers to extract
460 * the I2S block's configuration.
461 */
462 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
463 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
464 u32 idx;
465
466 if (COMP1_TX_ENABLED(comp1)) {
467 dev_dbg(dev->dev, " designware: play supported\n");
468 idx = COMP1_TX_WORDSIZE_0(comp1);
469 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
470 return -EINVAL;
471 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
472 dw_i2s_dai->playback.channels_max =
473 1 << (COMP1_TX_CHANNELS(comp1) + 1);
474 dw_i2s_dai->playback.formats = formats[idx];
475 dw_i2s_dai->playback.rates = rates;
476 }
477
478 if (COMP1_RX_ENABLED(comp1)) {
479 dev_dbg(dev->dev, "designware: record supported\n");
480 idx = COMP2_RX_WORDSIZE_0(comp2);
481 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
482 return -EINVAL;
483 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
484 dw_i2s_dai->capture.channels_max =
485 1 << (COMP1_RX_CHANNELS(comp1) + 1);
486 dw_i2s_dai->capture.formats = formats[idx];
487 dw_i2s_dai->capture.rates = rates;
488 }
489
490 if (COMP1_MODE_EN(comp1)) {
491 dev_dbg(dev->dev, "designware: i2s master mode supported\n");
492 dev->capability |= DW_I2S_MASTER;
493 } else {
494 dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
495 dev->capability |= DW_I2S_SLAVE;
496 }
497
498 return 0;
499 }
500
501 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
502 struct snd_soc_dai_driver *dw_i2s_dai,
503 struct resource *res,
504 const struct i2s_platform_data *pdata)
505 {
506 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
507 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
508 int ret;
509
510 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
511 return -EINVAL;
512
513 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
514 if (ret < 0)
515 return ret;
516
517 /* Set DMA slaves info */
518 dev->play_dma_data.pd.data = pdata->play_dma_data;
519 dev->capture_dma_data.pd.data = pdata->capture_dma_data;
520 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
521 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
522 dev->play_dma_data.pd.max_burst = 16;
523 dev->capture_dma_data.pd.max_burst = 16;
524 dev->play_dma_data.pd.addr_width = bus_widths[idx];
525 dev->capture_dma_data.pd.addr_width = bus_widths[idx];
526 dev->play_dma_data.pd.filter = pdata->filter;
527 dev->capture_dma_data.pd.filter = pdata->filter;
528
529 return 0;
530 }
531
532 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
533 struct snd_soc_dai_driver *dw_i2s_dai,
534 struct resource *res)
535 {
536 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
537 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
538 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
539 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
540 u32 idx2;
541 int ret;
542
543 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
544 return -EINVAL;
545
546 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
547 if (ret < 0)
548 return ret;
549
550 if (COMP1_TX_ENABLED(comp1)) {
551 idx2 = COMP1_TX_WORDSIZE_0(comp1);
552
553 dev->capability |= DWC_I2S_PLAY;
554 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
555 dev->play_dma_data.dt.addr_width = bus_widths[idx];
556 dev->play_dma_data.dt.chan_name = "TX";
557 dev->play_dma_data.dt.fifo_size = fifo_depth *
558 (fifo_width[idx2]) >> 8;
559 dev->play_dma_data.dt.maxburst = 16;
560 }
561 if (COMP1_RX_ENABLED(comp1)) {
562 idx2 = COMP2_RX_WORDSIZE_0(comp2);
563
564 dev->capability |= DWC_I2S_RECORD;
565 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
566 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
567 dev->capture_dma_data.dt.chan_name = "RX";
568 dev->capture_dma_data.dt.fifo_size = fifo_depth *
569 (fifo_width[idx2] >> 8);
570 dev->capture_dma_data.dt.maxburst = 16;
571 }
572
573 return 0;
574
575 }
576
577 static int dw_i2s_probe(struct platform_device *pdev)
578 {
579 const struct i2s_platform_data *pdata = pdev->dev.platform_data;
580 struct dw_i2s_dev *dev;
581 struct resource *res;
582 int ret;
583 struct snd_soc_dai_driver *dw_i2s_dai;
584 const char *clk_id;
585
586 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
587 if (!dev) {
588 dev_warn(&pdev->dev, "kzalloc fail\n");
589 return -ENOMEM;
590 }
591
592 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
593 if (!dw_i2s_dai)
594 return -ENOMEM;
595
596 dw_i2s_dai->ops = &dw_i2s_dai_ops;
597 dw_i2s_dai->suspend = dw_i2s_suspend;
598 dw_i2s_dai->resume = dw_i2s_resume;
599
600 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
601 dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
602 if (IS_ERR(dev->i2s_base))
603 return PTR_ERR(dev->i2s_base);
604
605 dev->dev = &pdev->dev;
606
607 if (pdata) {
608 dev->capability = pdata->cap;
609 clk_id = NULL;
610 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
611 } else {
612 clk_id = "i2sclk";
613 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
614 }
615 if (ret < 0)
616 return ret;
617
618 if (dev->capability & DW_I2S_MASTER) {
619 if (pdata) {
620 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
621 if (!dev->i2s_clk_cfg) {
622 dev_err(&pdev->dev, "no clock configure method\n");
623 return -ENODEV;
624 }
625 }
626 dev->clk = devm_clk_get(&pdev->dev, clk_id);
627
628 if (IS_ERR(dev->clk))
629 return PTR_ERR(dev->clk);
630
631 ret = clk_prepare_enable(dev->clk);
632 if (ret < 0)
633 return ret;
634 }
635
636 dev_set_drvdata(&pdev->dev, dev);
637 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
638 dw_i2s_dai, 1);
639 if (ret != 0) {
640 dev_err(&pdev->dev, "not able to register dai\n");
641 goto err_clk_disable;
642 }
643
644 if (!pdata) {
645 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
646 if (ret) {
647 dev_err(&pdev->dev,
648 "Could not register PCM: %d\n", ret);
649 goto err_clk_disable;
650 }
651 }
652
653 return 0;
654
655 err_clk_disable:
656 if (dev->capability & DW_I2S_MASTER)
657 clk_disable_unprepare(dev->clk);
658 return ret;
659 }
660
661 static int dw_i2s_remove(struct platform_device *pdev)
662 {
663 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
664
665 if (dev->capability & DW_I2S_MASTER)
666 clk_disable_unprepare(dev->clk);
667
668 return 0;
669 }
670
671 #ifdef CONFIG_OF
672 static const struct of_device_id dw_i2s_of_match[] = {
673 { .compatible = "snps,designware-i2s", },
674 {},
675 };
676
677 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
678 #endif
679
680 static struct platform_driver dw_i2s_driver = {
681 .probe = dw_i2s_probe,
682 .remove = dw_i2s_remove,
683 .driver = {
684 .name = "designware-i2s",
685 .of_match_table = of_match_ptr(dw_i2s_of_match),
686 },
687 };
688
689 module_platform_driver(dw_i2s_driver);
690
691 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
692 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
693 MODULE_LICENSE("GPL");
694 MODULE_ALIAS("platform:designware_i2s");
Linux with added FPC-III support