virt/kvm/arm/vgic-v2.c

   1 /*
   2  * Copyright (C) 2012,2013 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/kvm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/irqchip/arm-gic.h>
  28
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_arm.h>
  31 #include <asm/kvm_mmu.h>
  32
  33 static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
  34 {
  35         struct vgic_lr lr_desc;
  36         u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];
  37
  38         lr_desc.irq     = val & GICH_LR_VIRTUALID;
  39         if (lr_desc.irq <= 15)
  40                 lr_desc.source  = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
  41         else
  42                 lr_desc.source = 0;
  43         lr_desc.state   = 0;
  44
  45         if (val & GICH_LR_PENDING_BIT)
  46                 lr_desc.state |= LR_STATE_PENDING;
  47         if (val & GICH_LR_ACTIVE_BIT)
  48                 lr_desc.state |= LR_STATE_ACTIVE;
  49         if (val & GICH_LR_EOI)
  50                 lr_desc.state |= LR_EOI_INT;
  51         if (val & GICH_LR_HW) {
  52                 lr_desc.state |= LR_HW;
  53                 lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;
  54         }
  55
  56         return lr_desc;
  57 }
  58
  59 static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
  60                            struct vgic_lr lr_desc)
  61 {
  62         u32 lr_val;
  63
  64         lr_val = lr_desc.irq;
  65
  66         if (lr_desc.state & LR_STATE_PENDING)
  67                 lr_val |= GICH_LR_PENDING_BIT;
  68         if (lr_desc.state & LR_STATE_ACTIVE)
  69                 lr_val |= GICH_LR_ACTIVE_BIT;
  70         if (lr_desc.state & LR_EOI_INT)
  71                 lr_val |= GICH_LR_EOI;
  72
  73         if (lr_desc.state & LR_HW) {
  74                 lr_val |= GICH_LR_HW;
  75                 lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;
  76         }
  77
  78         if (lr_desc.irq < VGIC_NR_SGIS)
  79                 lr_val |= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);
  80
  81         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
  82
  83         if (!(lr_desc.state & LR_STATE_MASK))
  84                 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr |= (1ULL << lr);
  85         else
  86                 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr &= ~(1ULL << lr);
  87 }
  88
  89 static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
  90 {
  91         return vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
  92 }
  93
  94 static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
  95 {
  96         return vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
  97 }
  98
  99 static void vgic_v2_clear_eisr(struct kvm_vcpu *vcpu)
 100 {
 101         vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr = 0;
 102 }
 103
 104 static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu)
 105 {
 106         u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr;
 107         u32 ret = 0;
 108
 109         if (misr & GICH_MISR_EOI)
 110                 ret |= INT_STATUS_EOI;
 111         if (misr & GICH_MISR_U)
 112                 ret |= INT_STATUS_UNDERFLOW;
 113
 114         return ret;
 115 }
 116
 117 static void vgic_v2_enable_underflow(struct kvm_vcpu *vcpu)
 118 {
 119         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr |= GICH_HCR_UIE;
 120 }
 121
 122 static void vgic_v2_disable_underflow(struct kvm_vcpu *vcpu)
 123 {
 124         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
 125 }
 126
 127 static void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 128 {
 129         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
 130
 131         vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >> GICH_VMCR_CTRL_SHIFT;
 132         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 133         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >> GICH_VMCR_BINPOINT_SHIFT;
 134         vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >> GICH_VMCR_PRIMASK_SHIFT;
 135 }
 136
 137 static void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 138 {
 139         u32 vmcr;
 140
 141         vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
 142         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & GICH_VMCR_ALIAS_BINPOINT_MASK;
 143         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & GICH_VMCR_BINPOINT_MASK;
 144         vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 145
 146         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
 147 }
 148
 149 static void vgic_v2_enable(struct kvm_vcpu *vcpu)
 150 {
 151         /*
 152          * By forcing VMCR to zero, the GIC will restore the binary
 153          * points to their reset values. Anything else resets to zero
 154          * anyway.
 155          */
 156         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 157         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 158
 159         /* Get the show on the road... */
 160         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 161 }
 162
 163 static const struct vgic_ops vgic_v2_ops = {
 164         .get_lr                 = vgic_v2_get_lr,
 165         .set_lr                 = vgic_v2_set_lr,
 166         .get_elrsr              = vgic_v2_get_elrsr,
 167         .get_eisr               = vgic_v2_get_eisr,
 168         .clear_eisr             = vgic_v2_clear_eisr,
 169         .get_interrupt_status   = vgic_v2_get_interrupt_status,
 170         .enable_underflow       = vgic_v2_enable_underflow,
 171         .disable_underflow      = vgic_v2_disable_underflow,
 172         .get_vmcr               = vgic_v2_get_vmcr,
 173         .set_vmcr               = vgic_v2_set_vmcr,
 174         .enable                 = vgic_v2_enable,
 175 };
 176
 177 static struct vgic_params vgic_v2_params;
 178
 179 /**
 180  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 181  * @node:       pointer to the DT node
 182  * @ops:        address of a pointer to the GICv2 operations
 183  * @params:     address of a pointer to HW-specific parameters
 184  *
 185  * Returns 0 if a GICv2 has been found, with the low level operations
 186  * in *ops and the HW parameters in *params. Returns an error code
 187  * otherwise.
 188  */
 189 int vgic_v2_probe(struct device_node *vgic_node,
 190                   const struct vgic_ops **ops,
 191                   const struct vgic_params **params)
 192 {
 193         int ret;
 194         struct resource vctrl_res;
 195         struct resource vcpu_res;
 196         struct vgic_params *vgic = &vgic_v2_params;
 197
 198         vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
 199         if (!vgic->maint_irq) {
 200                 kvm_err("error getting vgic maintenance irq from DT\n");
 201                 ret = -ENXIO;
 202                 goto out;
 203         }
 204
 205         ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
 206         if (ret) {
 207                 kvm_err("Cannot obtain GICH resource\n");
 208                 goto out;
 209         }
 210
 211         vgic->vctrl_base = of_iomap(vgic_node, 2);
 212         if (!vgic->vctrl_base) {
 213                 kvm_err("Cannot ioremap GICH\n");
 214                 ret = -ENOMEM;
 215                 goto out;
 216         }
 217
 218         vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR);
 219         vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1;
 220
 221         ret = create_hyp_io_mappings(vgic->vctrl_base,
 222                                      vgic->vctrl_base + resource_size(&vctrl_res),
 223                                      vctrl_res.start);
 224         if (ret) {
 225                 kvm_err("Cannot map VCTRL into hyp\n");
 226                 goto out_unmap;
 227         }
 228
 229         if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
 230                 kvm_err("Cannot obtain GICV resource\n");
 231                 ret = -ENXIO;
 232                 goto out_unmap;
 233         }
 234
 235         if (!PAGE_ALIGNED(vcpu_res.start)) {
 236                 kvm_err("GICV physical address 0x%llx not page aligned\n",
 237                         (unsigned long long)vcpu_res.start);
 238                 ret = -ENXIO;
 239                 goto out_unmap;
 240         }
 241
 242         if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
 243                 kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 244                         (unsigned long long)resource_size(&vcpu_res),
 245                         PAGE_SIZE);
 246                 ret = -ENXIO;
 247                 goto out_unmap;
 248         }
 249
 250         vgic->can_emulate_gicv2 = true;
 251         kvm_register_device_ops(&kvm_arm_vgic_v2_ops, KVM_DEV_TYPE_ARM_VGIC_V2);
 252
 253         vgic->vcpu_base = vcpu_res.start;
 254
 255         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
 256                  vctrl_res.start, vgic->maint_irq);
 257
 258         vgic->type = VGIC_V2;
 259         vgic->max_gic_vcpus = VGIC_V2_MAX_CPUS;
 260         *ops = &vgic_v2_ops;
 261         *params = vgic;
 262         goto out;
 263
 264 out_unmap:
 265         iounmap(vgic->vctrl_base);
 266 out:
 267         of_node_put(vgic_node);
 268         return ret;
 269 }