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vmalloc: fix __GFP_HIGHMEM usage for vmalloc_32 on 32b systems
[linux/fpc-iii.git] / include / video / omapfb_dss.h
blob1d38901d599d37f5a174c17d25416d8ca706bb8e
1 /*
2 * Copyright (C) 2016 Texas Instruments, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #ifndef __OMAPFB_DSS_H
11 #define __OMAPFB_DSS_H
12
13 #include <linux/list.h>
14 #include <linux/kobject.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_data/omapdss.h>
18
19 #include <video/videomode.h>
20
21 #define DISPC_IRQ_FRAMEDONE (1 << 0)
22 #define DISPC_IRQ_VSYNC (1 << 1)
23 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
24 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
25 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
26 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
27 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
28 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
29 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
30 #define DISPC_IRQ_OCP_ERR (1 << 9)
31 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
32 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
33 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
34 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
35 #define DISPC_IRQ_SYNC_LOST (1 << 14)
36 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
37 #define DISPC_IRQ_WAKEUP (1 << 16)
38 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
39 #define DISPC_IRQ_VSYNC2 (1 << 18)
40 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
41 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
42 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
43 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
44 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
45 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
46 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
47 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
48 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
49 #define DISPC_IRQ_VSYNC3 (1 << 28)
50 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
51 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
52
53 struct omap_dss_device;
54 struct omap_overlay_manager;
55 struct dss_lcd_mgr_config;
56 struct snd_aes_iec958;
57 struct snd_cea_861_aud_if;
58 struct hdmi_avi_infoframe;
59
60 enum omap_display_type {
61 OMAP_DISPLAY_TYPE_NONE = 0,
62 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
63 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
64 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
65 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
66 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
67 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
68 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
69 };
70
71 enum omap_plane {
72 OMAP_DSS_GFX = 0,
73 OMAP_DSS_VIDEO1 = 1,
74 OMAP_DSS_VIDEO2 = 2,
75 OMAP_DSS_VIDEO3 = 3,
76 OMAP_DSS_WB = 4,
77 };
78
79 enum omap_channel {
80 OMAP_DSS_CHANNEL_LCD = 0,
81 OMAP_DSS_CHANNEL_DIGIT = 1,
82 OMAP_DSS_CHANNEL_LCD2 = 2,
83 OMAP_DSS_CHANNEL_LCD3 = 3,
84 OMAP_DSS_CHANNEL_WB = 4,
85 };
86
87 enum omap_color_mode {
88 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
89 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
90 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
91 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
92 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
93 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
94 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
95 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
96 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
97 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
98 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
99 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
100 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
101 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
102 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
103 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
104 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
105 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
106 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
107 };
108
109 enum omap_dss_load_mode {
110 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
111 OMAP_DSS_LOAD_CLUT_ONLY = 1,
112 OMAP_DSS_LOAD_FRAME_ONLY = 2,
113 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
114 };
115
116 enum omap_dss_trans_key_type {
117 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
118 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
119 };
120
121 enum omap_rfbi_te_mode {
122 OMAP_DSS_RFBI_TE_MODE_1 = 1,
123 OMAP_DSS_RFBI_TE_MODE_2 = 2,
124 };
125
126 enum omap_dss_signal_level {
127 OMAPDSS_SIG_ACTIVE_LOW,
128 OMAPDSS_SIG_ACTIVE_HIGH,
129 };
130
131 enum omap_dss_signal_edge {
132 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
133 OMAPDSS_DRIVE_SIG_RISING_EDGE,
134 };
135
136 enum omap_dss_venc_type {
137 OMAP_DSS_VENC_TYPE_COMPOSITE,
138 OMAP_DSS_VENC_TYPE_SVIDEO,
139 };
140
141 enum omap_dss_dsi_pixel_format {
142 OMAP_DSS_DSI_FMT_RGB888,
143 OMAP_DSS_DSI_FMT_RGB666,
144 OMAP_DSS_DSI_FMT_RGB666_PACKED,
145 OMAP_DSS_DSI_FMT_RGB565,
146 };
147
148 enum omap_dss_dsi_mode {
149 OMAP_DSS_DSI_CMD_MODE = 0,
150 OMAP_DSS_DSI_VIDEO_MODE,
151 };
152
153 enum omap_display_caps {
154 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
155 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
156 };
157
158 enum omap_dss_display_state {
159 OMAP_DSS_DISPLAY_DISABLED = 0,
160 OMAP_DSS_DISPLAY_ACTIVE,
161 };
162
163 enum omap_dss_rotation_type {
164 OMAP_DSS_ROT_DMA = 1 << 0,
165 OMAP_DSS_ROT_VRFB = 1 << 1,
166 OMAP_DSS_ROT_TILER = 1 << 2,
167 };
168
169 /* clockwise rotation angle */
170 enum omap_dss_rotation_angle {
171 OMAP_DSS_ROT_0 = 0,
172 OMAP_DSS_ROT_90 = 1,
173 OMAP_DSS_ROT_180 = 2,
174 OMAP_DSS_ROT_270 = 3,
175 };
176
177 enum omap_overlay_caps {
178 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
179 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
180 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
181 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
182 OMAP_DSS_OVL_CAP_POS = 1 << 4,
183 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
184 };
185
186 enum omap_dss_output_id {
187 OMAP_DSS_OUTPUT_DPI = 1 << 0,
188 OMAP_DSS_OUTPUT_DBI = 1 << 1,
189 OMAP_DSS_OUTPUT_SDI = 1 << 2,
190 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
191 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
192 OMAP_DSS_OUTPUT_VENC = 1 << 5,
193 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
194 };
195
196 /* RFBI */
197
198 struct rfbi_timings {
199 int cs_on_time;
200 int cs_off_time;
201 int we_on_time;
202 int we_off_time;
203 int re_on_time;
204 int re_off_time;
205 int we_cycle_time;
206 int re_cycle_time;
207 int cs_pulse_width;
208 int access_time;
209
210 int clk_div;
211
212 u32 tim[5]; /* set by rfbi_convert_timings() */
213
214 int converted;
215 };
216
217 /* DSI */
218
219 enum omap_dss_dsi_trans_mode {
220 /* Sync Pulses: both sync start and end packets sent */
221 OMAP_DSS_DSI_PULSE_MODE,
222 /* Sync Events: only sync start packets sent */
223 OMAP_DSS_DSI_EVENT_MODE,
224 /* Burst: only sync start packets sent, pixels are time compressed */
225 OMAP_DSS_DSI_BURST_MODE,
226 };
227
228 struct omap_dss_dsi_videomode_timings {
229 unsigned long hsclk;
230
231 unsigned ndl;
232 unsigned bitspp;
233
234 /* pixels */
235 u16 hact;
236 /* lines */
237 u16 vact;
238
239 /* DSI video mode blanking data */
240 /* Unit: byte clock cycles */
241 u16 hss;
242 u16 hsa;
243 u16 hse;
244 u16 hfp;
245 u16 hbp;
246 /* Unit: line clocks */
247 u16 vsa;
248 u16 vfp;
249 u16 vbp;
250
251 /* DSI blanking modes */
252 int blanking_mode;
253 int hsa_blanking_mode;
254 int hbp_blanking_mode;
255 int hfp_blanking_mode;
256
257 enum omap_dss_dsi_trans_mode trans_mode;
258
259 bool ddr_clk_always_on;
260 int window_sync;
261 };
262
263 struct omap_dss_dsi_config {
264 enum omap_dss_dsi_mode mode;
265 enum omap_dss_dsi_pixel_format pixel_format;
266 const struct omap_video_timings *timings;
267
268 unsigned long hs_clk_min, hs_clk_max;
269 unsigned long lp_clk_min, lp_clk_max;
270
271 bool ddr_clk_always_on;
272 enum omap_dss_dsi_trans_mode trans_mode;
273 };
274
275 struct omap_video_timings {
276 /* Unit: pixels */
277 u16 x_res;
278 /* Unit: pixels */
279 u16 y_res;
280 /* Unit: Hz */
281 u32 pixelclock;
282 /* Unit: pixel clocks */
283 u16 hsw; /* Horizontal synchronization pulse width */
284 /* Unit: pixel clocks */
285 u16 hfp; /* Horizontal front porch */
286 /* Unit: pixel clocks */
287 u16 hbp; /* Horizontal back porch */
288 /* Unit: line clocks */
289 u16 vsw; /* Vertical synchronization pulse width */
290 /* Unit: line clocks */
291 u16 vfp; /* Vertical front porch */
292 /* Unit: line clocks */
293 u16 vbp; /* Vertical back porch */
294
295 /* Vsync logic level */
296 enum omap_dss_signal_level vsync_level;
297 /* Hsync logic level */
298 enum omap_dss_signal_level hsync_level;
299 /* Interlaced or Progressive timings */
300 bool interlace;
301 /* Pixel clock edge to drive LCD data */
302 enum omap_dss_signal_edge data_pclk_edge;
303 /* Data enable logic level */
304 enum omap_dss_signal_level de_level;
305 /* Pixel clock edges to drive HSYNC and VSYNC signals */
306 enum omap_dss_signal_edge sync_pclk_edge;
307
308 bool double_pixel;
309 };
310
311 /* Hardcoded timings for tv modes. Venc only uses these to
312 * identify the mode, and does not actually use the configs
313 * itself. However, the configs should be something that
314 * a normal monitor can also show */
315 extern const struct omap_video_timings omap_dss_pal_timings;
316 extern const struct omap_video_timings omap_dss_ntsc_timings;
317
318 struct omap_dss_cpr_coefs {
319 s16 rr, rg, rb;
320 s16 gr, gg, gb;
321 s16 br, bg, bb;
322 };
323
324 struct omap_overlay_info {
325 dma_addr_t paddr;
326 dma_addr_t p_uv_addr; /* for NV12 format */
327 u16 screen_width;
328 u16 width;
329 u16 height;
330 enum omap_color_mode color_mode;
331 u8 rotation;
332 enum omap_dss_rotation_type rotation_type;
333 bool mirror;
334
335 u16 pos_x;
336 u16 pos_y;
337 u16 out_width; /* if 0, out_width == width */
338 u16 out_height; /* if 0, out_height == height */
339 u8 global_alpha;
340 u8 pre_mult_alpha;
341 u8 zorder;
342 };
343
344 struct omap_overlay {
345 struct kobject kobj;
346 struct list_head list;
347
348 /* static fields */
349 const char *name;
350 enum omap_plane id;
351 enum omap_color_mode supported_modes;
352 enum omap_overlay_caps caps;
353
354 /* dynamic fields */
355 struct omap_overlay_manager *manager;
356
357 /*
358 * The following functions do not block:
359 *
360 * is_enabled
361 * set_overlay_info
362 * get_overlay_info
363 *
364 * The rest of the functions may block and cannot be called from
365 * interrupt context
366 */
367
368 int (*enable)(struct omap_overlay *ovl);
369 int (*disable)(struct omap_overlay *ovl);
370 bool (*is_enabled)(struct omap_overlay *ovl);
371
372 int (*set_manager)(struct omap_overlay *ovl,
373 struct omap_overlay_manager *mgr);
374 int (*unset_manager)(struct omap_overlay *ovl);
375
376 int (*set_overlay_info)(struct omap_overlay *ovl,
377 struct omap_overlay_info *info);
378 void (*get_overlay_info)(struct omap_overlay *ovl,
379 struct omap_overlay_info *info);
380
381 int (*wait_for_go)(struct omap_overlay *ovl);
382
383 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
384 };
385
386 struct omap_overlay_manager_info {
387 u32 default_color;
388
389 enum omap_dss_trans_key_type trans_key_type;
390 u32 trans_key;
391 bool trans_enabled;
392
393 bool partial_alpha_enabled;
394
395 bool cpr_enable;
396 struct omap_dss_cpr_coefs cpr_coefs;
397 };
398
399 struct omap_overlay_manager {
400 struct kobject kobj;
401
402 /* static fields */
403 const char *name;
404 enum omap_channel id;
405 struct list_head overlays;
406 enum omap_display_type supported_displays;
407 enum omap_dss_output_id supported_outputs;
408
409 /* dynamic fields */
410 struct omap_dss_device *output;
411
412 /*
413 * The following functions do not block:
414 *
415 * set_manager_info
416 * get_manager_info
417 * apply
418 *
419 * The rest of the functions may block and cannot be called from
420 * interrupt context
421 */
422
423 int (*set_output)(struct omap_overlay_manager *mgr,
424 struct omap_dss_device *output);
425 int (*unset_output)(struct omap_overlay_manager *mgr);
426
427 int (*set_manager_info)(struct omap_overlay_manager *mgr,
428 struct omap_overlay_manager_info *info);
429 void (*get_manager_info)(struct omap_overlay_manager *mgr,
430 struct omap_overlay_manager_info *info);
431
432 int (*apply)(struct omap_overlay_manager *mgr);
433 int (*wait_for_go)(struct omap_overlay_manager *mgr);
434 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
435
436 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
437 };
438
439 /* 22 pins means 1 clk lane and 10 data lanes */
440 #define OMAP_DSS_MAX_DSI_PINS 22
441
442 struct omap_dsi_pin_config {
443 int num_pins;
444 /*
445 * pin numbers in the following order:
446 * clk+, clk-
447 * data1+, data1-
448 * data2+, data2-
449 * ...
450 */
451 int pins[OMAP_DSS_MAX_DSI_PINS];
452 };
453
454 struct omap_dss_writeback_info {
455 u32 paddr;
456 u32 p_uv_addr;
457 u16 buf_width;
458 u16 width;
459 u16 height;
460 enum omap_color_mode color_mode;
461 u8 rotation;
462 enum omap_dss_rotation_type rotation_type;
463 bool mirror;
464 u8 pre_mult_alpha;
465 };
466
467 struct omapdss_dpi_ops {
468 int (*connect)(struct omap_dss_device *dssdev,
469 struct omap_dss_device *dst);
470 void (*disconnect)(struct omap_dss_device *dssdev,
471 struct omap_dss_device *dst);
472
473 int (*enable)(struct omap_dss_device *dssdev);
474 void (*disable)(struct omap_dss_device *dssdev);
475
476 int (*check_timings)(struct omap_dss_device *dssdev,
477 struct omap_video_timings *timings);
478 void (*set_timings)(struct omap_dss_device *dssdev,
479 struct omap_video_timings *timings);
480 void (*get_timings)(struct omap_dss_device *dssdev,
481 struct omap_video_timings *timings);
482
483 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
484 };
485
486 struct omapdss_sdi_ops {
487 int (*connect)(struct omap_dss_device *dssdev,
488 struct omap_dss_device *dst);
489 void (*disconnect)(struct omap_dss_device *dssdev,
490 struct omap_dss_device *dst);
491
492 int (*enable)(struct omap_dss_device *dssdev);
493 void (*disable)(struct omap_dss_device *dssdev);
494
495 int (*check_timings)(struct omap_dss_device *dssdev,
496 struct omap_video_timings *timings);
497 void (*set_timings)(struct omap_dss_device *dssdev,
498 struct omap_video_timings *timings);
499 void (*get_timings)(struct omap_dss_device *dssdev,
500 struct omap_video_timings *timings);
501
502 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
503 };
504
505 struct omapdss_dvi_ops {
506 int (*connect)(struct omap_dss_device *dssdev,
507 struct omap_dss_device *dst);
508 void (*disconnect)(struct omap_dss_device *dssdev,
509 struct omap_dss_device *dst);
510
511 int (*enable)(struct omap_dss_device *dssdev);
512 void (*disable)(struct omap_dss_device *dssdev);
513
514 int (*check_timings)(struct omap_dss_device *dssdev,
515 struct omap_video_timings *timings);
516 void (*set_timings)(struct omap_dss_device *dssdev,
517 struct omap_video_timings *timings);
518 void (*get_timings)(struct omap_dss_device *dssdev,
519 struct omap_video_timings *timings);
520 };
521
522 struct omapdss_atv_ops {
523 int (*connect)(struct omap_dss_device *dssdev,
524 struct omap_dss_device *dst);
525 void (*disconnect)(struct omap_dss_device *dssdev,
526 struct omap_dss_device *dst);
527
528 int (*enable)(struct omap_dss_device *dssdev);
529 void (*disable)(struct omap_dss_device *dssdev);
530
531 int (*check_timings)(struct omap_dss_device *dssdev,
532 struct omap_video_timings *timings);
533 void (*set_timings)(struct omap_dss_device *dssdev,
534 struct omap_video_timings *timings);
535 void (*get_timings)(struct omap_dss_device *dssdev,
536 struct omap_video_timings *timings);
537
538 void (*set_type)(struct omap_dss_device *dssdev,
539 enum omap_dss_venc_type type);
540 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
541 bool invert_polarity);
542
543 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
544 u32 (*get_wss)(struct omap_dss_device *dssdev);
545 };
546
547 struct omapdss_hdmi_ops {
548 int (*connect)(struct omap_dss_device *dssdev,
549 struct omap_dss_device *dst);
550 void (*disconnect)(struct omap_dss_device *dssdev,
551 struct omap_dss_device *dst);
552
553 int (*enable)(struct omap_dss_device *dssdev);
554 void (*disable)(struct omap_dss_device *dssdev);
555
556 int (*check_timings)(struct omap_dss_device *dssdev,
557 struct omap_video_timings *timings);
558 void (*set_timings)(struct omap_dss_device *dssdev,
559 struct omap_video_timings *timings);
560 void (*get_timings)(struct omap_dss_device *dssdev,
561 struct omap_video_timings *timings);
562
563 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
564 bool (*detect)(struct omap_dss_device *dssdev);
565
566 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
567 int (*set_infoframe)(struct omap_dss_device *dssdev,
568 const struct hdmi_avi_infoframe *avi);
569 };
570
571 struct omapdss_dsi_ops {
572 int (*connect)(struct omap_dss_device *dssdev,
573 struct omap_dss_device *dst);
574 void (*disconnect)(struct omap_dss_device *dssdev,
575 struct omap_dss_device *dst);
576
577 int (*enable)(struct omap_dss_device *dssdev);
578 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
579 bool enter_ulps);
580
581 /* bus configuration */
582 int (*set_config)(struct omap_dss_device *dssdev,
583 const struct omap_dss_dsi_config *cfg);
584 int (*configure_pins)(struct omap_dss_device *dssdev,
585 const struct omap_dsi_pin_config *pin_cfg);
586
587 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
588 bool enable);
589 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
590
591 int (*update)(struct omap_dss_device *dssdev, int channel,
592 void (*callback)(int, void *), void *data);
593
594 void (*bus_lock)(struct omap_dss_device *dssdev);
595 void (*bus_unlock)(struct omap_dss_device *dssdev);
596
597 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
598 void (*disable_video_output)(struct omap_dss_device *dssdev,
599 int channel);
600
601 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
602 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
603 int vc_id);
604 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
605
606 /* data transfer */
607 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
608 u8 *data, int len);
609 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
610 u8 *data, int len);
611 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
612 u8 *data, int len);
613
614 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
615 u8 *data, int len);
616 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
617 u8 *data, int len);
618 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
619 u8 *reqdata, int reqlen,
620 u8 *data, int len);
621
622 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
623
624 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
625 int channel, u16 plen);
626 };
627
628 struct omap_dss_device {
629 struct kobject kobj;
630 struct device *dev;
631
632 struct module *owner;
633
634 struct list_head panel_list;
635
636 /* alias in the form of "display%d" */
637 char alias[16];
638
639 enum omap_display_type type;
640 enum omap_display_type output_type;
641
642 union {
643 struct {
644 u8 data_lines;
645 } dpi;
646
647 struct {
648 u8 channel;
649 u8 data_lines;
650 } rfbi;
651
652 struct {
653 u8 datapairs;
654 } sdi;
655
656 struct {
657 int module;
658 } dsi;
659
660 struct {
661 enum omap_dss_venc_type type;
662 bool invert_polarity;
663 } venc;
664 } phy;
665
666 struct {
667 struct omap_video_timings timings;
668
669 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
670 enum omap_dss_dsi_mode dsi_mode;
671 } panel;
672
673 struct {
674 u8 pixel_size;
675 struct rfbi_timings rfbi_timings;
676 } ctrl;
677
678 const char *name;
679
680 /* used to match device to driver */
681 const char *driver_name;
682
683 void *data;
684
685 struct omap_dss_driver *driver;
686
687 union {
688 const struct omapdss_dpi_ops *dpi;
689 const struct omapdss_sdi_ops *sdi;
690 const struct omapdss_dvi_ops *dvi;
691 const struct omapdss_hdmi_ops *hdmi;
692 const struct omapdss_atv_ops *atv;
693 const struct omapdss_dsi_ops *dsi;
694 } ops;
695
696 /* helper variable for driver suspend/resume */
697 bool activate_after_resume;
698
699 enum omap_display_caps caps;
700
701 struct omap_dss_device *src;
702
703 enum omap_dss_display_state state;
704
705 /* OMAP DSS output specific fields */
706
707 struct list_head list;
708
709 /* DISPC channel for this output */
710 enum omap_channel dispc_channel;
711 bool dispc_channel_connected;
712
713 /* output instance */
714 enum omap_dss_output_id id;
715
716 /* the port number in the DT node */
717 int port_num;
718
719 /* dynamic fields */
720 struct omap_overlay_manager *manager;
721
722 struct omap_dss_device *dst;
723 };
724
725 struct omap_dss_driver {
726 int (*probe)(struct omap_dss_device *);
727 void (*remove)(struct omap_dss_device *);
728
729 int (*connect)(struct omap_dss_device *dssdev);
730 void (*disconnect)(struct omap_dss_device *dssdev);
731
732 int (*enable)(struct omap_dss_device *display);
733 void (*disable)(struct omap_dss_device *display);
734 int (*run_test)(struct omap_dss_device *display, int test);
735
736 int (*update)(struct omap_dss_device *dssdev,
737 u16 x, u16 y, u16 w, u16 h);
738 int (*sync)(struct omap_dss_device *dssdev);
739
740 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
741 int (*get_te)(struct omap_dss_device *dssdev);
742
743 u8 (*get_rotate)(struct omap_dss_device *dssdev);
744 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
745
746 bool (*get_mirror)(struct omap_dss_device *dssdev);
747 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
748
749 int (*memory_read)(struct omap_dss_device *dssdev,
750 void *buf, size_t size,
751 u16 x, u16 y, u16 w, u16 h);
752
753 void (*get_resolution)(struct omap_dss_device *dssdev,
754 u16 *xres, u16 *yres);
755 void (*get_dimensions)(struct omap_dss_device *dssdev,
756 u32 *width, u32 *height);
757 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
758
759 int (*check_timings)(struct omap_dss_device *dssdev,
760 struct omap_video_timings *timings);
761 void (*set_timings)(struct omap_dss_device *dssdev,
762 struct omap_video_timings *timings);
763 void (*get_timings)(struct omap_dss_device *dssdev,
764 struct omap_video_timings *timings);
765
766 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
767 u32 (*get_wss)(struct omap_dss_device *dssdev);
768
769 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
770 bool (*detect)(struct omap_dss_device *dssdev);
771
772 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
773 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
774 const struct hdmi_avi_infoframe *avi);
775 };
776
777 enum omapdss_version omapdss_get_version(void);
778 bool omapdss_is_initialized(void);
779
780 int omap_dss_register_driver(struct omap_dss_driver *);
781 void omap_dss_unregister_driver(struct omap_dss_driver *);
782
783 int omapdss_register_display(struct omap_dss_device *dssdev);
784 void omapdss_unregister_display(struct omap_dss_device *dssdev);
785
786 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
787 void omap_dss_put_device(struct omap_dss_device *dssdev);
788 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
789 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
790 struct omap_dss_device *omap_dss_find_device(void *data,
791 int (*match)(struct omap_dss_device *dssdev, void *data));
792 const char *omapdss_get_default_display_name(void);
793
794 void videomode_to_omap_video_timings(const struct videomode *vm,
795 struct omap_video_timings *ovt);
796 void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
797 struct videomode *vm);
798
799 int dss_feat_get_num_mgrs(void);
800 int dss_feat_get_num_ovls(void);
801 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
802
803
804
805 int omap_dss_get_num_overlay_managers(void);
806 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
807
808 int omap_dss_get_num_overlays(void);
809 struct omap_overlay *omap_dss_get_overlay(int num);
810
811 int omapdss_register_output(struct omap_dss_device *output);
812 void omapdss_unregister_output(struct omap_dss_device *output);
813 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
814 struct omap_dss_device *omap_dss_find_output(const char *name);
815 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
816 int omapdss_output_set_device(struct omap_dss_device *out,
817 struct omap_dss_device *dssdev);
818 int omapdss_output_unset_device(struct omap_dss_device *out);
819
820 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
821 struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
822
823 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
824 u16 *xres, u16 *yres);
825 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
826 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
827 struct omap_video_timings *timings);
828
829 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
830 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
831 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
832
833 int omapdss_compat_init(void);
834 void omapdss_compat_uninit(void);
835
836 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
837 {
838 return dssdev->src;
839 }
840
841 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
842 {
843 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
844 }
845
846 struct device_node *
847 omapdss_of_get_next_port(const struct device_node *parent,
848 struct device_node *prev);
849
850 struct device_node *
851 omapdss_of_get_next_endpoint(const struct device_node *parent,
852 struct device_node *prev);
853
854 struct device_node *
855 omapdss_of_get_first_endpoint(const struct device_node *parent);
856
857 struct omap_dss_device *
858 omapdss_of_find_source_for_first_ep(struct device_node *node);
859
860 #endif /* __OMAPFB_DSS_H */
Linux with added FPC-III support