include/video/sstfb.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
   4  *
   5  *     Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr>
   6  *
   7  *     Created 28 Aug 2001 by Ghozlane Toumi
   8  */
   9
  10
  11 #ifndef _SSTFB_H_
  12 #define _SSTFB_H_
  13
  14 /*
  15  *
  16  *  Debug Stuff
  17  *
  18  */
  19
  20 #ifdef SST_DEBUG
  21 #  define dprintk(X...)         printk("sstfb: " X)
  22 #  define SST_DEBUG_REG  1
  23 #  define SST_DEBUG_FUNC 1
  24 #  define SST_DEBUG_VAR  1
  25 #else
  26 #  define dprintk(X...)
  27 #  define SST_DEBUG_REG  0
  28 #  define SST_DEBUG_FUNC 0
  29 #  define SST_DEBUG_VAR  0
  30 #endif
  31
  32 #if (SST_DEBUG_REG > 0)
  33 #  define r_dprintk(X...)       dprintk(X)
  34 #else
  35 #  define r_dprintk(X...)
  36 #endif
  37 #if (SST_DEBUG_REG > 1)
  38 #  define r_ddprintk(X...)      dprintk(" " X)
  39 #else
  40 #  define r_ddprintk(X...)
  41 #endif
  42
  43 #if (SST_DEBUG_FUNC > 0)
  44 #  define f_dprintk(X...)       dprintk(X)
  45 #else
  46 #  define f_dprintk(X...)
  47 #endif
  48 #if (SST_DEBUG_FUNC > 1)
  49 #  define f_ddprintk(X...)      dprintk(" " X)
  50 #else
  51 #  define f_ddprintk(X...)
  52 #endif
  53 #if (SST_DEBUG_FUNC > 2)
  54 #  define f_dddprintk(X...)     dprintk(" " X)
  55 #else
  56 #  define f_dddprintk(X...)
  57 #endif
  58
  59 #if (SST_DEBUG_VAR > 0)
  60 #  define v_dprintk(X...)       dprintk(X)
  61 #  define print_var(V, X...)    \
  62    {                            \
  63      dprintk(X);                \
  64      printk(" :\n");            \
  65      sst_dbg_print_var(V);      \
  66    }
  67 #else
  68 #  define v_dprintk(X...)
  69 #  define print_var(X,Y...)
  70 #endif
  71
  72 #define POW2(x)         (1ul<<(x))
  73
  74 /*
  75  *
  76  *  Const
  77  *
  78  */
  79
  80 /* pci stuff */
  81 #define PCI_INIT_ENABLE         0x40
  82 #  define PCI_EN_INIT_WR          BIT(0)
  83 #  define PCI_EN_FIFO_WR          BIT(1)
  84 #  define PCI_REMAP_DAC           BIT(2)
  85 #define PCI_VCLK_ENABLE         0xc0    /* enable video */
  86 #define PCI_VCLK_DISABLE        0xe0
  87
  88 /* register offsets from memBaseAddr */
  89 #define STATUS                  0x0000
  90 #  define STATUS_FBI_BUSY         BIT(7)
  91 #define FBZMODE                 0x0110
  92 #  define EN_CLIPPING             BIT(0)        /* enable clipping */
  93 #  define EN_RGB_WRITE            BIT(9)        /* enable writes to rgb area */
  94 #  define EN_ALPHA_WRITE          BIT(10)
  95 #  define ENGINE_INVERT_Y         BIT(17)       /* invert Y origin (pipe) */
  96 #define LFBMODE                 0x0114
  97 #  define LFB_565                 0             /* bits 3:0 .16 bits RGB */
  98 #  define LFB_888                 4             /* 24 bits RGB */
  99 #  define LFB_8888                5             /* 32 bits ARGB */
 100 #  define WR_BUFF_FRONT           0             /* write buf select (front) */
 101 #  define WR_BUFF_BACK            (1 << 4)      /* back */
 102 #  define RD_BUFF_FRONT           0             /* read buff select (front) */
 103 #  define RD_BUFF_BACK            (1 << 6)      /* back */
 104 #  define EN_PXL_PIPELINE         BIT(8)        /* pixel pipeline (clip..)*/
 105 #  define LFB_WORD_SWIZZLE_WR     BIT(11)       /* enable write-wordswap (big-endian) */
 106 #  define LFB_BYTE_SWIZZLE_WR     BIT(12)       /* enable write-byteswap (big-endian) */
 107 #  define LFB_INVERT_Y            BIT(13)       /* invert Y origin (LFB) */
 108 #  define LFB_WORD_SWIZZLE_RD     BIT(15)       /* enable read-wordswap (big-endian) */
 109 #  define LFB_BYTE_SWIZZLE_RD     BIT(16)       /* enable read-byteswap (big-endian) */
 110 #define CLIP_LEFT_RIGHT         0x0118
 111 #define CLIP_LOWY_HIGHY         0x011c
 112 #define NOPCMD                  0x0120
 113 #define FASTFILLCMD             0x0124
 114 #define SWAPBUFFCMD             0x0128
 115 #define FBIINIT4                0x0200          /* misc controls */
 116 #  define FAST_PCI_READS          0             /* 1 waitstate */
 117 #  define SLOW_PCI_READS          BIT(0)        /* 2 ws */
 118 #  define LFB_READ_AHEAD          BIT(1)
 119 #define BACKPORCH               0x0208
 120 #define VIDEODIMENSIONS         0x020c
 121 #define FBIINIT0                0x0210          /* misc+fifo  controls */
 122 #  define DIS_VGA_PASSTHROUGH     BIT(0)
 123 #  define FBI_RESET               BIT(1)
 124 #  define FIFO_RESET              BIT(2)
 125 #define FBIINIT1                0x0214          /* PCI + video controls */
 126 #  define VIDEO_MASK              0x8080010f    /* masks video related bits V1+V2*/
 127 #  define FAST_PCI_WRITES         0             /* 0 ws */
 128 #  define SLOW_PCI_WRITES         BIT(1)        /* 1 ws */
 129 #  define EN_LFB_READ             BIT(3)
 130 #  define TILES_IN_X_SHIFT        4
 131 #  define VIDEO_RESET             BIT(8)
 132 #  define EN_BLANKING             BIT(12)
 133 #  define EN_DATA_OE              BIT(13)
 134 #  define EN_BLANK_OE             BIT(14)
 135 #  define EN_HVSYNC_OE            BIT(15)
 136 #  define EN_DCLK_OE              BIT(16)
 137 #  define SEL_INPUT_VCLK_2X       0             /* bit 17 */
 138 #  define SEL_INPUT_VCLK_SLAVE    BIT(17)
 139 #  define SEL_SOURCE_VCLK_SLAVE   0             /* bits 21:20 */
 140 #  define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20)
 141 #  define SEL_SOURCE_VCLK_2X_SEL  (0x02 << 20)
 142 #  define EN_24BPP                BIT(22)
 143 #  define TILES_IN_X_MSB_SHIFT    24            /* v2 */
 144 #  define VCLK_2X_SEL_DEL_SHIFT   27            /* vclk out delay 0,4,6,8ns */
 145 #  define VCLK_DEL_SHIFT          29            /* vclk in delay */
 146 #define FBIINIT2                0x0218          /* Dram controls */
 147 #  define EN_FAST_RAS_READ        BIT(5)
 148 #  define EN_DRAM_OE              BIT(6)
 149 #  define EN_FAST_RD_AHEAD_WR     BIT(7)
 150 #  define VIDEO_OFFSET_SHIFT      11            /* unit: #rows tile 64x16/2 */
 151 #  define SWAP_DACVSYNC           0
 152 #  define SWAP_DACDATA0           (1 << 9)
 153 #  define SWAP_FIFO_STALL         (2 << 9)
 154 #  define EN_RD_AHEAD_FIFO        BIT(21)
 155 #  define EN_DRAM_REFRESH         BIT(22)
 156 #  define DRAM_REFRESH_16         (0x30 << 23)  /* dram 16 ms */
 157 #define DAC_READ                FBIINIT2        /* in remap mode */
 158 #define FBIINIT3                0x021c          /* fbi controls */
 159 #  define DISABLE_TEXTURE         BIT(6)
 160 #  define Y_SWAP_ORIGIN_SHIFT     22            /* Y swap subtraction value */
 161 #define HSYNC                   0x0220
 162 #define VSYNC                   0x0224
 163 #define DAC_DATA                0x022c
 164 #  define DAC_READ_CMD            BIT(11)       /* set read dacreg mode */
 165 #define FBIINIT5                0x0244          /* v2 specific */
 166 #  define FBIINIT5_MASK           0xfa40ffff    /* mask video bits*/
 167 #  define HDOUBLESCAN             BIT(20)
 168 #  define VDOUBLESCAN             BIT(21)
 169 #  define HSYNC_HIGH              BIT(23)
 170 #  define VSYNC_HIGH              BIT(24)
 171 #  define INTERLACE               BIT(26)
 172 #define FBIINIT6                0x0248          /* v2 specific */
 173 #  define TILES_IN_X_LSB_SHIFT    30            /* v2 */
 174 #define FBIINIT7                0x024c          /* v2 specific */
 175
 176 #define BLTSRCBASEADDR          0x02c0  /* BitBLT Source base address */
 177 #define BLTDSTBASEADDR          0x02c4  /* BitBLT Destination base address */
 178 #define BLTXYSTRIDES            0x02c8  /* BitBLT Source and Destination strides */
 179 #define BLTSRCCHROMARANGE       0x02cc  /* BitBLT Source Chroma key range */
 180 #define BLTDSTCHROMARANGE       0x02d0  /* BitBLT Destination Chroma key range */
 181 #define BLTCLIPX                0x02d4  /* BitBLT Min/Max X clip values */
 182 #define BLTCLIPY                0x02d8  /* BitBLT Min/Max Y clip values */
 183 #define BLTSRCXY                0x02e0  /* BitBLT Source starting XY coordinates */
 184 #define BLTDSTXY                0x02e4  /* BitBLT Destination starting XY coordinates */
 185 #define BLTSIZE                 0x02e8  /* BitBLT width and height */
 186 #define BLTROP                  0x02ec  /* BitBLT Raster operations */
 187 #  define BLTROP_COPY             0x0cccc
 188 #  define BLTROP_INVERT           0x05555
 189 #  define BLTROP_XOR              0x06666
 190 #define BLTCOLOR                0x02f0  /* BitBLT and foreground background colors */
 191 #define BLTCOMMAND              0x02f8  /* BitBLT command mode (v2 specific) */
 192 # define BLT_SCR2SCR_BITBLT       0       /* Screen-to-Screen BitBLT */
 193 # define BLT_CPU2SCR_BITBLT       1       /* CPU-to-screen BitBLT */
 194 # define BLT_RECFILL_BITBLT       2       /* BitBLT Rectangle Fill */
 195 # define BLT_16BPP_FMT            2       /* 16 BPP (5-6-5 RGB) */
 196 #define BLTDATA                 0x02fc  /* BitBLT data for CPU-to-Screen BitBLTs */
 197 #  define LAUNCH_BITBLT           BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */
 198
 199 /* Dac Registers */
 200 #define DACREG_WMA              0x0     /* pixel write mode address */
 201 #define DACREG_LUT              0x01    /* color value */
 202 #define DACREG_RMR              0x02    /* pixel mask */
 203 #define DACREG_RMA              0x03    /* pixel read mode address */
 204 /*Dac registers in indexed mode (TI, ATT dacs) */
 205 #define DACREG_ADDR_I           DACREG_WMA
 206 #define DACREG_DATA_I           DACREG_RMR
 207 #define DACREG_RMR_I            0x00
 208 #define DACREG_CR0_I            0x01
 209 #  define DACREG_CR0_EN_INDEXED   BIT(0)        /* enable indexec mode */
 210 #  define DACREG_CR0_8BIT         BIT(1)        /* set dac to 8 bits/read */
 211 #  define DACREG_CR0_PWDOWN       BIT(3)        /* powerdown dac */
 212 #  define DACREG_CR0_16BPP        0x30          /* mode 3 */
 213 #  define DACREG_CR0_24BPP        0x50          /* mode 5 */
 214 #define DACREG_CR1_I            0x05
 215 #define DACREG_CC_I             0x06
 216 #  define DACREG_CC_CLKA          BIT(7)        /* clk A controlled by regs */
 217 #  define DACREG_CC_CLKA_C        (2<<4)        /* clk A uses reg C */
 218 #  define DACREG_CC_CLKB          BIT(3)        /* clk B controlled by regs */
 219 #  define DACREG_CC_CLKB_D        3             /* clkB uses reg D */
 220 #define DACREG_AC0_I            0x48            /* clock A reg C */
 221 #define DACREG_AC1_I            0x49
 222 #define DACREG_BD0_I            0x6c            /* clock B reg D */
 223 #define DACREG_BD1_I            0x6d
 224
 225 /* identification constants */
 226 #define DACREG_MIR_TI           0x97
 227 #define DACREG_DIR_TI           0x09
 228 #define DACREG_MIR_ATT          0x84
 229 #define DACREG_DIR_ATT          0x09
 230 /* ics dac specific registers */
 231 #define DACREG_ICS_PLLWMA       0x04    /* PLL write mode address */
 232 #define DACREG_ICS_PLLDATA      0x05    /* PLL data /parameter */
 233 #define DACREG_ICS_CMD          0x06    /* command */
 234 #  define DACREG_ICS_CMD_16BPP    0x50  /* ics color mode 6 (16bpp bypass)*/
 235 #  define DACREG_ICS_CMD_24BPP    0x70  /* ics color mode 7 (24bpp bypass)*/
 236 #  define DACREG_ICS_CMD_PWDOWN BIT(0)  /* powerdown dac */
 237 #define DACREG_ICS_PLLRMA       0x07    /* PLL read mode address */
 238 /*
 239  * pll parameter register:
 240  * indexed : write addr to PLLWMA, write data in PLLDATA.
 241  * for reads use PLLRMA .
 242  * 8 freq registers (0-7) for video clock (CLK0)
 243  * 2 freq registers (a-b) for graphic clock (CLK1)
 244  */
 245 #define DACREG_ICS_PLL_CLK0_1_INI 0x55  /* initial pll M value for freq f1  */
 246 #define DACREG_ICS_PLL_CLK0_7_INI 0x71  /* f7 */
 247 #define DACREG_ICS_PLL_CLK1_B_INI 0x79  /* fb */
 248 #define DACREG_ICS_PLL_CTRL     0x0e
 249 #  define DACREG_ICS_CLK0         BIT(5)
 250 #  define DACREG_ICS_CLK0_0       0
 251 #  define DACREG_ICS_CLK1_A       0     /* bit4 */
 252
 253 /* sst default init registers */
 254 #define FBIINIT0_DEFAULT DIS_VGA_PASSTHROUGH
 255
 256 #define FBIINIT1_DEFAULT        \
 257         (                       \
 258           FAST_PCI_WRITES       \
 259 /*        SLOW_PCI_WRITES*/     \
 260         | VIDEO_RESET           \
 261         | 10 << TILES_IN_X_SHIFT\
 262         | SEL_SOURCE_VCLK_2X_SEL\
 263         | EN_LFB_READ           \
 264         )
 265
 266 #define FBIINIT2_DEFAULT        \
 267         (                       \
 268          SWAP_DACVSYNC          \
 269         | EN_DRAM_OE            \
 270         | DRAM_REFRESH_16       \
 271         | EN_DRAM_REFRESH       \
 272         | EN_FAST_RAS_READ      \
 273         | EN_RD_AHEAD_FIFO      \
 274         | EN_FAST_RD_AHEAD_WR   \
 275         )
 276
 277 #define FBIINIT3_DEFAULT        \
 278         ( DISABLE_TEXTURE )
 279
 280 #define FBIINIT4_DEFAULT        \
 281         (                       \
 282           FAST_PCI_READS        \
 283 /*        SLOW_PCI_READS*/      \
 284         | LFB_READ_AHEAD        \
 285         )
 286 /* Careful with this one : writing back the data just read will trash the DAC
 287    reading some fields give logic value on pins, but setting this field will
 288    set the source signal driving the pin. conclusion : just use the default
 289    as a base before writing back .
 290 */
 291 #define FBIINIT6_DEFAULT        (0x0)
 292
 293 /*
 294  *
 295  * Misc Const
 296  *
 297  */
 298
 299 /* ioctl to enable/disable VGA passthrough */
 300 #define SSTFB_SET_VGAPASS       _IOW('F', 0xdd, __u32)
 301 #define SSTFB_GET_VGAPASS       _IOR('F', 0xdd, __u32)
 302
 303
 304 /* used to know witch clock to set */
 305 enum {
 306         VID_CLOCK=0,
 307         GFX_CLOCK=1,
 308 };
 309
 310 /* freq max */
 311 #define DAC_FREF        14318   /* DAC reference freq (Khz) */
 312 #define VCO_MAX         260000
 313
 314 /*
 315  *  driver structs
 316  */
 317
 318 struct pll_timing {
 319         unsigned int m;
 320         unsigned int n;
 321         unsigned int p;
 322 };
 323
 324 struct dac_switch {
 325         const char *name;
 326         int (*detect) (struct fb_info *info);
 327         int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock);
 328         void (*set_vidmod) (struct fb_info *info, const int bpp);
 329 };
 330
 331 struct sst_spec {
 332         char * name;
 333         int default_gfx_clock;  /* 50000 for voodoo1, 75000 for voodoo2 */
 334         int max_gfxclk;         /* ! in Mhz ie 60 for voodoo 1 */
 335 };
 336
 337 struct sstfb_par {
 338         u32 palette[16];
 339         unsigned int yDim;
 340         unsigned int hSyncOn;   /* hsync_len */
 341         unsigned int hSyncOff;  /* left_margin + xres + right_margin */
 342         unsigned int hBackPorch;/* left_margin */
 343         unsigned int vSyncOn;
 344         unsigned int vSyncOff;
 345         unsigned int vBackPorch;
 346         struct pll_timing pll;
 347         unsigned int tiles_in_X;/* num of tiles in X res */
 348         u8 __iomem *mmio_vbase;
 349         struct dac_switch       dac_sw; /* dac specific functions */
 350         struct pci_dev          *dev;
 351         int     type;
 352         u8      revision;
 353         u8      vgapass;        /* VGA pass through: 1=enabled, 0=disabled */
 354 };
 355
 356 #endif /* _SSTFB_H_ */