arch/tile/include/asm/io.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_IO_H
  16 #define _ASM_TILE_IO_H
  17
  18 #include <linux/kernel.h>
  19 #include <linux/bug.h>
  20 #include <asm/page.h>
  21
  22 /* Maximum PCI I/O space address supported. */
  23 #define IO_SPACE_LIMIT 0xffffffff
  24
  25 /*
  26  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  27  * access.
  28  */
  29 #define xlate_dev_mem_ptr(p)    __va(p)
  30
  31 /*
  32  * Convert a virtual cached pointer to an uncached pointer.
  33  */
  34 #define xlate_dev_kmem_ptr(p)   p
  35
  36 /*
  37  * Change "struct page" to physical address.
  38  */
  39 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
  40
  41 /*
  42  * Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
  43  * long before casting it to a pointer to avoid compiler warnings.
  44  */
  45 #if CHIP_HAS_MMIO()
  46 extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
  47 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
  48         pgprot_t pgprot);
  49 extern void iounmap(volatile void __iomem *addr);
  50 #else
  51 #define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
  52 #define iounmap(addr)           ((void)0)
  53 #endif
  54
  55 #define ioremap_nocache(physaddr, size)         ioremap(physaddr, size)
  56 #define ioremap_wc(physaddr, size)              ioremap(physaddr, size)
  57 #define ioremap_wt(physaddr, size)              ioremap(physaddr, size)
  58 #define ioremap_uc(physaddr, size)              ioremap(physaddr, size)
  59 #define ioremap_fullcache(physaddr, size)       ioremap(physaddr, size)
  60
  61 #define mmiowb()
  62
  63 /* Conversion between virtual and physical mappings.  */
  64 #define mm_ptov(addr)           ((void *)phys_to_virt(addr))
  65 #define mm_vtop(addr)           ((unsigned long)virt_to_phys(addr))
  66
  67 #if CHIP_HAS_MMIO()
  68
  69 /*
  70  * We use inline assembly to guarantee that the compiler does not
  71  * split an access into multiple byte-sized accesses as it might
  72  * sometimes do if a register data structure is marked "packed".
  73  * Obviously on tile we can't tolerate such an access being
  74  * actually unaligned, but we want to avoid the case where the
  75  * compiler conservatively would generate multiple accesses even
  76  * for an aligned read or write.
  77  */
  78
  79 static inline u8 __raw_readb(const volatile void __iomem *addr)
  80 {
  81         return *(const volatile u8 __force *)addr;
  82 }
  83
  84 static inline u16 __raw_readw(const volatile void __iomem *addr)
  85 {
  86         u16 ret;
  87         asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
  88         barrier();
  89         return le16_to_cpu(ret);
  90 }
  91
  92 static inline u32 __raw_readl(const volatile void __iomem *addr)
  93 {
  94         u32 ret;
  95         /* Sign-extend to conform to u32 ABI sign-extension convention. */
  96         asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
  97         barrier();
  98         return le32_to_cpu(ret);
  99 }
 100
 101 static inline u64 __raw_readq(const volatile void __iomem *addr)
 102 {
 103         u64 ret;
 104         asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
 105         barrier();
 106         return le64_to_cpu(ret);
 107 }
 108
 109 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 110 {
 111         *(volatile u8 __force *)addr = val;
 112 }
 113
 114 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 115 {
 116         asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
 117 }
 118
 119 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 120 {
 121         asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
 122 }
 123
 124 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
 125 {
 126         asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
 127 }
 128
 129 /*
 130  * The on-chip I/O hardware on tilegx is configured with VA=PA for the
 131  * kernel's PA range.  The low-level APIs and field names use "va" and
 132  * "void *" nomenclature, to be consistent with the general notion
 133  * that the addresses in question are virtualizable, but in the kernel
 134  * context we are actually manipulating PA values.  (In other contexts,
 135  * e.g. access from user space, we do in fact use real virtual addresses
 136  * in the va fields.)  To allow readers of the code to understand what's
 137  * happening, we direct their attention to this comment by using the
 138  * following two functions that just duplicate __va() and __pa().
 139  */
 140 typedef unsigned long tile_io_addr_t;
 141 static inline tile_io_addr_t va_to_tile_io_addr(void *va)
 142 {
 143         BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
 144         return __pa(va);
 145 }
 146 static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
 147 {
 148         return __va(tile_io_addr);
 149 }
 150
 151 #else /* CHIP_HAS_MMIO() */
 152
 153 #ifdef CONFIG_PCI
 154
 155 extern u8 _tile_readb(unsigned long addr);
 156 extern u16 _tile_readw(unsigned long addr);
 157 extern u32 _tile_readl(unsigned long addr);
 158 extern u64 _tile_readq(unsigned long addr);
 159 extern void _tile_writeb(u8  val, unsigned long addr);
 160 extern void _tile_writew(u16 val, unsigned long addr);
 161 extern void _tile_writel(u32 val, unsigned long addr);
 162 extern void _tile_writeq(u64 val, unsigned long addr);
 163
 164 #define __raw_readb(addr) _tile_readb((unsigned long)(addr))
 165 #define __raw_readw(addr) _tile_readw((unsigned long)(addr))
 166 #define __raw_readl(addr) _tile_readl((unsigned long)(addr))
 167 #define __raw_readq(addr) _tile_readq((unsigned long)(addr))
 168 #define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)(addr))
 169 #define __raw_writew(val, addr) _tile_writew(val, (unsigned long)(addr))
 170 #define __raw_writel(val, addr) _tile_writel(val, (unsigned long)(addr))
 171 #define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)(addr))
 172
 173 #else /* CONFIG_PCI */
 174
 175 /*
 176  * The tilepro architecture does not support IOMEM unless PCI is enabled.
 177  * Unfortunately we can't yet simply not declare these methods,
 178  * since some generic code that compiles into the kernel, but
 179  * we never run, uses them unconditionally.
 180  */
 181
 182 static inline int iomem_panic(void)
 183 {
 184         panic("readb/writeb and friends do not exist on tile without PCI");
 185         return 0;
 186 }
 187
 188 static inline u8 readb(unsigned long addr)
 189 {
 190         return iomem_panic();
 191 }
 192
 193 static inline u16 _readw(unsigned long addr)
 194 {
 195         return iomem_panic();
 196 }
 197
 198 static inline u32 readl(unsigned long addr)
 199 {
 200         return iomem_panic();
 201 }
 202
 203 static inline u64 readq(unsigned long addr)
 204 {
 205         return iomem_panic();
 206 }
 207
 208 static inline void writeb(u8  val, unsigned long addr)
 209 {
 210         iomem_panic();
 211 }
 212
 213 static inline void writew(u16 val, unsigned long addr)
 214 {
 215         iomem_panic();
 216 }
 217
 218 static inline void writel(u32 val, unsigned long addr)
 219 {
 220         iomem_panic();
 221 }
 222
 223 static inline void writeq(u64 val, unsigned long addr)
 224 {
 225         iomem_panic();
 226 }
 227
 228 #endif /* CONFIG_PCI */
 229
 230 #endif /* CHIP_HAS_MMIO() */
 231
 232 #define readb __raw_readb
 233 #define readw __raw_readw
 234 #define readl __raw_readl
 235 #define readq __raw_readq
 236 #define writeb __raw_writeb
 237 #define writew __raw_writew
 238 #define writel __raw_writel
 239 #define writeq __raw_writeq
 240
 241 #define readb_relaxed readb
 242 #define readw_relaxed readw
 243 #define readl_relaxed readl
 244 #define readq_relaxed readq
 245 #define writeb_relaxed writeb
 246 #define writew_relaxed writew
 247 #define writel_relaxed writel
 248 #define writeq_relaxed writeq
 249
 250 #define ioread8 readb
 251 #define ioread16 readw
 252 #define ioread32 readl
 253 #define ioread64 readq
 254 #define iowrite8 writeb
 255 #define iowrite16 writew
 256 #define iowrite32 writel
 257 #define iowrite64 writeq
 258
 259 #if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
 260
 261 static inline void memset_io(volatile void *dst, int val, size_t len)
 262 {
 263         size_t x;
 264         BUG_ON((unsigned long)dst & 0x3);
 265         val = (val & 0xff) * 0x01010101;
 266         for (x = 0; x < len; x += 4)
 267                 writel(val, dst + x);
 268 }
 269
 270 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
 271                                  size_t len)
 272 {
 273         size_t x;
 274         BUG_ON((unsigned long)src & 0x3);
 275         for (x = 0; x < len; x += 4)
 276                 *(u32 *)(dst + x) = readl(src + x);
 277 }
 278
 279 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
 280                                 size_t len)
 281 {
 282         size_t x;
 283         BUG_ON((unsigned long)dst & 0x3);
 284         for (x = 0; x < len; x += 4)
 285                 writel(*(u32 *)(src + x), dst + x);
 286 }
 287
 288 #endif
 289
 290 #if CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO)
 291
 292 static inline u8 inb(unsigned long addr)
 293 {
 294         return readb((volatile void __iomem *) addr);
 295 }
 296
 297 static inline u16 inw(unsigned long addr)
 298 {
 299         return readw((volatile void __iomem *) addr);
 300 }
 301
 302 static inline u32 inl(unsigned long addr)
 303 {
 304         return readl((volatile void __iomem *) addr);
 305 }
 306
 307 static inline void outb(u8 b, unsigned long addr)
 308 {
 309         writeb(b, (volatile void __iomem *) addr);
 310 }
 311
 312 static inline void outw(u16 b, unsigned long addr)
 313 {
 314         writew(b, (volatile void __iomem *) addr);
 315 }
 316
 317 static inline void outl(u32 b, unsigned long addr)
 318 {
 319         writel(b, (volatile void __iomem *) addr);
 320 }
 321
 322 static inline void insb(unsigned long addr, void *buffer, int count)
 323 {
 324         if (count) {
 325                 u8 *buf = buffer;
 326                 do {
 327                         u8 x = inb(addr);
 328                         *buf++ = x;
 329                 } while (--count);
 330         }
 331 }
 332
 333 static inline void insw(unsigned long addr, void *buffer, int count)
 334 {
 335         if (count) {
 336                 u16 *buf = buffer;
 337                 do {
 338                         u16 x = inw(addr);
 339                         *buf++ = x;
 340                 } while (--count);
 341         }
 342 }
 343
 344 static inline void insl(unsigned long addr, void *buffer, int count)
 345 {
 346         if (count) {
 347                 u32 *buf = buffer;
 348                 do {
 349                         u32 x = inl(addr);
 350                         *buf++ = x;
 351                 } while (--count);
 352         }
 353 }
 354
 355 static inline void outsb(unsigned long addr, const void *buffer, int count)
 356 {
 357         if (count) {
 358                 const u8 *buf = buffer;
 359                 do {
 360                         outb(*buf++, addr);
 361                 } while (--count);
 362         }
 363 }
 364
 365 static inline void outsw(unsigned long addr, const void *buffer, int count)
 366 {
 367         if (count) {
 368                 const u16 *buf = buffer;
 369                 do {
 370                         outw(*buf++, addr);
 371                 } while (--count);
 372         }
 373 }
 374
 375 static inline void outsl(unsigned long addr, const void *buffer, int count)
 376 {
 377         if (count) {
 378                 const u32 *buf = buffer;
 379                 do {
 380                         outl(*buf++, addr);
 381                 } while (--count);
 382         }
 383 }
 384
 385 extern void __iomem *ioport_map(unsigned long port, unsigned int len);
 386 extern void ioport_unmap(void __iomem *addr);
 387
 388 #else
 389
 390 /*
 391  * The TilePro architecture does not support IOPORT, even with PCI.
 392  * Unfortunately we can't yet simply not declare these methods,
 393  * since some generic code that compiles into the kernel, but
 394  * we never run, uses them unconditionally.
 395  */
 396
 397 static inline long ioport_panic(void)
 398 {
 399 #ifdef __tilegx__
 400         panic("PCI IO space support is disabled. Configure the kernel with CONFIG_TILE_PCI_IO to enable it");
 401 #else
 402         panic("inb/outb and friends do not exist on tile");
 403 #endif
 404         return 0;
 405 }
 406
 407 static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
 408 {
 409         pr_info("ioport_map: mapping IO resources is unsupported on tile\n");
 410         return NULL;
 411 }
 412
 413 static inline void ioport_unmap(void __iomem *addr)
 414 {
 415         ioport_panic();
 416 }
 417
 418 static inline u8 inb(unsigned long addr)
 419 {
 420         return ioport_panic();
 421 }
 422
 423 static inline u16 inw(unsigned long addr)
 424 {
 425         return ioport_panic();
 426 }
 427
 428 static inline u32 inl(unsigned long addr)
 429 {
 430         return ioport_panic();
 431 }
 432
 433 static inline void outb(u8 b, unsigned long addr)
 434 {
 435         ioport_panic();
 436 }
 437
 438 static inline void outw(u16 b, unsigned long addr)
 439 {
 440         ioport_panic();
 441 }
 442
 443 static inline void outl(u32 b, unsigned long addr)
 444 {
 445         ioport_panic();
 446 }
 447
 448 static inline void insb(unsigned long addr, void *buffer, int count)
 449 {
 450         ioport_panic();
 451 }
 452
 453 static inline void insw(unsigned long addr, void *buffer, int count)
 454 {
 455         ioport_panic();
 456 }
 457
 458 static inline void insl(unsigned long addr, void *buffer, int count)
 459 {
 460         ioport_panic();
 461 }
 462
 463 static inline void outsb(unsigned long addr, const void *buffer, int count)
 464 {
 465         ioport_panic();
 466 }
 467
 468 static inline void outsw(unsigned long addr, const void *buffer, int count)
 469 {
 470         ioport_panic();
 471 }
 472
 473 static inline void outsl(unsigned long addr, const void *buffer, int count)
 474 {
 475         ioport_panic();
 476 }
 477
 478 #endif /* CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO) */
 479
 480 #define inb_p(addr)     inb(addr)
 481 #define inw_p(addr)     inw(addr)
 482 #define inl_p(addr)     inl(addr)
 483 #define outb_p(x, addr) outb((x), (addr))
 484 #define outw_p(x, addr) outw((x), (addr))
 485 #define outl_p(x, addr) outl((x), (addr))
 486
 487 #define ioread16be(addr)        be16_to_cpu(ioread16(addr))
 488 #define ioread32be(addr)        be32_to_cpu(ioread32(addr))
 489 #define iowrite16be(v, addr)    iowrite16(be16_to_cpu(v), (addr))
 490 #define iowrite32be(v, addr)    iowrite32(be32_to_cpu(v), (addr))
 491
 492 #define ioread8_rep(p, dst, count) \
 493         insb((unsigned long) (p), (dst), (count))
 494 #define ioread16_rep(p, dst, count) \
 495         insw((unsigned long) (p), (dst), (count))
 496 #define ioread32_rep(p, dst, count) \
 497         insl((unsigned long) (p), (dst), (count))
 498
 499 #define iowrite8_rep(p, src, count) \
 500         outsb((unsigned long) (p), (src), (count))
 501 #define iowrite16_rep(p, src, count) \
 502         outsw((unsigned long) (p), (src), (count))
 503 #define iowrite32_rep(p, src, count) \
 504         outsl((unsigned long) (p), (src), (count))
 505
 506 #define virt_to_bus     virt_to_phys
 507 #define bus_to_virt     phys_to_virt
 508
 509 #endif /* _ASM_TILE_IO_H */