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[linux/fpc-iii.git] / arch / x86 / kvm / irq_comm.c
blob25810b144b58d979c5ba9355fc7b0907494f5869
1 /*
2 * irq_comm.c: Common API for in kernel interrupt controller
3 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Authors:
18 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
20 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
23 #include <linux/kvm_host.h>
24 #include <linux/slab.h>
25 #include <linux/export.h>
26 #include <trace/events/kvm.h>
28 #include <asm/msidef.h>
30 #include "irq.h"
32 #include "ioapic.h"
34 #include "lapic.h"
36 #include "hyperv.h"
37 #include "x86.h"
39 static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
40 struct kvm *kvm, int irq_source_id, int level,
41 bool line_status)
43 struct kvm_pic *pic = pic_irqchip(kvm);
44 return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
47 static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
48 struct kvm *kvm, int irq_source_id, int level,
49 bool line_status)
51 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
52 return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
53 line_status);
56 int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
57 struct kvm_lapic_irq *irq, struct dest_map *dest_map)
59 int i, r = -1;
60 struct kvm_vcpu *vcpu, *lowest = NULL;
61 unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)];
62 unsigned int dest_vcpus = 0;
64 if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
65 kvm_lowest_prio_delivery(irq)) {
66 printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
67 irq->delivery_mode = APIC_DM_FIXED;
70 if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
71 return r;
73 memset(dest_vcpu_bitmap, 0, sizeof(dest_vcpu_bitmap));
75 kvm_for_each_vcpu(i, vcpu, kvm) {
76 if (!kvm_apic_present(vcpu))
77 continue;
79 if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
80 irq->dest_id, irq->dest_mode))
81 continue;
83 if (!kvm_lowest_prio_delivery(irq)) {
84 if (r < 0)
85 r = 0;
86 r += kvm_apic_set_irq(vcpu, irq, dest_map);
87 } else if (kvm_lapic_enabled(vcpu)) {
88 if (!kvm_vector_hashing_enabled()) {
89 if (!lowest)
90 lowest = vcpu;
91 else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
92 lowest = vcpu;
93 } else {
94 __set_bit(i, dest_vcpu_bitmap);
95 dest_vcpus++;
100 if (dest_vcpus != 0) {
101 int idx = kvm_vector_to_index(irq->vector, dest_vcpus,
102 dest_vcpu_bitmap, KVM_MAX_VCPUS);
104 lowest = kvm_get_vcpu(kvm, idx);
107 if (lowest)
108 r = kvm_apic_set_irq(lowest, irq, dest_map);
110 return r;
113 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
114 struct kvm_lapic_irq *irq)
116 trace_kvm_msi_set_irq(e->msi.address_lo | (kvm->arch.x2apic_format ?
117 (u64)e->msi.address_hi << 32 : 0),
118 e->msi.data);
120 irq->dest_id = (e->msi.address_lo &
121 MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
122 if (kvm->arch.x2apic_format)
123 irq->dest_id |= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi);
124 irq->vector = (e->msi.data &
125 MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
126 irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
127 irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
128 irq->delivery_mode = e->msi.data & 0x700;
129 irq->msi_redir_hint = ((e->msi.address_lo
130 & MSI_ADDR_REDIRECTION_LOWPRI) > 0);
131 irq->level = 1;
132 irq->shorthand = 0;
134 EXPORT_SYMBOL_GPL(kvm_set_msi_irq);
136 static inline bool kvm_msi_route_invalid(struct kvm *kvm,
137 struct kvm_kernel_irq_routing_entry *e)
139 return kvm->arch.x2apic_format && (e->msi.address_hi & 0xff);
142 int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
143 struct kvm *kvm, int irq_source_id, int level, bool line_status)
145 struct kvm_lapic_irq irq;
147 if (kvm_msi_route_invalid(kvm, e))
148 return -EINVAL;
150 if (!level)
151 return -1;
153 kvm_set_msi_irq(kvm, e, &irq);
155 return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
159 int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
160 struct kvm *kvm, int irq_source_id, int level,
161 bool line_status)
163 struct kvm_lapic_irq irq;
164 int r;
166 if (unlikely(e->type != KVM_IRQ_ROUTING_MSI))
167 return -EWOULDBLOCK;
169 if (kvm_msi_route_invalid(kvm, e))
170 return -EINVAL;
172 kvm_set_msi_irq(kvm, e, &irq);
174 if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
175 return r;
176 else
177 return -EWOULDBLOCK;
180 int kvm_request_irq_source_id(struct kvm *kvm)
182 unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
183 int irq_source_id;
185 mutex_lock(&kvm->irq_lock);
186 irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
188 if (irq_source_id >= BITS_PER_LONG) {
189 printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
190 irq_source_id = -EFAULT;
191 goto unlock;
194 ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
195 ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
196 set_bit(irq_source_id, bitmap);
197 unlock:
198 mutex_unlock(&kvm->irq_lock);
200 return irq_source_id;
203 void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
205 ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
206 ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
208 mutex_lock(&kvm->irq_lock);
209 if (irq_source_id < 0 ||
210 irq_source_id >= BITS_PER_LONG) {
211 printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
212 goto unlock;
214 clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
215 if (!ioapic_in_kernel(kvm))
216 goto unlock;
218 kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
219 kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
220 unlock:
221 mutex_unlock(&kvm->irq_lock);
224 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
225 struct kvm_irq_mask_notifier *kimn)
227 mutex_lock(&kvm->irq_lock);
228 kimn->irq = irq;
229 hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
230 mutex_unlock(&kvm->irq_lock);
233 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
234 struct kvm_irq_mask_notifier *kimn)
236 mutex_lock(&kvm->irq_lock);
237 hlist_del_rcu(&kimn->link);
238 mutex_unlock(&kvm->irq_lock);
239 synchronize_srcu(&kvm->irq_srcu);
242 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
243 bool mask)
245 struct kvm_irq_mask_notifier *kimn;
246 int idx, gsi;
248 idx = srcu_read_lock(&kvm->irq_srcu);
249 gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
250 if (gsi != -1)
251 hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
252 if (kimn->irq == gsi)
253 kimn->func(kimn, mask);
254 srcu_read_unlock(&kvm->irq_srcu, idx);
257 static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e,
258 struct kvm *kvm, int irq_source_id, int level,
259 bool line_status)
261 if (!level)
262 return -1;
264 return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
267 int kvm_set_routing_entry(struct kvm *kvm,
268 struct kvm_kernel_irq_routing_entry *e,
269 const struct kvm_irq_routing_entry *ue)
271 int r = -EINVAL;
272 int delta;
273 unsigned max_pin;
275 switch (ue->type) {
276 case KVM_IRQ_ROUTING_IRQCHIP:
277 delta = 0;
278 switch (ue->u.irqchip.irqchip) {
279 case KVM_IRQCHIP_PIC_MASTER:
280 e->set = kvm_set_pic_irq;
281 max_pin = PIC_NUM_PINS;
282 break;
283 case KVM_IRQCHIP_PIC_SLAVE:
284 e->set = kvm_set_pic_irq;
285 max_pin = PIC_NUM_PINS;
286 delta = 8;
287 break;
288 case KVM_IRQCHIP_IOAPIC:
289 max_pin = KVM_IOAPIC_NUM_PINS;
290 e->set = kvm_set_ioapic_irq;
291 break;
292 default:
293 goto out;
295 e->irqchip.irqchip = ue->u.irqchip.irqchip;
296 e->irqchip.pin = ue->u.irqchip.pin + delta;
297 if (e->irqchip.pin >= max_pin)
298 goto out;
299 break;
300 case KVM_IRQ_ROUTING_MSI:
301 e->set = kvm_set_msi;
302 e->msi.address_lo = ue->u.msi.address_lo;
303 e->msi.address_hi = ue->u.msi.address_hi;
304 e->msi.data = ue->u.msi.data;
306 if (kvm_msi_route_invalid(kvm, e))
307 goto out;
308 break;
309 case KVM_IRQ_ROUTING_HV_SINT:
310 e->set = kvm_hv_set_sint;
311 e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
312 e->hv_sint.sint = ue->u.hv_sint.sint;
313 break;
314 default:
315 goto out;
318 r = 0;
319 out:
320 return r;
323 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
324 struct kvm_vcpu **dest_vcpu)
326 int i, r = 0;
327 struct kvm_vcpu *vcpu;
329 if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu))
330 return true;
332 kvm_for_each_vcpu(i, vcpu, kvm) {
333 if (!kvm_apic_present(vcpu))
334 continue;
336 if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand,
337 irq->dest_id, irq->dest_mode))
338 continue;
340 if (++r == 2)
341 return false;
343 *dest_vcpu = vcpu;
346 return r == 1;
348 EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu);
350 #define IOAPIC_ROUTING_ENTRY(irq) \
351 { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
352 .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
353 #define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
355 #define PIC_ROUTING_ENTRY(irq) \
356 { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
357 .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
358 #define ROUTING_ENTRY2(irq) \
359 IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
361 static const struct kvm_irq_routing_entry default_routing[] = {
362 ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
363 ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
364 ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
365 ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
366 ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
367 ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
368 ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
369 ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
370 ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
371 ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
372 ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
373 ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
376 int kvm_setup_default_irq_routing(struct kvm *kvm)
378 return kvm_set_irq_routing(kvm, default_routing,
379 ARRAY_SIZE(default_routing), 0);
382 static const struct kvm_irq_routing_entry empty_routing[] = {};
384 int kvm_setup_empty_irq_routing(struct kvm *kvm)
386 return kvm_set_irq_routing(kvm, empty_routing, 0, 0);
389 void kvm_arch_post_irq_routing_update(struct kvm *kvm)
391 if (ioapic_in_kernel(kvm) || !irqchip_in_kernel(kvm))
392 return;
393 kvm_make_scan_ioapic_request(kvm);
396 void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu,
397 ulong *ioapic_handled_vectors)
399 struct kvm *kvm = vcpu->kvm;
400 struct kvm_kernel_irq_routing_entry *entry;
401 struct kvm_irq_routing_table *table;
402 u32 i, nr_ioapic_pins;
403 int idx;
405 idx = srcu_read_lock(&kvm->irq_srcu);
406 table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
407 nr_ioapic_pins = min_t(u32, table->nr_rt_entries,
408 kvm->arch.nr_reserved_ioapic_pins);
409 for (i = 0; i < nr_ioapic_pins; ++i) {
410 hlist_for_each_entry(entry, &table->map[i], link) {
411 struct kvm_lapic_irq irq;
413 if (entry->type != KVM_IRQ_ROUTING_MSI)
414 continue;
416 kvm_set_msi_irq(vcpu->kvm, entry, &irq);
418 if (irq.level && kvm_apic_match_dest(vcpu, NULL, 0,
419 irq.dest_id, irq.dest_mode))
420 __set_bit(irq.vector, ioapic_handled_vectors);
423 srcu_read_unlock(&kvm->irq_srcu, idx);
426 int kvm_arch_set_irq(struct kvm_kernel_irq_routing_entry *irq, struct kvm *kvm,
427 int irq_source_id, int level, bool line_status)
429 switch (irq->type) {
430 case KVM_IRQ_ROUTING_HV_SINT:
431 return kvm_hv_set_sint(irq, kvm, irq_source_id, level,
432 line_status);
433 default:
434 return -EWOULDBLOCK;
438 void kvm_arch_irq_routing_update(struct kvm *kvm)
440 kvm_hv_irq_routing_update(kvm);