?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ALSA: hda - Add the top speaker pin config for HP Spectre x360
[linux/fpc-iii.git] / drivers / infiniband / hw / qib / qib_iba7322.c
blobce4034071f9c4db9d67376357d3f64c8db1792b0
1 /*
2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 /*
35 * This file contains all of the code that is specific to the
36 * InfiniPath 7322 chip
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/io.h>
43 #include <linux/jiffies.h>
44 #include <linux/module.h>
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_smi.h>
47 #ifdef CONFIG_INFINIBAND_QIB_DCA
48 #include <linux/dca.h>
49 #endif
50
51 #include "qib.h"
52 #include "qib_7322_regs.h"
53 #include "qib_qsfp.h"
54
55 #include "qib_mad.h"
56 #include "qib_verbs.h"
57
58 #undef pr_fmt
59 #define pr_fmt(fmt) QIB_DRV_NAME " " fmt
60
61 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
62 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
63 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
64 static irqreturn_t qib_7322intr(int irq, void *data);
65 static irqreturn_t qib_7322bufavail(int irq, void *data);
66 static irqreturn_t sdma_intr(int irq, void *data);
67 static irqreturn_t sdma_idle_intr(int irq, void *data);
68 static irqreturn_t sdma_progress_intr(int irq, void *data);
69 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
70 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
71 struct qib_ctxtdata *rcd);
72 static u8 qib_7322_phys_portstate(u64);
73 static u32 qib_7322_iblink_state(u64);
74 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
75 u16 linitcmd);
76 static void force_h1(struct qib_pportdata *);
77 static void adj_tx_serdes(struct qib_pportdata *);
78 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
79 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
80
81 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
82 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
83 static void serdes_7322_los_enable(struct qib_pportdata *, int);
84 static int serdes_7322_init_old(struct qib_pportdata *);
85 static int serdes_7322_init_new(struct qib_pportdata *);
86 static void dump_sdma_7322_state(struct qib_pportdata *);
87
88 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
89
90 /* LE2 serdes values for different cases */
91 #define LE2_DEFAULT 5
92 #define LE2_5m 4
93 #define LE2_QME 0
94
95 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
96 #define IBSD(hw_pidx) (hw_pidx + 2)
97
98 /* these are variables for documentation and experimentation purposes */
99 static const unsigned rcv_int_timeout = 375;
100 static const unsigned rcv_int_count = 16;
101 static const unsigned sdma_idle_cnt = 64;
102
103 /* Time to stop altering Rx Equalization parameters, after link up. */
104 #define RXEQ_DISABLE_MSECS 2500
105
106 /*
107 * Number of VLs we are configured to use (to allow for more
108 * credits per vl, etc.)
109 */
110 ushort qib_num_cfg_vls = 2;
111 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
112 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
113
114 static ushort qib_chase = 1;
115 module_param_named(chase, qib_chase, ushort, S_IRUGO);
116 MODULE_PARM_DESC(chase, "Enable state chase handling");
117
118 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
119 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
120 MODULE_PARM_DESC(long_attenuation,
121 "attenuation cutoff (dB) for long copper cable setup");
122
123 static ushort qib_singleport;
124 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
125 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
126
127 static ushort qib_krcvq01_no_msi;
128 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
129 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
130
131 /*
132 * Receive header queue sizes
133 */
134 static unsigned qib_rcvhdrcnt;
135 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
136 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
137
138 static unsigned qib_rcvhdrsize;
139 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
140 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
141
142 static unsigned qib_rcvhdrentsize;
143 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
144 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
145
146 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
147 /* for read back, default index is ~5m copper cable */
148 static char txselect_list[MAX_ATTEN_LEN] = "10";
149 static struct kparam_string kp_txselect = {
150 .string = txselect_list,
151 .maxlen = MAX_ATTEN_LEN
152 };
153 static int setup_txselect(const char *, struct kernel_param *);
154 module_param_call(txselect, setup_txselect, param_get_string,
155 &kp_txselect, S_IWUSR | S_IRUGO);
156 MODULE_PARM_DESC(txselect,
157 "Tx serdes indices (for no QSFP or invalid QSFP data)");
158
159 #define BOARD_QME7342 5
160 #define BOARD_QMH7342 6
161 #define BOARD_QMH7360 9
162 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
163 BOARD_QMH7342)
164 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
165 BOARD_QME7342)
166
167 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
168
169 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
170
171 #define MASK_ACROSS(lsb, msb) \
172 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
173
174 #define SYM_RMASK(regname, fldname) ((u64) \
175 QIB_7322_##regname##_##fldname##_RMASK)
176
177 #define SYM_MASK(regname, fldname) ((u64) \
178 QIB_7322_##regname##_##fldname##_RMASK << \
179 QIB_7322_##regname##_##fldname##_LSB)
180
181 #define SYM_FIELD(value, regname, fldname) ((u64) \
182 (((value) >> SYM_LSB(regname, fldname)) & \
183 SYM_RMASK(regname, fldname)))
184
185 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
186 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
187 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
188
189 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
190 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
191 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
192 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
193 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
194 /* Below because most, but not all, fields of IntMask have that full suffix */
195 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
196
197
198 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
199
200 /*
201 * the size bits give us 2^N, in KB units. 0 marks as invalid,
202 * and 7 is reserved. We currently use only 2KB and 4KB
203 */
204 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
205 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
206 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
207 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
208
209 #define SendIBSLIDAssignMask \
210 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
211 #define SendIBSLMCMask \
212 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
213
214 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
215 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
216 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
217 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
218 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
219 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
220
221 #define _QIB_GPIO_SDA_NUM 1
222 #define _QIB_GPIO_SCL_NUM 0
223 #define QIB_EEPROM_WEN_NUM 14
224 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
225
226 /* HW counter clock is at 4nsec */
227 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
228
229 /* full speed IB port 1 only */
230 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
231 #define PORT_SPD_CAP_SHIFT 3
232
233 /* full speed featuremask, both ports */
234 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
235
236 /*
237 * This file contains almost all the chip-specific register information and
238 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
239 */
240
241 /* Use defines to tie machine-generated names to lower-case names */
242 #define kr_contextcnt KREG_IDX(ContextCnt)
243 #define kr_control KREG_IDX(Control)
244 #define kr_counterregbase KREG_IDX(CntrRegBase)
245 #define kr_errclear KREG_IDX(ErrClear)
246 #define kr_errmask KREG_IDX(ErrMask)
247 #define kr_errstatus KREG_IDX(ErrStatus)
248 #define kr_extctrl KREG_IDX(EXTCtrl)
249 #define kr_extstatus KREG_IDX(EXTStatus)
250 #define kr_gpio_clear KREG_IDX(GPIOClear)
251 #define kr_gpio_mask KREG_IDX(GPIOMask)
252 #define kr_gpio_out KREG_IDX(GPIOOut)
253 #define kr_gpio_status KREG_IDX(GPIOStatus)
254 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
255 #define kr_debugportval KREG_IDX(DebugPortValueReg)
256 #define kr_fmask KREG_IDX(feature_mask)
257 #define kr_act_fmask KREG_IDX(active_feature_mask)
258 #define kr_hwerrclear KREG_IDX(HwErrClear)
259 #define kr_hwerrmask KREG_IDX(HwErrMask)
260 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
261 #define kr_intclear KREG_IDX(IntClear)
262 #define kr_intmask KREG_IDX(IntMask)
263 #define kr_intredirect KREG_IDX(IntRedirect0)
264 #define kr_intstatus KREG_IDX(IntStatus)
265 #define kr_pagealign KREG_IDX(PageAlign)
266 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
267 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
268 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
269 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
270 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
271 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
272 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
273 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
274 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
275 #define kr_revision KREG_IDX(Revision)
276 #define kr_scratch KREG_IDX(Scratch)
277 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
278 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
279 #define kr_sendctrl KREG_IDX(SendCtrl)
280 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
281 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
282 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
283 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
284 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
285 #define kr_sendpiosize KREG_IDX(SendBufSize)
286 #define kr_sendregbase KREG_IDX(SendRegBase)
287 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
288 #define kr_userregbase KREG_IDX(UserRegBase)
289 #define kr_intgranted KREG_IDX(Int_Granted)
290 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
291 #define kr_intblocked KREG_IDX(IntBlocked)
292 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
293
294 /*
295 * per-port kernel registers. Access only with qib_read_kreg_port()
296 * or qib_write_kreg_port()
297 */
298 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
299 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
300 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
301 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
302 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
303 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
304 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
305 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
306 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
307 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
308 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
309 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
310 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
311 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
312 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
313 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
314 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
315 #define krp_psstart KREG_IBPORT_IDX(PSStart)
316 #define krp_psstat KREG_IBPORT_IDX(PSStat)
317 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
318 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
319 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
320 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
321 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
322 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
323 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
324 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
325 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
326 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
327 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
328 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
329 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
330 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
331 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
332 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
333 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
334 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
335 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
336 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
337 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
338 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
339 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
340 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
341 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
342 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
343 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
344 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
345 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
346 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
347 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
348
349 /*
350 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
351 * or qib_write_kreg_ctxt()
352 */
353 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
354 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
355
356 /*
357 * TID Flow table, per context. Reduces
358 * number of hdrq updates to one per flow (or on errors).
359 * context 0 and 1 share same memory, but have distinct
360 * addresses. Since for now, we never use expected sends
361 * on kernel contexts, we don't worry about that (we initialize
362 * those entries for ctxt 0/1 on driver load twice, for example).
363 */
364 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
365 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
366
367 /* these are the error bits in the tid flows, and are W1C */
368 #define TIDFLOW_ERRBITS ( \
369 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
370 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
371 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
372 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
373
374 /* Most (not all) Counters are per-IBport.
375 * Requires LBIntCnt is at offset 0 in the group
376 */
377 #define CREG_IDX(regname) \
378 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
379
380 #define crp_badformat CREG_IDX(RxVersionErrCnt)
381 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
382 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
383 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
384 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
385 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
386 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
387 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
388 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
389 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
390 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
391 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
392 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
393 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
394 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
395 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
396 #define crp_pktsend CREG_IDX(TxDataPktCnt)
397 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
398 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
399 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
400 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
401 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
402 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
403 #define crp_rcvebp CREG_IDX(RxEBPCnt)
404 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
405 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
406 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
407 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
408 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
409 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
410 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
411 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
412 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
413 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
414 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
415 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
416 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
417 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
418 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
419 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
420 #define crp_wordrcv CREG_IDX(RxDwordCnt)
421 #define crp_wordsend CREG_IDX(TxDwordCnt)
422 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
423
424 /* these are the (few) counters that are not port-specific */
425 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
426 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
427 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
428 #define cr_lbint CREG_DEVIDX(LBIntCnt)
429 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
430 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
431 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
432 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
433 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
434
435 /* no chip register for # of IB ports supported, so define */
436 #define NUM_IB_PORTS 2
437
438 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
439 #define NUM_VL15_BUFS NUM_IB_PORTS
440
441 /*
442 * context 0 and 1 are special, and there is no chip register that
443 * defines this value, so we have to define it here.
444 * These are all allocated to either 0 or 1 for single port
445 * hardware configuration, otherwise each gets half
446 */
447 #define KCTXT0_EGRCNT 2048
448
449 /* values for vl and port fields in PBC, 7322-specific */
450 #define PBC_PORT_SEL_LSB 26
451 #define PBC_PORT_SEL_RMASK 1
452 #define PBC_VL_NUM_LSB 27
453 #define PBC_VL_NUM_RMASK 7
454 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
455 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
456
457 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
458 [IB_RATE_2_5_GBPS] = 16,
459 [IB_RATE_5_GBPS] = 8,
460 [IB_RATE_10_GBPS] = 4,
461 [IB_RATE_20_GBPS] = 2,
462 [IB_RATE_30_GBPS] = 2,
463 [IB_RATE_40_GBPS] = 1
464 };
465
466 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
467 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
468
469 /* link training states, from IBC */
470 #define IB_7322_LT_STATE_DISABLED 0x00
471 #define IB_7322_LT_STATE_LINKUP 0x01
472 #define IB_7322_LT_STATE_POLLACTIVE 0x02
473 #define IB_7322_LT_STATE_POLLQUIET 0x03
474 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
475 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
476 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
477 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
478 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
479 #define IB_7322_LT_STATE_CFGIDLE 0x0b
480 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
481 #define IB_7322_LT_STATE_TXREVLANES 0x0d
482 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
483 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
484 #define IB_7322_LT_STATE_CFGENH 0x10
485 #define IB_7322_LT_STATE_CFGTEST 0x11
486 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
487 #define IB_7322_LT_STATE_CFGWAITENH 0x13
488
489 /* link state machine states from IBC */
490 #define IB_7322_L_STATE_DOWN 0x0
491 #define IB_7322_L_STATE_INIT 0x1
492 #define IB_7322_L_STATE_ARM 0x2
493 #define IB_7322_L_STATE_ACTIVE 0x3
494 #define IB_7322_L_STATE_ACT_DEFER 0x4
495
496 static const u8 qib_7322_physportstate[0x20] = {
497 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
498 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
499 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
500 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
501 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
502 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
503 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
504 [IB_7322_LT_STATE_CFGRCVFCFG] =
505 IB_PHYSPORTSTATE_CFG_TRAIN,
506 [IB_7322_LT_STATE_CFGWAITRMT] =
507 IB_PHYSPORTSTATE_CFG_TRAIN,
508 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
509 [IB_7322_LT_STATE_RECOVERRETRAIN] =
510 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
511 [IB_7322_LT_STATE_RECOVERWAITRMT] =
512 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
513 [IB_7322_LT_STATE_RECOVERIDLE] =
514 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
515 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
516 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
517 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
518 IB_PHYSPORTSTATE_CFG_TRAIN,
519 [IB_7322_LT_STATE_CFGWAITENH] =
520 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
521 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
522 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
523 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
524 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
525 };
526
527 #ifdef CONFIG_INFINIBAND_QIB_DCA
528 struct qib_irq_notify {
529 int rcv;
530 void *arg;
531 struct irq_affinity_notify notify;
532 };
533 #endif
534
535 struct qib_chip_specific {
536 u64 __iomem *cregbase;
537 u64 *cntrs;
538 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
539 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
540 u64 main_int_mask; /* clear bits which have dedicated handlers */
541 u64 int_enable_mask; /* for per port interrupts in single port mode */
542 u64 errormask;
543 u64 hwerrmask;
544 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
545 u64 gpio_mask; /* shadow the gpio mask register */
546 u64 extctrl; /* shadow the gpio output enable, etc... */
547 u32 ncntrs;
548 u32 nportcntrs;
549 u32 cntrnamelen;
550 u32 portcntrnamelen;
551 u32 numctxts;
552 u32 rcvegrcnt;
553 u32 updthresh; /* current AvailUpdThld */
554 u32 updthresh_dflt; /* default AvailUpdThld */
555 u32 r1;
556 int irq;
557 u32 num_msix_entries;
558 u32 sdmabufcnt;
559 u32 lastbuf_for_pio;
560 u32 stay_in_freeze;
561 u32 recovery_ports_initted;
562 #ifdef CONFIG_INFINIBAND_QIB_DCA
563 u32 dca_ctrl;
564 int rhdr_cpu[18];
565 int sdma_cpu[2];
566 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
567 #endif
568 struct qib_msix_entry *msix_entries;
569 unsigned long *sendchkenable;
570 unsigned long *sendgrhchk;
571 unsigned long *sendibchk;
572 u32 rcvavail_timeout[18];
573 char emsgbuf[128]; /* for device error interrupt msg buffer */
574 };
575
576 /* Table of entries in "human readable" form Tx Emphasis. */
577 struct txdds_ent {
578 u8 amp;
579 u8 pre;
580 u8 main;
581 u8 post;
582 };
583
584 struct vendor_txdds_ent {
585 u8 oui[QSFP_VOUI_LEN];
586 u8 *partnum;
587 struct txdds_ent sdr;
588 struct txdds_ent ddr;
589 struct txdds_ent qdr;
590 };
591
592 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
593
594 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
595 #define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */
596 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
597 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
598
599 #define H1_FORCE_VAL 8
600 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
601 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
602
603 /* The static and dynamic registers are paired, and the pairs indexed by spd */
604 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
605 + ((spd) * 2))
606
607 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
608 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
609 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
610 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
611 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
612
613 struct qib_chippport_specific {
614 u64 __iomem *kpregbase;
615 u64 __iomem *cpregbase;
616 u64 *portcntrs;
617 struct qib_pportdata *ppd;
618 wait_queue_head_t autoneg_wait;
619 struct delayed_work autoneg_work;
620 struct delayed_work ipg_work;
621 struct timer_list chase_timer;
622 /*
623 * these 5 fields are used to establish deltas for IB symbol
624 * errors and linkrecovery errors. They can be reported on
625 * some chips during link negotiation prior to INIT, and with
626 * DDR when faking DDR negotiations with non-IBTA switches.
627 * The chip counters are adjusted at driver unload if there is
628 * a non-zero delta.
629 */
630 u64 ibdeltainprog;
631 u64 ibsymdelta;
632 u64 ibsymsnap;
633 u64 iblnkerrdelta;
634 u64 iblnkerrsnap;
635 u64 iblnkdownsnap;
636 u64 iblnkdowndelta;
637 u64 ibmalfdelta;
638 u64 ibmalfsnap;
639 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
640 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
641 unsigned long qdr_dfe_time;
642 unsigned long chase_end;
643 u32 autoneg_tries;
644 u32 recovery_init;
645 u32 qdr_dfe_on;
646 u32 qdr_reforce;
647 /*
648 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
649 * entry zero is unused, to simplify indexing
650 */
651 u8 h1_val;
652 u8 no_eep; /* txselect table index to use if no qsfp info */
653 u8 ipg_tries;
654 u8 ibmalfusesnap;
655 struct qib_qsfp_data qsfp_data;
656 char epmsgbuf[192]; /* for port error interrupt msg buffer */
657 char sdmamsgbuf[192]; /* for per-port sdma error messages */
658 };
659
660 static struct {
661 const char *name;
662 irq_handler_t handler;
663 int lsb;
664 int port; /* 0 if not port-specific, else port # */
665 int dca;
666 } irq_table[] = {
667 { "", qib_7322intr, -1, 0, 0 },
668 { " (buf avail)", qib_7322bufavail,
669 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
670 { " (sdma 0)", sdma_intr,
671 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
672 { " (sdma 1)", sdma_intr,
673 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
674 { " (sdmaI 0)", sdma_idle_intr,
675 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
676 { " (sdmaI 1)", sdma_idle_intr,
677 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
678 { " (sdmaP 0)", sdma_progress_intr,
679 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
680 { " (sdmaP 1)", sdma_progress_intr,
681 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
682 { " (sdmaC 0)", sdma_cleanup_intr,
683 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
684 { " (sdmaC 1)", sdma_cleanup_intr,
685 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
686 };
687
688 #ifdef CONFIG_INFINIBAND_QIB_DCA
689
690 static const struct dca_reg_map {
691 int shadow_inx;
692 int lsb;
693 u64 mask;
694 u16 regno;
695 } dca_rcvhdr_reg_map[] = {
696 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
697 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
698 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
699 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
700 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
701 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
702 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
703 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
704 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
705 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
706 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
707 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
708 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
709 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
710 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
711 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
712 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
713 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
714 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
715 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
716 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
717 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
718 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
719 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
720 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
721 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
722 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
723 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
724 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
725 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
726 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
727 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
728 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
729 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
730 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
731 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
732 };
733 #endif
734
735 /* ibcctrl bits */
736 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
737 /* cycle through TS1/TS2 till OK */
738 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
739 /* wait for TS1, then go on */
740 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
741 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
742
743 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
744 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
745 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
746
747 #define BLOB_7322_IBCHG 0x101
748
749 static inline void qib_write_kreg(const struct qib_devdata *dd,
750 const u32 regno, u64 value);
751 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
752 static void write_7322_initregs(struct qib_devdata *);
753 static void write_7322_init_portregs(struct qib_pportdata *);
754 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
755 static void check_7322_rxe_status(struct qib_pportdata *);
756 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
757 #ifdef CONFIG_INFINIBAND_QIB_DCA
758 static void qib_setup_dca(struct qib_devdata *dd);
759 static void setup_dca_notifier(struct qib_devdata *dd,
760 struct qib_msix_entry *m);
761 static void reset_dca_notifier(struct qib_devdata *dd,
762 struct qib_msix_entry *m);
763 #endif
764
765 /**
766 * qib_read_ureg32 - read 32-bit virtualized per-context register
767 * @dd: device
768 * @regno: register number
769 * @ctxt: context number
770 *
771 * Return the contents of a register that is virtualized to be per context.
772 * Returns -1 on errors (not distinguishable from valid contents at
773 * runtime; we may add a separate error variable at some point).
774 */
775 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
776 enum qib_ureg regno, int ctxt)
777 {
778 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
779 return 0;
780 return readl(regno + (u64 __iomem *)(
781 (dd->ureg_align * ctxt) + (dd->userbase ?
782 (char __iomem *)dd->userbase :
783 (char __iomem *)dd->kregbase + dd->uregbase)));
784 }
785
786 /**
787 * qib_read_ureg - read virtualized per-context register
788 * @dd: device
789 * @regno: register number
790 * @ctxt: context number
791 *
792 * Return the contents of a register that is virtualized to be per context.
793 * Returns -1 on errors (not distinguishable from valid contents at
794 * runtime; we may add a separate error variable at some point).
795 */
796 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
797 enum qib_ureg regno, int ctxt)
798 {
799
800 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
801 return 0;
802 return readq(regno + (u64 __iomem *)(
803 (dd->ureg_align * ctxt) + (dd->userbase ?
804 (char __iomem *)dd->userbase :
805 (char __iomem *)dd->kregbase + dd->uregbase)));
806 }
807
808 /**
809 * qib_write_ureg - write virtualized per-context register
810 * @dd: device
811 * @regno: register number
812 * @value: value
813 * @ctxt: context
814 *
815 * Write the contents of a register that is virtualized to be per context.
816 */
817 static inline void qib_write_ureg(const struct qib_devdata *dd,
818 enum qib_ureg regno, u64 value, int ctxt)
819 {
820 u64 __iomem *ubase;
821
822 if (dd->userbase)
823 ubase = (u64 __iomem *)
824 ((char __iomem *) dd->userbase +
825 dd->ureg_align * ctxt);
826 else
827 ubase = (u64 __iomem *)
828 (dd->uregbase +
829 (char __iomem *) dd->kregbase +
830 dd->ureg_align * ctxt);
831
832 if (dd->kregbase && (dd->flags & QIB_PRESENT))
833 writeq(value, &ubase[regno]);
834 }
835
836 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
837 const u32 regno)
838 {
839 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
840 return -1;
841 return readl((u32 __iomem *) &dd->kregbase[regno]);
842 }
843
844 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
845 const u32 regno)
846 {
847 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
848 return -1;
849 return readq(&dd->kregbase[regno]);
850 }
851
852 static inline void qib_write_kreg(const struct qib_devdata *dd,
853 const u32 regno, u64 value)
854 {
855 if (dd->kregbase && (dd->flags & QIB_PRESENT))
856 writeq(value, &dd->kregbase[regno]);
857 }
858
859 /*
860 * not many sanity checks for the port-specific kernel register routines,
861 * since they are only used when it's known to be safe.
862 */
863 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
864 const u16 regno)
865 {
866 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
867 return 0ULL;
868 return readq(&ppd->cpspec->kpregbase[regno]);
869 }
870
871 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
872 const u16 regno, u64 value)
873 {
874 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
875 (ppd->dd->flags & QIB_PRESENT))
876 writeq(value, &ppd->cpspec->kpregbase[regno]);
877 }
878
879 /**
880 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
881 * @dd: the qlogic_ib device
882 * @regno: the register number to write
883 * @ctxt: the context containing the register
884 * @value: the value to write
885 */
886 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
887 const u16 regno, unsigned ctxt,
888 u64 value)
889 {
890 qib_write_kreg(dd, regno + ctxt, value);
891 }
892
893 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
894 {
895 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
896 return 0;
897 return readq(&dd->cspec->cregbase[regno]);
898
899
900 }
901
902 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
903 {
904 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
905 return 0;
906 return readl(&dd->cspec->cregbase[regno]);
907
908
909 }
910
911 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
912 u16 regno, u64 value)
913 {
914 if (ppd->cpspec && ppd->cpspec->cpregbase &&
915 (ppd->dd->flags & QIB_PRESENT))
916 writeq(value, &ppd->cpspec->cpregbase[regno]);
917 }
918
919 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
920 u16 regno)
921 {
922 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
923 !(ppd->dd->flags & QIB_PRESENT))
924 return 0;
925 return readq(&ppd->cpspec->cpregbase[regno]);
926 }
927
928 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
929 u16 regno)
930 {
931 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
932 !(ppd->dd->flags & QIB_PRESENT))
933 return 0;
934 return readl(&ppd->cpspec->cpregbase[regno]);
935 }
936
937 /* bits in Control register */
938 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
939 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
940
941 /* bits in general interrupt regs */
942 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
943 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
944 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
945 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
946 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
947 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
948 #define QIB_I_C_ERROR INT_MASK(Err)
949
950 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
951 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
952 #define QIB_I_GPIO INT_MASK(AssertGPIO)
953 #define QIB_I_P_SDMAINT(pidx) \
954 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
955 INT_MASK_P(SDmaProgress, pidx) | \
956 INT_MASK_PM(SDmaCleanupDone, pidx))
957
958 /* Interrupt bits that are "per port" */
959 #define QIB_I_P_BITSEXTANT(pidx) \
960 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
961 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
962 INT_MASK_P(SDmaProgress, pidx) | \
963 INT_MASK_PM(SDmaCleanupDone, pidx))
964
965 /* Interrupt bits that are common to a device */
966 /* currently unused: QIB_I_SPIOSENT */
967 #define QIB_I_C_BITSEXTANT \
968 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
969 QIB_I_SPIOSENT | \
970 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
971
972 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
973 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
974
975 /*
976 * Error bits that are "per port".
977 */
978 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
979 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
980 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
981 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
982 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
983 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
984 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
985 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
986 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
987 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
988 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
989 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
990 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
991 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
992 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
993 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
994 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
995 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
996 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
997 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
998 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
999 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
1000 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
1001 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
1002 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
1003 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
1004 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
1005 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
1006
1007 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
1008 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
1009 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
1010 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
1011 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
1012 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
1013 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
1014 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
1015 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
1016 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
1017 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
1018
1019 /* Error bits that are common to a device */
1020 #define QIB_E_RESET ERR_MASK(ResetNegated)
1021 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
1022 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
1023
1024
1025 /*
1026 * Per chip (rather than per-port) errors. Most either do
1027 * nothing but trigger a print (because they self-recover, or
1028 * always occur in tandem with other errors that handle the
1029 * issue), or because they indicate errors with no recovery,
1030 * but we want to know that they happened.
1031 */
1032 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
1033 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
1034 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
1035 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
1036 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
1037 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
1038 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
1039 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
1040
1041 /* SDMA chip errors (not per port)
1042 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
1043 * the SDMAHALT error immediately, so we just print the dup error via the
1044 * E_AUTO mechanism. This is true of most of the per-port fatal errors
1045 * as well, but since this is port-independent, by definition, it's
1046 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
1047 * packet send errors, and so are handled in the same manner as other
1048 * per-packet errors.
1049 */
1050 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
1051 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
1052 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
1053
1054 /*
1055 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
1056 * it is used to print "common" packet errors.
1057 */
1058 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
1059 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
1060 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
1061 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1062 QIB_E_P_REBP)
1063
1064 /* Error Bits that Packet-related (Receive, per-port) */
1065 #define QIB_E_P_RPKTERRS (\
1066 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
1067 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
1068 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
1069 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
1070 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
1071 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
1072
1073 /*
1074 * Error bits that are Send-related (per port)
1075 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
1076 * All of these potentially need to have a buffer disarmed
1077 */
1078 #define QIB_E_P_SPKTERRS (\
1079 QIB_E_P_SUNEXP_PKTNUM |\
1080 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1081 QIB_E_P_SMAXPKTLEN |\
1082 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1083 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1084 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1085
1086 #define QIB_E_SPKTERRS ( \
1087 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1088 ERR_MASK_N(SendUnsupportedVLErr) | \
1089 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1090
1091 #define QIB_E_P_SDMAERRS ( \
1092 QIB_E_P_SDMAHALT | \
1093 QIB_E_P_SDMADESCADDRMISALIGN | \
1094 QIB_E_P_SDMAUNEXPDATA | \
1095 QIB_E_P_SDMAMISSINGDW | \
1096 QIB_E_P_SDMADWEN | \
1097 QIB_E_P_SDMARPYTAG | \
1098 QIB_E_P_SDMA1STDESC | \
1099 QIB_E_P_SDMABASE | \
1100 QIB_E_P_SDMATAILOUTOFBOUND | \
1101 QIB_E_P_SDMAOUTOFBOUND | \
1102 QIB_E_P_SDMAGENMISMATCH)
1103
1104 /*
1105 * This sets some bits more than once, but makes it more obvious which
1106 * bits are not handled under other categories, and the repeat definition
1107 * is not a problem.
1108 */
1109 #define QIB_E_P_BITSEXTANT ( \
1110 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1111 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1112 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1113 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1114 )
1115
1116 /*
1117 * These are errors that can occur when the link
1118 * changes state while a packet is being sent or received. This doesn't
1119 * cover things like EBP or VCRC that can be the result of a sending
1120 * having the link change state, so we receive a "known bad" packet.
1121 * All of these are "per port", so renamed:
1122 */
1123 #define QIB_E_P_LINK_PKTERRS (\
1124 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1125 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1126 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1127 QIB_E_P_RUNEXPCHAR)
1128
1129 /*
1130 * This sets some bits more than once, but makes it more obvious which
1131 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1132 * and the repeat definition is not a problem.
1133 */
1134 #define QIB_E_C_BITSEXTANT (\
1135 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1136 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1137 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1138
1139 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1140 #define E_SPKT_ERRS_IGNORE 0
1141
1142 #define QIB_EXTS_MEMBIST_DISABLED \
1143 SYM_MASK(EXTStatus, MemBISTDisabled)
1144 #define QIB_EXTS_MEMBIST_ENDTEST \
1145 SYM_MASK(EXTStatus, MemBISTEndTest)
1146
1147 #define QIB_E_SPIOARMLAUNCH \
1148 ERR_MASK(SendArmLaunchErr)
1149
1150 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1151 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1152
1153 /*
1154 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1155 * and also if forced QDR (only QDR enabled). It's enabled for the
1156 * forced QDR case so that scrambling will be enabled by the TS3
1157 * exchange, when supported by both sides of the link.
1158 */
1159 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1160 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1161 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1162 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1163 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1164 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1165 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1166 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1167
1168 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1169 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1170
1171 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1172 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1173 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1174
1175 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1176 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1177 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1178 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1179 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1180 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1181 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1182
1183 #define IBA7322_REDIRECT_VEC_PER_REG 12
1184
1185 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1186 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1187 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1188 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1189 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1190
1191 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1192
1193 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1194 .msg = #fldname , .sz = sizeof(#fldname) }
1195 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1196 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1197 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1198 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1199 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1200 HWE_AUTO(PCIESerdesPClkNotDetect),
1201 HWE_AUTO(PowerOnBISTFailed),
1202 HWE_AUTO(TempsenseTholdReached),
1203 HWE_AUTO(MemoryErr),
1204 HWE_AUTO(PCIeBusParityErr),
1205 HWE_AUTO(PcieCplTimeout),
1206 HWE_AUTO(PciePoisonedTLP),
1207 HWE_AUTO_P(SDmaMemReadErr, 1),
1208 HWE_AUTO_P(SDmaMemReadErr, 0),
1209 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1210 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1211 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1212 HWE_AUTO(statusValidNoEop),
1213 HWE_AUTO(LATriggered),
1214 { .mask = 0, .sz = 0 }
1215 };
1216
1217 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1218 .msg = #fldname, .sz = sizeof(#fldname) }
1219 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1220 .msg = #fldname, .sz = sizeof(#fldname) }
1221 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1222 E_AUTO(RcvEgrFullErr),
1223 E_AUTO(RcvHdrFullErr),
1224 E_AUTO(ResetNegated),
1225 E_AUTO(HardwareErr),
1226 E_AUTO(InvalidAddrErr),
1227 E_AUTO(SDmaVL15Err),
1228 E_AUTO(SBufVL15MisUseErr),
1229 E_AUTO(InvalidEEPCmd),
1230 E_AUTO(RcvContextShareErr),
1231 E_AUTO(SendVLMismatchErr),
1232 E_AUTO(SendArmLaunchErr),
1233 E_AUTO(SendSpecialTriggerErr),
1234 E_AUTO(SDmaWrongPortErr),
1235 E_AUTO(SDmaBufMaskDuplicateErr),
1236 { .mask = 0, .sz = 0 }
1237 };
1238
1239 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1240 E_P_AUTO(IBStatusChanged),
1241 E_P_AUTO(SHeadersErr),
1242 E_P_AUTO(VL15BufMisuseErr),
1243 /*
1244 * SDmaHaltErr is not really an error, make it clearer;
1245 */
1246 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1247 .sz = 11},
1248 E_P_AUTO(SDmaDescAddrMisalignErr),
1249 E_P_AUTO(SDmaUnexpDataErr),
1250 E_P_AUTO(SDmaMissingDwErr),
1251 E_P_AUTO(SDmaDwEnErr),
1252 E_P_AUTO(SDmaRpyTagErr),
1253 E_P_AUTO(SDma1stDescErr),
1254 E_P_AUTO(SDmaBaseErr),
1255 E_P_AUTO(SDmaTailOutOfBoundErr),
1256 E_P_AUTO(SDmaOutOfBoundErr),
1257 E_P_AUTO(SDmaGenMismatchErr),
1258 E_P_AUTO(SendBufMisuseErr),
1259 E_P_AUTO(SendUnsupportedVLErr),
1260 E_P_AUTO(SendUnexpectedPktNumErr),
1261 E_P_AUTO(SendDroppedDataPktErr),
1262 E_P_AUTO(SendDroppedSmpPktErr),
1263 E_P_AUTO(SendPktLenErr),
1264 E_P_AUTO(SendUnderRunErr),
1265 E_P_AUTO(SendMaxPktLenErr),
1266 E_P_AUTO(SendMinPktLenErr),
1267 E_P_AUTO(RcvIBLostLinkErr),
1268 E_P_AUTO(RcvHdrErr),
1269 E_P_AUTO(RcvHdrLenErr),
1270 E_P_AUTO(RcvBadTidErr),
1271 E_P_AUTO(RcvBadVersionErr),
1272 E_P_AUTO(RcvIBFlowErr),
1273 E_P_AUTO(RcvEBPErr),
1274 E_P_AUTO(RcvUnsupportedVLErr),
1275 E_P_AUTO(RcvUnexpectedCharErr),
1276 E_P_AUTO(RcvShortPktLenErr),
1277 E_P_AUTO(RcvLongPktLenErr),
1278 E_P_AUTO(RcvMaxPktLenErr),
1279 E_P_AUTO(RcvMinPktLenErr),
1280 E_P_AUTO(RcvICRCErr),
1281 E_P_AUTO(RcvVCRCErr),
1282 E_P_AUTO(RcvFormatErr),
1283 { .mask = 0, .sz = 0 }
1284 };
1285
1286 /*
1287 * Below generates "auto-message" for interrupts not specific to any port or
1288 * context
1289 */
1290 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1291 .msg = #fldname, .sz = sizeof(#fldname) }
1292 /* Below generates "auto-message" for interrupts specific to a port */
1293 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1294 SYM_LSB(IntMask, fldname##Mask##_0), \
1295 SYM_LSB(IntMask, fldname##Mask##_1)), \
1296 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1297 /* For some reason, the SerDesTrimDone bits are reversed */
1298 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1299 SYM_LSB(IntMask, fldname##Mask##_1), \
1300 SYM_LSB(IntMask, fldname##Mask##_0)), \
1301 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1302 /*
1303 * Below generates "auto-message" for interrupts specific to a context,
1304 * with ctxt-number appended
1305 */
1306 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1307 SYM_LSB(IntMask, fldname##0IntMask), \
1308 SYM_LSB(IntMask, fldname##17IntMask)), \
1309 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1310
1311 #define TXSYMPTOM_AUTO_P(fldname) \
1312 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1313 .msg = #fldname, .sz = sizeof(#fldname) }
1314 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1315 TXSYMPTOM_AUTO_P(NonKeyPacket),
1316 TXSYMPTOM_AUTO_P(GRHFail),
1317 TXSYMPTOM_AUTO_P(PkeyFail),
1318 TXSYMPTOM_AUTO_P(QPFail),
1319 TXSYMPTOM_AUTO_P(SLIDFail),
1320 TXSYMPTOM_AUTO_P(RawIPV6),
1321 TXSYMPTOM_AUTO_P(PacketTooSmall),
1322 { .mask = 0, .sz = 0 }
1323 };
1324
1325 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1326
1327 /*
1328 * Called when we might have an error that is specific to a particular
1329 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1330 * because we don't need to force the update of pioavail
1331 */
1332 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1333 {
1334 struct qib_devdata *dd = ppd->dd;
1335 u32 i;
1336 int any;
1337 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1338 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1339 unsigned long sbuf[4];
1340
1341 /*
1342 * It's possible that sendbuffererror could have bits set; might
1343 * have already done this as a result of hardware error handling.
1344 */
1345 any = 0;
1346 for (i = 0; i < regcnt; ++i) {
1347 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1348 if (sbuf[i]) {
1349 any = 1;
1350 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1351 }
1352 }
1353
1354 if (any)
1355 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1356 }
1357
1358 /* No txe_recover yet, if ever */
1359
1360 /* No decode__errors yet */
1361 static void err_decode(char *msg, size_t len, u64 errs,
1362 const struct qib_hwerror_msgs *msp)
1363 {
1364 u64 these, lmask;
1365 int took, multi, n = 0;
1366
1367 while (errs && msp && msp->mask) {
1368 multi = (msp->mask & (msp->mask - 1));
1369 while (errs & msp->mask) {
1370 these = (errs & msp->mask);
1371 lmask = (these & (these - 1)) ^ these;
1372 if (len) {
1373 if (n++) {
1374 /* separate the strings */
1375 *msg++ = ',';
1376 len--;
1377 }
1378 BUG_ON(!msp->sz);
1379 /* msp->sz counts the nul */
1380 took = min_t(size_t, msp->sz - (size_t)1, len);
1381 memcpy(msg, msp->msg, took);
1382 len -= took;
1383 msg += took;
1384 if (len)
1385 *msg = '\0';
1386 }
1387 errs &= ~lmask;
1388 if (len && multi) {
1389 /* More than one bit this mask */
1390 int idx = -1;
1391
1392 while (lmask & msp->mask) {
1393 ++idx;
1394 lmask >>= 1;
1395 }
1396 took = scnprintf(msg, len, "_%d", idx);
1397 len -= took;
1398 msg += took;
1399 }
1400 }
1401 ++msp;
1402 }
1403 /* If some bits are left, show in hex. */
1404 if (len && errs)
1405 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1406 (unsigned long long) errs);
1407 }
1408
1409 /* only called if r1 set */
1410 static void flush_fifo(struct qib_pportdata *ppd)
1411 {
1412 struct qib_devdata *dd = ppd->dd;
1413 u32 __iomem *piobuf;
1414 u32 bufn;
1415 u32 *hdr;
1416 u64 pbc;
1417 const unsigned hdrwords = 7;
1418 static struct qib_ib_header ibhdr = {
1419 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1420 .lrh[1] = IB_LID_PERMISSIVE,
1421 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1422 .lrh[3] = IB_LID_PERMISSIVE,
1423 .u.oth.bth[0] = cpu_to_be32(
1424 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1425 .u.oth.bth[1] = cpu_to_be32(0),
1426 .u.oth.bth[2] = cpu_to_be32(0),
1427 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1428 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1429 };
1430
1431 /*
1432 * Send a dummy VL15 packet to flush the launch FIFO.
1433 * This will not actually be sent since the TxeBypassIbc bit is set.
1434 */
1435 pbc = PBC_7322_VL15_SEND |
1436 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1437 (hdrwords + SIZE_OF_CRC);
1438 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1439 if (!piobuf)
1440 return;
1441 writeq(pbc, piobuf);
1442 hdr = (u32 *) &ibhdr;
1443 if (dd->flags & QIB_PIO_FLUSH_WC) {
1444 qib_flush_wc();
1445 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1446 qib_flush_wc();
1447 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1448 qib_flush_wc();
1449 } else
1450 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1451 qib_sendbuf_done(dd, bufn);
1452 }
1453
1454 /*
1455 * This is called with interrupts disabled and sdma_lock held.
1456 */
1457 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1458 {
1459 struct qib_devdata *dd = ppd->dd;
1460 u64 set_sendctrl = 0;
1461 u64 clr_sendctrl = 0;
1462
1463 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1464 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1465 else
1466 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1467
1468 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1469 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1470 else
1471 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1472
1473 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1474 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1475 else
1476 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1477
1478 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1479 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1480 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1481 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1482 else
1483 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1484 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1485 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1486
1487 spin_lock(&dd->sendctrl_lock);
1488
1489 /* If we are draining everything, block sends first */
1490 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1491 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1492 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1493 qib_write_kreg(dd, kr_scratch, 0);
1494 }
1495
1496 ppd->p_sendctrl |= set_sendctrl;
1497 ppd->p_sendctrl &= ~clr_sendctrl;
1498
1499 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1500 qib_write_kreg_port(ppd, krp_sendctrl,
1501 ppd->p_sendctrl |
1502 SYM_MASK(SendCtrl_0, SDmaCleanup));
1503 else
1504 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1505 qib_write_kreg(dd, kr_scratch, 0);
1506
1507 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1508 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1509 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1510 qib_write_kreg(dd, kr_scratch, 0);
1511 }
1512
1513 spin_unlock(&dd->sendctrl_lock);
1514
1515 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1516 flush_fifo(ppd);
1517 }
1518
1519 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1520 {
1521 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1522 }
1523
1524 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1525 {
1526 /*
1527 * Set SendDmaLenGen and clear and set
1528 * the MSB of the generation count to enable generation checking
1529 * and load the internal generation counter.
1530 */
1531 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1532 qib_write_kreg_port(ppd, krp_senddmalengen,
1533 ppd->sdma_descq_cnt |
1534 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1535 }
1536
1537 /*
1538 * Must be called with sdma_lock held, or before init finished.
1539 */
1540 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1541 {
1542 /* Commit writes to memory and advance the tail on the chip */
1543 wmb();
1544 ppd->sdma_descq_tail = tail;
1545 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1546 }
1547
1548 /*
1549 * This is called with interrupts disabled and sdma_lock held.
1550 */
1551 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1552 {
1553 /*
1554 * Drain all FIFOs.
1555 * The hardware doesn't require this but we do it so that verbs
1556 * and user applications don't wait for link active to send stale
1557 * data.
1558 */
1559 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1560
1561 qib_sdma_7322_setlengen(ppd);
1562 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1563 ppd->sdma_head_dma[0] = 0;
1564 qib_7322_sdma_sendctrl(ppd,
1565 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1566 }
1567
1568 #define DISABLES_SDMA ( \
1569 QIB_E_P_SDMAHALT | \
1570 QIB_E_P_SDMADESCADDRMISALIGN | \
1571 QIB_E_P_SDMAMISSINGDW | \
1572 QIB_E_P_SDMADWEN | \
1573 QIB_E_P_SDMARPYTAG | \
1574 QIB_E_P_SDMA1STDESC | \
1575 QIB_E_P_SDMABASE | \
1576 QIB_E_P_SDMATAILOUTOFBOUND | \
1577 QIB_E_P_SDMAOUTOFBOUND | \
1578 QIB_E_P_SDMAGENMISMATCH)
1579
1580 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1581 {
1582 unsigned long flags;
1583 struct qib_devdata *dd = ppd->dd;
1584
1585 errs &= QIB_E_P_SDMAERRS;
1586 err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf),
1587 errs, qib_7322p_error_msgs);
1588
1589 if (errs & QIB_E_P_SDMAUNEXPDATA)
1590 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1591 ppd->port);
1592
1593 spin_lock_irqsave(&ppd->sdma_lock, flags);
1594
1595 if (errs != QIB_E_P_SDMAHALT) {
1596 /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */
1597 qib_dev_porterr(dd, ppd->port,
1598 "SDMA %s 0x%016llx %s\n",
1599 qib_sdma_state_names[ppd->sdma_state.current_state],
1600 errs, ppd->cpspec->sdmamsgbuf);
1601 dump_sdma_7322_state(ppd);
1602 }
1603
1604 switch (ppd->sdma_state.current_state) {
1605 case qib_sdma_state_s00_hw_down:
1606 break;
1607
1608 case qib_sdma_state_s10_hw_start_up_wait:
1609 if (errs & QIB_E_P_SDMAHALT)
1610 __qib_sdma_process_event(ppd,
1611 qib_sdma_event_e20_hw_started);
1612 break;
1613
1614 case qib_sdma_state_s20_idle:
1615 break;
1616
1617 case qib_sdma_state_s30_sw_clean_up_wait:
1618 break;
1619
1620 case qib_sdma_state_s40_hw_clean_up_wait:
1621 if (errs & QIB_E_P_SDMAHALT)
1622 __qib_sdma_process_event(ppd,
1623 qib_sdma_event_e50_hw_cleaned);
1624 break;
1625
1626 case qib_sdma_state_s50_hw_halt_wait:
1627 if (errs & QIB_E_P_SDMAHALT)
1628 __qib_sdma_process_event(ppd,
1629 qib_sdma_event_e60_hw_halted);
1630 break;
1631
1632 case qib_sdma_state_s99_running:
1633 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1634 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1635 break;
1636 }
1637
1638 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1639 }
1640
1641 /*
1642 * handle per-device errors (not per-port errors)
1643 */
1644 static noinline void handle_7322_errors(struct qib_devdata *dd)
1645 {
1646 char *msg;
1647 u64 iserr = 0;
1648 u64 errs;
1649 u64 mask;
1650 int log_idx;
1651
1652 qib_stats.sps_errints++;
1653 errs = qib_read_kreg64(dd, kr_errstatus);
1654 if (!errs) {
1655 qib_devinfo(dd->pcidev,
1656 "device error interrupt, but no error bits set!\n");
1657 goto done;
1658 }
1659
1660 /* don't report errors that are masked */
1661 errs &= dd->cspec->errormask;
1662 msg = dd->cspec->emsgbuf;
1663
1664 /* do these first, they are most important */
1665 if (errs & QIB_E_HARDWARE) {
1666 *msg = '\0';
1667 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1668 } else
1669 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1670 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1671 qib_inc_eeprom_err(dd, log_idx, 1);
1672
1673 if (errs & QIB_E_SPKTERRS) {
1674 qib_disarm_7322_senderrbufs(dd->pport);
1675 qib_stats.sps_txerrs++;
1676 } else if (errs & QIB_E_INVALIDADDR)
1677 qib_stats.sps_txerrs++;
1678 else if (errs & QIB_E_ARMLAUNCH) {
1679 qib_stats.sps_txerrs++;
1680 qib_disarm_7322_senderrbufs(dd->pport);
1681 }
1682 qib_write_kreg(dd, kr_errclear, errs);
1683
1684 /*
1685 * The ones we mask off are handled specially below
1686 * or above. Also mask SDMADISABLED by default as it
1687 * is too chatty.
1688 */
1689 mask = QIB_E_HARDWARE;
1690 *msg = '\0';
1691
1692 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
1693 qib_7322error_msgs);
1694
1695 /*
1696 * Getting reset is a tragedy for all ports. Mark the device
1697 * _and_ the ports as "offline" in way meaningful to each.
1698 */
1699 if (errs & QIB_E_RESET) {
1700 int pidx;
1701
1702 qib_dev_err(dd,
1703 "Got reset, requires re-init (unload and reload driver)\n");
1704 dd->flags &= ~QIB_INITTED; /* needs re-init */
1705 /* mark as having had error */
1706 *dd->devstatusp |= QIB_STATUS_HWERROR;
1707 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1708 if (dd->pport[pidx].link_speed_supported)
1709 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1710 }
1711
1712 if (*msg && iserr)
1713 qib_dev_err(dd, "%s error\n", msg);
1714
1715 /*
1716 * If there were hdrq or egrfull errors, wake up any processes
1717 * waiting in poll. We used to try to check which contexts had
1718 * the overflow, but given the cost of that and the chip reads
1719 * to support it, it's better to just wake everybody up if we
1720 * get an overflow; waiters can poll again if it's not them.
1721 */
1722 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1723 qib_handle_urcv(dd, ~0U);
1724 if (errs & ERR_MASK(RcvEgrFullErr))
1725 qib_stats.sps_buffull++;
1726 else
1727 qib_stats.sps_hdrfull++;
1728 }
1729
1730 done:
1731 return;
1732 }
1733
1734 static void qib_error_tasklet(unsigned long data)
1735 {
1736 struct qib_devdata *dd = (struct qib_devdata *)data;
1737
1738 handle_7322_errors(dd);
1739 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1740 }
1741
1742 static void reenable_chase(unsigned long opaque)
1743 {
1744 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1745
1746 ppd->cpspec->chase_timer.expires = 0;
1747 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1748 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1749 }
1750
1751 static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
1752 u8 ibclt)
1753 {
1754 ppd->cpspec->chase_end = 0;
1755
1756 if (!qib_chase)
1757 return;
1758
1759 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1760 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1761 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1762 add_timer(&ppd->cpspec->chase_timer);
1763 }
1764
1765 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1766 {
1767 u8 ibclt;
1768 unsigned long tnow;
1769
1770 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1771
1772 /*
1773 * Detect and handle the state chase issue, where we can
1774 * get stuck if we are unlucky on timing on both sides of
1775 * the link. If we are, we disable, set a timer, and
1776 * then re-enable.
1777 */
1778 switch (ibclt) {
1779 case IB_7322_LT_STATE_CFGRCVFCFG:
1780 case IB_7322_LT_STATE_CFGWAITRMT:
1781 case IB_7322_LT_STATE_TXREVLANES:
1782 case IB_7322_LT_STATE_CFGENH:
1783 tnow = jiffies;
1784 if (ppd->cpspec->chase_end &&
1785 time_after(tnow, ppd->cpspec->chase_end))
1786 disable_chase(ppd, tnow, ibclt);
1787 else if (!ppd->cpspec->chase_end)
1788 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1789 break;
1790 default:
1791 ppd->cpspec->chase_end = 0;
1792 break;
1793 }
1794
1795 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1796 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1797 ibclt == IB_7322_LT_STATE_LINKUP) &&
1798 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1799 force_h1(ppd);
1800 ppd->cpspec->qdr_reforce = 1;
1801 if (!ppd->dd->cspec->r1)
1802 serdes_7322_los_enable(ppd, 0);
1803 } else if (ppd->cpspec->qdr_reforce &&
1804 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1805 (ibclt == IB_7322_LT_STATE_CFGENH ||
1806 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1807 ibclt == IB_7322_LT_STATE_LINKUP))
1808 force_h1(ppd);
1809
1810 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1811 ppd->link_speed_enabled == QIB_IB_QDR &&
1812 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1813 ibclt == IB_7322_LT_STATE_CFGENH ||
1814 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1815 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1816 adj_tx_serdes(ppd);
1817
1818 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1819 u8 ltstate = qib_7322_phys_portstate(ibcst);
1820 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1821 LinkTrainingState);
1822 if (!ppd->dd->cspec->r1 &&
1823 pibclt == IB_7322_LT_STATE_LINKUP &&
1824 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1825 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1826 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1827 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1828 /* If the link went down (but no into recovery,
1829 * turn LOS back on */
1830 serdes_7322_los_enable(ppd, 1);
1831 if (!ppd->cpspec->qdr_dfe_on &&
1832 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1833 ppd->cpspec->qdr_dfe_on = 1;
1834 ppd->cpspec->qdr_dfe_time = 0;
1835 /* On link down, reenable QDR adaptation */
1836 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1837 ppd->dd->cspec->r1 ?
1838 QDR_STATIC_ADAPT_DOWN_R1 :
1839 QDR_STATIC_ADAPT_DOWN);
1840 pr_info(
1841 "IB%u:%u re-enabled QDR adaptation ibclt %x\n",
1842 ppd->dd->unit, ppd->port, ibclt);
1843 }
1844 }
1845 }
1846
1847 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1848
1849 /*
1850 * This is per-pport error handling.
1851 * will likely get it's own MSIx interrupt (one for each port,
1852 * although just a single handler).
1853 */
1854 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1855 {
1856 char *msg;
1857 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1858 struct qib_devdata *dd = ppd->dd;
1859
1860 /* do this as soon as possible */
1861 fmask = qib_read_kreg64(dd, kr_act_fmask);
1862 if (!fmask)
1863 check_7322_rxe_status(ppd);
1864
1865 errs = qib_read_kreg_port(ppd, krp_errstatus);
1866 if (!errs)
1867 qib_devinfo(dd->pcidev,
1868 "Port%d error interrupt, but no error bits set!\n",
1869 ppd->port);
1870 if (!fmask)
1871 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1872 if (!errs)
1873 goto done;
1874
1875 msg = ppd->cpspec->epmsgbuf;
1876 *msg = '\0';
1877
1878 if (errs & ~QIB_E_P_BITSEXTANT) {
1879 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
1880 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1881 if (!*msg)
1882 snprintf(msg, sizeof(ppd->cpspec->epmsgbuf),
1883 "no others");
1884 qib_dev_porterr(dd, ppd->port,
1885 "error interrupt with unknown errors 0x%016Lx set (and %s)\n",
1886 (errs & ~QIB_E_P_BITSEXTANT), msg);
1887 *msg = '\0';
1888 }
1889
1890 if (errs & QIB_E_P_SHDR) {
1891 u64 symptom;
1892
1893 /* determine cause, then write to clear */
1894 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1895 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1896 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom,
1897 hdrchk_msgs);
1898 *msg = '\0';
1899 /* senderrbuf cleared in SPKTERRS below */
1900 }
1901
1902 if (errs & QIB_E_P_SPKTERRS) {
1903 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1904 !(ppd->lflags & QIBL_LINKACTIVE)) {
1905 /*
1906 * This can happen when trying to bring the link
1907 * up, but the IB link changes state at the "wrong"
1908 * time. The IB logic then complains that the packet
1909 * isn't valid. We don't want to confuse people, so
1910 * we just don't print them, except at debug
1911 */
1912 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
1913 (errs & QIB_E_P_LINK_PKTERRS),
1914 qib_7322p_error_msgs);
1915 *msg = '\0';
1916 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1917 }
1918 qib_disarm_7322_senderrbufs(ppd);
1919 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1920 !(ppd->lflags & QIBL_LINKACTIVE)) {
1921 /*
1922 * This can happen when SMA is trying to bring the link
1923 * up, but the IB link changes state at the "wrong" time.
1924 * The IB logic then complains that the packet isn't
1925 * valid. We don't want to confuse people, so we just
1926 * don't print them, except at debug
1927 */
1928 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs,
1929 qib_7322p_error_msgs);
1930 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1931 *msg = '\0';
1932 }
1933
1934 qib_write_kreg_port(ppd, krp_errclear, errs);
1935
1936 errs &= ~ignore_this_time;
1937 if (!errs)
1938 goto done;
1939
1940 if (errs & QIB_E_P_RPKTERRS)
1941 qib_stats.sps_rcverrs++;
1942 if (errs & QIB_E_P_SPKTERRS)
1943 qib_stats.sps_txerrs++;
1944
1945 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1946
1947 if (errs & QIB_E_P_SDMAERRS)
1948 sdma_7322_p_errors(ppd, errs);
1949
1950 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1951 u64 ibcs;
1952 u8 ltstate;
1953
1954 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1955 ltstate = qib_7322_phys_portstate(ibcs);
1956
1957 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1958 handle_serdes_issues(ppd, ibcs);
1959 if (!(ppd->cpspec->ibcctrl_a &
1960 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1961 /*
1962 * We got our interrupt, so init code should be
1963 * happy and not try alternatives. Now squelch
1964 * other "chatter" from link-negotiation (pre Init)
1965 */
1966 ppd->cpspec->ibcctrl_a |=
1967 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1968 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1969 ppd->cpspec->ibcctrl_a);
1970 }
1971
1972 /* Update our picture of width and speed from chip */
1973 ppd->link_width_active =
1974 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1975 IB_WIDTH_4X : IB_WIDTH_1X;
1976 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1977 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1978 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1979 QIB_IB_DDR : QIB_IB_SDR;
1980
1981 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1982 IB_PHYSPORTSTATE_DISABLED)
1983 qib_set_ib_7322_lstate(ppd, 0,
1984 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1985 else
1986 /*
1987 * Since going into a recovery state causes the link
1988 * state to go down and since recovery is transitory,
1989 * it is better if we "miss" ever seeing the link
1990 * training state go into recovery (i.e., ignore this
1991 * transition for link state special handling purposes)
1992 * without updating lastibcstat.
1993 */
1994 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1995 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1996 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1997 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1998 qib_handle_e_ibstatuschanged(ppd, ibcs);
1999 }
2000 if (*msg && iserr)
2001 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
2002
2003 if (ppd->state_wanted & ppd->lflags)
2004 wake_up_interruptible(&ppd->state_wait);
2005 done:
2006 return;
2007 }
2008
2009 /* enable/disable chip from delivering interrupts */
2010 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
2011 {
2012 if (enable) {
2013 if (dd->flags & QIB_BADINTR)
2014 return;
2015 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
2016 /* cause any pending enabled interrupts to be re-delivered */
2017 qib_write_kreg(dd, kr_intclear, 0ULL);
2018 if (dd->cspec->num_msix_entries) {
2019 /* and same for MSIx */
2020 u64 val = qib_read_kreg64(dd, kr_intgranted);
2021
2022 if (val)
2023 qib_write_kreg(dd, kr_intgranted, val);
2024 }
2025 } else
2026 qib_write_kreg(dd, kr_intmask, 0ULL);
2027 }
2028
2029 /*
2030 * Try to cleanup as much as possible for anything that might have gone
2031 * wrong while in freeze mode, such as pio buffers being written by user
2032 * processes (causing armlaunch), send errors due to going into freeze mode,
2033 * etc., and try to avoid causing extra interrupts while doing so.
2034 * Forcibly update the in-memory pioavail register copies after cleanup
2035 * because the chip won't do it while in freeze mode (the register values
2036 * themselves are kept correct).
2037 * Make sure that we don't lose any important interrupts by using the chip
2038 * feature that says that writing 0 to a bit in *clear that is set in
2039 * *status will cause an interrupt to be generated again (if allowed by
2040 * the *mask value).
2041 * This is in chip-specific code because of all of the register accesses,
2042 * even though the details are similar on most chips.
2043 */
2044 static void qib_7322_clear_freeze(struct qib_devdata *dd)
2045 {
2046 int pidx;
2047
2048 /* disable error interrupts, to avoid confusion */
2049 qib_write_kreg(dd, kr_errmask, 0ULL);
2050
2051 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2052 if (dd->pport[pidx].link_speed_supported)
2053 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2054 0ULL);
2055
2056 /* also disable interrupts; errormask is sometimes overwriten */
2057 qib_7322_set_intr_state(dd, 0);
2058
2059 /* clear the freeze, and be sure chip saw it */
2060 qib_write_kreg(dd, kr_control, dd->control);
2061 qib_read_kreg32(dd, kr_scratch);
2062
2063 /*
2064 * Force new interrupt if any hwerr, error or interrupt bits are
2065 * still set, and clear "safe" send packet errors related to freeze
2066 * and cancelling sends. Re-enable error interrupts before possible
2067 * force of re-interrupt on pending interrupts.
2068 */
2069 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2070 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
2071 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2072 /* We need to purge per-port errs and reset mask, too */
2073 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
2074 if (!dd->pport[pidx].link_speed_supported)
2075 continue;
2076 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
2077 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2078 }
2079 qib_7322_set_intr_state(dd, 1);
2080 }
2081
2082 /* no error handling to speak of */
2083 /**
2084 * qib_7322_handle_hwerrors - display hardware errors.
2085 * @dd: the qlogic_ib device
2086 * @msg: the output buffer
2087 * @msgl: the size of the output buffer
2088 *
2089 * Use same msg buffer as regular errors to avoid excessive stack
2090 * use. Most hardware errors are catastrophic, but for right now,
2091 * we'll print them and continue. We reuse the same message buffer as
2092 * qib_handle_errors() to avoid excessive stack usage.
2093 */
2094 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2095 size_t msgl)
2096 {
2097 u64 hwerrs;
2098 u32 ctrl;
2099 int isfatal = 0;
2100
2101 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2102 if (!hwerrs)
2103 goto bail;
2104 if (hwerrs == ~0ULL) {
2105 qib_dev_err(dd,
2106 "Read of hardware error status failed (all bits set); ignoring\n");
2107 goto bail;
2108 }
2109 qib_stats.sps_hwerrs++;
2110
2111 /* Always clear the error status register, except BIST fail */
2112 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2113 ~HWE_MASK(PowerOnBISTFailed));
2114
2115 hwerrs &= dd->cspec->hwerrmask;
2116
2117 /* no EEPROM logging, yet */
2118
2119 if (hwerrs)
2120 qib_devinfo(dd->pcidev,
2121 "Hardware error: hwerr=0x%llx (cleared)\n",
2122 (unsigned long long) hwerrs);
2123
2124 ctrl = qib_read_kreg32(dd, kr_control);
2125 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2126 /*
2127 * No recovery yet...
2128 */
2129 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2130 dd->cspec->stay_in_freeze) {
2131 /*
2132 * If any set that we aren't ignoring only make the
2133 * complaint once, in case it's stuck or recurring,
2134 * and we get here multiple times
2135 * Force link down, so switch knows, and
2136 * LEDs are turned off.
2137 */
2138 if (dd->flags & QIB_INITTED)
2139 isfatal = 1;
2140 } else
2141 qib_7322_clear_freeze(dd);
2142 }
2143
2144 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2145 isfatal = 1;
2146 strlcpy(msg,
2147 "[Memory BIST test failed, InfiniPath hardware unusable]",
2148 msgl);
2149 /* ignore from now on, so disable until driver reloaded */
2150 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2151 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2152 }
2153
2154 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2155
2156 /* Ignore esoteric PLL failures et al. */
2157
2158 qib_dev_err(dd, "%s hardware error\n", msg);
2159
2160 if (hwerrs &
2161 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) |
2162 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) {
2163 int pidx = 0;
2164 int err;
2165 unsigned long flags;
2166 struct qib_pportdata *ppd = dd->pport;
2167
2168 for (; pidx < dd->num_pports; ++pidx, ppd++) {
2169 err = 0;
2170 if (pidx == 0 && (hwerrs &
2171 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0)))
2172 err++;
2173 if (pidx == 1 && (hwerrs &
2174 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1)))
2175 err++;
2176 if (err) {
2177 spin_lock_irqsave(&ppd->sdma_lock, flags);
2178 dump_sdma_7322_state(ppd);
2179 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
2180 }
2181 }
2182 }
2183
2184 if (isfatal && !dd->diag_client) {
2185 qib_dev_err(dd,
2186 "Fatal Hardware Error, no longer usable, SN %.16s\n",
2187 dd->serial);
2188 /*
2189 * for /sys status file and user programs to print; if no
2190 * trailing brace is copied, we'll know it was truncated.
2191 */
2192 if (dd->freezemsg)
2193 snprintf(dd->freezemsg, dd->freezelen,
2194 "{%s}", msg);
2195 qib_disable_after_error(dd);
2196 }
2197 bail:;
2198 }
2199
2200 /**
2201 * qib_7322_init_hwerrors - enable hardware errors
2202 * @dd: the qlogic_ib device
2203 *
2204 * now that we have finished initializing everything that might reasonably
2205 * cause a hardware error, and cleared those errors bits as they occur,
2206 * we can enable hardware errors in the mask (potentially enabling
2207 * freeze mode), and enable hardware errors as errors (along with
2208 * everything else) in errormask
2209 */
2210 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2211 {
2212 int pidx;
2213 u64 extsval;
2214
2215 extsval = qib_read_kreg64(dd, kr_extstatus);
2216 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2217 QIB_EXTS_MEMBIST_ENDTEST)))
2218 qib_dev_err(dd, "MemBIST did not complete!\n");
2219
2220 /* never clear BIST failure, so reported on each driver load */
2221 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2222 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2223
2224 /* clear all */
2225 qib_write_kreg(dd, kr_errclear, ~0ULL);
2226 /* enable errors that are masked, at least this first time. */
2227 qib_write_kreg(dd, kr_errmask, ~0ULL);
2228 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2229 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2230 if (dd->pport[pidx].link_speed_supported)
2231 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2232 ~0ULL);
2233 }
2234
2235 /*
2236 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2237 * on chips that are count-based, rather than trigger-based. There is no
2238 * reference counting, but that's also fine, given the intended use.
2239 * Only chip-specific because it's all register accesses
2240 */
2241 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2242 {
2243 if (enable) {
2244 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2245 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2246 } else
2247 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2248 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2249 }
2250
2251 /*
2252 * Formerly took parameter <which> in pre-shifted,
2253 * pre-merged form with LinkCmd and LinkInitCmd
2254 * together, and assuming the zero was NOP.
2255 */
2256 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2257 u16 linitcmd)
2258 {
2259 u64 mod_wd;
2260 struct qib_devdata *dd = ppd->dd;
2261 unsigned long flags;
2262
2263 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2264 /*
2265 * If we are told to disable, note that so link-recovery
2266 * code does not attempt to bring us back up.
2267 * Also reset everything that we can, so we start
2268 * completely clean when re-enabled (before we
2269 * actually issue the disable to the IBC)
2270 */
2271 qib_7322_mini_pcs_reset(ppd);
2272 spin_lock_irqsave(&ppd->lflags_lock, flags);
2273 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2274 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2275 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2276 /*
2277 * Any other linkinitcmd will lead to LINKDOWN and then
2278 * to INIT (if all is well), so clear flag to let
2279 * link-recovery code attempt to bring us back up.
2280 */
2281 spin_lock_irqsave(&ppd->lflags_lock, flags);
2282 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2283 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2284 /*
2285 * Clear status change interrupt reduction so the
2286 * new state is seen.
2287 */
2288 ppd->cpspec->ibcctrl_a &=
2289 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2290 }
2291
2292 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2293 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2294
2295 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2296 mod_wd);
2297 /* write to chip to prevent back-to-back writes of ibc reg */
2298 qib_write_kreg(dd, kr_scratch, 0);
2299
2300 }
2301
2302 /*
2303 * The total RCV buffer memory is 64KB, used for both ports, and is
2304 * in units of 64 bytes (same as IB flow control credit unit).
2305 * The consumedVL unit in the same registers are in 32 byte units!
2306 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2307 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2308 * in krp_rxcreditvl15, rather than 10.
2309 */
2310 #define RCV_BUF_UNITSZ 64
2311 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2312
2313 static void set_vls(struct qib_pportdata *ppd)
2314 {
2315 int i, numvls, totcred, cred_vl, vl0extra;
2316 struct qib_devdata *dd = ppd->dd;
2317 u64 val;
2318
2319 numvls = qib_num_vls(ppd->vls_operational);
2320
2321 /*
2322 * Set up per-VL credits. Below is kluge based on these assumptions:
2323 * 1) port is disabled at the time early_init is called.
2324 * 2) give VL15 17 credits, for two max-plausible packets.
2325 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2326 */
2327 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2328 totcred = NUM_RCV_BUF_UNITS(dd);
2329 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2330 totcred -= cred_vl;
2331 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2332 cred_vl = totcred / numvls;
2333 vl0extra = totcred - cred_vl * numvls;
2334 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2335 for (i = 1; i < numvls; i++)
2336 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2337 for (; i < 8; i++) /* no buffer space for other VLs */
2338 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2339
2340 /* Notify IBC that credits need to be recalculated */
2341 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2342 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2343 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2344 qib_write_kreg(dd, kr_scratch, 0ULL);
2345 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2346 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2347
2348 for (i = 0; i < numvls; i++)
2349 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2350 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2351
2352 /* Change the number of operational VLs */
2353 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2354 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2355 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2356 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2357 qib_write_kreg(dd, kr_scratch, 0ULL);
2358 }
2359
2360 /*
2361 * The code that deals with actual SerDes is in serdes_7322_init().
2362 * Compared to the code for iba7220, it is minimal.
2363 */
2364 static int serdes_7322_init(struct qib_pportdata *ppd);
2365
2366 /**
2367 * qib_7322_bringup_serdes - bring up the serdes
2368 * @ppd: physical port on the qlogic_ib device
2369 */
2370 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2371 {
2372 struct qib_devdata *dd = ppd->dd;
2373 u64 val, guid, ibc;
2374 unsigned long flags;
2375 int ret = 0;
2376
2377 /*
2378 * SerDes model not in Pd, but still need to
2379 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2380 * eventually.
2381 */
2382 /* Put IBC in reset, sends disabled (should be in reset already) */
2383 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2384 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2385 qib_write_kreg(dd, kr_scratch, 0ULL);
2386
2387 /* ensure previous Tx parameters are not still forced */
2388 qib_write_kreg_port(ppd, krp_tx_deemph_override,
2389 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
2390 reset_tx_deemphasis_override));
2391
2392 if (qib_compat_ddr_negotiate) {
2393 ppd->cpspec->ibdeltainprog = 1;
2394 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2395 crp_ibsymbolerr);
2396 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2397 crp_iblinkerrrecov);
2398 }
2399
2400 /* flowcontrolwatermark is in units of KBytes */
2401 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2402 /*
2403 * Flow control is sent this often, even if no changes in
2404 * buffer space occur. Units are 128ns for this chip.
2405 * Set to 3usec.
2406 */
2407 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2408 /* max error tolerance */
2409 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2410 /* IB credit flow control. */
2411 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2412 /*
2413 * set initial max size pkt IBC will send, including ICRC; it's the
2414 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2415 */
2416 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2417 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2418 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2419
2420 /*
2421 * Reset the PCS interface to the serdes (and also ibc, which is still
2422 * in reset from above). Writes new value of ibcctrl_a as last step.
2423 */
2424 qib_7322_mini_pcs_reset(ppd);
2425
2426 if (!ppd->cpspec->ibcctrl_b) {
2427 unsigned lse = ppd->link_speed_enabled;
2428
2429 /*
2430 * Not on re-init after reset, establish shadow
2431 * and force initial config.
2432 */
2433 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2434 krp_ibcctrl_b);
2435 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2436 IBA7322_IBC_SPEED_DDR |
2437 IBA7322_IBC_SPEED_SDR |
2438 IBA7322_IBC_WIDTH_AUTONEG |
2439 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2440 if (lse & (lse - 1)) /* Muliple speeds enabled */
2441 ppd->cpspec->ibcctrl_b |=
2442 (lse << IBA7322_IBC_SPEED_LSB) |
2443 IBA7322_IBC_IBTA_1_2_MASK |
2444 IBA7322_IBC_MAX_SPEED_MASK;
2445 else
2446 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2447 IBA7322_IBC_SPEED_QDR |
2448 IBA7322_IBC_IBTA_1_2_MASK :
2449 (lse == QIB_IB_DDR) ?
2450 IBA7322_IBC_SPEED_DDR :
2451 IBA7322_IBC_SPEED_SDR;
2452 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2453 (IB_WIDTH_1X | IB_WIDTH_4X))
2454 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2455 else
2456 ppd->cpspec->ibcctrl_b |=
2457 ppd->link_width_enabled == IB_WIDTH_4X ?
2458 IBA7322_IBC_WIDTH_4X_ONLY :
2459 IBA7322_IBC_WIDTH_1X_ONLY;
2460
2461 /* always enable these on driver reload, not sticky */
2462 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2463 IBA7322_IBC_HRTBT_MASK);
2464 }
2465 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2466
2467 /* setup so we have more time at CFGTEST to change H1 */
2468 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2469 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2470 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2471 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2472
2473 serdes_7322_init(ppd);
2474
2475 guid = be64_to_cpu(ppd->guid);
2476 if (!guid) {
2477 if (dd->base_guid)
2478 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2479 ppd->guid = cpu_to_be64(guid);
2480 }
2481
2482 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2483 /* write to chip to prevent back-to-back writes of ibc reg */
2484 qib_write_kreg(dd, kr_scratch, 0);
2485
2486 /* Enable port */
2487 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2488 set_vls(ppd);
2489
2490 /* initially come up DISABLED, without sending anything. */
2491 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2492 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2493 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2494 qib_write_kreg(dd, kr_scratch, 0ULL);
2495 /* clear the linkinit cmds */
2496 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2497
2498 /* be paranoid against later code motion, etc. */
2499 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2500 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2501 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2502 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2503
2504 /* Also enable IBSTATUSCHG interrupt. */
2505 val = qib_read_kreg_port(ppd, krp_errmask);
2506 qib_write_kreg_port(ppd, krp_errmask,
2507 val | ERR_MASK_N(IBStatusChanged));
2508
2509 /* Always zero until we start messing with SerDes for real */
2510 return ret;
2511 }
2512
2513 /**
2514 * qib_7322_quiet_serdes - set serdes to txidle
2515 * @dd: the qlogic_ib device
2516 * Called when driver is being unloaded
2517 */
2518 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2519 {
2520 u64 val;
2521 unsigned long flags;
2522
2523 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2524
2525 spin_lock_irqsave(&ppd->lflags_lock, flags);
2526 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2527 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2528 wake_up(&ppd->cpspec->autoneg_wait);
2529 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2530 if (ppd->dd->cspec->r1)
2531 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2532
2533 ppd->cpspec->chase_end = 0;
2534 if (ppd->cpspec->chase_timer.data) /* if initted */
2535 del_timer_sync(&ppd->cpspec->chase_timer);
2536
2537 /*
2538 * Despite the name, actually disables IBC as well. Do it when
2539 * we are as sure as possible that no more packets can be
2540 * received, following the down and the PCS reset.
2541 * The actual disabling happens in qib_7322_mini_pci_reset(),
2542 * along with the PCS being reset.
2543 */
2544 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2545 qib_7322_mini_pcs_reset(ppd);
2546
2547 /*
2548 * Update the adjusted counters so the adjustment persists
2549 * across driver reload.
2550 */
2551 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2552 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2553 struct qib_devdata *dd = ppd->dd;
2554 u64 diagc;
2555
2556 /* enable counter writes */
2557 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2558 qib_write_kreg(dd, kr_hwdiagctrl,
2559 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2560
2561 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2562 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2563 if (ppd->cpspec->ibdeltainprog)
2564 val -= val - ppd->cpspec->ibsymsnap;
2565 val -= ppd->cpspec->ibsymdelta;
2566 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2567 }
2568 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2569 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2570 if (ppd->cpspec->ibdeltainprog)
2571 val -= val - ppd->cpspec->iblnkerrsnap;
2572 val -= ppd->cpspec->iblnkerrdelta;
2573 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2574 }
2575 if (ppd->cpspec->iblnkdowndelta) {
2576 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2577 val += ppd->cpspec->iblnkdowndelta;
2578 write_7322_creg_port(ppd, crp_iblinkdown, val);
2579 }
2580 /*
2581 * No need to save ibmalfdelta since IB perfcounters
2582 * are cleared on driver reload.
2583 */
2584
2585 /* and disable counter writes */
2586 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2587 }
2588 }
2589
2590 /**
2591 * qib_setup_7322_setextled - set the state of the two external LEDs
2592 * @ppd: physical port on the qlogic_ib device
2593 * @on: whether the link is up or not
2594 *
2595 * The exact combo of LEDs if on is true is determined by looking
2596 * at the ibcstatus.
2597 *
2598 * These LEDs indicate the physical and logical state of IB link.
2599 * For this chip (at least with recommended board pinouts), LED1
2600 * is Yellow (logical state) and LED2 is Green (physical state),
2601 *
2602 * Note: We try to match the Mellanox HCA LED behavior as best
2603 * we can. Green indicates physical link state is OK (something is
2604 * plugged in, and we can train).
2605 * Amber indicates the link is logically up (ACTIVE).
2606 * Mellanox further blinks the amber LED to indicate data packet
2607 * activity, but we have no hardware support for that, so it would
2608 * require waking up every 10-20 msecs and checking the counters
2609 * on the chip, and then turning the LED off if appropriate. That's
2610 * visible overhead, so not something we will do.
2611 */
2612 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2613 {
2614 struct qib_devdata *dd = ppd->dd;
2615 u64 extctl, ledblink = 0, val;
2616 unsigned long flags;
2617 int yel, grn;
2618
2619 /*
2620 * The diags use the LED to indicate diag info, so we leave
2621 * the external LED alone when the diags are running.
2622 */
2623 if (dd->diag_client)
2624 return;
2625
2626 /* Allow override of LED display for, e.g. Locating system in rack */
2627 if (ppd->led_override) {
2628 grn = (ppd->led_override & QIB_LED_PHYS);
2629 yel = (ppd->led_override & QIB_LED_LOG);
2630 } else if (on) {
2631 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2632 grn = qib_7322_phys_portstate(val) ==
2633 IB_PHYSPORTSTATE_LINKUP;
2634 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2635 } else {
2636 grn = 0;
2637 yel = 0;
2638 }
2639
2640 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2641 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2642 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2643 if (grn) {
2644 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2645 /*
2646 * Counts are in chip clock (4ns) periods.
2647 * This is 1/16 sec (66.6ms) on,
2648 * 3/16 sec (187.5 ms) off, with packets rcvd.
2649 */
2650 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2651 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2652 }
2653 if (yel)
2654 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2655 dd->cspec->extctrl = extctl;
2656 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2657 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2658
2659 if (ledblink) /* blink the LED on packet receive */
2660 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2661 }
2662
2663 #ifdef CONFIG_INFINIBAND_QIB_DCA
2664
2665 static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event)
2666 {
2667 switch (event) {
2668 case DCA_PROVIDER_ADD:
2669 if (dd->flags & QIB_DCA_ENABLED)
2670 break;
2671 if (!dca_add_requester(&dd->pcidev->dev)) {
2672 qib_devinfo(dd->pcidev, "DCA enabled\n");
2673 dd->flags |= QIB_DCA_ENABLED;
2674 qib_setup_dca(dd);
2675 }
2676 break;
2677 case DCA_PROVIDER_REMOVE:
2678 if (dd->flags & QIB_DCA_ENABLED) {
2679 dca_remove_requester(&dd->pcidev->dev);
2680 dd->flags &= ~QIB_DCA_ENABLED;
2681 dd->cspec->dca_ctrl = 0;
2682 qib_write_kreg(dd, KREG_IDX(DCACtrlA),
2683 dd->cspec->dca_ctrl);
2684 }
2685 break;
2686 }
2687 return 0;
2688 }
2689
2690 static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu)
2691 {
2692 struct qib_devdata *dd = rcd->dd;
2693 struct qib_chip_specific *cspec = dd->cspec;
2694
2695 if (!(dd->flags & QIB_DCA_ENABLED))
2696 return;
2697 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2698 const struct dca_reg_map *rmp;
2699
2700 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2701 rmp = &dca_rcvhdr_reg_map[rcd->ctxt];
2702 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2703 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2704 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb;
2705 qib_devinfo(dd->pcidev,
2706 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu,
2707 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2708 qib_write_kreg(dd, rmp->regno,
2709 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2710 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2711 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2712 }
2713 }
2714
2715 static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu)
2716 {
2717 struct qib_devdata *dd = ppd->dd;
2718 struct qib_chip_specific *cspec = dd->cspec;
2719 unsigned pidx = ppd->port - 1;
2720
2721 if (!(dd->flags & QIB_DCA_ENABLED))
2722 return;
2723 if (cspec->sdma_cpu[pidx] != cpu) {
2724 cspec->sdma_cpu[pidx] = cpu;
2725 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2726 SYM_MASK(DCACtrlF, SendDma1DCAOPH) :
2727 SYM_MASK(DCACtrlF, SendDma0DCAOPH));
2728 cspec->dca_rcvhdr_ctrl[4] |=
2729 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) <<
2730 (ppd->hw_pidx ?
2731 SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
2732 SYM_LSB(DCACtrlF, SendDma0DCAOPH));
2733 qib_devinfo(dd->pcidev,
2734 "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu,
2735 (long long) cspec->dca_rcvhdr_ctrl[4]);
2736 qib_write_kreg(dd, KREG_IDX(DCACtrlF),
2737 cspec->dca_rcvhdr_ctrl[4]);
2738 cspec->dca_ctrl |= ppd->hw_pidx ?
2739 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) :
2740 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable);
2741 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2742 }
2743 }
2744
2745 static void qib_setup_dca(struct qib_devdata *dd)
2746 {
2747 struct qib_chip_specific *cspec = dd->cspec;
2748 int i;
2749
2750 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2751 cspec->rhdr_cpu[i] = -1;
2752 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2753 cspec->sdma_cpu[i] = -1;
2754 cspec->dca_rcvhdr_ctrl[0] =
2755 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
2756 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
2757 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
2758 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
2759 cspec->dca_rcvhdr_ctrl[1] =
2760 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
2761 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
2762 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
2763 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
2764 cspec->dca_rcvhdr_ctrl[2] =
2765 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
2766 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
2767 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
2768 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
2769 cspec->dca_rcvhdr_ctrl[3] =
2770 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
2771 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
2772 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
2773 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
2774 cspec->dca_rcvhdr_ctrl[4] =
2775 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
2776 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
2777 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2778 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
2779 cspec->dca_rcvhdr_ctrl[i]);
2780 for (i = 0; i < cspec->num_msix_entries; i++)
2781 setup_dca_notifier(dd, &cspec->msix_entries[i]);
2782 }
2783
2784 static void qib_irq_notifier_notify(struct irq_affinity_notify *notify,
2785 const cpumask_t *mask)
2786 {
2787 struct qib_irq_notify *n =
2788 container_of(notify, struct qib_irq_notify, notify);
2789 int cpu = cpumask_first(mask);
2790
2791 if (n->rcv) {
2792 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
2793
2794 qib_update_rhdrq_dca(rcd, cpu);
2795 } else {
2796 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
2797
2798 qib_update_sdma_dca(ppd, cpu);
2799 }
2800 }
2801
2802 static void qib_irq_notifier_release(struct kref *ref)
2803 {
2804 struct qib_irq_notify *n =
2805 container_of(ref, struct qib_irq_notify, notify.kref);
2806 struct qib_devdata *dd;
2807
2808 if (n->rcv) {
2809 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
2810
2811 dd = rcd->dd;
2812 } else {
2813 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
2814
2815 dd = ppd->dd;
2816 }
2817 qib_devinfo(dd->pcidev,
2818 "release on HCA notify 0x%p n 0x%p\n", ref, n);
2819 kfree(n);
2820 }
2821 #endif
2822
2823 /*
2824 * Disable MSIx interrupt if enabled, call generic MSIx code
2825 * to cleanup, and clear pending MSIx interrupts.
2826 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2827 */
2828 static void qib_7322_nomsix(struct qib_devdata *dd)
2829 {
2830 u64 intgranted;
2831 int n;
2832
2833 dd->cspec->main_int_mask = ~0ULL;
2834 n = dd->cspec->num_msix_entries;
2835 if (n) {
2836 int i;
2837
2838 dd->cspec->num_msix_entries = 0;
2839 for (i = 0; i < n; i++) {
2840 #ifdef CONFIG_INFINIBAND_QIB_DCA
2841 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]);
2842 #endif
2843 irq_set_affinity_hint(
2844 dd->cspec->msix_entries[i].msix.vector, NULL);
2845 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2846 free_irq(dd->cspec->msix_entries[i].msix.vector,
2847 dd->cspec->msix_entries[i].arg);
2848 }
2849 qib_nomsix(dd);
2850 }
2851 /* make sure no MSIx interrupts are left pending */
2852 intgranted = qib_read_kreg64(dd, kr_intgranted);
2853 if (intgranted)
2854 qib_write_kreg(dd, kr_intgranted, intgranted);
2855 }
2856
2857 static void qib_7322_free_irq(struct qib_devdata *dd)
2858 {
2859 if (dd->cspec->irq) {
2860 free_irq(dd->cspec->irq, dd);
2861 dd->cspec->irq = 0;
2862 }
2863 qib_7322_nomsix(dd);
2864 }
2865
2866 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2867 {
2868 int i;
2869
2870 #ifdef CONFIG_INFINIBAND_QIB_DCA
2871 if (dd->flags & QIB_DCA_ENABLED) {
2872 dca_remove_requester(&dd->pcidev->dev);
2873 dd->flags &= ~QIB_DCA_ENABLED;
2874 dd->cspec->dca_ctrl = 0;
2875 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2876 }
2877 #endif
2878
2879 qib_7322_free_irq(dd);
2880 kfree(dd->cspec->cntrs);
2881 kfree(dd->cspec->sendchkenable);
2882 kfree(dd->cspec->sendgrhchk);
2883 kfree(dd->cspec->sendibchk);
2884 kfree(dd->cspec->msix_entries);
2885 for (i = 0; i < dd->num_pports; i++) {
2886 unsigned long flags;
2887 u32 mask = QSFP_GPIO_MOD_PRS_N |
2888 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2889
2890 kfree(dd->pport[i].cpspec->portcntrs);
2891 if (dd->flags & QIB_HAS_QSFP) {
2892 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2893 dd->cspec->gpio_mask &= ~mask;
2894 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2895 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2896 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2897 }
2898 }
2899 }
2900
2901 /* handle SDMA interrupts */
2902 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2903 {
2904 struct qib_pportdata *ppd0 = &dd->pport[0];
2905 struct qib_pportdata *ppd1 = &dd->pport[1];
2906 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2907 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2908 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2909 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2910
2911 if (intr0)
2912 qib_sdma_intr(ppd0);
2913 if (intr1)
2914 qib_sdma_intr(ppd1);
2915
2916 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2917 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2918 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2919 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2920 }
2921
2922 /*
2923 * Set or clear the Send buffer available interrupt enable bit.
2924 */
2925 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2926 {
2927 unsigned long flags;
2928
2929 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2930 if (needint)
2931 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2932 else
2933 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2934 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2935 qib_write_kreg(dd, kr_scratch, 0ULL);
2936 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2937 }
2938
2939 /*
2940 * Somehow got an interrupt with reserved bits set in interrupt status.
2941 * Print a message so we know it happened, then clear them.
2942 * keep mainline interrupt handler cache-friendly
2943 */
2944 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2945 {
2946 u64 kills;
2947 char msg[128];
2948
2949 kills = istat & ~QIB_I_BITSEXTANT;
2950 qib_dev_err(dd,
2951 "Clearing reserved interrupt(s) 0x%016llx: %s\n",
2952 (unsigned long long) kills, msg);
2953 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2954 }
2955
2956 /* keep mainline interrupt handler cache-friendly */
2957 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2958 {
2959 u32 gpiostatus;
2960 int handled = 0;
2961 int pidx;
2962
2963 /*
2964 * Boards for this chip currently don't use GPIO interrupts,
2965 * so clear by writing GPIOstatus to GPIOclear, and complain
2966 * to developer. To avoid endless repeats, clear
2967 * the bits in the mask, since there is some kind of
2968 * programming error or chip problem.
2969 */
2970 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2971 /*
2972 * In theory, writing GPIOstatus to GPIOclear could
2973 * have a bad side-effect on some diagnostic that wanted
2974 * to poll for a status-change, but the various shadows
2975 * make that problematic at best. Diags will just suppress
2976 * all GPIO interrupts during such tests.
2977 */
2978 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2979 /*
2980 * Check for QSFP MOD_PRS changes
2981 * only works for single port if IB1 != pidx1
2982 */
2983 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2984 ++pidx) {
2985 struct qib_pportdata *ppd;
2986 struct qib_qsfp_data *qd;
2987 u32 mask;
2988
2989 if (!dd->pport[pidx].link_speed_supported)
2990 continue;
2991 mask = QSFP_GPIO_MOD_PRS_N;
2992 ppd = dd->pport + pidx;
2993 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2994 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2995 u64 pins;
2996
2997 qd = &ppd->cpspec->qsfp_data;
2998 gpiostatus &= ~mask;
2999 pins = qib_read_kreg64(dd, kr_extstatus);
3000 pins >>= SYM_LSB(EXTStatus, GPIOIn);
3001 if (!(pins & mask)) {
3002 ++handled;
3003 qd->t_insert = jiffies;
3004 queue_work(ib_wq, &qd->work);
3005 }
3006 }
3007 }
3008
3009 if (gpiostatus && !handled) {
3010 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
3011 u32 gpio_irq = mask & gpiostatus;
3012
3013 /*
3014 * Clear any troublemakers, and update chip from shadow
3015 */
3016 dd->cspec->gpio_mask &= ~gpio_irq;
3017 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
3018 }
3019 }
3020
3021 /*
3022 * Handle errors and unusual events first, separate function
3023 * to improve cache hits for fast path interrupt handling.
3024 */
3025 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
3026 {
3027 if (istat & ~QIB_I_BITSEXTANT)
3028 unknown_7322_ibits(dd, istat);
3029 if (istat & QIB_I_GPIO)
3030 unknown_7322_gpio_intr(dd);
3031 if (istat & QIB_I_C_ERROR) {
3032 qib_write_kreg(dd, kr_errmask, 0ULL);
3033 tasklet_schedule(&dd->error_tasklet);
3034 }
3035 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
3036 handle_7322_p_errors(dd->rcd[0]->ppd);
3037 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
3038 handle_7322_p_errors(dd->rcd[1]->ppd);
3039 }
3040
3041 /*
3042 * Dynamically adjust the rcv int timeout for a context based on incoming
3043 * packet rate.
3044 */
3045 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
3046 {
3047 struct qib_devdata *dd = rcd->dd;
3048 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
3049
3050 /*
3051 * Dynamically adjust idle timeout on chip
3052 * based on number of packets processed.
3053 */
3054 if (npkts < rcv_int_count && timeout > 2)
3055 timeout >>= 1;
3056 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
3057 timeout = min(timeout << 1, rcv_int_timeout);
3058 else
3059 return;
3060
3061 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
3062 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
3063 }
3064
3065 /*
3066 * This is the main interrupt handler.
3067 * It will normally only be used for low frequency interrupts but may
3068 * have to handle all interrupts if INTx is enabled or fewer than normal
3069 * MSIx interrupts were allocated.
3070 * This routine should ignore the interrupt bits for any of the
3071 * dedicated MSIx handlers.
3072 */
3073 static irqreturn_t qib_7322intr(int irq, void *data)
3074 {
3075 struct qib_devdata *dd = data;
3076 irqreturn_t ret;
3077 u64 istat;
3078 u64 ctxtrbits;
3079 u64 rmask;
3080 unsigned i;
3081 u32 npkts;
3082
3083 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
3084 /*
3085 * This return value is not great, but we do not want the
3086 * interrupt core code to remove our interrupt handler
3087 * because we don't appear to be handling an interrupt
3088 * during a chip reset.
3089 */
3090 ret = IRQ_HANDLED;
3091 goto bail;
3092 }
3093
3094 istat = qib_read_kreg64(dd, kr_intstatus);
3095
3096 if (unlikely(istat == ~0ULL)) {
3097 qib_bad_intrstatus(dd);
3098 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
3099 /* don't know if it was our interrupt or not */
3100 ret = IRQ_NONE;
3101 goto bail;
3102 }
3103
3104 istat &= dd->cspec->main_int_mask;
3105 if (unlikely(!istat)) {
3106 /* already handled, or shared and not us */
3107 ret = IRQ_NONE;
3108 goto bail;
3109 }
3110
3111 this_cpu_inc(*dd->int_counter);
3112
3113 /* handle "errors" of various kinds first, device ahead of port */
3114 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
3115 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
3116 INT_MASK_P(Err, 1))))
3117 unlikely_7322_intr(dd, istat);
3118
3119 /*
3120 * Clear the interrupt bits we found set, relatively early, so we
3121 * "know" know the chip will have seen this by the time we process
3122 * the queue, and will re-interrupt if necessary. The processor
3123 * itself won't take the interrupt again until we return.
3124 */
3125 qib_write_kreg(dd, kr_intclear, istat);
3126
3127 /*
3128 * Handle kernel receive queues before checking for pio buffers
3129 * available since receives can overflow; piobuf waiters can afford
3130 * a few extra cycles, since they were waiting anyway.
3131 */
3132 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
3133 if (ctxtrbits) {
3134 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
3135 (1ULL << QIB_I_RCVURG_LSB);
3136 for (i = 0; i < dd->first_user_ctxt; i++) {
3137 if (ctxtrbits & rmask) {
3138 ctxtrbits &= ~rmask;
3139 if (dd->rcd[i])
3140 qib_kreceive(dd->rcd[i], NULL, &npkts);
3141 }
3142 rmask <<= 1;
3143 }
3144 if (ctxtrbits) {
3145 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
3146 (ctxtrbits >> QIB_I_RCVURG_LSB);
3147 qib_handle_urcv(dd, ctxtrbits);
3148 }
3149 }
3150
3151 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
3152 sdma_7322_intr(dd, istat);
3153
3154 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
3155 qib_ib_piobufavail(dd);
3156
3157 ret = IRQ_HANDLED;
3158 bail:
3159 return ret;
3160 }
3161
3162 /*
3163 * Dedicated receive packet available interrupt handler.
3164 */
3165 static irqreturn_t qib_7322pintr(int irq, void *data)
3166 {
3167 struct qib_ctxtdata *rcd = data;
3168 struct qib_devdata *dd = rcd->dd;
3169 u32 npkts;
3170
3171 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3172 /*
3173 * This return value is not great, but we do not want the
3174 * interrupt core code to remove our interrupt handler
3175 * because we don't appear to be handling an interrupt
3176 * during a chip reset.
3177 */
3178 return IRQ_HANDLED;
3179
3180 this_cpu_inc(*dd->int_counter);
3181
3182 /* Clear the interrupt bit we expect to be set. */
3183 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
3184 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
3185
3186 qib_kreceive(rcd, NULL, &npkts);
3187
3188 return IRQ_HANDLED;
3189 }
3190
3191 /*
3192 * Dedicated Send buffer available interrupt handler.
3193 */
3194 static irqreturn_t qib_7322bufavail(int irq, void *data)
3195 {
3196 struct qib_devdata *dd = data;
3197
3198 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3199 /*
3200 * This return value is not great, but we do not want the
3201 * interrupt core code to remove our interrupt handler
3202 * because we don't appear to be handling an interrupt
3203 * during a chip reset.
3204 */
3205 return IRQ_HANDLED;
3206
3207 this_cpu_inc(*dd->int_counter);
3208
3209 /* Clear the interrupt bit we expect to be set. */
3210 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
3211
3212 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
3213 if (dd->flags & QIB_INITTED)
3214 qib_ib_piobufavail(dd);
3215 else
3216 qib_wantpiobuf_7322_intr(dd, 0);
3217
3218 return IRQ_HANDLED;
3219 }
3220
3221 /*
3222 * Dedicated Send DMA interrupt handler.
3223 */
3224 static irqreturn_t sdma_intr(int irq, void *data)
3225 {
3226 struct qib_pportdata *ppd = data;
3227 struct qib_devdata *dd = ppd->dd;
3228
3229 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3230 /*
3231 * This return value is not great, but we do not want the
3232 * interrupt core code to remove our interrupt handler
3233 * because we don't appear to be handling an interrupt
3234 * during a chip reset.
3235 */
3236 return IRQ_HANDLED;
3237
3238 this_cpu_inc(*dd->int_counter);
3239
3240 /* Clear the interrupt bit we expect to be set. */
3241 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3242 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
3243 qib_sdma_intr(ppd);
3244
3245 return IRQ_HANDLED;
3246 }
3247
3248 /*
3249 * Dedicated Send DMA idle interrupt handler.
3250 */
3251 static irqreturn_t sdma_idle_intr(int irq, void *data)
3252 {
3253 struct qib_pportdata *ppd = data;
3254 struct qib_devdata *dd = ppd->dd;
3255
3256 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3257 /*
3258 * This return value is not great, but we do not want the
3259 * interrupt core code to remove our interrupt handler
3260 * because we don't appear to be handling an interrupt
3261 * during a chip reset.
3262 */
3263 return IRQ_HANDLED;
3264
3265 this_cpu_inc(*dd->int_counter);
3266
3267 /* Clear the interrupt bit we expect to be set. */
3268 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3269 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3270 qib_sdma_intr(ppd);
3271
3272 return IRQ_HANDLED;
3273 }
3274
3275 /*
3276 * Dedicated Send DMA progress interrupt handler.
3277 */
3278 static irqreturn_t sdma_progress_intr(int irq, void *data)
3279 {
3280 struct qib_pportdata *ppd = data;
3281 struct qib_devdata *dd = ppd->dd;
3282
3283 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3284 /*
3285 * This return value is not great, but we do not want the
3286 * interrupt core code to remove our interrupt handler
3287 * because we don't appear to be handling an interrupt
3288 * during a chip reset.
3289 */
3290 return IRQ_HANDLED;
3291
3292 this_cpu_inc(*dd->int_counter);
3293
3294 /* Clear the interrupt bit we expect to be set. */
3295 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3296 INT_MASK_P(SDmaProgress, 1) :
3297 INT_MASK_P(SDmaProgress, 0));
3298 qib_sdma_intr(ppd);
3299
3300 return IRQ_HANDLED;
3301 }
3302
3303 /*
3304 * Dedicated Send DMA cleanup interrupt handler.
3305 */
3306 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3307 {
3308 struct qib_pportdata *ppd = data;
3309 struct qib_devdata *dd = ppd->dd;
3310
3311 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3312 /*
3313 * This return value is not great, but we do not want the
3314 * interrupt core code to remove our interrupt handler
3315 * because we don't appear to be handling an interrupt
3316 * during a chip reset.
3317 */
3318 return IRQ_HANDLED;
3319
3320 this_cpu_inc(*dd->int_counter);
3321
3322 /* Clear the interrupt bit we expect to be set. */
3323 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3324 INT_MASK_PM(SDmaCleanupDone, 1) :
3325 INT_MASK_PM(SDmaCleanupDone, 0));
3326 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3327
3328 return IRQ_HANDLED;
3329 }
3330
3331 #ifdef CONFIG_INFINIBAND_QIB_DCA
3332
3333 static void reset_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3334 {
3335 if (!m->dca)
3336 return;
3337 qib_devinfo(dd->pcidev,
3338 "Disabling notifier on HCA %d irq %d\n",
3339 dd->unit,
3340 m->msix.vector);
3341 irq_set_affinity_notifier(
3342 m->msix.vector,
3343 NULL);
3344 m->notifier = NULL;
3345 }
3346
3347 static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3348 {
3349 struct qib_irq_notify *n;
3350
3351 if (!m->dca)
3352 return;
3353 n = kzalloc(sizeof(*n), GFP_KERNEL);
3354 if (n) {
3355 int ret;
3356
3357 m->notifier = n;
3358 n->notify.irq = m->msix.vector;
3359 n->notify.notify = qib_irq_notifier_notify;
3360 n->notify.release = qib_irq_notifier_release;
3361 n->arg = m->arg;
3362 n->rcv = m->rcv;
3363 qib_devinfo(dd->pcidev,
3364 "set notifier irq %d rcv %d notify %p\n",
3365 n->notify.irq, n->rcv, &n->notify);
3366 ret = irq_set_affinity_notifier(
3367 n->notify.irq,
3368 &n->notify);
3369 if (ret) {
3370 m->notifier = NULL;
3371 kfree(n);
3372 }
3373 }
3374 }
3375
3376 #endif
3377
3378 /*
3379 * Set up our chip-specific interrupt handler.
3380 * The interrupt type has already been setup, so
3381 * we just need to do the registration and error checking.
3382 * If we are using MSIx interrupts, we may fall back to
3383 * INTx later, if the interrupt handler doesn't get called
3384 * within 1/2 second (see verify_interrupt()).
3385 */
3386 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3387 {
3388 int ret, i, msixnum;
3389 u64 redirect[6];
3390 u64 mask;
3391 const struct cpumask *local_mask;
3392 int firstcpu, secondcpu = 0, currrcvcpu = 0;
3393
3394 if (!dd->num_pports)
3395 return;
3396
3397 if (clearpend) {
3398 /*
3399 * if not switching interrupt types, be sure interrupts are
3400 * disabled, and then clear anything pending at this point,
3401 * because we are starting clean.
3402 */
3403 qib_7322_set_intr_state(dd, 0);
3404
3405 /* clear the reset error, init error/hwerror mask */
3406 qib_7322_init_hwerrors(dd);
3407
3408 /* clear any interrupt bits that might be set */
3409 qib_write_kreg(dd, kr_intclear, ~0ULL);
3410
3411 /* make sure no pending MSIx intr, and clear diag reg */
3412 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3413 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3414 }
3415
3416 if (!dd->cspec->num_msix_entries) {
3417 /* Try to get INTx interrupt */
3418 try_intx:
3419 if (!dd->pcidev->irq) {
3420 qib_dev_err(dd,
3421 "irq is 0, BIOS error? Interrupts won't work\n");
3422 goto bail;
3423 }
3424 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3425 IRQF_SHARED, QIB_DRV_NAME, dd);
3426 if (ret) {
3427 qib_dev_err(dd,
3428 "Couldn't setup INTx interrupt (irq=%d): %d\n",
3429 dd->pcidev->irq, ret);
3430 goto bail;
3431 }
3432 dd->cspec->irq = dd->pcidev->irq;
3433 dd->cspec->main_int_mask = ~0ULL;
3434 goto bail;
3435 }
3436
3437 /* Try to get MSIx interrupts */
3438 memset(redirect, 0, sizeof(redirect));
3439 mask = ~0ULL;
3440 msixnum = 0;
3441 local_mask = cpumask_of_pcibus(dd->pcidev->bus);
3442 firstcpu = cpumask_first(local_mask);
3443 if (firstcpu >= nr_cpu_ids ||
3444 cpumask_weight(local_mask) == num_online_cpus()) {
3445 local_mask = topology_core_cpumask(0);
3446 firstcpu = cpumask_first(local_mask);
3447 }
3448 if (firstcpu < nr_cpu_ids) {
3449 secondcpu = cpumask_next(firstcpu, local_mask);
3450 if (secondcpu >= nr_cpu_ids)
3451 secondcpu = firstcpu;
3452 currrcvcpu = secondcpu;
3453 }
3454 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3455 irq_handler_t handler;
3456 void *arg;
3457 u64 val;
3458 int lsb, reg, sh;
3459 #ifdef CONFIG_INFINIBAND_QIB_DCA
3460 int dca = 0;
3461 #endif
3462
3463 dd->cspec->msix_entries[msixnum].
3464 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3465 = '\0';
3466 if (i < ARRAY_SIZE(irq_table)) {
3467 if (irq_table[i].port) {
3468 /* skip if for a non-configured port */
3469 if (irq_table[i].port > dd->num_pports)
3470 continue;
3471 arg = dd->pport + irq_table[i].port - 1;
3472 } else
3473 arg = dd;
3474 #ifdef CONFIG_INFINIBAND_QIB_DCA
3475 dca = irq_table[i].dca;
3476 #endif
3477 lsb = irq_table[i].lsb;
3478 handler = irq_table[i].handler;
3479 snprintf(dd->cspec->msix_entries[msixnum].name,
3480 sizeof(dd->cspec->msix_entries[msixnum].name)
3481 - 1,
3482 QIB_DRV_NAME "%d%s", dd->unit,
3483 irq_table[i].name);
3484 } else {
3485 unsigned ctxt;
3486
3487 ctxt = i - ARRAY_SIZE(irq_table);
3488 /* per krcvq context receive interrupt */
3489 arg = dd->rcd[ctxt];
3490 if (!arg)
3491 continue;
3492 if (qib_krcvq01_no_msi && ctxt < 2)
3493 continue;
3494 #ifdef CONFIG_INFINIBAND_QIB_DCA
3495 dca = 1;
3496 #endif
3497 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3498 handler = qib_7322pintr;
3499 snprintf(dd->cspec->msix_entries[msixnum].name,
3500 sizeof(dd->cspec->msix_entries[msixnum].name)
3501 - 1,
3502 QIB_DRV_NAME "%d (kctx)", dd->unit);
3503 }
3504 ret = request_irq(
3505 dd->cspec->msix_entries[msixnum].msix.vector,
3506 handler, 0, dd->cspec->msix_entries[msixnum].name,
3507 arg);
3508 if (ret) {
3509 /*
3510 * Shouldn't happen since the enable said we could
3511 * have as many as we are trying to setup here.
3512 */
3513 qib_dev_err(dd,
3514 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n",
3515 msixnum,
3516 dd->cspec->msix_entries[msixnum].msix.vector,
3517 ret);
3518 qib_7322_nomsix(dd);
3519 goto try_intx;
3520 }
3521 dd->cspec->msix_entries[msixnum].arg = arg;
3522 #ifdef CONFIG_INFINIBAND_QIB_DCA
3523 dd->cspec->msix_entries[msixnum].dca = dca;
3524 dd->cspec->msix_entries[msixnum].rcv =
3525 handler == qib_7322pintr;
3526 #endif
3527 if (lsb >= 0) {
3528 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3529 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3530 SYM_LSB(IntRedirect0, vec1);
3531 mask &= ~(1ULL << lsb);
3532 redirect[reg] |= ((u64) msixnum) << sh;
3533 }
3534 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3535 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3536 if (firstcpu < nr_cpu_ids &&
3537 zalloc_cpumask_var(
3538 &dd->cspec->msix_entries[msixnum].mask,
3539 GFP_KERNEL)) {
3540 if (handler == qib_7322pintr) {
3541 cpumask_set_cpu(currrcvcpu,
3542 dd->cspec->msix_entries[msixnum].mask);
3543 currrcvcpu = cpumask_next(currrcvcpu,
3544 local_mask);
3545 if (currrcvcpu >= nr_cpu_ids)
3546 currrcvcpu = secondcpu;
3547 } else {
3548 cpumask_set_cpu(firstcpu,
3549 dd->cspec->msix_entries[msixnum].mask);
3550 }
3551 irq_set_affinity_hint(
3552 dd->cspec->msix_entries[msixnum].msix.vector,
3553 dd->cspec->msix_entries[msixnum].mask);
3554 }
3555 msixnum++;
3556 }
3557 /* Initialize the vector mapping */
3558 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3559 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3560 dd->cspec->main_int_mask = mask;
3561 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3562 (unsigned long)dd);
3563 bail:;
3564 }
3565
3566 /**
3567 * qib_7322_boardname - fill in the board name and note features
3568 * @dd: the qlogic_ib device
3569 *
3570 * info will be based on the board revision register
3571 */
3572 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3573 {
3574 /* Will need enumeration of board-types here */
3575 char *n;
3576 u32 boardid, namelen;
3577 unsigned features = DUAL_PORT_CAP;
3578
3579 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3580
3581 switch (boardid) {
3582 case 0:
3583 n = "InfiniPath_QLE7342_Emulation";
3584 break;
3585 case 1:
3586 n = "InfiniPath_QLE7340";
3587 dd->flags |= QIB_HAS_QSFP;
3588 features = PORT_SPD_CAP;
3589 break;
3590 case 2:
3591 n = "InfiniPath_QLE7342";
3592 dd->flags |= QIB_HAS_QSFP;
3593 break;
3594 case 3:
3595 n = "InfiniPath_QMI7342";
3596 break;
3597 case 4:
3598 n = "InfiniPath_Unsupported7342";
3599 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3600 features = 0;
3601 break;
3602 case BOARD_QMH7342:
3603 n = "InfiniPath_QMH7342";
3604 features = 0x24;
3605 break;
3606 case BOARD_QME7342:
3607 n = "InfiniPath_QME7342";
3608 break;
3609 case 8:
3610 n = "InfiniPath_QME7362";
3611 dd->flags |= QIB_HAS_QSFP;
3612 break;
3613 case BOARD_QMH7360:
3614 n = "Intel IB QDR 1P FLR-QSFP Adptr";
3615 dd->flags |= QIB_HAS_QSFP;
3616 break;
3617 case 15:
3618 n = "InfiniPath_QLE7342_TEST";
3619 dd->flags |= QIB_HAS_QSFP;
3620 break;
3621 default:
3622 n = "InfiniPath_QLE73xy_UNKNOWN";
3623 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3624 break;
3625 }
3626 dd->board_atten = 1; /* index into txdds_Xdr */
3627
3628 namelen = strlen(n) + 1;
3629 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3630 if (!dd->boardname)
3631 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3632 else
3633 snprintf(dd->boardname, namelen, "%s", n);
3634
3635 snprintf(dd->boardversion, sizeof(dd->boardversion),
3636 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3637 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3638 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3639 dd->majrev, dd->minrev,
3640 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3641
3642 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3643 qib_devinfo(dd->pcidev,
3644 "IB%u: Forced to single port mode by module parameter\n",
3645 dd->unit);
3646 features &= PORT_SPD_CAP;
3647 }
3648
3649 return features;
3650 }
3651
3652 /*
3653 * This routine sleeps, so it can only be called from user context, not
3654 * from interrupt context.
3655 */
3656 static int qib_do_7322_reset(struct qib_devdata *dd)
3657 {
3658 u64 val;
3659 u64 *msix_vecsave;
3660 int i, msix_entries, ret = 1;
3661 u16 cmdval;
3662 u8 int_line, clinesz;
3663 unsigned long flags;
3664
3665 /* Use dev_err so it shows up in logs, etc. */
3666 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3667
3668 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3669
3670 msix_entries = dd->cspec->num_msix_entries;
3671
3672 /* no interrupts till re-initted */
3673 qib_7322_set_intr_state(dd, 0);
3674
3675 if (msix_entries) {
3676 qib_7322_nomsix(dd);
3677 /* can be up to 512 bytes, too big for stack */
3678 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3679 sizeof(u64), GFP_KERNEL);
3680 if (!msix_vecsave)
3681 qib_dev_err(dd, "No mem to save MSIx data\n");
3682 } else
3683 msix_vecsave = NULL;
3684
3685 /*
3686 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3687 * info that is set up by the BIOS, so we have to save and restore
3688 * it ourselves. There is some risk something could change it,
3689 * after we save it, but since we have disabled the MSIx, it
3690 * shouldn't be touched...
3691 */
3692 for (i = 0; i < msix_entries; i++) {
3693 u64 vecaddr, vecdata;
3694
3695 vecaddr = qib_read_kreg64(dd, 2 * i +
3696 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3697 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3698 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3699 if (msix_vecsave) {
3700 msix_vecsave[2 * i] = vecaddr;
3701 /* save it without the masked bit set */
3702 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3703 }
3704 }
3705
3706 dd->pport->cpspec->ibdeltainprog = 0;
3707 dd->pport->cpspec->ibsymdelta = 0;
3708 dd->pport->cpspec->iblnkerrdelta = 0;
3709 dd->pport->cpspec->ibmalfdelta = 0;
3710 /* so we check interrupts work again */
3711 dd->z_int_counter = qib_int_counter(dd);
3712
3713 /*
3714 * Keep chip from being accessed until we are ready. Use
3715 * writeq() directly, to allow the write even though QIB_PRESENT
3716 * isn't set.
3717 */
3718 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3719 dd->flags |= QIB_DOING_RESET;
3720 val = dd->control | QLOGIC_IB_C_RESET;
3721 writeq(val, &dd->kregbase[kr_control]);
3722
3723 for (i = 1; i <= 5; i++) {
3724 /*
3725 * Allow MBIST, etc. to complete; longer on each retry.
3726 * We sometimes get machine checks from bus timeout if no
3727 * response, so for now, make it *really* long.
3728 */
3729 msleep(1000 + (1 + i) * 3000);
3730
3731 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3732
3733 /*
3734 * Use readq directly, so we don't need to mark it as PRESENT
3735 * until we get a successful indication that all is well.
3736 */
3737 val = readq(&dd->kregbase[kr_revision]);
3738 if (val == dd->revision)
3739 break;
3740 if (i == 5) {
3741 qib_dev_err(dd,
3742 "Failed to initialize after reset, unusable\n");
3743 ret = 0;
3744 goto bail;
3745 }
3746 }
3747
3748 dd->flags |= QIB_PRESENT; /* it's back */
3749
3750 if (msix_entries) {
3751 /* restore the MSIx vector address and data if saved above */
3752 for (i = 0; i < msix_entries; i++) {
3753 dd->cspec->msix_entries[i].msix.entry = i;
3754 if (!msix_vecsave || !msix_vecsave[2 * i])
3755 continue;
3756 qib_write_kreg(dd, 2 * i +
3757 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3758 msix_vecsave[2 * i]);
3759 qib_write_kreg(dd, 1 + 2 * i +
3760 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3761 msix_vecsave[1 + 2 * i]);
3762 }
3763 }
3764
3765 /* initialize the remaining registers. */
3766 for (i = 0; i < dd->num_pports; ++i)
3767 write_7322_init_portregs(&dd->pport[i]);
3768 write_7322_initregs(dd);
3769
3770 if (qib_pcie_params(dd, dd->lbus_width,
3771 &dd->cspec->num_msix_entries,
3772 dd->cspec->msix_entries))
3773 qib_dev_err(dd,
3774 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
3775
3776 qib_setup_7322_interrupt(dd, 1);
3777
3778 for (i = 0; i < dd->num_pports; ++i) {
3779 struct qib_pportdata *ppd = &dd->pport[i];
3780
3781 spin_lock_irqsave(&ppd->lflags_lock, flags);
3782 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3783 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3784 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3785 }
3786
3787 bail:
3788 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3789 kfree(msix_vecsave);
3790 return ret;
3791 }
3792
3793 /**
3794 * qib_7322_put_tid - write a TID to the chip
3795 * @dd: the qlogic_ib device
3796 * @tidptr: pointer to the expected TID (in chip) to update
3797 * @tidtype: 0 for eager, 1 for expected
3798 * @pa: physical address of in memory buffer; tidinvalid if freeing
3799 */
3800 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3801 u32 type, unsigned long pa)
3802 {
3803 if (!(dd->flags & QIB_PRESENT))
3804 return;
3805 if (pa != dd->tidinvalid) {
3806 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3807
3808 /* paranoia checks */
3809 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3810 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3811 pa);
3812 return;
3813 }
3814 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3815 qib_dev_err(dd,
3816 "Physical page address 0x%lx larger than supported\n",
3817 pa);
3818 return;
3819 }
3820
3821 if (type == RCVHQ_RCV_TYPE_EAGER)
3822 chippa |= dd->tidtemplate;
3823 else /* for now, always full 4KB page */
3824 chippa |= IBA7322_TID_SZ_4K;
3825 pa = chippa;
3826 }
3827 writeq(pa, tidptr);
3828 mmiowb();
3829 }
3830
3831 /**
3832 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3833 * @dd: the qlogic_ib device
3834 * @ctxt: the ctxt
3835 *
3836 * clear all TID entries for a ctxt, expected and eager.
3837 * Used from qib_close().
3838 */
3839 static void qib_7322_clear_tids(struct qib_devdata *dd,
3840 struct qib_ctxtdata *rcd)
3841 {
3842 u64 __iomem *tidbase;
3843 unsigned long tidinv;
3844 u32 ctxt;
3845 int i;
3846
3847 if (!dd->kregbase || !rcd)
3848 return;
3849
3850 ctxt = rcd->ctxt;
3851
3852 tidinv = dd->tidinvalid;
3853 tidbase = (u64 __iomem *)
3854 ((char __iomem *) dd->kregbase +
3855 dd->rcvtidbase +
3856 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3857
3858 for (i = 0; i < dd->rcvtidcnt; i++)
3859 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3860 tidinv);
3861
3862 tidbase = (u64 __iomem *)
3863 ((char __iomem *) dd->kregbase +
3864 dd->rcvegrbase +
3865 rcd->rcvegr_tid_base * sizeof(*tidbase));
3866
3867 for (i = 0; i < rcd->rcvegrcnt; i++)
3868 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3869 tidinv);
3870 }
3871
3872 /**
3873 * qib_7322_tidtemplate - setup constants for TID updates
3874 * @dd: the qlogic_ib device
3875 *
3876 * We setup stuff that we use a lot, to avoid calculating each time
3877 */
3878 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3879 {
3880 /*
3881 * For now, we always allocate 4KB buffers (at init) so we can
3882 * receive max size packets. We may want a module parameter to
3883 * specify 2KB or 4KB and/or make it per port instead of per device
3884 * for those who want to reduce memory footprint. Note that the
3885 * rcvhdrentsize size must be large enough to hold the largest
3886 * IB header (currently 96 bytes) that we expect to handle (plus of
3887 * course the 2 dwords of RHF).
3888 */
3889 if (dd->rcvegrbufsize == 2048)
3890 dd->tidtemplate = IBA7322_TID_SZ_2K;
3891 else if (dd->rcvegrbufsize == 4096)
3892 dd->tidtemplate = IBA7322_TID_SZ_4K;
3893 dd->tidinvalid = 0;
3894 }
3895
3896 /**
3897 * qib_init_7322_get_base_info - set chip-specific flags for user code
3898 * @rcd: the qlogic_ib ctxt
3899 * @kbase: qib_base_info pointer
3900 *
3901 * We set the PCIE flag because the lower bandwidth on PCIe vs
3902 * HyperTransport can affect some user packet algorithims.
3903 */
3904
3905 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3906 struct qib_base_info *kinfo)
3907 {
3908 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3909 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3910 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3911 if (rcd->dd->cspec->r1)
3912 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3913 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3914 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3915
3916 return 0;
3917 }
3918
3919 static struct qib_message_header *
3920 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3921 {
3922 u32 offset = qib_hdrget_offset(rhf_addr);
3923
3924 return (struct qib_message_header *)
3925 (rhf_addr - dd->rhf_offset + offset);
3926 }
3927
3928 /*
3929 * Configure number of contexts.
3930 */
3931 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3932 {
3933 unsigned long flags;
3934 u32 nchipctxts;
3935
3936 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3937 dd->cspec->numctxts = nchipctxts;
3938 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3939 dd->first_user_ctxt = NUM_IB_PORTS +
3940 (qib_n_krcv_queues - 1) * dd->num_pports;
3941 if (dd->first_user_ctxt > nchipctxts)
3942 dd->first_user_ctxt = nchipctxts;
3943 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3944 } else {
3945 dd->first_user_ctxt = NUM_IB_PORTS;
3946 dd->n_krcv_queues = 1;
3947 }
3948
3949 if (!qib_cfgctxts) {
3950 int nctxts = dd->first_user_ctxt + num_online_cpus();
3951
3952 if (nctxts <= 6)
3953 dd->ctxtcnt = 6;
3954 else if (nctxts <= 10)
3955 dd->ctxtcnt = 10;
3956 else if (nctxts <= nchipctxts)
3957 dd->ctxtcnt = nchipctxts;
3958 } else if (qib_cfgctxts < dd->num_pports)
3959 dd->ctxtcnt = dd->num_pports;
3960 else if (qib_cfgctxts <= nchipctxts)
3961 dd->ctxtcnt = qib_cfgctxts;
3962 if (!dd->ctxtcnt) /* none of the above, set to max */
3963 dd->ctxtcnt = nchipctxts;
3964
3965 /*
3966 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3967 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3968 * Lock to be paranoid about later motion, etc.
3969 */
3970 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3971 if (dd->ctxtcnt > 10)
3972 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3973 else if (dd->ctxtcnt > 6)
3974 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3975 /* else configure for default 6 receive ctxts */
3976
3977 /* The XRC opcode is 5. */
3978 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3979
3980 /*
3981 * RcvCtrl *must* be written here so that the
3982 * chip understands how to change rcvegrcnt below.
3983 */
3984 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3985 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3986
3987 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3988 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3989 if (qib_rcvhdrcnt)
3990 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3991 else
3992 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
3993 dd->num_pports > 1 ? 1024U : 2048U);
3994 }
3995
3996 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3997 {
3998
3999 int lsb, ret = 0;
4000 u64 maskr; /* right-justified mask */
4001
4002 switch (which) {
4003
4004 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
4005 ret = ppd->link_width_enabled;
4006 goto done;
4007
4008 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
4009 ret = ppd->link_width_active;
4010 goto done;
4011
4012 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
4013 ret = ppd->link_speed_enabled;
4014 goto done;
4015
4016 case QIB_IB_CFG_SPD: /* Get current Link spd */
4017 ret = ppd->link_speed_active;
4018 goto done;
4019
4020 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
4021 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4022 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4023 break;
4024
4025 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
4026 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4027 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4028 break;
4029
4030 case QIB_IB_CFG_LINKLATENCY:
4031 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
4032 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
4033 goto done;
4034
4035 case QIB_IB_CFG_OP_VLS:
4036 ret = ppd->vls_operational;
4037 goto done;
4038
4039 case QIB_IB_CFG_VL_HIGH_CAP:
4040 ret = 16;
4041 goto done;
4042
4043 case QIB_IB_CFG_VL_LOW_CAP:
4044 ret = 16;
4045 goto done;
4046
4047 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4048 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4049 OverrunThreshold);
4050 goto done;
4051
4052 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4053 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4054 PhyerrThreshold);
4055 goto done;
4056
4057 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4058 /* will only take effect when the link state changes */
4059 ret = (ppd->cpspec->ibcctrl_a &
4060 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
4061 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
4062 goto done;
4063
4064 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
4065 lsb = IBA7322_IBC_HRTBT_LSB;
4066 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4067 break;
4068
4069 case QIB_IB_CFG_PMA_TICKS:
4070 /*
4071 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
4072 * Since the clock is always 250MHz, the value is 3, 1 or 0.
4073 */
4074 if (ppd->link_speed_active == QIB_IB_QDR)
4075 ret = 3;
4076 else if (ppd->link_speed_active == QIB_IB_DDR)
4077 ret = 1;
4078 else
4079 ret = 0;
4080 goto done;
4081
4082 default:
4083 ret = -EINVAL;
4084 goto done;
4085 }
4086 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
4087 done:
4088 return ret;
4089 }
4090
4091 /*
4092 * Below again cribbed liberally from older version. Do not lean
4093 * heavily on it.
4094 */
4095 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
4096 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
4097 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
4098
4099 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
4100 {
4101 struct qib_devdata *dd = ppd->dd;
4102 u64 maskr; /* right-justified mask */
4103 int lsb, ret = 0;
4104 u16 lcmd, licmd;
4105 unsigned long flags;
4106
4107 switch (which) {
4108 case QIB_IB_CFG_LIDLMC:
4109 /*
4110 * Set LID and LMC. Combined to avoid possible hazard
4111 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
4112 */
4113 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
4114 maskr = IBA7322_IBC_DLIDLMC_MASK;
4115 /*
4116 * For header-checking, the SLID in the packet will
4117 * be masked with SendIBSLMCMask, and compared
4118 * with SendIBSLIDAssignMask. Make sure we do not
4119 * set any bits not covered by the mask, or we get
4120 * false-positives.
4121 */
4122 qib_write_kreg_port(ppd, krp_sendslid,
4123 val & (val >> 16) & SendIBSLIDAssignMask);
4124 qib_write_kreg_port(ppd, krp_sendslidmask,
4125 (val >> 16) & SendIBSLMCMask);
4126 break;
4127
4128 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
4129 ppd->link_width_enabled = val;
4130 /* convert IB value to chip register value */
4131 if (val == IB_WIDTH_1X)
4132 val = 0;
4133 else if (val == IB_WIDTH_4X)
4134 val = 1;
4135 else
4136 val = 3;
4137 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
4138 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
4139 break;
4140
4141 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
4142 /*
4143 * As with width, only write the actual register if the
4144 * link is currently down, otherwise takes effect on next
4145 * link change. Since setting is being explicitly requested
4146 * (via MAD or sysfs), clear autoneg failure status if speed
4147 * autoneg is enabled.
4148 */
4149 ppd->link_speed_enabled = val;
4150 val <<= IBA7322_IBC_SPEED_LSB;
4151 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
4152 IBA7322_IBC_MAX_SPEED_MASK;
4153 if (val & (val - 1)) {
4154 /* Muliple speeds enabled */
4155 val |= IBA7322_IBC_IBTA_1_2_MASK |
4156 IBA7322_IBC_MAX_SPEED_MASK;
4157 spin_lock_irqsave(&ppd->lflags_lock, flags);
4158 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
4159 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4160 } else if (val & IBA7322_IBC_SPEED_QDR)
4161 val |= IBA7322_IBC_IBTA_1_2_MASK;
4162 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
4163 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
4164 break;
4165
4166 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
4167 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4168 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4169 break;
4170
4171 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
4172 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4173 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4174 break;
4175
4176 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4177 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4178 OverrunThreshold);
4179 if (maskr != val) {
4180 ppd->cpspec->ibcctrl_a &=
4181 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
4182 ppd->cpspec->ibcctrl_a |= (u64) val <<
4183 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
4184 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4185 ppd->cpspec->ibcctrl_a);
4186 qib_write_kreg(dd, kr_scratch, 0ULL);
4187 }
4188 goto bail;
4189
4190 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4191 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4192 PhyerrThreshold);
4193 if (maskr != val) {
4194 ppd->cpspec->ibcctrl_a &=
4195 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
4196 ppd->cpspec->ibcctrl_a |= (u64) val <<
4197 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
4198 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4199 ppd->cpspec->ibcctrl_a);
4200 qib_write_kreg(dd, kr_scratch, 0ULL);
4201 }
4202 goto bail;
4203
4204 case QIB_IB_CFG_PKEYS: /* update pkeys */
4205 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
4206 ((u64) ppd->pkeys[2] << 32) |
4207 ((u64) ppd->pkeys[3] << 48);
4208 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
4209 goto bail;
4210
4211 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4212 /* will only take effect when the link state changes */
4213 if (val == IB_LINKINITCMD_POLL)
4214 ppd->cpspec->ibcctrl_a &=
4215 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4216 else /* SLEEP */
4217 ppd->cpspec->ibcctrl_a |=
4218 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4219 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4220 qib_write_kreg(dd, kr_scratch, 0ULL);
4221 goto bail;
4222
4223 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
4224 /*
4225 * Update our housekeeping variables, and set IBC max
4226 * size, same as init code; max IBC is max we allow in
4227 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
4228 * Set even if it's unchanged, print debug message only
4229 * on changes.
4230 */
4231 val = (ppd->ibmaxlen >> 2) + 1;
4232 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
4233 ppd->cpspec->ibcctrl_a |= (u64)val <<
4234 SYM_LSB(IBCCtrlA_0, MaxPktLen);
4235 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4236 ppd->cpspec->ibcctrl_a);
4237 qib_write_kreg(dd, kr_scratch, 0ULL);
4238 goto bail;
4239
4240 case QIB_IB_CFG_LSTATE: /* set the IB link state */
4241 switch (val & 0xffff0000) {
4242 case IB_LINKCMD_DOWN:
4243 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
4244 ppd->cpspec->ibmalfusesnap = 1;
4245 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
4246 crp_errlink);
4247 if (!ppd->cpspec->ibdeltainprog &&
4248 qib_compat_ddr_negotiate) {
4249 ppd->cpspec->ibdeltainprog = 1;
4250 ppd->cpspec->ibsymsnap =
4251 read_7322_creg32_port(ppd,
4252 crp_ibsymbolerr);
4253 ppd->cpspec->iblnkerrsnap =
4254 read_7322_creg32_port(ppd,
4255 crp_iblinkerrrecov);
4256 }
4257 break;
4258
4259 case IB_LINKCMD_ARMED:
4260 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
4261 if (ppd->cpspec->ibmalfusesnap) {
4262 ppd->cpspec->ibmalfusesnap = 0;
4263 ppd->cpspec->ibmalfdelta +=
4264 read_7322_creg32_port(ppd,
4265 crp_errlink) -
4266 ppd->cpspec->ibmalfsnap;
4267 }
4268 break;
4269
4270 case IB_LINKCMD_ACTIVE:
4271 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
4272 break;
4273
4274 default:
4275 ret = -EINVAL;
4276 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
4277 goto bail;
4278 }
4279 switch (val & 0xffff) {
4280 case IB_LINKINITCMD_NOP:
4281 licmd = 0;
4282 break;
4283
4284 case IB_LINKINITCMD_POLL:
4285 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
4286 break;
4287
4288 case IB_LINKINITCMD_SLEEP:
4289 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
4290 break;
4291
4292 case IB_LINKINITCMD_DISABLE:
4293 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
4294 ppd->cpspec->chase_end = 0;
4295 /*
4296 * stop state chase counter and timer, if running.
4297 * wait forpending timer, but don't clear .data (ppd)!
4298 */
4299 if (ppd->cpspec->chase_timer.expires) {
4300 del_timer_sync(&ppd->cpspec->chase_timer);
4301 ppd->cpspec->chase_timer.expires = 0;
4302 }
4303 break;
4304
4305 default:
4306 ret = -EINVAL;
4307 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
4308 val & 0xffff);
4309 goto bail;
4310 }
4311 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
4312 goto bail;
4313
4314 case QIB_IB_CFG_OP_VLS:
4315 if (ppd->vls_operational != val) {
4316 ppd->vls_operational = val;
4317 set_vls(ppd);
4318 }
4319 goto bail;
4320
4321 case QIB_IB_CFG_VL_HIGH_LIMIT:
4322 qib_write_kreg_port(ppd, krp_highprio_limit, val);
4323 goto bail;
4324
4325 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
4326 if (val > 3) {
4327 ret = -EINVAL;
4328 goto bail;
4329 }
4330 lsb = IBA7322_IBC_HRTBT_LSB;
4331 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4332 break;
4333
4334 case QIB_IB_CFG_PORT:
4335 /* val is the port number of the switch we are connected to. */
4336 if (ppd->dd->cspec->r1) {
4337 cancel_delayed_work(&ppd->cpspec->ipg_work);
4338 ppd->cpspec->ipg_tries = 0;
4339 }
4340 goto bail;
4341
4342 default:
4343 ret = -EINVAL;
4344 goto bail;
4345 }
4346 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4347 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4348 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4349 qib_write_kreg(dd, kr_scratch, 0);
4350 bail:
4351 return ret;
4352 }
4353
4354 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4355 {
4356 int ret = 0;
4357 u64 val, ctrlb;
4358
4359 /* only IBC loopback, may add serdes and xgxs loopbacks later */
4360 if (!strncmp(what, "ibc", 3)) {
4361 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4362 Loopback);
4363 val = 0; /* disable heart beat, so link will come up */
4364 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4365 ppd->dd->unit, ppd->port);
4366 } else if (!strncmp(what, "off", 3)) {
4367 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4368 Loopback);
4369 /* enable heart beat again */
4370 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4371 qib_devinfo(ppd->dd->pcidev,
4372 "Disabling IB%u:%u IBC loopback (normal)\n",
4373 ppd->dd->unit, ppd->port);
4374 } else
4375 ret = -EINVAL;
4376 if (!ret) {
4377 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4378 ppd->cpspec->ibcctrl_a);
4379 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4380 << IBA7322_IBC_HRTBT_LSB);
4381 ppd->cpspec->ibcctrl_b = ctrlb | val;
4382 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4383 ppd->cpspec->ibcctrl_b);
4384 qib_write_kreg(ppd->dd, kr_scratch, 0);
4385 }
4386 return ret;
4387 }
4388
4389 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4390 struct ib_vl_weight_elem *vl)
4391 {
4392 unsigned i;
4393
4394 for (i = 0; i < 16; i++, regno++, vl++) {
4395 u32 val = qib_read_kreg_port(ppd, regno);
4396
4397 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4398 SYM_RMASK(LowPriority0_0, VirtualLane);
4399 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4400 SYM_RMASK(LowPriority0_0, Weight);
4401 }
4402 }
4403
4404 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4405 struct ib_vl_weight_elem *vl)
4406 {
4407 unsigned i;
4408
4409 for (i = 0; i < 16; i++, regno++, vl++) {
4410 u64 val;
4411
4412 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4413 SYM_LSB(LowPriority0_0, VirtualLane)) |
4414 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4415 SYM_LSB(LowPriority0_0, Weight));
4416 qib_write_kreg_port(ppd, regno, val);
4417 }
4418 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4419 struct qib_devdata *dd = ppd->dd;
4420 unsigned long flags;
4421
4422 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4423 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4424 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4425 qib_write_kreg(dd, kr_scratch, 0);
4426 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4427 }
4428 }
4429
4430 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4431 {
4432 switch (which) {
4433 case QIB_IB_TBL_VL_HIGH_ARB:
4434 get_vl_weights(ppd, krp_highprio_0, t);
4435 break;
4436
4437 case QIB_IB_TBL_VL_LOW_ARB:
4438 get_vl_weights(ppd, krp_lowprio_0, t);
4439 break;
4440
4441 default:
4442 return -EINVAL;
4443 }
4444 return 0;
4445 }
4446
4447 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4448 {
4449 switch (which) {
4450 case QIB_IB_TBL_VL_HIGH_ARB:
4451 set_vl_weights(ppd, krp_highprio_0, t);
4452 break;
4453
4454 case QIB_IB_TBL_VL_LOW_ARB:
4455 set_vl_weights(ppd, krp_lowprio_0, t);
4456 break;
4457
4458 default:
4459 return -EINVAL;
4460 }
4461 return 0;
4462 }
4463
4464 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4465 u32 updegr, u32 egrhd, u32 npkts)
4466 {
4467 /*
4468 * Need to write timeout register before updating rcvhdrhead to ensure
4469 * that the timer is enabled on reception of a packet.
4470 */
4471 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4472 adjust_rcv_timeout(rcd, npkts);
4473 if (updegr)
4474 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4475 mmiowb();
4476 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4477 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4478 mmiowb();
4479 }
4480
4481 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4482 {
4483 u32 head, tail;
4484
4485 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4486 if (rcd->rcvhdrtail_kvaddr)
4487 tail = qib_get_rcvhdrtail(rcd);
4488 else
4489 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4490 return head == tail;
4491 }
4492
4493 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4494 QIB_RCVCTRL_CTXT_DIS | \
4495 QIB_RCVCTRL_TIDFLOW_ENB | \
4496 QIB_RCVCTRL_TIDFLOW_DIS | \
4497 QIB_RCVCTRL_TAILUPD_ENB | \
4498 QIB_RCVCTRL_TAILUPD_DIS | \
4499 QIB_RCVCTRL_INTRAVAIL_ENB | \
4500 QIB_RCVCTRL_INTRAVAIL_DIS | \
4501 QIB_RCVCTRL_BP_ENB | \
4502 QIB_RCVCTRL_BP_DIS)
4503
4504 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4505 QIB_RCVCTRL_CTXT_DIS | \
4506 QIB_RCVCTRL_PKEY_DIS | \
4507 QIB_RCVCTRL_PKEY_ENB)
4508
4509 /*
4510 * Modify the RCVCTRL register in chip-specific way. This
4511 * is a function because bit positions and (future) register
4512 * location is chip-specifc, but the needed operations are
4513 * generic. <op> is a bit-mask because we often want to
4514 * do multiple modifications.
4515 */
4516 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4517 int ctxt)
4518 {
4519 struct qib_devdata *dd = ppd->dd;
4520 struct qib_ctxtdata *rcd;
4521 u64 mask, val;
4522 unsigned long flags;
4523
4524 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4525
4526 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4527 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4528 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4529 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4530 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4531 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4532 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4533 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4534 if (op & QIB_RCVCTRL_PKEY_ENB)
4535 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4536 if (op & QIB_RCVCTRL_PKEY_DIS)
4537 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4538 if (ctxt < 0) {
4539 mask = (1ULL << dd->ctxtcnt) - 1;
4540 rcd = NULL;
4541 } else {
4542 mask = (1ULL << ctxt);
4543 rcd = dd->rcd[ctxt];
4544 }
4545 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4546 ppd->p_rcvctrl |=
4547 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4548 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4549 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4550 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4551 }
4552 /* Write these registers before the context is enabled. */
4553 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4554 rcd->rcvhdrqtailaddr_phys);
4555 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4556 rcd->rcvhdrq_phys);
4557 rcd->seq_cnt = 1;
4558 }
4559 if (op & QIB_RCVCTRL_CTXT_DIS)
4560 ppd->p_rcvctrl &=
4561 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4562 if (op & QIB_RCVCTRL_BP_ENB)
4563 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4564 if (op & QIB_RCVCTRL_BP_DIS)
4565 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4566 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4567 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4568 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4569 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4570 /*
4571 * Decide which registers to write depending on the ops enabled.
4572 * Special case is "flush" (no bits set at all)
4573 * which needs to write both.
4574 */
4575 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4576 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4577 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4578 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4579 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4580 /*
4581 * Init the context registers also; if we were
4582 * disabled, tail and head should both be zero
4583 * already from the enable, but since we don't
4584 * know, we have to do it explicitly.
4585 */
4586 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4587 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4588
4589 /* be sure enabling write seen; hd/tl should be 0 */
4590 (void) qib_read_kreg32(dd, kr_scratch);
4591 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4592 dd->rcd[ctxt]->head = val;
4593 /* If kctxt, interrupt on next receive. */
4594 if (ctxt < dd->first_user_ctxt)
4595 val |= dd->rhdrhead_intr_off;
4596 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4597 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4598 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4599 /* arm rcv interrupt */
4600 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4601 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4602 }
4603 if (op & QIB_RCVCTRL_CTXT_DIS) {
4604 unsigned f;
4605
4606 /* Now that the context is disabled, clear these registers. */
4607 if (ctxt >= 0) {
4608 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4609 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4610 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4611 qib_write_ureg(dd, ur_rcvflowtable + f,
4612 TIDFLOW_ERRBITS, ctxt);
4613 } else {
4614 unsigned i;
4615
4616 for (i = 0; i < dd->cfgctxts; i++) {
4617 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4618 i, 0);
4619 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4620 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4621 qib_write_ureg(dd, ur_rcvflowtable + f,
4622 TIDFLOW_ERRBITS, i);
4623 }
4624 }
4625 }
4626 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4627 }
4628
4629 /*
4630 * Modify the SENDCTRL register in chip-specific way. This
4631 * is a function where there are multiple such registers with
4632 * slightly different layouts.
4633 * The chip doesn't allow back-to-back sendctrl writes, so write
4634 * the scratch register after writing sendctrl.
4635 *
4636 * Which register is written depends on the operation.
4637 * Most operate on the common register, while
4638 * SEND_ENB and SEND_DIS operate on the per-port ones.
4639 * SEND_ENB is included in common because it can change SPCL_TRIG
4640 */
4641 #define SENDCTRL_COMMON_MODS (\
4642 QIB_SENDCTRL_CLEAR | \
4643 QIB_SENDCTRL_AVAIL_DIS | \
4644 QIB_SENDCTRL_AVAIL_ENB | \
4645 QIB_SENDCTRL_AVAIL_BLIP | \
4646 QIB_SENDCTRL_DISARM | \
4647 QIB_SENDCTRL_DISARM_ALL | \
4648 QIB_SENDCTRL_SEND_ENB)
4649
4650 #define SENDCTRL_PORT_MODS (\
4651 QIB_SENDCTRL_CLEAR | \
4652 QIB_SENDCTRL_SEND_ENB | \
4653 QIB_SENDCTRL_SEND_DIS | \
4654 QIB_SENDCTRL_FLUSH)
4655
4656 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4657 {
4658 struct qib_devdata *dd = ppd->dd;
4659 u64 tmp_dd_sendctrl;
4660 unsigned long flags;
4661
4662 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4663
4664 /* First the dd ones that are "sticky", saved in shadow */
4665 if (op & QIB_SENDCTRL_CLEAR)
4666 dd->sendctrl = 0;
4667 if (op & QIB_SENDCTRL_AVAIL_DIS)
4668 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4669 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4670 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4671 if (dd->flags & QIB_USE_SPCL_TRIG)
4672 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4673 }
4674
4675 /* Then the ppd ones that are "sticky", saved in shadow */
4676 if (op & QIB_SENDCTRL_SEND_DIS)
4677 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4678 else if (op & QIB_SENDCTRL_SEND_ENB)
4679 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4680
4681 if (op & QIB_SENDCTRL_DISARM_ALL) {
4682 u32 i, last;
4683
4684 tmp_dd_sendctrl = dd->sendctrl;
4685 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4686 /*
4687 * Disarm any buffers that are not yet launched,
4688 * disabling updates until done.
4689 */
4690 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4691 for (i = 0; i < last; i++) {
4692 qib_write_kreg(dd, kr_sendctrl,
4693 tmp_dd_sendctrl |
4694 SYM_MASK(SendCtrl, Disarm) | i);
4695 qib_write_kreg(dd, kr_scratch, 0);
4696 }
4697 }
4698
4699 if (op & QIB_SENDCTRL_FLUSH) {
4700 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4701
4702 /*
4703 * Now drain all the fifos. The Abort bit should never be
4704 * needed, so for now, at least, we don't use it.
4705 */
4706 tmp_ppd_sendctrl |=
4707 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4708 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4709 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4710 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4711 qib_write_kreg(dd, kr_scratch, 0);
4712 }
4713
4714 tmp_dd_sendctrl = dd->sendctrl;
4715
4716 if (op & QIB_SENDCTRL_DISARM)
4717 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4718 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4719 SYM_LSB(SendCtrl, DisarmSendBuf));
4720 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4721 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4722 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4723
4724 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4725 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4726 qib_write_kreg(dd, kr_scratch, 0);
4727 }
4728
4729 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4730 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4731 qib_write_kreg(dd, kr_scratch, 0);
4732 }
4733
4734 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4735 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4736 qib_write_kreg(dd, kr_scratch, 0);
4737 }
4738
4739 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4740
4741 if (op & QIB_SENDCTRL_FLUSH) {
4742 u32 v;
4743 /*
4744 * ensure writes have hit chip, then do a few
4745 * more reads, to allow DMA of pioavail registers
4746 * to occur, so in-memory copy is in sync with
4747 * the chip. Not always safe to sleep.
4748 */
4749 v = qib_read_kreg32(dd, kr_scratch);
4750 qib_write_kreg(dd, kr_scratch, v);
4751 v = qib_read_kreg32(dd, kr_scratch);
4752 qib_write_kreg(dd, kr_scratch, v);
4753 qib_read_kreg32(dd, kr_scratch);
4754 }
4755 }
4756
4757 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4758 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4759 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4760
4761 /**
4762 * qib_portcntr_7322 - read a per-port chip counter
4763 * @ppd: the qlogic_ib pport
4764 * @creg: the counter to read (not a chip offset)
4765 */
4766 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4767 {
4768 struct qib_devdata *dd = ppd->dd;
4769 u64 ret = 0ULL;
4770 u16 creg;
4771 /* 0xffff for unimplemented or synthesized counters */
4772 static const u32 xlator[] = {
4773 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4774 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4775 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4776 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4777 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4778 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4779 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4780 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4781 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4782 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4783 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4784 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4785 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4786 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4787 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4788 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4789 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4790 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4791 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4792 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4793 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4794 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4795 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4796 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4797 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4798 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4799 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4800 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4801 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4802 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4803 /*
4804 * the next 3 aren't really counters, but were implemented
4805 * as counters in older chips, so still get accessed as
4806 * though they were counters from this code.
4807 */
4808 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4809 [QIBPORTCNTR_PSSTART] = krp_psstart,
4810 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4811 /* pseudo-counter, summed for all ports */
4812 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4813 };
4814
4815 if (reg >= ARRAY_SIZE(xlator)) {
4816 qib_devinfo(ppd->dd->pcidev,
4817 "Unimplemented portcounter %u\n", reg);
4818 goto done;
4819 }
4820 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4821
4822 /* handle non-counters and special cases first */
4823 if (reg == QIBPORTCNTR_KHDROVFL) {
4824 int i;
4825
4826 /* sum over all kernel contexts (skip if mini_init) */
4827 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4828 struct qib_ctxtdata *rcd = dd->rcd[i];
4829
4830 if (!rcd || rcd->ppd != ppd)
4831 continue;
4832 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4833 }
4834 goto done;
4835 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4836 /*
4837 * Used as part of the synthesis of port_rcv_errors
4838 * in the verbs code for IBTA counters. Not needed for 7322,
4839 * because all the errors are already counted by other cntrs.
4840 */
4841 goto done;
4842 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4843 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4844 /* were counters in older chips, now per-port kernel regs */
4845 ret = qib_read_kreg_port(ppd, creg);
4846 goto done;
4847 }
4848
4849 /*
4850 * Only fast increment counters are 64 bits; use 32 bit reads to
4851 * avoid two independent reads when on Opteron.
4852 */
4853 if (xlator[reg] & _PORT_64BIT_FLAG)
4854 ret = read_7322_creg_port(ppd, creg);
4855 else
4856 ret = read_7322_creg32_port(ppd, creg);
4857 if (creg == crp_ibsymbolerr) {
4858 if (ppd->cpspec->ibdeltainprog)
4859 ret -= ret - ppd->cpspec->ibsymsnap;
4860 ret -= ppd->cpspec->ibsymdelta;
4861 } else if (creg == crp_iblinkerrrecov) {
4862 if (ppd->cpspec->ibdeltainprog)
4863 ret -= ret - ppd->cpspec->iblnkerrsnap;
4864 ret -= ppd->cpspec->iblnkerrdelta;
4865 } else if (creg == crp_errlink)
4866 ret -= ppd->cpspec->ibmalfdelta;
4867 else if (creg == crp_iblinkdown)
4868 ret += ppd->cpspec->iblnkdowndelta;
4869 done:
4870 return ret;
4871 }
4872
4873 /*
4874 * Device counter names (not port-specific), one line per stat,
4875 * single string. Used by utilities like ipathstats to print the stats
4876 * in a way which works for different versions of drivers, without changing
4877 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4878 * display by utility.
4879 * Non-error counters are first.
4880 * Start of "error" conters is indicated by a leading "E " on the first
4881 * "error" counter, and doesn't count in label length.
4882 * The EgrOvfl list needs to be last so we truncate them at the configured
4883 * context count for the device.
4884 * cntr7322indices contains the corresponding register indices.
4885 */
4886 static const char cntr7322names[] =
4887 "Interrupts\n"
4888 "HostBusStall\n"
4889 "E RxTIDFull\n"
4890 "RxTIDInvalid\n"
4891 "RxTIDFloDrop\n" /* 7322 only */
4892 "Ctxt0EgrOvfl\n"
4893 "Ctxt1EgrOvfl\n"
4894 "Ctxt2EgrOvfl\n"
4895 "Ctxt3EgrOvfl\n"
4896 "Ctxt4EgrOvfl\n"
4897 "Ctxt5EgrOvfl\n"
4898 "Ctxt6EgrOvfl\n"
4899 "Ctxt7EgrOvfl\n"
4900 "Ctxt8EgrOvfl\n"
4901 "Ctxt9EgrOvfl\n"
4902 "Ctx10EgrOvfl\n"
4903 "Ctx11EgrOvfl\n"
4904 "Ctx12EgrOvfl\n"
4905 "Ctx13EgrOvfl\n"
4906 "Ctx14EgrOvfl\n"
4907 "Ctx15EgrOvfl\n"
4908 "Ctx16EgrOvfl\n"
4909 "Ctx17EgrOvfl\n"
4910 ;
4911
4912 static const u32 cntr7322indices[] = {
4913 cr_lbint | _PORT_64BIT_FLAG,
4914 cr_lbstall | _PORT_64BIT_FLAG,
4915 cr_tidfull,
4916 cr_tidinvalid,
4917 cr_rxtidflowdrop,
4918 cr_base_egrovfl + 0,
4919 cr_base_egrovfl + 1,
4920 cr_base_egrovfl + 2,
4921 cr_base_egrovfl + 3,
4922 cr_base_egrovfl + 4,
4923 cr_base_egrovfl + 5,
4924 cr_base_egrovfl + 6,
4925 cr_base_egrovfl + 7,
4926 cr_base_egrovfl + 8,
4927 cr_base_egrovfl + 9,
4928 cr_base_egrovfl + 10,
4929 cr_base_egrovfl + 11,
4930 cr_base_egrovfl + 12,
4931 cr_base_egrovfl + 13,
4932 cr_base_egrovfl + 14,
4933 cr_base_egrovfl + 15,
4934 cr_base_egrovfl + 16,
4935 cr_base_egrovfl + 17,
4936 };
4937
4938 /*
4939 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4940 * portcntr7322indices is somewhat complicated by some registers needing
4941 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4942 */
4943 static const char portcntr7322names[] =
4944 "TxPkt\n"
4945 "TxFlowPkt\n"
4946 "TxWords\n"
4947 "RxPkt\n"
4948 "RxFlowPkt\n"
4949 "RxWords\n"
4950 "TxFlowStall\n"
4951 "TxDmaDesc\n" /* 7220 and 7322-only */
4952 "E RxDlidFltr\n" /* 7220 and 7322-only */
4953 "IBStatusChng\n"
4954 "IBLinkDown\n"
4955 "IBLnkRecov\n"
4956 "IBRxLinkErr\n"
4957 "IBSymbolErr\n"
4958 "RxLLIErr\n"
4959 "RxBadFormat\n"
4960 "RxBadLen\n"
4961 "RxBufOvrfl\n"
4962 "RxEBP\n"
4963 "RxFlowCtlErr\n"
4964 "RxICRCerr\n"
4965 "RxLPCRCerr\n"
4966 "RxVCRCerr\n"
4967 "RxInvalLen\n"
4968 "RxInvalPKey\n"
4969 "RxPktDropped\n"
4970 "TxBadLength\n"
4971 "TxDropped\n"
4972 "TxInvalLen\n"
4973 "TxUnderrun\n"
4974 "TxUnsupVL\n"
4975 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4976 "RxVL15Drop\n"
4977 "RxVlErr\n"
4978 "XcessBufOvfl\n"
4979 "RxQPBadCtxt\n" /* 7322-only from here down */
4980 "TXBadHeader\n"
4981 ;
4982
4983 static const u32 portcntr7322indices[] = {
4984 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4985 crp_pktsendflow,
4986 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4987 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4988 crp_pktrcvflowctrl,
4989 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4990 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4991 crp_txsdmadesc | _PORT_64BIT_FLAG,
4992 crp_rxdlidfltr,
4993 crp_ibstatuschange,
4994 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4995 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4996 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4997 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4998 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4999 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
5000 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
5001 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
5002 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
5003 crp_rcvflowctrlviol,
5004 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
5005 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
5006 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
5007 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
5008 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
5009 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
5010 crp_txminmaxlenerr,
5011 crp_txdroppedpkt,
5012 crp_txlenerr,
5013 crp_txunderrun,
5014 crp_txunsupvl,
5015 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
5016 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
5017 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
5018 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
5019 crp_rxqpinvalidctxt,
5020 crp_txhdrerr,
5021 };
5022
5023 /* do all the setup to make the counter reads efficient later */
5024 static void init_7322_cntrnames(struct qib_devdata *dd)
5025 {
5026 int i, j = 0;
5027 char *s;
5028
5029 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
5030 i++) {
5031 /* we always have at least one counter before the egrovfl */
5032 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
5033 j = 1;
5034 s = strchr(s + 1, '\n');
5035 if (s && j)
5036 j++;
5037 }
5038 dd->cspec->ncntrs = i;
5039 if (!s)
5040 /* full list; size is without terminating null */
5041 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
5042 else
5043 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
5044 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
5045 * sizeof(u64), GFP_KERNEL);
5046 if (!dd->cspec->cntrs)
5047 qib_dev_err(dd, "Failed allocation for counters\n");
5048
5049 for (i = 0, s = (char *)portcntr7322names; s; i++)
5050 s = strchr(s + 1, '\n');
5051 dd->cspec->nportcntrs = i - 1;
5052 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
5053 for (i = 0; i < dd->num_pports; ++i) {
5054 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
5055 * sizeof(u64), GFP_KERNEL);
5056 if (!dd->pport[i].cpspec->portcntrs)
5057 qib_dev_err(dd,
5058 "Failed allocation for portcounters\n");
5059 }
5060 }
5061
5062 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
5063 u64 **cntrp)
5064 {
5065 u32 ret;
5066
5067 if (namep) {
5068 ret = dd->cspec->cntrnamelen;
5069 if (pos >= ret)
5070 ret = 0; /* final read after getting everything */
5071 else
5072 *namep = (char *) cntr7322names;
5073 } else {
5074 u64 *cntr = dd->cspec->cntrs;
5075 int i;
5076
5077 ret = dd->cspec->ncntrs * sizeof(u64);
5078 if (!cntr || pos >= ret) {
5079 /* everything read, or couldn't get memory */
5080 ret = 0;
5081 goto done;
5082 }
5083 *cntrp = cntr;
5084 for (i = 0; i < dd->cspec->ncntrs; i++)
5085 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
5086 *cntr++ = read_7322_creg(dd,
5087 cntr7322indices[i] &
5088 _PORT_CNTR_IDXMASK);
5089 else
5090 *cntr++ = read_7322_creg32(dd,
5091 cntr7322indices[i]);
5092 }
5093 done:
5094 return ret;
5095 }
5096
5097 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
5098 char **namep, u64 **cntrp)
5099 {
5100 u32 ret;
5101
5102 if (namep) {
5103 ret = dd->cspec->portcntrnamelen;
5104 if (pos >= ret)
5105 ret = 0; /* final read after getting everything */
5106 else
5107 *namep = (char *)portcntr7322names;
5108 } else {
5109 struct qib_pportdata *ppd = &dd->pport[port];
5110 u64 *cntr = ppd->cpspec->portcntrs;
5111 int i;
5112
5113 ret = dd->cspec->nportcntrs * sizeof(u64);
5114 if (!cntr || pos >= ret) {
5115 /* everything read, or couldn't get memory */
5116 ret = 0;
5117 goto done;
5118 }
5119 *cntrp = cntr;
5120 for (i = 0; i < dd->cspec->nportcntrs; i++) {
5121 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
5122 *cntr++ = qib_portcntr_7322(ppd,
5123 portcntr7322indices[i] &
5124 _PORT_CNTR_IDXMASK);
5125 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
5126 *cntr++ = read_7322_creg_port(ppd,
5127 portcntr7322indices[i] &
5128 _PORT_CNTR_IDXMASK);
5129 else
5130 *cntr++ = read_7322_creg32_port(ppd,
5131 portcntr7322indices[i]);
5132 }
5133 }
5134 done:
5135 return ret;
5136 }
5137
5138 /**
5139 * qib_get_7322_faststats - get word counters from chip before they overflow
5140 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
5141 *
5142 * VESTIGIAL IBA7322 has no "small fast counters", so the only
5143 * real purpose of this function is to maintain the notion of
5144 * "active time", which in turn is only logged into the eeprom,
5145 * which we don;t have, yet, for 7322-based boards.
5146 *
5147 * called from add_timer
5148 */
5149 static void qib_get_7322_faststats(unsigned long opaque)
5150 {
5151 struct qib_devdata *dd = (struct qib_devdata *) opaque;
5152 struct qib_pportdata *ppd;
5153 unsigned long flags;
5154 u64 traffic_wds;
5155 int pidx;
5156
5157 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5158 ppd = dd->pport + pidx;
5159
5160 /*
5161 * If port isn't enabled or not operational ports, or
5162 * diags is running (can cause memory diags to fail)
5163 * skip this port this time.
5164 */
5165 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
5166 || dd->diag_client)
5167 continue;
5168
5169 /*
5170 * Maintain an activity timer, based on traffic
5171 * exceeding a threshold, so we need to check the word-counts
5172 * even if they are 64-bit.
5173 */
5174 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
5175 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
5176 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
5177 traffic_wds -= ppd->dd->traffic_wds;
5178 ppd->dd->traffic_wds += traffic_wds;
5179 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
5180 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
5181 QIB_IB_QDR) &&
5182 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
5183 QIBL_LINKACTIVE)) &&
5184 ppd->cpspec->qdr_dfe_time &&
5185 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) {
5186 ppd->cpspec->qdr_dfe_on = 0;
5187
5188 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
5189 ppd->dd->cspec->r1 ?
5190 QDR_STATIC_ADAPT_INIT_R1 :
5191 QDR_STATIC_ADAPT_INIT);
5192 force_h1(ppd);
5193 }
5194 }
5195 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
5196 }
5197
5198 /*
5199 * If we were using MSIx, try to fallback to INTx.
5200 */
5201 static int qib_7322_intr_fallback(struct qib_devdata *dd)
5202 {
5203 if (!dd->cspec->num_msix_entries)
5204 return 0; /* already using INTx */
5205
5206 qib_devinfo(dd->pcidev,
5207 "MSIx interrupt not detected, trying INTx interrupts\n");
5208 qib_7322_nomsix(dd);
5209 qib_enable_intx(dd->pcidev);
5210 qib_setup_7322_interrupt(dd, 0);
5211 return 1;
5212 }
5213
5214 /*
5215 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
5216 * than resetting the IBC or external link state, and useful in some
5217 * cases to cause some retraining. To do this right, we reset IBC
5218 * as well, then return to previous state (which may be still in reset)
5219 * NOTE: some callers of this "know" this writes the current value
5220 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
5221 * check all callers.
5222 */
5223 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
5224 {
5225 u64 val;
5226 struct qib_devdata *dd = ppd->dd;
5227 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
5228 SYM_MASK(IBPCSConfig_0, xcv_treset) |
5229 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
5230
5231 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
5232 qib_write_kreg(dd, kr_hwerrmask,
5233 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
5234 qib_write_kreg_port(ppd, krp_ibcctrl_a,
5235 ppd->cpspec->ibcctrl_a &
5236 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
5237
5238 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
5239 qib_read_kreg32(dd, kr_scratch);
5240 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
5241 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
5242 qib_write_kreg(dd, kr_scratch, 0ULL);
5243 qib_write_kreg(dd, kr_hwerrclear,
5244 SYM_MASK(HwErrClear, statusValidNoEopClear));
5245 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
5246 }
5247
5248 /*
5249 * This code for non-IBTA-compliant IB speed negotiation is only known to
5250 * work for the SDR to DDR transition, and only between an HCA and a switch
5251 * with recent firmware. It is based on observed heuristics, rather than
5252 * actual knowledge of the non-compliant speed negotiation.
5253 * It has a number of hard-coded fields, since the hope is to rewrite this
5254 * when a spec is available on how the negoation is intended to work.
5255 */
5256 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
5257 u32 dcnt, u32 *data)
5258 {
5259 int i;
5260 u64 pbc;
5261 u32 __iomem *piobuf;
5262 u32 pnum, control, len;
5263 struct qib_devdata *dd = ppd->dd;
5264
5265 i = 0;
5266 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
5267 control = qib_7322_setpbc_control(ppd, len, 0, 15);
5268 pbc = ((u64) control << 32) | len;
5269 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
5270 if (i++ > 15)
5271 return;
5272 udelay(2);
5273 }
5274 /* disable header check on this packet, since it can't be valid */
5275 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
5276 writeq(pbc, piobuf);
5277 qib_flush_wc();
5278 qib_pio_copy(piobuf + 2, hdr, 7);
5279 qib_pio_copy(piobuf + 9, data, dcnt);
5280 if (dd->flags & QIB_USE_SPCL_TRIG) {
5281 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
5282
5283 qib_flush_wc();
5284 __raw_writel(0xaebecede, piobuf + spcl_off);
5285 }
5286 qib_flush_wc();
5287 qib_sendbuf_done(dd, pnum);
5288 /* and re-enable hdr check */
5289 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
5290 }
5291
5292 /*
5293 * _start packet gets sent twice at start, _done gets sent twice at end
5294 */
5295 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
5296 {
5297 struct qib_devdata *dd = ppd->dd;
5298 static u32 swapped;
5299 u32 dw, i, hcnt, dcnt, *data;
5300 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
5301 static u32 madpayload_start[0x40] = {
5302 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5303 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5304 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
5305 };
5306 static u32 madpayload_done[0x40] = {
5307 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5308 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5309 0x40000001, 0x1388, 0x15e, /* rest 0's */
5310 };
5311
5312 dcnt = ARRAY_SIZE(madpayload_start);
5313 hcnt = ARRAY_SIZE(hdr);
5314 if (!swapped) {
5315 /* for maintainability, do it at runtime */
5316 for (i = 0; i < hcnt; i++) {
5317 dw = (__force u32) cpu_to_be32(hdr[i]);
5318 hdr[i] = dw;
5319 }
5320 for (i = 0; i < dcnt; i++) {
5321 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
5322 madpayload_start[i] = dw;
5323 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
5324 madpayload_done[i] = dw;
5325 }
5326 swapped = 1;
5327 }
5328
5329 data = which ? madpayload_done : madpayload_start;
5330
5331 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5332 qib_read_kreg64(dd, kr_scratch);
5333 udelay(2);
5334 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5335 qib_read_kreg64(dd, kr_scratch);
5336 udelay(2);
5337 }
5338
5339 /*
5340 * Do the absolute minimum to cause an IB speed change, and make it
5341 * ready, but don't actually trigger the change. The caller will
5342 * do that when ready (if link is in Polling training state, it will
5343 * happen immediately, otherwise when link next goes down)
5344 *
5345 * This routine should only be used as part of the DDR autonegotation
5346 * code for devices that are not compliant with IB 1.2 (or code that
5347 * fixes things up for same).
5348 *
5349 * When link has gone down, and autoneg enabled, or autoneg has
5350 * failed and we give up until next time we set both speeds, and
5351 * then we want IBTA enabled as well as "use max enabled speed.
5352 */
5353 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5354 {
5355 u64 newctrlb;
5356
5357 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5358 IBA7322_IBC_IBTA_1_2_MASK |
5359 IBA7322_IBC_MAX_SPEED_MASK);
5360
5361 if (speed & (speed - 1)) /* multiple speeds */
5362 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5363 IBA7322_IBC_IBTA_1_2_MASK |
5364 IBA7322_IBC_MAX_SPEED_MASK;
5365 else
5366 newctrlb |= speed == QIB_IB_QDR ?
5367 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5368 ((speed == QIB_IB_DDR ?
5369 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5370
5371 if (newctrlb == ppd->cpspec->ibcctrl_b)
5372 return;
5373
5374 ppd->cpspec->ibcctrl_b = newctrlb;
5375 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5376 qib_write_kreg(ppd->dd, kr_scratch, 0);
5377 }
5378
5379 /*
5380 * This routine is only used when we are not talking to another
5381 * IB 1.2-compliant device that we think can do DDR.
5382 * (This includes all existing switch chips as of Oct 2007.)
5383 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5384 */
5385 static void try_7322_autoneg(struct qib_pportdata *ppd)
5386 {
5387 unsigned long flags;
5388
5389 spin_lock_irqsave(&ppd->lflags_lock, flags);
5390 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5391 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5392 qib_autoneg_7322_send(ppd, 0);
5393 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5394 qib_7322_mini_pcs_reset(ppd);
5395 /* 2 msec is minimum length of a poll cycle */
5396 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5397 msecs_to_jiffies(2));
5398 }
5399
5400 /*
5401 * Handle the empirically determined mechanism for auto-negotiation
5402 * of DDR speed with switches.
5403 */
5404 static void autoneg_7322_work(struct work_struct *work)
5405 {
5406 struct qib_pportdata *ppd;
5407 struct qib_devdata *dd;
5408 u64 startms;
5409 u32 i;
5410 unsigned long flags;
5411
5412 ppd = container_of(work, struct qib_chippport_specific,
5413 autoneg_work.work)->ppd;
5414 dd = ppd->dd;
5415
5416 startms = jiffies_to_msecs(jiffies);
5417
5418 /*
5419 * Busy wait for this first part, it should be at most a
5420 * few hundred usec, since we scheduled ourselves for 2msec.
5421 */
5422 for (i = 0; i < 25; i++) {
5423 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5424 == IB_7322_LT_STATE_POLLQUIET) {
5425 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5426 break;
5427 }
5428 udelay(100);
5429 }
5430
5431 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5432 goto done; /* we got there early or told to stop */
5433
5434 /* we expect this to timeout */
5435 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5436 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5437 msecs_to_jiffies(90)))
5438 goto done;
5439 qib_7322_mini_pcs_reset(ppd);
5440
5441 /* we expect this to timeout */
5442 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5443 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5444 msecs_to_jiffies(1700)))
5445 goto done;
5446 qib_7322_mini_pcs_reset(ppd);
5447
5448 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5449
5450 /*
5451 * Wait up to 250 msec for link to train and get to INIT at DDR;
5452 * this should terminate early.
5453 */
5454 wait_event_timeout(ppd->cpspec->autoneg_wait,
5455 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5456 msecs_to_jiffies(250));
5457 done:
5458 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5459 spin_lock_irqsave(&ppd->lflags_lock, flags);
5460 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5461 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5462 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5463 ppd->cpspec->autoneg_tries = 0;
5464 }
5465 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5466 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5467 }
5468 }
5469
5470 /*
5471 * This routine is used to request IPG set in the QLogic switch.
5472 * Only called if r1.
5473 */
5474 static void try_7322_ipg(struct qib_pportdata *ppd)
5475 {
5476 struct qib_ibport *ibp = &ppd->ibport_data;
5477 struct ib_mad_send_buf *send_buf;
5478 struct ib_mad_agent *agent;
5479 struct ib_smp *smp;
5480 unsigned delay;
5481 int ret;
5482
5483 agent = ibp->rvp.send_agent;
5484 if (!agent)
5485 goto retry;
5486
5487 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5488 IB_MGMT_MAD_DATA, GFP_ATOMIC,
5489 IB_MGMT_BASE_VERSION);
5490 if (IS_ERR(send_buf))
5491 goto retry;
5492
5493 if (!ibp->smi_ah) {
5494 struct ib_ah *ah;
5495
5496 ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE));
5497 if (IS_ERR(ah))
5498 ret = PTR_ERR(ah);
5499 else {
5500 send_buf->ah = ah;
5501 ibp->smi_ah = ibah_to_rvtah(ah);
5502 ret = 0;
5503 }
5504 } else {
5505 send_buf->ah = &ibp->smi_ah->ibah;
5506 ret = 0;
5507 }
5508
5509 smp = send_buf->mad;
5510 smp->base_version = IB_MGMT_BASE_VERSION;
5511 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5512 smp->class_version = 1;
5513 smp->method = IB_MGMT_METHOD_SEND;
5514 smp->hop_cnt = 1;
5515 smp->attr_id = QIB_VENDOR_IPG;
5516 smp->attr_mod = 0;
5517
5518 if (!ret)
5519 ret = ib_post_send_mad(send_buf, NULL);
5520 if (ret)
5521 ib_free_send_mad(send_buf);
5522 retry:
5523 delay = 2 << ppd->cpspec->ipg_tries;
5524 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5525 msecs_to_jiffies(delay));
5526 }
5527
5528 /*
5529 * Timeout handler for setting IPG.
5530 * Only called if r1.
5531 */
5532 static void ipg_7322_work(struct work_struct *work)
5533 {
5534 struct qib_pportdata *ppd;
5535
5536 ppd = container_of(work, struct qib_chippport_specific,
5537 ipg_work.work)->ppd;
5538 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5539 && ++ppd->cpspec->ipg_tries <= 10)
5540 try_7322_ipg(ppd);
5541 }
5542
5543 static u32 qib_7322_iblink_state(u64 ibcs)
5544 {
5545 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5546
5547 switch (state) {
5548 case IB_7322_L_STATE_INIT:
5549 state = IB_PORT_INIT;
5550 break;
5551 case IB_7322_L_STATE_ARM:
5552 state = IB_PORT_ARMED;
5553 break;
5554 case IB_7322_L_STATE_ACTIVE:
5555 /* fall through */
5556 case IB_7322_L_STATE_ACT_DEFER:
5557 state = IB_PORT_ACTIVE;
5558 break;
5559 default: /* fall through */
5560 case IB_7322_L_STATE_DOWN:
5561 state = IB_PORT_DOWN;
5562 break;
5563 }
5564 return state;
5565 }
5566
5567 /* returns the IBTA port state, rather than the IBC link training state */
5568 static u8 qib_7322_phys_portstate(u64 ibcs)
5569 {
5570 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5571 return qib_7322_physportstate[state];
5572 }
5573
5574 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5575 {
5576 int ret = 0, symadj = 0;
5577 unsigned long flags;
5578 int mult;
5579
5580 spin_lock_irqsave(&ppd->lflags_lock, flags);
5581 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5582 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5583
5584 /* Update our picture of width and speed from chip */
5585 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5586 ppd->link_speed_active = QIB_IB_QDR;
5587 mult = 4;
5588 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5589 ppd->link_speed_active = QIB_IB_DDR;
5590 mult = 2;
5591 } else {
5592 ppd->link_speed_active = QIB_IB_SDR;
5593 mult = 1;
5594 }
5595 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5596 ppd->link_width_active = IB_WIDTH_4X;
5597 mult *= 4;
5598 } else
5599 ppd->link_width_active = IB_WIDTH_1X;
5600 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5601
5602 if (!ibup) {
5603 u64 clr;
5604
5605 /* Link went down. */
5606 /* do IPG MAD again after linkdown, even if last time failed */
5607 ppd->cpspec->ipg_tries = 0;
5608 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5609 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5610 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5611 if (clr)
5612 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5613 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5614 QIBL_IB_AUTONEG_INPROG)))
5615 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5616 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5617 struct qib_qsfp_data *qd =
5618 &ppd->cpspec->qsfp_data;
5619 /* unlock the Tx settings, speed may change */
5620 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5621 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5622 reset_tx_deemphasis_override));
5623 qib_cancel_sends(ppd);
5624 /* on link down, ensure sane pcs state */
5625 qib_7322_mini_pcs_reset(ppd);
5626 /* schedule the qsfp refresh which should turn the link
5627 off */
5628 if (ppd->dd->flags & QIB_HAS_QSFP) {
5629 qd->t_insert = jiffies;
5630 queue_work(ib_wq, &qd->work);
5631 }
5632 spin_lock_irqsave(&ppd->sdma_lock, flags);
5633 if (__qib_sdma_running(ppd))
5634 __qib_sdma_process_event(ppd,
5635 qib_sdma_event_e70_go_idle);
5636 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5637 }
5638 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5639 if (clr == ppd->cpspec->iblnkdownsnap)
5640 ppd->cpspec->iblnkdowndelta++;
5641 } else {
5642 if (qib_compat_ddr_negotiate &&
5643 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5644 QIBL_IB_AUTONEG_INPROG)) &&
5645 ppd->link_speed_active == QIB_IB_SDR &&
5646 (ppd->link_speed_enabled & QIB_IB_DDR)
5647 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5648 /* we are SDR, and auto-negotiation enabled */
5649 ++ppd->cpspec->autoneg_tries;
5650 if (!ppd->cpspec->ibdeltainprog) {
5651 ppd->cpspec->ibdeltainprog = 1;
5652 ppd->cpspec->ibsymdelta +=
5653 read_7322_creg32_port(ppd,
5654 crp_ibsymbolerr) -
5655 ppd->cpspec->ibsymsnap;
5656 ppd->cpspec->iblnkerrdelta +=
5657 read_7322_creg32_port(ppd,
5658 crp_iblinkerrrecov) -
5659 ppd->cpspec->iblnkerrsnap;
5660 }
5661 try_7322_autoneg(ppd);
5662 ret = 1; /* no other IB status change processing */
5663 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5664 ppd->link_speed_active == QIB_IB_SDR) {
5665 qib_autoneg_7322_send(ppd, 1);
5666 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5667 qib_7322_mini_pcs_reset(ppd);
5668 udelay(2);
5669 ret = 1; /* no other IB status change processing */
5670 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5671 (ppd->link_speed_active & QIB_IB_DDR)) {
5672 spin_lock_irqsave(&ppd->lflags_lock, flags);
5673 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5674 QIBL_IB_AUTONEG_FAILED);
5675 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5676 ppd->cpspec->autoneg_tries = 0;
5677 /* re-enable SDR, for next link down */
5678 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5679 wake_up(&ppd->cpspec->autoneg_wait);
5680 symadj = 1;
5681 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5682 /*
5683 * Clear autoneg failure flag, and do setup
5684 * so we'll try next time link goes down and
5685 * back to INIT (possibly connected to a
5686 * different device).
5687 */
5688 spin_lock_irqsave(&ppd->lflags_lock, flags);
5689 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5690 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5691 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5692 symadj = 1;
5693 }
5694 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5695 symadj = 1;
5696 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5697 try_7322_ipg(ppd);
5698 if (!ppd->cpspec->recovery_init)
5699 setup_7322_link_recovery(ppd, 0);
5700 ppd->cpspec->qdr_dfe_time = jiffies +
5701 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5702 }
5703 ppd->cpspec->ibmalfusesnap = 0;
5704 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5705 crp_errlink);
5706 }
5707 if (symadj) {
5708 ppd->cpspec->iblnkdownsnap =
5709 read_7322_creg32_port(ppd, crp_iblinkdown);
5710 if (ppd->cpspec->ibdeltainprog) {
5711 ppd->cpspec->ibdeltainprog = 0;
5712 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5713 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5714 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5715 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5716 }
5717 } else if (!ibup && qib_compat_ddr_negotiate &&
5718 !ppd->cpspec->ibdeltainprog &&
5719 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5720 ppd->cpspec->ibdeltainprog = 1;
5721 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5722 crp_ibsymbolerr);
5723 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5724 crp_iblinkerrrecov);
5725 }
5726
5727 if (!ret)
5728 qib_setup_7322_setextled(ppd, ibup);
5729 return ret;
5730 }
5731
5732 /*
5733 * Does read/modify/write to appropriate registers to
5734 * set output and direction bits selected by mask.
5735 * these are in their canonical postions (e.g. lsb of
5736 * dir will end up in D48 of extctrl on existing chips).
5737 * returns contents of GP Inputs.
5738 */
5739 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5740 {
5741 u64 read_val, new_out;
5742 unsigned long flags;
5743
5744 if (mask) {
5745 /* some bits being written, lock access to GPIO */
5746 dir &= mask;
5747 out &= mask;
5748 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5749 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5750 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5751 new_out = (dd->cspec->gpio_out & ~mask) | out;
5752
5753 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5754 qib_write_kreg(dd, kr_gpio_out, new_out);
5755 dd->cspec->gpio_out = new_out;
5756 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5757 }
5758 /*
5759 * It is unlikely that a read at this time would get valid
5760 * data on a pin whose direction line was set in the same
5761 * call to this function. We include the read here because
5762 * that allows us to potentially combine a change on one pin with
5763 * a read on another, and because the old code did something like
5764 * this.
5765 */
5766 read_val = qib_read_kreg64(dd, kr_extstatus);
5767 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5768 }
5769
5770 /* Enable writes to config EEPROM, if possible. Returns previous state */
5771 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5772 {
5773 int prev_wen;
5774 u32 mask;
5775
5776 mask = 1 << QIB_EEPROM_WEN_NUM;
5777 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5778 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5779
5780 return prev_wen & 1;
5781 }
5782
5783 /*
5784 * Read fundamental info we need to use the chip. These are
5785 * the registers that describe chip capabilities, and are
5786 * saved in shadow registers.
5787 */
5788 static void get_7322_chip_params(struct qib_devdata *dd)
5789 {
5790 u64 val;
5791 u32 piobufs;
5792 int mtu;
5793
5794 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5795
5796 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5797
5798 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5799 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5800 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5801 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5802 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5803
5804 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5805 dd->piobcnt2k = val & ~0U;
5806 dd->piobcnt4k = val >> 32;
5807 val = qib_read_kreg64(dd, kr_sendpiosize);
5808 dd->piosize2k = val & ~0U;
5809 dd->piosize4k = val >> 32;
5810
5811 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5812 if (mtu == -1)
5813 mtu = QIB_DEFAULT_MTU;
5814 dd->pport[0].ibmtu = (u32)mtu;
5815 dd->pport[1].ibmtu = (u32)mtu;
5816
5817 /* these may be adjusted in init_chip_wc_pat() */
5818 dd->pio2kbase = (u32 __iomem *)
5819 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5820 dd->pio4kbase = (u32 __iomem *)
5821 ((char __iomem *) dd->kregbase +
5822 (dd->piobufbase >> 32));
5823 /*
5824 * 4K buffers take 2 pages; we use roundup just to be
5825 * paranoid; we calculate it once here, rather than on
5826 * ever buf allocate
5827 */
5828 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5829
5830 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5831
5832 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5833 (sizeof(u64) * BITS_PER_BYTE / 2);
5834 }
5835
5836 /*
5837 * The chip base addresses in cspec and cpspec have to be set
5838 * after possible init_chip_wc_pat(), rather than in
5839 * get_7322_chip_params(), so split out as separate function
5840 */
5841 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5842 {
5843 u32 cregbase;
5844
5845 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5846
5847 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5848 (char __iomem *)dd->kregbase);
5849
5850 dd->egrtidbase = (u64 __iomem *)
5851 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5852
5853 /* port registers are defined as relative to base of chip */
5854 dd->pport[0].cpspec->kpregbase =
5855 (u64 __iomem *)((char __iomem *)dd->kregbase);
5856 dd->pport[1].cpspec->kpregbase =
5857 (u64 __iomem *)(dd->palign +
5858 (char __iomem *)dd->kregbase);
5859 dd->pport[0].cpspec->cpregbase =
5860 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5861 kr_counterregbase) + (char __iomem *)dd->kregbase);
5862 dd->pport[1].cpspec->cpregbase =
5863 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5864 kr_counterregbase) + (char __iomem *)dd->kregbase);
5865 }
5866
5867 /*
5868 * This is a fairly special-purpose observer, so we only support
5869 * the port-specific parts of SendCtrl
5870 */
5871
5872 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5873 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5874 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5875 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5876 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5877 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5878 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5879
5880 static int sendctrl_hook(struct qib_devdata *dd,
5881 const struct diag_observer *op, u32 offs,
5882 u64 *data, u64 mask, int only_32)
5883 {
5884 unsigned long flags;
5885 unsigned idx;
5886 unsigned pidx;
5887 struct qib_pportdata *ppd = NULL;
5888 u64 local_data, all_bits;
5889
5890 /*
5891 * The fixed correspondence between Physical ports and pports is
5892 * severed. We need to hunt for the ppd that corresponds
5893 * to the offset we got. And we have to do that without admitting
5894 * we know the stride, apparently.
5895 */
5896 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5897 u64 __iomem *psptr;
5898 u32 psoffs;
5899
5900 ppd = dd->pport + pidx;
5901 if (!ppd->cpspec->kpregbase)
5902 continue;
5903
5904 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5905 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5906 if (psoffs == offs)
5907 break;
5908 }
5909
5910 /* If pport is not being managed by driver, just avoid shadows. */
5911 if (pidx >= dd->num_pports)
5912 ppd = NULL;
5913
5914 /* In any case, "idx" is flat index in kreg space */
5915 idx = offs / sizeof(u64);
5916
5917 all_bits = ~0ULL;
5918 if (only_32)
5919 all_bits >>= 32;
5920
5921 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5922 if (!ppd || (mask & all_bits) != all_bits) {
5923 /*
5924 * At least some mask bits are zero, so we need
5925 * to read. The judgement call is whether from
5926 * reg or shadow. First-cut: read reg, and complain
5927 * if any bits which should be shadowed are different
5928 * from their shadowed value.
5929 */
5930 if (only_32)
5931 local_data = (u64)qib_read_kreg32(dd, idx);
5932 else
5933 local_data = qib_read_kreg64(dd, idx);
5934 *data = (local_data & ~mask) | (*data & mask);
5935 }
5936 if (mask) {
5937 /*
5938 * At least some mask bits are one, so we need
5939 * to write, but only shadow some bits.
5940 */
5941 u64 sval, tval; /* Shadowed, transient */
5942
5943 /*
5944 * New shadow val is bits we don't want to touch,
5945 * ORed with bits we do, that are intended for shadow.
5946 */
5947 if (ppd) {
5948 sval = ppd->p_sendctrl & ~mask;
5949 sval |= *data & SENDCTRL_SHADOWED & mask;
5950 ppd->p_sendctrl = sval;
5951 } else
5952 sval = *data & SENDCTRL_SHADOWED & mask;
5953 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5954 qib_write_kreg(dd, idx, tval);
5955 qib_write_kreg(dd, kr_scratch, 0Ull);
5956 }
5957 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5958 return only_32 ? 4 : 8;
5959 }
5960
5961 static const struct diag_observer sendctrl_0_observer = {
5962 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5963 KREG_IDX(SendCtrl_0) * sizeof(u64)
5964 };
5965
5966 static const struct diag_observer sendctrl_1_observer = {
5967 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5968 KREG_IDX(SendCtrl_1) * sizeof(u64)
5969 };
5970
5971 static ushort sdma_fetch_prio = 8;
5972 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5973 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5974
5975 /* Besides logging QSFP events, we set appropriate TxDDS values */
5976 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5977
5978 static void qsfp_7322_event(struct work_struct *work)
5979 {
5980 struct qib_qsfp_data *qd;
5981 struct qib_pportdata *ppd;
5982 unsigned long pwrup;
5983 unsigned long flags;
5984 int ret;
5985 u32 le2;
5986
5987 qd = container_of(work, struct qib_qsfp_data, work);
5988 ppd = qd->ppd;
5989 pwrup = qd->t_insert +
5990 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
5991
5992 /* Delay for 20 msecs to allow ModPrs resistor to setup */
5993 mdelay(QSFP_MODPRS_LAG_MSEC);
5994
5995 if (!qib_qsfp_mod_present(ppd)) {
5996 ppd->cpspec->qsfp_data.modpresent = 0;
5997 /* Set the physical link to disabled */
5998 qib_set_ib_7322_lstate(ppd, 0,
5999 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
6000 spin_lock_irqsave(&ppd->lflags_lock, flags);
6001 ppd->lflags &= ~QIBL_LINKV;
6002 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6003 } else {
6004 /*
6005 * Some QSFP's not only do not respond until the full power-up
6006 * time, but may behave badly if we try. So hold off responding
6007 * to insertion.
6008 */
6009 while (1) {
6010 if (time_is_before_jiffies(pwrup))
6011 break;
6012 msleep(20);
6013 }
6014
6015 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
6016
6017 /*
6018 * Need to change LE2 back to defaults if we couldn't
6019 * read the cable type (to handle cable swaps), so do this
6020 * even on failure to read cable information. We don't
6021 * get here for QME, so IS_QME check not needed here.
6022 */
6023 if (!ret && !ppd->dd->cspec->r1) {
6024 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
6025 le2 = LE2_QME;
6026 else if (qd->cache.atten[1] >= qib_long_atten &&
6027 QSFP_IS_CU(qd->cache.tech))
6028 le2 = LE2_5m;
6029 else
6030 le2 = LE2_DEFAULT;
6031 } else
6032 le2 = LE2_DEFAULT;
6033 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
6034 /*
6035 * We always change parameteters, since we can choose
6036 * values for cables without eeproms, and the cable may have
6037 * changed from a cable with full or partial eeprom content
6038 * to one with partial or no content.
6039 */
6040 init_txdds_table(ppd, 0);
6041 /* The physical link is being re-enabled only when the
6042 * previous state was DISABLED and the VALID bit is not
6043 * set. This should only happen when the cable has been
6044 * physically pulled. */
6045 if (!ppd->cpspec->qsfp_data.modpresent &&
6046 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
6047 ppd->cpspec->qsfp_data.modpresent = 1;
6048 qib_set_ib_7322_lstate(ppd, 0,
6049 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
6050 spin_lock_irqsave(&ppd->lflags_lock, flags);
6051 ppd->lflags |= QIBL_LINKV;
6052 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6053 }
6054 }
6055 }
6056
6057 /*
6058 * There is little we can do but complain to the user if QSFP
6059 * initialization fails.
6060 */
6061 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
6062 {
6063 unsigned long flags;
6064 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
6065 struct qib_devdata *dd = ppd->dd;
6066 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
6067
6068 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
6069 qd->ppd = ppd;
6070 qib_qsfp_init(qd, qsfp_7322_event);
6071 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
6072 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6073 dd->cspec->gpio_mask |= mod_prs_bit;
6074 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
6075 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
6076 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
6077 }
6078
6079 /*
6080 * called at device initialization time, and also if the txselect
6081 * module parameter is changed. This is used for cables that don't
6082 * have valid QSFP EEPROMs (not present, or attenuation is zero).
6083 * We initialize to the default, then if there is a specific
6084 * unit,port match, we use that (and set it immediately, for the
6085 * current speed, if the link is at INIT or better).
6086 * String format is "default# unit#,port#=# ... u,p=#", separators must
6087 * be a SPACE character. A newline terminates. The u,p=# tuples may
6088 * optionally have "u,p=#,#", where the final # is the H1 value
6089 * The last specific match is used (actually, all are used, but last
6090 * one is the one that winds up set); if none at all, fall back on default.
6091 */
6092 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
6093 {
6094 char *nxt, *str;
6095 u32 pidx, unit, port, deflt, h1;
6096 unsigned long val;
6097 int any = 0, seth1;
6098 int txdds_size;
6099
6100 str = txselect_list;
6101
6102 /* default number is validated in setup_txselect() */
6103 deflt = simple_strtoul(str, &nxt, 0);
6104 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6105 dd->pport[pidx].cpspec->no_eep = deflt;
6106
6107 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
6108 if (IS_QME(dd) || IS_QMH(dd))
6109 txdds_size += TXDDS_MFG_SZ;
6110
6111 while (*nxt && nxt[1]) {
6112 str = ++nxt;
6113 unit = simple_strtoul(str, &nxt, 0);
6114 if (nxt == str || !*nxt || *nxt != ',') {
6115 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6116 ;
6117 continue;
6118 }
6119 str = ++nxt;
6120 port = simple_strtoul(str, &nxt, 0);
6121 if (nxt == str || *nxt != '=') {
6122 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6123 ;
6124 continue;
6125 }
6126 str = ++nxt;
6127 val = simple_strtoul(str, &nxt, 0);
6128 if (nxt == str) {
6129 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6130 ;
6131 continue;
6132 }
6133 if (val >= txdds_size)
6134 continue;
6135 seth1 = 0;
6136 h1 = 0; /* gcc thinks it might be used uninitted */
6137 if (*nxt == ',' && nxt[1]) {
6138 str = ++nxt;
6139 h1 = (u32)simple_strtoul(str, &nxt, 0);
6140 if (nxt == str)
6141 while (*nxt && *nxt++ != ' ') /* skip */
6142 ;
6143 else
6144 seth1 = 1;
6145 }
6146 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
6147 ++pidx) {
6148 struct qib_pportdata *ppd = &dd->pport[pidx];
6149
6150 if (ppd->port != port || !ppd->link_speed_supported)
6151 continue;
6152 ppd->cpspec->no_eep = val;
6153 if (seth1)
6154 ppd->cpspec->h1_val = h1;
6155 /* now change the IBC and serdes, overriding generic */
6156 init_txdds_table(ppd, 1);
6157 /* Re-enable the physical state machine on mezz boards
6158 * now that the correct settings have been set.
6159 * QSFP boards are handles by the QSFP event handler */
6160 if (IS_QMH(dd) || IS_QME(dd))
6161 qib_set_ib_7322_lstate(ppd, 0,
6162 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
6163 any++;
6164 }
6165 if (*nxt == '\n')
6166 break; /* done */
6167 }
6168 if (change && !any) {
6169 /* no specific setting, use the default.
6170 * Change the IBC and serdes, but since it's
6171 * general, don't override specific settings.
6172 */
6173 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6174 if (dd->pport[pidx].link_speed_supported)
6175 init_txdds_table(&dd->pport[pidx], 0);
6176 }
6177 }
6178
6179 /* handle the txselect parameter changing */
6180 static int setup_txselect(const char *str, struct kernel_param *kp)
6181 {
6182 struct qib_devdata *dd;
6183 unsigned long val;
6184 char *n;
6185
6186 if (strlen(str) >= MAX_ATTEN_LEN) {
6187 pr_info("txselect_values string too long\n");
6188 return -ENOSPC;
6189 }
6190 val = simple_strtoul(str, &n, 0);
6191 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
6192 TXDDS_MFG_SZ)) {
6193 pr_info("txselect_values must start with a number < %d\n",
6194 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
6195 return -EINVAL;
6196 }
6197 strcpy(txselect_list, str);
6198
6199 list_for_each_entry(dd, &qib_dev_list, list)
6200 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
6201 set_no_qsfp_atten(dd, 1);
6202 return 0;
6203 }
6204
6205 /*
6206 * Write the final few registers that depend on some of the
6207 * init setup. Done late in init, just before bringing up
6208 * the serdes.
6209 */
6210 static int qib_late_7322_initreg(struct qib_devdata *dd)
6211 {
6212 int ret = 0, n;
6213 u64 val;
6214
6215 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
6216 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
6217 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
6218 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
6219 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
6220 if (val != dd->pioavailregs_phys) {
6221 qib_dev_err(dd,
6222 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
6223 (unsigned long) dd->pioavailregs_phys,
6224 (unsigned long long) val);
6225 ret = -EINVAL;
6226 }
6227
6228 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
6229 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
6230 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
6231 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
6232
6233 qib_register_observer(dd, &sendctrl_0_observer);
6234 qib_register_observer(dd, &sendctrl_1_observer);
6235
6236 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
6237 qib_write_kreg(dd, kr_control, dd->control);
6238 /*
6239 * Set SendDmaFetchPriority and init Tx params, including
6240 * QSFP handler on boards that have QSFP.
6241 * First set our default attenuation entry for cables that
6242 * don't have valid attenuation.
6243 */
6244 set_no_qsfp_atten(dd, 0);
6245 for (n = 0; n < dd->num_pports; ++n) {
6246 struct qib_pportdata *ppd = dd->pport + n;
6247
6248 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
6249 sdma_fetch_prio & 0xf);
6250 /* Initialize qsfp if present on board. */
6251 if (dd->flags & QIB_HAS_QSFP)
6252 qib_init_7322_qsfp(ppd);
6253 }
6254 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
6255 qib_write_kreg(dd, kr_control, dd->control);
6256
6257 return ret;
6258 }
6259
6260 /* per IB port errors. */
6261 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
6262 MASK_ACROSS(8, 15))
6263 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
6264 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
6265 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
6266 MASK_ACROSS(0, 11))
6267
6268 /*
6269 * Write the initialization per-port registers that need to be done at
6270 * driver load and after reset completes (i.e., that aren't done as part
6271 * of other init procedures called from qib_init.c).
6272 * Some of these should be redundant on reset, but play safe.
6273 */
6274 static void write_7322_init_portregs(struct qib_pportdata *ppd)
6275 {
6276 u64 val;
6277 int i;
6278
6279 if (!ppd->link_speed_supported) {
6280 /* no buffer credits for this port */
6281 for (i = 1; i < 8; i++)
6282 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
6283 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
6284 qib_write_kreg(ppd->dd, kr_scratch, 0);
6285 return;
6286 }
6287
6288 /*
6289 * Set the number of supported virtual lanes in IBC,
6290 * for flow control packet handling on unsupported VLs
6291 */
6292 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
6293 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
6294 val |= (u64)(ppd->vls_supported - 1) <<
6295 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
6296 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
6297
6298 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
6299
6300 /* enable tx header checking */
6301 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
6302 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
6303 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
6304
6305 qib_write_kreg_port(ppd, krp_ncmodectrl,
6306 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
6307
6308 /*
6309 * Unconditionally clear the bufmask bits. If SDMA is
6310 * enabled, we'll set them appropriately later.
6311 */
6312 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
6313 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
6314 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
6315 if (ppd->dd->cspec->r1)
6316 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
6317 }
6318
6319 /*
6320 * Write the initialization per-device registers that need to be done at
6321 * driver load and after reset completes (i.e., that aren't done as part
6322 * of other init procedures called from qib_init.c). Also write per-port
6323 * registers that are affected by overall device config, such as QP mapping
6324 * Some of these should be redundant on reset, but play safe.
6325 */
6326 static void write_7322_initregs(struct qib_devdata *dd)
6327 {
6328 struct qib_pportdata *ppd;
6329 int i, pidx;
6330 u64 val;
6331
6332 /* Set Multicast QPs received by port 2 to map to context one. */
6333 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
6334
6335 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
6336 unsigned n, regno;
6337 unsigned long flags;
6338
6339 if (dd->n_krcv_queues < 2 ||
6340 !dd->pport[pidx].link_speed_supported)
6341 continue;
6342
6343 ppd = &dd->pport[pidx];
6344
6345 /* be paranoid against later code motion, etc. */
6346 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6347 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
6348 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6349
6350 /* Initialize QP to context mapping */
6351 regno = krp_rcvqpmaptable;
6352 val = 0;
6353 if (dd->num_pports > 1)
6354 n = dd->first_user_ctxt / dd->num_pports;
6355 else
6356 n = dd->first_user_ctxt - 1;
6357 for (i = 0; i < 32; ) {
6358 unsigned ctxt;
6359
6360 if (dd->num_pports > 1)
6361 ctxt = (i % n) * dd->num_pports + pidx;
6362 else if (i % n)
6363 ctxt = (i % n) + 1;
6364 else
6365 ctxt = ppd->hw_pidx;
6366 val |= ctxt << (5 * (i % 6));
6367 i++;
6368 if (i % 6 == 0) {
6369 qib_write_kreg_port(ppd, regno, val);
6370 val = 0;
6371 regno++;
6372 }
6373 }
6374 qib_write_kreg_port(ppd, regno, val);
6375 }
6376
6377 /*
6378 * Setup up interrupt mitigation for kernel contexts, but
6379 * not user contexts (user contexts use interrupts when
6380 * stalled waiting for any packet, so want those interrupts
6381 * right away).
6382 */
6383 for (i = 0; i < dd->first_user_ctxt; i++) {
6384 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6385 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6386 }
6387
6388 /*
6389 * Initialize as (disabled) rcvflow tables. Application code
6390 * will setup each flow as it uses the flow.
6391 * Doesn't clear any of the error bits that might be set.
6392 */
6393 val = TIDFLOW_ERRBITS; /* these are W1C */
6394 for (i = 0; i < dd->cfgctxts; i++) {
6395 int flow;
6396
6397 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6398 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6399 }
6400
6401 /*
6402 * dual cards init to dual port recovery, single port cards to
6403 * the one port. Dual port cards may later adjust to 1 port,
6404 * and then back to dual port if both ports are connected
6405 * */
6406 if (dd->num_pports)
6407 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6408 }
6409
6410 static int qib_init_7322_variables(struct qib_devdata *dd)
6411 {
6412 struct qib_pportdata *ppd;
6413 unsigned features, pidx, sbufcnt;
6414 int ret, mtu;
6415 u32 sbufs, updthresh;
6416 resource_size_t vl15off;
6417
6418 /* pport structs are contiguous, allocated after devdata */
6419 ppd = (struct qib_pportdata *)(dd + 1);
6420 dd->pport = ppd;
6421 ppd[0].dd = dd;
6422 ppd[1].dd = dd;
6423
6424 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6425
6426 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6427 ppd[1].cpspec = &ppd[0].cpspec[1];
6428 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6429 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6430
6431 spin_lock_init(&dd->cspec->rcvmod_lock);
6432 spin_lock_init(&dd->cspec->gpio_lock);
6433
6434 /* we haven't yet set QIB_PRESENT, so use read directly */
6435 dd->revision = readq(&dd->kregbase[kr_revision]);
6436
6437 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6438 qib_dev_err(dd,
6439 "Revision register read failure, giving up initialization\n");
6440 ret = -ENODEV;
6441 goto bail;
6442 }
6443 dd->flags |= QIB_PRESENT; /* now register routines work */
6444
6445 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6446 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6447 dd->cspec->r1 = dd->minrev == 1;
6448
6449 get_7322_chip_params(dd);
6450 features = qib_7322_boardname(dd);
6451
6452 /* now that piobcnt2k and 4k set, we can allocate these */
6453 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6454 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6455 sbufcnt /= BITS_PER_LONG;
6456 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6457 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6458 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6459 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6460 dd->cspec->sendibchk = kmalloc(sbufcnt *
6461 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6462 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6463 !dd->cspec->sendibchk) {
6464 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6465 ret = -ENOMEM;
6466 goto bail;
6467 }
6468
6469 ppd = dd->pport;
6470
6471 /*
6472 * GPIO bits for TWSI data and clock,
6473 * used for serial EEPROM.
6474 */
6475 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6476 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6477 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6478
6479 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6480 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6481 QIB_HAS_THRESH_UPDATE |
6482 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6483 dd->flags |= qib_special_trigger ?
6484 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6485
6486 /*
6487 * Setup initial values. These may change when PAT is enabled, but
6488 * we need these to do initial chip register accesses.
6489 */
6490 qib_7322_set_baseaddrs(dd);
6491
6492 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6493 if (mtu == -1)
6494 mtu = QIB_DEFAULT_MTU;
6495
6496 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6497 /* all hwerrors become interrupts, unless special purposed */
6498 dd->cspec->hwerrmask = ~0ULL;
6499 /* link_recovery setup causes these errors, so ignore them,
6500 * other than clearing them when they occur */
6501 dd->cspec->hwerrmask &=
6502 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6503 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6504 HWE_MASK(LATriggered));
6505
6506 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6507 struct qib_chippport_specific *cp = ppd->cpspec;
6508
6509 ppd->link_speed_supported = features & PORT_SPD_CAP;
6510 features >>= PORT_SPD_CAP_SHIFT;
6511 if (!ppd->link_speed_supported) {
6512 /* single port mode (7340, or configured) */
6513 dd->skip_kctxt_mask |= 1 << pidx;
6514 if (pidx == 0) {
6515 /* Make sure port is disabled. */
6516 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6517 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6518 ppd[0] = ppd[1];
6519 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6520 IBSerdesPClkNotDetectMask_0)
6521 | SYM_MASK(HwErrMask,
6522 SDmaMemReadErrMask_0));
6523 dd->cspec->int_enable_mask &= ~(
6524 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6525 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6526 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6527 SYM_MASK(IntMask, SDmaIntMask_0) |
6528 SYM_MASK(IntMask, ErrIntMask_0) |
6529 SYM_MASK(IntMask, SendDoneIntMask_0));
6530 } else {
6531 /* Make sure port is disabled. */
6532 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6533 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6534 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6535 IBSerdesPClkNotDetectMask_1)
6536 | SYM_MASK(HwErrMask,
6537 SDmaMemReadErrMask_1));
6538 dd->cspec->int_enable_mask &= ~(
6539 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6540 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6541 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6542 SYM_MASK(IntMask, SDmaIntMask_1) |
6543 SYM_MASK(IntMask, ErrIntMask_1) |
6544 SYM_MASK(IntMask, SendDoneIntMask_1));
6545 }
6546 continue;
6547 }
6548
6549 dd->num_pports++;
6550 ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6551 if (ret) {
6552 dd->num_pports--;
6553 goto bail;
6554 }
6555
6556 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6557 ppd->link_width_enabled = IB_WIDTH_4X;
6558 ppd->link_speed_enabled = ppd->link_speed_supported;
6559 /*
6560 * Set the initial values to reasonable default, will be set
6561 * for real when link is up.
6562 */
6563 ppd->link_width_active = IB_WIDTH_4X;
6564 ppd->link_speed_active = QIB_IB_SDR;
6565 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6566 switch (qib_num_cfg_vls) {
6567 case 1:
6568 ppd->vls_supported = IB_VL_VL0;
6569 break;
6570 case 2:
6571 ppd->vls_supported = IB_VL_VL0_1;
6572 break;
6573 default:
6574 qib_devinfo(dd->pcidev,
6575 "Invalid num_vls %u, using 4 VLs\n",
6576 qib_num_cfg_vls);
6577 qib_num_cfg_vls = 4;
6578 /* fall through */
6579 case 4:
6580 ppd->vls_supported = IB_VL_VL0_3;
6581 break;
6582 case 8:
6583 if (mtu <= 2048)
6584 ppd->vls_supported = IB_VL_VL0_7;
6585 else {
6586 qib_devinfo(dd->pcidev,
6587 "Invalid num_vls %u for MTU %d , using 4 VLs\n",
6588 qib_num_cfg_vls, mtu);
6589 ppd->vls_supported = IB_VL_VL0_3;
6590 qib_num_cfg_vls = 4;
6591 }
6592 break;
6593 }
6594 ppd->vls_operational = ppd->vls_supported;
6595
6596 init_waitqueue_head(&cp->autoneg_wait);
6597 INIT_DELAYED_WORK(&cp->autoneg_work,
6598 autoneg_7322_work);
6599 if (ppd->dd->cspec->r1)
6600 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6601
6602 /*
6603 * For Mez and similar cards, no qsfp info, so do
6604 * the "cable info" setup here. Can be overridden
6605 * in adapter-specific routines.
6606 */
6607 if (!(dd->flags & QIB_HAS_QSFP)) {
6608 if (!IS_QMH(dd) && !IS_QME(dd))
6609 qib_devinfo(dd->pcidev,
6610 "IB%u:%u: Unknown mezzanine card type\n",
6611 dd->unit, ppd->port);
6612 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6613 /*
6614 * Choose center value as default tx serdes setting
6615 * until changed through module parameter.
6616 */
6617 ppd->cpspec->no_eep = IS_QMH(dd) ?
6618 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6619 } else
6620 cp->h1_val = H1_FORCE_VAL;
6621
6622 /* Avoid writes to chip for mini_init */
6623 if (!qib_mini_init)
6624 write_7322_init_portregs(ppd);
6625
6626 init_timer(&cp->chase_timer);
6627 cp->chase_timer.function = reenable_chase;
6628 cp->chase_timer.data = (unsigned long)ppd;
6629
6630 ppd++;
6631 }
6632
6633 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6634 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6635 dd->rcvhdrsize = qib_rcvhdrsize ?
6636 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6637 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6638
6639 /* we always allocate at least 2048 bytes for eager buffers */
6640 dd->rcvegrbufsize = max(mtu, 2048);
6641 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6642 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
6643
6644 qib_7322_tidtemplate(dd);
6645
6646 /*
6647 * We can request a receive interrupt for 1 or
6648 * more packets from current offset.
6649 */
6650 dd->rhdrhead_intr_off =
6651 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6652
6653 /* setup the stats timer; the add_timer is done at end of init */
6654 init_timer(&dd->stats_timer);
6655 dd->stats_timer.function = qib_get_7322_faststats;
6656 dd->stats_timer.data = (unsigned long) dd;
6657
6658 dd->ureg_align = 0x10000; /* 64KB alignment */
6659
6660 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6661
6662 qib_7322_config_ctxts(dd);
6663 qib_set_ctxtcnt(dd);
6664
6665 /*
6666 * We do not set WC on the VL15 buffers to avoid
6667 * a rare problem with unaligned writes from
6668 * interrupt-flushed store buffers, so we need
6669 * to map those separately here. We can't solve
6670 * this for the rarely used mtrr case.
6671 */
6672 ret = init_chip_wc_pat(dd, 0);
6673 if (ret)
6674 goto bail;
6675
6676 /* vl15 buffers start just after the 4k buffers */
6677 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6678 dd->piobcnt4k * dd->align4k;
6679 dd->piovl15base = ioremap_nocache(vl15off,
6680 NUM_VL15_BUFS * dd->align4k);
6681 if (!dd->piovl15base) {
6682 ret = -ENOMEM;
6683 goto bail;
6684 }
6685
6686 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6687
6688 ret = 0;
6689 if (qib_mini_init)
6690 goto bail;
6691 if (!dd->num_pports) {
6692 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6693 goto bail; /* no error, so can still figure out why err */
6694 }
6695
6696 write_7322_initregs(dd);
6697 ret = qib_create_ctxts(dd);
6698 init_7322_cntrnames(dd);
6699
6700 updthresh = 8U; /* update threshold */
6701
6702 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6703 * reserve the update threshold amount for other kernel use, such
6704 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6705 * unless we aren't enabling SDMA, in which case we want to use
6706 * all the 4k bufs for the kernel.
6707 * if this was less than the update threshold, we could wait
6708 * a long time for an update. Coded this way because we
6709 * sometimes change the update threshold for various reasons,
6710 * and we want this to remain robust.
6711 */
6712 if (dd->flags & QIB_HAS_SEND_DMA) {
6713 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6714 sbufs = updthresh > 3 ? updthresh : 3;
6715 } else {
6716 dd->cspec->sdmabufcnt = 0;
6717 sbufs = dd->piobcnt4k;
6718 }
6719 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6720 dd->cspec->sdmabufcnt;
6721 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6722 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6723 dd->last_pio = dd->cspec->lastbuf_for_pio;
6724 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6725 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6726
6727 /*
6728 * If we have 16 user contexts, we will have 7 sbufs
6729 * per context, so reduce the update threshold to match. We
6730 * want to update before we actually run out, at low pbufs/ctxt
6731 * so give ourselves some margin.
6732 */
6733 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6734 updthresh = dd->pbufsctxt - 2;
6735 dd->cspec->updthresh_dflt = updthresh;
6736 dd->cspec->updthresh = updthresh;
6737
6738 /* before full enable, no interrupts, no locking needed */
6739 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6740 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6741 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6742
6743 dd->psxmitwait_supported = 1;
6744 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6745 bail:
6746 if (!dd->ctxtcnt)
6747 dd->ctxtcnt = 1; /* for other initialization code */
6748
6749 return ret;
6750 }
6751
6752 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6753 u32 *pbufnum)
6754 {
6755 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6756 struct qib_devdata *dd = ppd->dd;
6757
6758 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6759 if (pbc & PBC_7322_VL15_SEND) {
6760 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6761 last = first;
6762 } else {
6763 if ((plen + 1) > dd->piosize2kmax_dwords)
6764 first = dd->piobcnt2k;
6765 else
6766 first = 0;
6767 last = dd->cspec->lastbuf_for_pio;
6768 }
6769 return qib_getsendbuf_range(dd, pbufnum, first, last);
6770 }
6771
6772 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6773 u32 start)
6774 {
6775 qib_write_kreg_port(ppd, krp_psinterval, intv);
6776 qib_write_kreg_port(ppd, krp_psstart, start);
6777 }
6778
6779 /*
6780 * Must be called with sdma_lock held, or before init finished.
6781 */
6782 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6783 {
6784 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6785 }
6786
6787 /*
6788 * sdma_lock should be acquired before calling this routine
6789 */
6790 static void dump_sdma_7322_state(struct qib_pportdata *ppd)
6791 {
6792 u64 reg, reg1, reg2;
6793
6794 reg = qib_read_kreg_port(ppd, krp_senddmastatus);
6795 qib_dev_porterr(ppd->dd, ppd->port,
6796 "SDMA senddmastatus: 0x%016llx\n", reg);
6797
6798 reg = qib_read_kreg_port(ppd, krp_sendctrl);
6799 qib_dev_porterr(ppd->dd, ppd->port,
6800 "SDMA sendctrl: 0x%016llx\n", reg);
6801
6802 reg = qib_read_kreg_port(ppd, krp_senddmabase);
6803 qib_dev_porterr(ppd->dd, ppd->port,
6804 "SDMA senddmabase: 0x%016llx\n", reg);
6805
6806 reg = qib_read_kreg_port(ppd, krp_senddmabufmask0);
6807 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1);
6808 reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2);
6809 qib_dev_porterr(ppd->dd, ppd->port,
6810 "SDMA senddmabufmask 0:%llx 1:%llx 2:%llx\n",
6811 reg, reg1, reg2);
6812
6813 /* get bufuse bits, clear them, and print them again if non-zero */
6814 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6815 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg);
6816 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6817 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1);
6818 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6819 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2);
6820 /* 0 and 1 should always be zero, so print as short form */
6821 qib_dev_porterr(ppd->dd, ppd->port,
6822 "SDMA current senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6823 reg, reg1, reg2);
6824 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6825 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6826 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6827 /* 0 and 1 should always be zero, so print as short form */
6828 qib_dev_porterr(ppd->dd, ppd->port,
6829 "SDMA cleared senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6830 reg, reg1, reg2);
6831
6832 reg = qib_read_kreg_port(ppd, krp_senddmatail);
6833 qib_dev_porterr(ppd->dd, ppd->port,
6834 "SDMA senddmatail: 0x%016llx\n", reg);
6835
6836 reg = qib_read_kreg_port(ppd, krp_senddmahead);
6837 qib_dev_porterr(ppd->dd, ppd->port,
6838 "SDMA senddmahead: 0x%016llx\n", reg);
6839
6840 reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr);
6841 qib_dev_porterr(ppd->dd, ppd->port,
6842 "SDMA senddmaheadaddr: 0x%016llx\n", reg);
6843
6844 reg = qib_read_kreg_port(ppd, krp_senddmalengen);
6845 qib_dev_porterr(ppd->dd, ppd->port,
6846 "SDMA senddmalengen: 0x%016llx\n", reg);
6847
6848 reg = qib_read_kreg_port(ppd, krp_senddmadesccnt);
6849 qib_dev_porterr(ppd->dd, ppd->port,
6850 "SDMA senddmadesccnt: 0x%016llx\n", reg);
6851
6852 reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt);
6853 qib_dev_porterr(ppd->dd, ppd->port,
6854 "SDMA senddmaidlecnt: 0x%016llx\n", reg);
6855
6856 reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld);
6857 qib_dev_porterr(ppd->dd, ppd->port,
6858 "SDMA senddmapriorityhld: 0x%016llx\n", reg);
6859
6860 reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt);
6861 qib_dev_porterr(ppd->dd, ppd->port,
6862 "SDMA senddmareloadcnt: 0x%016llx\n", reg);
6863
6864 dump_sdma_state(ppd);
6865 }
6866
6867 static struct sdma_set_state_action sdma_7322_action_table[] = {
6868 [qib_sdma_state_s00_hw_down] = {
6869 .go_s99_running_tofalse = 1,
6870 .op_enable = 0,
6871 .op_intenable = 0,
6872 .op_halt = 0,
6873 .op_drain = 0,
6874 },
6875 [qib_sdma_state_s10_hw_start_up_wait] = {
6876 .op_enable = 0,
6877 .op_intenable = 1,
6878 .op_halt = 1,
6879 .op_drain = 0,
6880 },
6881 [qib_sdma_state_s20_idle] = {
6882 .op_enable = 1,
6883 .op_intenable = 1,
6884 .op_halt = 1,
6885 .op_drain = 0,
6886 },
6887 [qib_sdma_state_s30_sw_clean_up_wait] = {
6888 .op_enable = 0,
6889 .op_intenable = 1,
6890 .op_halt = 1,
6891 .op_drain = 0,
6892 },
6893 [qib_sdma_state_s40_hw_clean_up_wait] = {
6894 .op_enable = 1,
6895 .op_intenable = 1,
6896 .op_halt = 1,
6897 .op_drain = 0,
6898 },
6899 [qib_sdma_state_s50_hw_halt_wait] = {
6900 .op_enable = 1,
6901 .op_intenable = 1,
6902 .op_halt = 1,
6903 .op_drain = 1,
6904 },
6905 [qib_sdma_state_s99_running] = {
6906 .op_enable = 1,
6907 .op_intenable = 1,
6908 .op_halt = 0,
6909 .op_drain = 0,
6910 .go_s99_running_totrue = 1,
6911 },
6912 };
6913
6914 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6915 {
6916 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6917 }
6918
6919 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6920 {
6921 struct qib_devdata *dd = ppd->dd;
6922 unsigned lastbuf, erstbuf;
6923 u64 senddmabufmask[3] = { 0 };
6924 int n, ret = 0;
6925
6926 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6927 qib_sdma_7322_setlengen(ppd);
6928 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6929 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6930 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6931 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6932
6933 if (dd->num_pports)
6934 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6935 else
6936 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6937 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6938 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6939 dd->cspec->sdmabufcnt);
6940 lastbuf = erstbuf + n;
6941
6942 ppd->sdma_state.first_sendbuf = erstbuf;
6943 ppd->sdma_state.last_sendbuf = lastbuf;
6944 for (; erstbuf < lastbuf; ++erstbuf) {
6945 unsigned word = erstbuf / BITS_PER_LONG;
6946 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6947
6948 BUG_ON(word >= 3);
6949 senddmabufmask[word] |= 1ULL << bit;
6950 }
6951 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6952 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6953 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6954 return ret;
6955 }
6956
6957 /* sdma_lock must be held */
6958 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6959 {
6960 struct qib_devdata *dd = ppd->dd;
6961 int sane;
6962 int use_dmahead;
6963 u16 swhead;
6964 u16 swtail;
6965 u16 cnt;
6966 u16 hwhead;
6967
6968 use_dmahead = __qib_sdma_running(ppd) &&
6969 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6970 retry:
6971 hwhead = use_dmahead ?
6972 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6973 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6974
6975 swhead = ppd->sdma_descq_head;
6976 swtail = ppd->sdma_descq_tail;
6977 cnt = ppd->sdma_descq_cnt;
6978
6979 if (swhead < swtail)
6980 /* not wrapped */
6981 sane = (hwhead >= swhead) & (hwhead <= swtail);
6982 else if (swhead > swtail)
6983 /* wrapped around */
6984 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6985 (hwhead <= swtail);
6986 else
6987 /* empty */
6988 sane = (hwhead == swhead);
6989
6990 if (unlikely(!sane)) {
6991 if (use_dmahead) {
6992 /* try one more time, directly from the register */
6993 use_dmahead = 0;
6994 goto retry;
6995 }
6996 /* proceed as if no progress */
6997 hwhead = swhead;
6998 }
6999
7000 return hwhead;
7001 }
7002
7003 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
7004 {
7005 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
7006
7007 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
7008 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
7009 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
7010 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
7011 }
7012
7013 /*
7014 * Compute the amount of delay before sending the next packet if the
7015 * port's send rate differs from the static rate set for the QP.
7016 * The delay affects the next packet and the amount of the delay is
7017 * based on the length of the this packet.
7018 */
7019 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
7020 u8 srate, u8 vl)
7021 {
7022 u8 snd_mult = ppd->delay_mult;
7023 u8 rcv_mult = ib_rate_to_delay[srate];
7024 u32 ret;
7025
7026 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
7027
7028 /* Indicate VL15, else set the VL in the control word */
7029 if (vl == 15)
7030 ret |= PBC_7322_VL15_SEND_CTRL;
7031 else
7032 ret |= vl << PBC_VL_NUM_LSB;
7033 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
7034
7035 return ret;
7036 }
7037
7038 /*
7039 * Enable the per-port VL15 send buffers for use.
7040 * They follow the rest of the buffers, without a config parameter.
7041 * This was in initregs, but that is done before the shadow
7042 * is set up, and this has to be done after the shadow is
7043 * set up.
7044 */
7045 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
7046 {
7047 unsigned vl15bufs;
7048
7049 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
7050 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
7051 TXCHK_CHG_TYPE_KERN, NULL);
7052 }
7053
7054 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
7055 {
7056 if (rcd->ctxt < NUM_IB_PORTS) {
7057 if (rcd->dd->num_pports > 1) {
7058 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
7059 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
7060 } else {
7061 rcd->rcvegrcnt = KCTXT0_EGRCNT;
7062 rcd->rcvegr_tid_base = 0;
7063 }
7064 } else {
7065 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
7066 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
7067 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
7068 }
7069 }
7070
7071 #define QTXSLEEPS 5000
7072 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
7073 u32 len, u32 which, struct qib_ctxtdata *rcd)
7074 {
7075 int i;
7076 const int last = start + len - 1;
7077 const int lastr = last / BITS_PER_LONG;
7078 u32 sleeps = 0;
7079 int wait = rcd != NULL;
7080 unsigned long flags;
7081
7082 while (wait) {
7083 unsigned long shadow;
7084 int cstart, previ = -1;
7085
7086 /*
7087 * when flipping from kernel to user, we can't change
7088 * the checking type if the buffer is allocated to the
7089 * driver. It's OK the other direction, because it's
7090 * from close, and we have just disarm'ed all the
7091 * buffers. All the kernel to kernel changes are also
7092 * OK.
7093 */
7094 for (cstart = start; cstart <= last; cstart++) {
7095 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7096 / BITS_PER_LONG;
7097 if (i != previ) {
7098 shadow = (unsigned long)
7099 le64_to_cpu(dd->pioavailregs_dma[i]);
7100 previ = i;
7101 }
7102 if (test_bit(((2 * cstart) +
7103 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7104 % BITS_PER_LONG, &shadow))
7105 break;
7106 }
7107
7108 if (cstart > last)
7109 break;
7110
7111 if (sleeps == QTXSLEEPS)
7112 break;
7113 /* make sure we see an updated copy next time around */
7114 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7115 sleeps++;
7116 msleep(20);
7117 }
7118
7119 switch (which) {
7120 case TXCHK_CHG_TYPE_DIS1:
7121 /*
7122 * disable checking on a range; used by diags; just
7123 * one buffer, but still written generically
7124 */
7125 for (i = start; i <= last; i++)
7126 clear_bit(i, dd->cspec->sendchkenable);
7127 break;
7128
7129 case TXCHK_CHG_TYPE_ENAB1:
7130 /*
7131 * (re)enable checking on a range; used by diags; just
7132 * one buffer, but still written generically; read
7133 * scratch to be sure buffer actually triggered, not
7134 * just flushed from processor.
7135 */
7136 qib_read_kreg32(dd, kr_scratch);
7137 for (i = start; i <= last; i++)
7138 set_bit(i, dd->cspec->sendchkenable);
7139 break;
7140
7141 case TXCHK_CHG_TYPE_KERN:
7142 /* usable by kernel */
7143 for (i = start; i <= last; i++) {
7144 set_bit(i, dd->cspec->sendibchk);
7145 clear_bit(i, dd->cspec->sendgrhchk);
7146 }
7147 spin_lock_irqsave(&dd->uctxt_lock, flags);
7148 /* see if we need to raise avail update threshold */
7149 for (i = dd->first_user_ctxt;
7150 dd->cspec->updthresh != dd->cspec->updthresh_dflt
7151 && i < dd->cfgctxts; i++)
7152 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
7153 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
7154 < dd->cspec->updthresh_dflt)
7155 break;
7156 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
7157 if (i == dd->cfgctxts) {
7158 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7159 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
7160 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7161 dd->sendctrl |= (dd->cspec->updthresh &
7162 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
7163 SYM_LSB(SendCtrl, AvailUpdThld);
7164 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7165 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7166 }
7167 break;
7168
7169 case TXCHK_CHG_TYPE_USER:
7170 /* for user process */
7171 for (i = start; i <= last; i++) {
7172 clear_bit(i, dd->cspec->sendibchk);
7173 set_bit(i, dd->cspec->sendgrhchk);
7174 }
7175 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7176 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
7177 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
7178 dd->cspec->updthresh = (rcd->piocnt /
7179 rcd->subctxt_cnt) - 1;
7180 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7181 dd->sendctrl |= (dd->cspec->updthresh &
7182 SYM_RMASK(SendCtrl, AvailUpdThld))
7183 << SYM_LSB(SendCtrl, AvailUpdThld);
7184 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7185 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7186 } else
7187 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7188 break;
7189
7190 default:
7191 break;
7192 }
7193
7194 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
7195 qib_write_kreg(dd, kr_sendcheckmask + i,
7196 dd->cspec->sendchkenable[i]);
7197
7198 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
7199 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
7200 dd->cspec->sendgrhchk[i]);
7201 qib_write_kreg(dd, kr_sendibpktmask + i,
7202 dd->cspec->sendibchk[i]);
7203 }
7204
7205 /*
7206 * Be sure whatever we did was seen by the chip and acted upon,
7207 * before we return. Mostly important for which >= 2.
7208 */
7209 qib_read_kreg32(dd, kr_scratch);
7210 }
7211
7212
7213 /* useful for trigger analyzers, etc. */
7214 static void writescratch(struct qib_devdata *dd, u32 val)
7215 {
7216 qib_write_kreg(dd, kr_scratch, val);
7217 }
7218
7219 /* Dummy for now, use chip regs soon */
7220 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
7221 {
7222 return -ENXIO;
7223 }
7224
7225 /**
7226 * qib_init_iba7322_funcs - set up the chip-specific function pointers
7227 * @dev: the pci_dev for qlogic_ib device
7228 * @ent: pci_device_id struct for this dev
7229 *
7230 * Also allocates, inits, and returns the devdata struct for this
7231 * device instance
7232 *
7233 * This is global, and is called directly at init to set up the
7234 * chip-specific function pointers for later use.
7235 */
7236 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
7237 const struct pci_device_id *ent)
7238 {
7239 struct qib_devdata *dd;
7240 int ret, i;
7241 u32 tabsize, actual_cnt = 0;
7242
7243 dd = qib_alloc_devdata(pdev,
7244 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
7245 sizeof(struct qib_chip_specific) +
7246 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
7247 if (IS_ERR(dd))
7248 goto bail;
7249
7250 dd->f_bringup_serdes = qib_7322_bringup_serdes;
7251 dd->f_cleanup = qib_setup_7322_cleanup;
7252 dd->f_clear_tids = qib_7322_clear_tids;
7253 dd->f_free_irq = qib_7322_free_irq;
7254 dd->f_get_base_info = qib_7322_get_base_info;
7255 dd->f_get_msgheader = qib_7322_get_msgheader;
7256 dd->f_getsendbuf = qib_7322_getsendbuf;
7257 dd->f_gpio_mod = gpio_7322_mod;
7258 dd->f_eeprom_wen = qib_7322_eeprom_wen;
7259 dd->f_hdrqempty = qib_7322_hdrqempty;
7260 dd->f_ib_updown = qib_7322_ib_updown;
7261 dd->f_init_ctxt = qib_7322_init_ctxt;
7262 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
7263 dd->f_intr_fallback = qib_7322_intr_fallback;
7264 dd->f_late_initreg = qib_late_7322_initreg;
7265 dd->f_setpbc_control = qib_7322_setpbc_control;
7266 dd->f_portcntr = qib_portcntr_7322;
7267 dd->f_put_tid = qib_7322_put_tid;
7268 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
7269 dd->f_rcvctrl = rcvctrl_7322_mod;
7270 dd->f_read_cntrs = qib_read_7322cntrs;
7271 dd->f_read_portcntrs = qib_read_7322portcntrs;
7272 dd->f_reset = qib_do_7322_reset;
7273 dd->f_init_sdma_regs = init_sdma_7322_regs;
7274 dd->f_sdma_busy = qib_sdma_7322_busy;
7275 dd->f_sdma_gethead = qib_sdma_7322_gethead;
7276 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
7277 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
7278 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
7279 dd->f_sendctrl = sendctrl_7322_mod;
7280 dd->f_set_armlaunch = qib_set_7322_armlaunch;
7281 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
7282 dd->f_iblink_state = qib_7322_iblink_state;
7283 dd->f_ibphys_portstate = qib_7322_phys_portstate;
7284 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
7285 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
7286 dd->f_set_ib_loopback = qib_7322_set_loopback;
7287 dd->f_get_ib_table = qib_7322_get_ib_table;
7288 dd->f_set_ib_table = qib_7322_set_ib_table;
7289 dd->f_set_intr_state = qib_7322_set_intr_state;
7290 dd->f_setextled = qib_setup_7322_setextled;
7291 dd->f_txchk_change = qib_7322_txchk_change;
7292 dd->f_update_usrhead = qib_update_7322_usrhead;
7293 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
7294 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
7295 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
7296 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
7297 dd->f_sdma_init_early = qib_7322_sdma_init_early;
7298 dd->f_writescratch = writescratch;
7299 dd->f_tempsense_rd = qib_7322_tempsense_rd;
7300 #ifdef CONFIG_INFINIBAND_QIB_DCA
7301 dd->f_notify_dca = qib_7322_notify_dca;
7302 #endif
7303 /*
7304 * Do remaining PCIe setup and save PCIe values in dd.
7305 * Any error printing is already done by the init code.
7306 * On return, we have the chip mapped, but chip registers
7307 * are not set up until start of qib_init_7322_variables.
7308 */
7309 ret = qib_pcie_ddinit(dd, pdev, ent);
7310 if (ret < 0)
7311 goto bail_free;
7312
7313 /* initialize chip-specific variables */
7314 ret = qib_init_7322_variables(dd);
7315 if (ret)
7316 goto bail_cleanup;
7317
7318 if (qib_mini_init || !dd->num_pports)
7319 goto bail;
7320
7321 /*
7322 * Determine number of vectors we want; depends on port count
7323 * and number of configured kernel receive queues actually used.
7324 * Should also depend on whether sdma is enabled or not, but
7325 * that's such a rare testing case it's not worth worrying about.
7326 */
7327 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
7328 for (i = 0; i < tabsize; i++)
7329 if ((i < ARRAY_SIZE(irq_table) &&
7330 irq_table[i].port <= dd->num_pports) ||
7331 (i >= ARRAY_SIZE(irq_table) &&
7332 dd->rcd[i - ARRAY_SIZE(irq_table)]))
7333 actual_cnt++;
7334 /* reduce by ctxt's < 2 */
7335 if (qib_krcvq01_no_msi)
7336 actual_cnt -= dd->num_pports;
7337
7338 tabsize = actual_cnt;
7339 dd->cspec->msix_entries = kzalloc(tabsize *
7340 sizeof(struct qib_msix_entry), GFP_KERNEL);
7341 if (!dd->cspec->msix_entries) {
7342 qib_dev_err(dd, "No memory for MSIx table\n");
7343 tabsize = 0;
7344 }
7345 for (i = 0; i < tabsize; i++)
7346 dd->cspec->msix_entries[i].msix.entry = i;
7347
7348 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
7349 qib_dev_err(dd,
7350 "Failed to setup PCIe or interrupts; continuing anyway\n");
7351 /* may be less than we wanted, if not enough available */
7352 dd->cspec->num_msix_entries = tabsize;
7353
7354 /* setup interrupt handler */
7355 qib_setup_7322_interrupt(dd, 1);
7356
7357 /* clear diagctrl register, in case diags were running and crashed */
7358 qib_write_kreg(dd, kr_hwdiagctrl, 0);
7359 #ifdef CONFIG_INFINIBAND_QIB_DCA
7360 if (!dca_add_requester(&pdev->dev)) {
7361 qib_devinfo(dd->pcidev, "DCA enabled\n");
7362 dd->flags |= QIB_DCA_ENABLED;
7363 qib_setup_dca(dd);
7364 }
7365 #endif
7366 goto bail;
7367
7368 bail_cleanup:
7369 qib_pcie_ddcleanup(dd);
7370 bail_free:
7371 qib_free_devdata(dd);
7372 dd = ERR_PTR(ret);
7373 bail:
7374 return dd;
7375 }
7376
7377 /*
7378 * Set the table entry at the specified index from the table specifed.
7379 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
7380 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
7381 * 'idx' below addresses the correct entry, while its 4 LSBs select the
7382 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
7383 */
7384 #define DDS_ENT_AMP_LSB 14
7385 #define DDS_ENT_MAIN_LSB 9
7386 #define DDS_ENT_POST_LSB 5
7387 #define DDS_ENT_PRE_XTRA_LSB 3
7388 #define DDS_ENT_PRE_LSB 0
7389
7390 /*
7391 * Set one entry in the TxDDS table for spec'd port
7392 * ridx picks one of the entries, while tp points
7393 * to the appropriate table entry.
7394 */
7395 static void set_txdds(struct qib_pportdata *ppd, int ridx,
7396 const struct txdds_ent *tp)
7397 {
7398 struct qib_devdata *dd = ppd->dd;
7399 u32 pack_ent;
7400 int regidx;
7401
7402 /* Get correct offset in chip-space, and in source table */
7403 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
7404 /*
7405 * We do not use qib_write_kreg_port() because it was intended
7406 * only for registers in the lower "port specific" pages.
7407 * So do index calculation by hand.
7408 */
7409 if (ppd->hw_pidx)
7410 regidx += (dd->palign / sizeof(u64));
7411
7412 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
7413 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
7414 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
7415 pack_ent |= tp->post << DDS_ENT_POST_LSB;
7416 qib_write_kreg(dd, regidx, pack_ent);
7417 /* Prevent back-to-back writes by hitting scratch */
7418 qib_write_kreg(ppd->dd, kr_scratch, 0);
7419 }
7420
7421 static const struct vendor_txdds_ent vendor_txdds[] = {
7422 { /* Amphenol 1m 30awg NoEq */
7423 { 0x41, 0x50, 0x48 }, "584470002 ",
7424 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
7425 },
7426 { /* Amphenol 3m 28awg NoEq */
7427 { 0x41, 0x50, 0x48 }, "584470004 ",
7428 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
7429 },
7430 { /* Finisar 3m OM2 Optical */
7431 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7432 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
7433 },
7434 { /* Finisar 30m OM2 Optical */
7435 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7436 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
7437 },
7438 { /* Finisar Default OM2 Optical */
7439 { 0x00, 0x90, 0x65 }, NULL,
7440 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
7441 },
7442 { /* Gore 1m 30awg NoEq */
7443 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7444 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
7445 },
7446 { /* Gore 2m 30awg NoEq */
7447 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7448 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
7449 },
7450 { /* Gore 1m 28awg NoEq */
7451 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7452 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
7453 },
7454 { /* Gore 3m 28awg NoEq */
7455 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7456 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
7457 },
7458 { /* Gore 5m 24awg Eq */
7459 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7460 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
7461 },
7462 { /* Gore 7m 24awg Eq */
7463 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7464 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7465 },
7466 { /* Gore 5m 26awg Eq */
7467 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7468 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7469 },
7470 { /* Gore 7m 26awg Eq */
7471 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7472 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7473 },
7474 { /* Intersil 12m 24awg Active */
7475 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7476 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7477 },
7478 { /* Intersil 10m 28awg Active */
7479 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7480 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7481 },
7482 { /* Intersil 7m 30awg Active */
7483 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7484 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7485 },
7486 { /* Intersil 5m 32awg Active */
7487 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7488 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7489 },
7490 { /* Intersil Default Active */
7491 { 0x00, 0x30, 0xB4 }, NULL,
7492 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7493 },
7494 { /* Luxtera 20m Active Optical */
7495 { 0x00, 0x25, 0x63 }, NULL,
7496 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7497 },
7498 { /* Molex 1M Cu loopback */
7499 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7500 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7501 },
7502 { /* Molex 2m 28awg NoEq */
7503 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7504 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7505 },
7506 };
7507
7508 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7509 /* amp, pre, main, post */
7510 { 2, 2, 15, 6 }, /* Loopback */
7511 { 0, 0, 0, 1 }, /* 2 dB */
7512 { 0, 0, 0, 2 }, /* 3 dB */
7513 { 0, 0, 0, 3 }, /* 4 dB */
7514 { 0, 0, 0, 4 }, /* 5 dB */
7515 { 0, 0, 0, 5 }, /* 6 dB */
7516 { 0, 0, 0, 6 }, /* 7 dB */
7517 { 0, 0, 0, 7 }, /* 8 dB */
7518 { 0, 0, 0, 8 }, /* 9 dB */
7519 { 0, 0, 0, 9 }, /* 10 dB */
7520 { 0, 0, 0, 10 }, /* 11 dB */
7521 { 0, 0, 0, 11 }, /* 12 dB */
7522 { 0, 0, 0, 12 }, /* 13 dB */
7523 { 0, 0, 0, 13 }, /* 14 dB */
7524 { 0, 0, 0, 14 }, /* 15 dB */
7525 { 0, 0, 0, 15 }, /* 16 dB */
7526 };
7527
7528 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7529 /* amp, pre, main, post */
7530 { 2, 2, 15, 6 }, /* Loopback */
7531 { 0, 0, 0, 8 }, /* 2 dB */
7532 { 0, 0, 0, 8 }, /* 3 dB */
7533 { 0, 0, 0, 9 }, /* 4 dB */
7534 { 0, 0, 0, 9 }, /* 5 dB */
7535 { 0, 0, 0, 10 }, /* 6 dB */
7536 { 0, 0, 0, 10 }, /* 7 dB */
7537 { 0, 0, 0, 11 }, /* 8 dB */
7538 { 0, 0, 0, 11 }, /* 9 dB */
7539 { 0, 0, 0, 12 }, /* 10 dB */
7540 { 0, 0, 0, 12 }, /* 11 dB */
7541 { 0, 0, 0, 13 }, /* 12 dB */
7542 { 0, 0, 0, 13 }, /* 13 dB */
7543 { 0, 0, 0, 14 }, /* 14 dB */
7544 { 0, 0, 0, 14 }, /* 15 dB */
7545 { 0, 0, 0, 15 }, /* 16 dB */
7546 };
7547
7548 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7549 /* amp, pre, main, post */
7550 { 2, 2, 15, 6 }, /* Loopback */
7551 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7552 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7553 { 0, 1, 0, 11 }, /* 4 dB */
7554 { 0, 1, 0, 13 }, /* 5 dB */
7555 { 0, 1, 0, 15 }, /* 6 dB */
7556 { 0, 1, 3, 15 }, /* 7 dB */
7557 { 0, 1, 7, 15 }, /* 8 dB */
7558 { 0, 1, 7, 15 }, /* 9 dB */
7559 { 0, 1, 8, 15 }, /* 10 dB */
7560 { 0, 1, 9, 15 }, /* 11 dB */
7561 { 0, 1, 10, 15 }, /* 12 dB */
7562 { 0, 2, 6, 15 }, /* 13 dB */
7563 { 0, 2, 7, 15 }, /* 14 dB */
7564 { 0, 2, 8, 15 }, /* 15 dB */
7565 { 0, 2, 9, 15 }, /* 16 dB */
7566 };
7567
7568 /*
7569 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7570 * These are mostly used for mez cards going through connectors
7571 * and backplane traces, but can be used to add other "unusual"
7572 * table values as well.
7573 */
7574 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7575 /* amp, pre, main, post */
7576 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7577 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7578 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7579 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7580 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7581 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7582 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7583 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7584 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7585 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7586 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7587 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7588 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7589 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7590 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7591 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7592 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7593 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7594 };
7595
7596 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7597 /* amp, pre, main, post */
7598 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7599 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7600 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7601 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7602 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7603 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7604 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7605 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7606 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7607 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7608 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7609 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7610 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7611 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7612 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7613 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7614 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7615 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7616 };
7617
7618 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7619 /* amp, pre, main, post */
7620 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7621 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7622 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7623 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7624 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7625 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7626 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7627 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7628 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7629 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7630 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7631 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7632 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7633 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7634 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7635 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7636 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7637 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7638 };
7639
7640 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7641 /* amp, pre, main, post */
7642 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7643 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7644 };
7645
7646 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7647 unsigned atten)
7648 {
7649 /*
7650 * The attenuation table starts at 2dB for entry 1,
7651 * with entry 0 being the loopback entry.
7652 */
7653 if (atten <= 2)
7654 atten = 1;
7655 else if (atten > TXDDS_TABLE_SZ)
7656 atten = TXDDS_TABLE_SZ - 1;
7657 else
7658 atten--;
7659 return txdds + atten;
7660 }
7661
7662 /*
7663 * if override is set, the module parameter txselect has a value
7664 * for this specific port, so use it, rather than our normal mechanism.
7665 */
7666 static void find_best_ent(struct qib_pportdata *ppd,
7667 const struct txdds_ent **sdr_dds,
7668 const struct txdds_ent **ddr_dds,
7669 const struct txdds_ent **qdr_dds, int override)
7670 {
7671 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7672 int idx;
7673
7674 /* Search table of known cables */
7675 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7676 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7677
7678 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7679 (!v->partnum ||
7680 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7681 *sdr_dds = &v->sdr;
7682 *ddr_dds = &v->ddr;
7683 *qdr_dds = &v->qdr;
7684 return;
7685 }
7686 }
7687
7688 /* Active cables don't have attenuation so we only set SERDES
7689 * settings to account for the attenuation of the board traces. */
7690 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7691 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7692 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7693 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7694 return;
7695 }
7696
7697 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7698 qd->atten[1])) {
7699 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7700 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7701 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7702 return;
7703 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7704 /*
7705 * If we have no (or incomplete) data from the cable
7706 * EEPROM, or no QSFP, or override is set, use the
7707 * module parameter value to index into the attentuation
7708 * table.
7709 */
7710 idx = ppd->cpspec->no_eep;
7711 *sdr_dds = &txdds_sdr[idx];
7712 *ddr_dds = &txdds_ddr[idx];
7713 *qdr_dds = &txdds_qdr[idx];
7714 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7715 /* similar to above, but index into the "extra" table. */
7716 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7717 *sdr_dds = &txdds_extra_sdr[idx];
7718 *ddr_dds = &txdds_extra_ddr[idx];
7719 *qdr_dds = &txdds_extra_qdr[idx];
7720 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7721 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7722 TXDDS_MFG_SZ)) {
7723 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7724 pr_info("IB%u:%u use idx %u into txdds_mfg\n",
7725 ppd->dd->unit, ppd->port, idx);
7726 *sdr_dds = &txdds_extra_mfg[idx];
7727 *ddr_dds = &txdds_extra_mfg[idx];
7728 *qdr_dds = &txdds_extra_mfg[idx];
7729 } else {
7730 /* this shouldn't happen, it's range checked */
7731 *sdr_dds = txdds_sdr + qib_long_atten;
7732 *ddr_dds = txdds_ddr + qib_long_atten;
7733 *qdr_dds = txdds_qdr + qib_long_atten;
7734 }
7735 }
7736
7737 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7738 {
7739 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7740 struct txdds_ent *dds;
7741 int idx;
7742 int single_ent = 0;
7743
7744 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7745
7746 /* for mez cards or override, use the selected value for all entries */
7747 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7748 single_ent = 1;
7749
7750 /* Fill in the first entry with the best entry found. */
7751 set_txdds(ppd, 0, sdr_dds);
7752 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7753 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7754 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7755 QIBL_LINKACTIVE)) {
7756 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7757 QIB_IB_QDR ? qdr_dds :
7758 (ppd->link_speed_active ==
7759 QIB_IB_DDR ? ddr_dds : sdr_dds));
7760 write_tx_serdes_param(ppd, dds);
7761 }
7762
7763 /* Fill in the remaining entries with the default table values. */
7764 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7765 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7766 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7767 single_ent ? ddr_dds : txdds_ddr + idx);
7768 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7769 single_ent ? qdr_dds : txdds_qdr + idx);
7770 }
7771 }
7772
7773 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7774 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7775 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7776 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7777 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7778 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7779 #define AHB_TRANS_TRIES 10
7780
7781 /*
7782 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7783 * 5=subsystem which is why most calls have "chan + chan >> 1"
7784 * for the channel argument.
7785 */
7786 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7787 u32 data, u32 mask)
7788 {
7789 u32 rd_data, wr_data, sz_mask;
7790 u64 trans, acc, prev_acc;
7791 u32 ret = 0xBAD0BAD;
7792 int tries;
7793
7794 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7795 /* From this point on, make sure we return access */
7796 acc = (quad << 1) | 1;
7797 qib_write_kreg(dd, KR_AHB_ACC, acc);
7798
7799 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7800 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7801 if (trans & AHB_TRANS_RDY)
7802 break;
7803 }
7804 if (tries >= AHB_TRANS_TRIES) {
7805 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7806 goto bail;
7807 }
7808
7809 /* If mask is not all 1s, we need to read, but different SerDes
7810 * entities have different sizes
7811 */
7812 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7813 wr_data = data & mask & sz_mask;
7814 if ((~mask & sz_mask) != 0) {
7815 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7816 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7817
7818 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7819 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7820 if (trans & AHB_TRANS_RDY)
7821 break;
7822 }
7823 if (tries >= AHB_TRANS_TRIES) {
7824 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7825 AHB_TRANS_TRIES);
7826 goto bail;
7827 }
7828 /* Re-read in case host split reads and read data first */
7829 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7830 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7831 wr_data |= (rd_data & ~mask & sz_mask);
7832 }
7833
7834 /* If mask is not zero, we need to write. */
7835 if (mask & sz_mask) {
7836 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7837 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7838 trans |= AHB_WR;
7839 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7840
7841 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7842 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7843 if (trans & AHB_TRANS_RDY)
7844 break;
7845 }
7846 if (tries >= AHB_TRANS_TRIES) {
7847 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7848 AHB_TRANS_TRIES);
7849 goto bail;
7850 }
7851 }
7852 ret = wr_data;
7853 bail:
7854 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7855 return ret;
7856 }
7857
7858 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7859 unsigned mask)
7860 {
7861 struct qib_devdata *dd = ppd->dd;
7862 int chan;
7863 u32 rbc;
7864
7865 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7866 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7867 data, mask);
7868 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7869 addr, 0, 0);
7870 }
7871 }
7872
7873 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7874 {
7875 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7876 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7877
7878 if (enable && !state) {
7879 pr_info("IB%u:%u Turning LOS on\n",
7880 ppd->dd->unit, ppd->port);
7881 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7882 } else if (!enable && state) {
7883 pr_info("IB%u:%u Turning LOS off\n",
7884 ppd->dd->unit, ppd->port);
7885 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7886 }
7887 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7888 }
7889
7890 static int serdes_7322_init(struct qib_pportdata *ppd)
7891 {
7892 int ret = 0;
7893
7894 if (ppd->dd->cspec->r1)
7895 ret = serdes_7322_init_old(ppd);
7896 else
7897 ret = serdes_7322_init_new(ppd);
7898 return ret;
7899 }
7900
7901 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7902 {
7903 u32 le_val;
7904
7905 /*
7906 * Initialize the Tx DDS tables. Also done every QSFP event,
7907 * for adapters with QSFP
7908 */
7909 init_txdds_table(ppd, 0);
7910
7911 /* ensure no tx overrides from earlier driver loads */
7912 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7913 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7914 reset_tx_deemphasis_override));
7915
7916 /* Patch some SerDes defaults to "Better for IB" */
7917 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7918 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7919
7920 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7921 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7922 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7923 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7924
7925 /* May be overridden in qsfp_7322_event */
7926 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7927 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7928
7929 /* enable LE1 adaptation for all but QME, which is disabled */
7930 le_val = IS_QME(ppd->dd) ? 0 : 1;
7931 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7932
7933 /* Clear cmode-override, may be set from older driver */
7934 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7935
7936 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7937 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7938
7939 /* setup LoS params; these are subsystem, so chan == 5 */
7940 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7941 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7942 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7943 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7944 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7945
7946 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7947 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7948 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7949 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7950 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7951
7952 /* LoS filter select enabled */
7953 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7954
7955 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7956 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7957 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7958 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7959
7960 serdes_7322_los_enable(ppd, 1);
7961
7962 /* rxbistena; set 0 to avoid effects of it switch later */
7963 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7964
7965 /* Configure 4 DFE taps, and only they adapt */
7966 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7967
7968 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7969 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7970 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7971
7972 /*
7973 * Set receive adaptation mode. SDR and DDR adaptation are
7974 * always on, and QDR is initially enabled; later disabled.
7975 */
7976 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7977 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7978 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7979 ppd->dd->cspec->r1 ?
7980 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7981 ppd->cpspec->qdr_dfe_on = 1;
7982
7983 /* FLoop LOS gate: PPM filter enabled */
7984 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7985
7986 /* rx offset center enabled */
7987 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7988
7989 if (!ppd->dd->cspec->r1) {
7990 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7991 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7992 }
7993
7994 /* Set the frequency loop bandwidth to 15 */
7995 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7996
7997 return 0;
7998 }
7999
8000 static int serdes_7322_init_new(struct qib_pportdata *ppd)
8001 {
8002 unsigned long tend;
8003 u32 le_val, rxcaldone;
8004 int chan, chan_done = (1 << SERDES_CHANS) - 1;
8005
8006 /* Clear cmode-override, may be set from older driver */
8007 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
8008
8009 /* ensure no tx overrides from earlier driver loads */
8010 qib_write_kreg_port(ppd, krp_tx_deemph_override,
8011 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8012 reset_tx_deemphasis_override));
8013
8014 /* START OF LSI SUGGESTED SERDES BRINGUP */
8015 /* Reset - Calibration Setup */
8016 /* Stop DFE adaptaion */
8017 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
8018 /* Disable LE1 */
8019 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
8020 /* Disable autoadapt for LE1 */
8021 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
8022 /* Disable LE2 */
8023 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
8024 /* Disable VGA */
8025 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8026 /* Disable AFE Offset Cancel */
8027 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
8028 /* Disable Timing Loop */
8029 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
8030 /* Disable Frequency Loop */
8031 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
8032 /* Disable Baseline Wander Correction */
8033 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
8034 /* Disable RX Calibration */
8035 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8036 /* Disable RX Offset Calibration */
8037 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
8038 /* Select BB CDR */
8039 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
8040 /* CDR Step Size */
8041 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
8042 /* Enable phase Calibration */
8043 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
8044 /* DFE Bandwidth [2:14-12] */
8045 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
8046 /* DFE Config (4 taps only) */
8047 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
8048 /* Gain Loop Bandwidth */
8049 if (!ppd->dd->cspec->r1) {
8050 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
8051 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
8052 } else {
8053 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
8054 }
8055 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
8056 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
8057 /* Data Rate Select [5:7-6] (leave as default) */
8058 /* RX Parallel Word Width [3:10-8] (leave as default) */
8059
8060 /* RX REST */
8061 /* Single- or Multi-channel reset */
8062 /* RX Analog reset */
8063 /* RX Digital reset */
8064 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
8065 msleep(20);
8066 /* RX Analog reset */
8067 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
8068 msleep(20);
8069 /* RX Digital reset */
8070 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
8071 msleep(20);
8072
8073 /* setup LoS params; these are subsystem, so chan == 5 */
8074 /* LoS filter threshold_count on, ch 0-3, set to 8 */
8075 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
8076 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
8077 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
8078 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
8079
8080 /* LoS filter threshold_count off, ch 0-3, set to 4 */
8081 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
8082 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
8083 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
8084 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
8085
8086 /* LoS filter select enabled */
8087 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
8088
8089 /* LoS target data: SDR=4, DDR=2, QDR=1 */
8090 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
8091 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
8092 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
8093
8094 /* Turn on LOS on initial SERDES init */
8095 serdes_7322_los_enable(ppd, 1);
8096 /* FLoop LOS gate: PPM filter enabled */
8097 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
8098
8099 /* RX LATCH CALIBRATION */
8100 /* Enable Eyefinder Phase Calibration latch */
8101 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
8102 /* Enable RX Offset Calibration latch */
8103 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
8104 msleep(20);
8105 /* Start Calibration */
8106 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
8107 tend = jiffies + msecs_to_jiffies(500);
8108 while (chan_done && !time_is_before_jiffies(tend)) {
8109 msleep(20);
8110 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8111 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8112 (chan + (chan >> 1)),
8113 25, 0, 0);
8114 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
8115 (~chan_done & (1 << chan)) == 0)
8116 chan_done &= ~(1 << chan);
8117 }
8118 }
8119 if (chan_done) {
8120 pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n",
8121 IBSD(ppd->hw_pidx), chan_done);
8122 } else {
8123 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8124 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8125 (chan + (chan >> 1)),
8126 25, 0, 0);
8127 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
8128 pr_info("Serdes %d chan %d calibration failed\n",
8129 IBSD(ppd->hw_pidx), chan);
8130 }
8131 }
8132
8133 /* Turn off Calibration */
8134 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8135 msleep(20);
8136
8137 /* BRING RX UP */
8138 /* Set LE2 value (May be overridden in qsfp_7322_event) */
8139 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
8140 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
8141 /* Set LE2 Loop bandwidth */
8142 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
8143 /* Enable LE2 */
8144 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
8145 msleep(20);
8146 /* Enable H0 only */
8147 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
8148 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
8149 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
8150 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
8151 /* Enable VGA */
8152 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8153 msleep(20);
8154 /* Set Frequency Loop Bandwidth */
8155 ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5));
8156 /* Enable Frequency Loop */
8157 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
8158 /* Set Timing Loop Bandwidth */
8159 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
8160 /* Enable Timing Loop */
8161 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
8162 msleep(50);
8163 /* Enable DFE
8164 * Set receive adaptation mode. SDR and DDR adaptation are
8165 * always on, and QDR is initially enabled; later disabled.
8166 */
8167 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
8168 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
8169 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
8170 ppd->dd->cspec->r1 ?
8171 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
8172 ppd->cpspec->qdr_dfe_on = 1;
8173 /* Disable LE1 */
8174 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
8175 /* Disable auto adapt for LE1 */
8176 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
8177 msleep(20);
8178 /* Enable AFE Offset Cancel */
8179 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
8180 /* Enable Baseline Wander Correction */
8181 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
8182 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
8183 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
8184 /* VGA output common mode */
8185 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
8186
8187 /*
8188 * Initialize the Tx DDS tables. Also done every QSFP event,
8189 * for adapters with QSFP
8190 */
8191 init_txdds_table(ppd, 0);
8192
8193 return 0;
8194 }
8195
8196 /* start adjust QMH serdes parameters */
8197
8198 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
8199 {
8200 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8201 9, code << 9, 0x3f << 9);
8202 }
8203
8204 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
8205 int enable, u32 tapenable)
8206 {
8207 if (enable)
8208 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8209 1, 3 << 10, 0x1f << 10);
8210 else
8211 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8212 1, 0, 0x1f << 10);
8213 }
8214
8215 /* Set clock to 1, 0, 1, 0 */
8216 static void clock_man(struct qib_pportdata *ppd, int chan)
8217 {
8218 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8219 4, 0x4000, 0x4000);
8220 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8221 4, 0, 0x4000);
8222 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8223 4, 0x4000, 0x4000);
8224 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8225 4, 0, 0x4000);
8226 }
8227
8228 /*
8229 * write the current Tx serdes pre,post,main,amp settings into the serdes.
8230 * The caller must pass the settings appropriate for the current speed,
8231 * or not care if they are correct for the current speed.
8232 */
8233 static void write_tx_serdes_param(struct qib_pportdata *ppd,
8234 struct txdds_ent *txdds)
8235 {
8236 u64 deemph;
8237
8238 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
8239 /* field names for amp, main, post, pre, respectively */
8240 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
8241 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
8242 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
8243 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
8244
8245 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8246 tx_override_deemphasis_select);
8247 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8248 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8249 txampcntl_d2a);
8250 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8251 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8252 txc0_ena);
8253 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8254 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8255 txcp1_ena);
8256 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8257 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8258 txcn1_ena);
8259 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
8260 }
8261
8262 /*
8263 * Set the parameters for mez cards on link bounce, so they are
8264 * always exactly what was requested. Similar logic to init_txdds
8265 * but does just the serdes.
8266 */
8267 static void adj_tx_serdes(struct qib_pportdata *ppd)
8268 {
8269 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
8270 struct txdds_ent *dds;
8271
8272 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
8273 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
8274 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
8275 ddr_dds : sdr_dds));
8276 write_tx_serdes_param(ppd, dds);
8277 }
8278
8279 /* set QDR forced value for H1, if needed */
8280 static void force_h1(struct qib_pportdata *ppd)
8281 {
8282 int chan;
8283
8284 ppd->cpspec->qdr_reforce = 0;
8285 if (!ppd->dd->cspec->r1)
8286 return;
8287
8288 for (chan = 0; chan < SERDES_CHANS; chan++) {
8289 set_man_mode_h1(ppd, chan, 1, 0);
8290 set_man_code(ppd, chan, ppd->cpspec->h1_val);
8291 clock_man(ppd, chan);
8292 set_man_mode_h1(ppd, chan, 0, 0);
8293 }
8294 }
8295
8296 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
8297 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
8298
8299 #define R_OPCODE_LSB 3
8300 #define R_OP_NOP 0
8301 #define R_OP_SHIFT 2
8302 #define R_OP_UPDATE 3
8303 #define R_TDI_LSB 2
8304 #define R_TDO_LSB 1
8305 #define R_RDY 1
8306
8307 static int qib_r_grab(struct qib_devdata *dd)
8308 {
8309 u64 val = SJA_EN;
8310
8311 qib_write_kreg(dd, kr_r_access, val);
8312 qib_read_kreg32(dd, kr_scratch);
8313 return 0;
8314 }
8315
8316 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
8317 * returns the current state of R_TDO
8318 */
8319 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
8320 {
8321 u64 val;
8322 int timeout;
8323
8324 for (timeout = 0; timeout < 100 ; ++timeout) {
8325 val = qib_read_kreg32(dd, kr_r_access);
8326 if (val & R_RDY)
8327 return (val >> R_TDO_LSB) & 1;
8328 }
8329 return -1;
8330 }
8331
8332 static int qib_r_shift(struct qib_devdata *dd, int bisten,
8333 int len, u8 *inp, u8 *outp)
8334 {
8335 u64 valbase, val;
8336 int ret, pos;
8337
8338 valbase = SJA_EN | (bisten << BISTEN_LSB) |
8339 (R_OP_SHIFT << R_OPCODE_LSB);
8340 ret = qib_r_wait_for_rdy(dd);
8341 if (ret < 0)
8342 goto bail;
8343 for (pos = 0; pos < len; ++pos) {
8344 val = valbase;
8345 if (outp) {
8346 outp[pos >> 3] &= ~(1 << (pos & 7));
8347 outp[pos >> 3] |= (ret << (pos & 7));
8348 }
8349 if (inp) {
8350 int tdi = inp[pos >> 3] >> (pos & 7);
8351
8352 val |= ((tdi & 1) << R_TDI_LSB);
8353 }
8354 qib_write_kreg(dd, kr_r_access, val);
8355 qib_read_kreg32(dd, kr_scratch);
8356 ret = qib_r_wait_for_rdy(dd);
8357 if (ret < 0)
8358 break;
8359 }
8360 /* Restore to NOP between operations. */
8361 val = SJA_EN | (bisten << BISTEN_LSB);
8362 qib_write_kreg(dd, kr_r_access, val);
8363 qib_read_kreg32(dd, kr_scratch);
8364 ret = qib_r_wait_for_rdy(dd);
8365
8366 if (ret >= 0)
8367 ret = pos;
8368 bail:
8369 return ret;
8370 }
8371
8372 static int qib_r_update(struct qib_devdata *dd, int bisten)
8373 {
8374 u64 val;
8375 int ret;
8376
8377 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
8378 ret = qib_r_wait_for_rdy(dd);
8379 if (ret >= 0) {
8380 qib_write_kreg(dd, kr_r_access, val);
8381 qib_read_kreg32(dd, kr_scratch);
8382 }
8383 return ret;
8384 }
8385
8386 #define BISTEN_PORT_SEL 15
8387 #define LEN_PORT_SEL 625
8388 #define BISTEN_AT 17
8389 #define LEN_AT 156
8390 #define BISTEN_ETM 16
8391 #define LEN_ETM 632
8392
8393 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
8394
8395 /* these are common for all IB port use cases. */
8396 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
8397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8399 };
8400 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
8401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8403 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
8404 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
8405 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
8406 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
8407 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8408 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
8409 };
8410 static u8 at[BIT2BYTE(LEN_AT)] = {
8411 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
8412 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8413 };
8414
8415 /* used for IB1 or IB2, only one in use */
8416 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
8417 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8418 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8419 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8420 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
8421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8422 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
8423 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
8424 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
8425 };
8426
8427 /* used when both IB1 and IB2 are in use */
8428 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
8429 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8430 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
8431 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8432 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
8433 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
8434 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
8435 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
8436 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
8437 };
8438
8439 /* used when only IB1 is in use */
8440 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
8441 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8442 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8443 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8444 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8445 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8446 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8447 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8448 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8449 };
8450
8451 /* used when only IB2 is in use */
8452 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
8453 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
8454 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
8455 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8456 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8457 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
8458 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8459 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8460 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
8461 };
8462
8463 /* used when both IB1 and IB2 are in use */
8464 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
8465 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8466 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8467 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8468 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8469 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8470 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
8471 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8472 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8473 };
8474
8475 /*
8476 * Do setup to properly handle IB link recovery; if port is zero, we
8477 * are initializing to cover both ports; otherwise we are initializing
8478 * to cover a single port card, or the port has reached INIT and we may
8479 * need to switch coverage types.
8480 */
8481 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
8482 {
8483 u8 *portsel, *etm;
8484 struct qib_devdata *dd = ppd->dd;
8485
8486 if (!ppd->dd->cspec->r1)
8487 return;
8488 if (!both) {
8489 dd->cspec->recovery_ports_initted++;
8490 ppd->cpspec->recovery_init = 1;
8491 }
8492 if (!both && dd->cspec->recovery_ports_initted == 1) {
8493 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8494 etm = atetm_1port;
8495 } else {
8496 portsel = portsel_2port;
8497 etm = atetm_2port;
8498 }
8499
8500 if (qib_r_grab(dd) < 0 ||
8501 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8502 qib_r_update(dd, BISTEN_ETM) < 0 ||
8503 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8504 qib_r_update(dd, BISTEN_AT) < 0 ||
8505 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8506 portsel, NULL) < 0 ||
8507 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8508 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8509 qib_r_update(dd, BISTEN_AT) < 0 ||
8510 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8511 qib_r_update(dd, BISTEN_ETM) < 0)
8512 qib_dev_err(dd, "Failed IB link recovery setup\n");
8513 }
8514
8515 static void check_7322_rxe_status(struct qib_pportdata *ppd)
8516 {
8517 struct qib_devdata *dd = ppd->dd;
8518 u64 fmask;
8519
8520 if (dd->cspec->recovery_ports_initted != 1)
8521 return; /* rest doesn't apply to dualport */
8522 qib_write_kreg(dd, kr_control, dd->control |
8523 SYM_MASK(Control, FreezeMode));
8524 (void)qib_read_kreg64(dd, kr_scratch);
8525 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
8526 fmask = qib_read_kreg64(dd, kr_act_fmask);
8527 if (!fmask) {
8528 /*
8529 * require a powercycle before we'll work again, and make
8530 * sure we get no more interrupts, and don't turn off
8531 * freeze.
8532 */
8533 ppd->dd->cspec->stay_in_freeze = 1;
8534 qib_7322_set_intr_state(ppd->dd, 0);
8535 qib_write_kreg(dd, kr_fmask, 0ULL);
8536 qib_dev_err(dd, "HCA unusable until powercycled\n");
8537 return; /* eventually reset */
8538 }
8539
8540 qib_write_kreg(ppd->dd, kr_hwerrclear,
8541 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8542
8543 /* don't do the full clear_freeze(), not needed for this */
8544 qib_write_kreg(dd, kr_control, dd->control);
8545 qib_read_kreg32(dd, kr_scratch);
8546 /* take IBC out of reset */
8547 if (ppd->link_speed_supported) {
8548 ppd->cpspec->ibcctrl_a &=
8549 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8550 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8551 ppd->cpspec->ibcctrl_a);
8552 qib_read_kreg32(dd, kr_scratch);
8553 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8554 qib_set_ib_7322_lstate(ppd, 0,
8555 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
8556 }
8557 }
Linux with added FPC-III support