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x86: merge sched_clock handling
[linux/fpc-iii.git] / drivers / net / sky2.c
blobc8a5ef2d75f4280f896306ce06ebefef4358fa32
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 /* This driver supports yukon2 chipset only */
151 static const char *yukon2_name[] = {
152 "XL", /* 0xb3 */
153 "EC Ultra", /* 0xb4 */
154 "Extreme", /* 0xb5 */
155 "EC", /* 0xb6 */
156 "FE", /* 0xb7 */
157 "FE+", /* 0xb8 */
158 "Supreme", /* 0xb9 */
159 };
160
161 static void sky2_set_multicast(struct net_device *dev);
162
163 /* Access to PHY via serial interconnect */
164 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
165 {
166 int i;
167
168 gma_write16(hw, port, GM_SMI_DATA, val);
169 gma_write16(hw, port, GM_SMI_CTRL,
170 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
171
172 for (i = 0; i < PHY_RETRIES; i++) {
173 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
174 if (ctrl == 0xffff)
175 goto io_error;
176
177 if (!(ctrl & GM_SMI_CT_BUSY))
178 return 0;
179
180 udelay(10);
181 }
182
183 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
184 return -ETIMEDOUT;
185
186 io_error:
187 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
188 return -EIO;
189 }
190
191 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
192 {
193 int i;
194
195 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
196 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
197
198 for (i = 0; i < PHY_RETRIES; i++) {
199 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
200 if (ctrl == 0xffff)
201 goto io_error;
202
203 if (ctrl & GM_SMI_CT_RD_VAL) {
204 *val = gma_read16(hw, port, GM_SMI_DATA);
205 return 0;
206 }
207
208 udelay(10);
209 }
210
211 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
212 return -ETIMEDOUT;
213 io_error:
214 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
215 return -EIO;
216 }
217
218 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
219 {
220 u16 v;
221 __gm_phy_read(hw, port, reg, &v);
222 return v;
223 }
224
225
226 static void sky2_power_on(struct sky2_hw *hw)
227 {
228 /* switch power to VCC (WA for VAUX problem) */
229 sky2_write8(hw, B0_POWER_CTRL,
230 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
231
232 /* disable Core Clock Division, */
233 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
234
235 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
236 /* enable bits are inverted */
237 sky2_write8(hw, B2_Y2_CLK_GATE,
238 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
239 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
240 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
241 else
242 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
243
244 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
245 u32 reg;
246
247 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
248
249 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
250 /* set all bits to 0 except bits 15..12 and 8 */
251 reg &= P_ASPM_CONTROL_MSK;
252 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
253
254 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
255 /* set all bits to 0 except bits 28 & 27 */
256 reg &= P_CTL_TIM_VMAIN_AV_MSK;
257 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
258
259 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
260
261 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
262 reg = sky2_read32(hw, B2_GP_IO);
263 reg |= GLB_GPIO_STAT_RACE_DIS;
264 sky2_write32(hw, B2_GP_IO, reg);
265
266 sky2_read32(hw, B2_GP_IO);
267 }
268 }
269
270 static void sky2_power_aux(struct sky2_hw *hw)
271 {
272 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
273 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
274 else
275 /* enable bits are inverted */
276 sky2_write8(hw, B2_Y2_CLK_GATE,
277 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
278 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
279 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
280
281 /* switch power to VAUX */
282 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
283 sky2_write8(hw, B0_POWER_CTRL,
284 (PC_VAUX_ENA | PC_VCC_ENA |
285 PC_VAUX_ON | PC_VCC_OFF));
286 }
287
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 {
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303 }
304
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 };
312
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 };
320
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327 };
328
329
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 {
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334
335 if (sky2->autoneg == AUTONEG_ENABLE &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 PHY_M_EC_MAC_S_MSK);
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if (sky2->autoneg == AUTONEG_ENABLE
378 && (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 }
390
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 }
413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
415 }
416
417 ctrl = PHY_CT_RESET;
418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
420 reg = 0;
421
422 if (sky2->autoneg == AUTONEG_ENABLE) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
436
437 adv |= copper_fc_adv[sky2->flow_mode];
438 } else { /* special defines for FIBER (88E1040S only) */
439 if (sky2->advertising & ADVERTISED_1000baseT_Full)
440 adv |= PHY_M_AN_1000X_AFD;
441 if (sky2->advertising & ADVERTISED_1000baseT_Half)
442 adv |= PHY_M_AN_1000X_AHD;
443
444 adv |= fiber_fc_adv[sky2->flow_mode];
445 }
446
447 /* Restart Auto-negotiation */
448 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 } else {
450 /* forced speed/duplex settings */
451 ct1000 = PHY_M_1000C_MSE;
452
453 /* Disable auto update for duplex flow control and speed */
454 reg |= GM_GPCR_AU_ALL_DIS;
455
456 switch (sky2->speed) {
457 case SPEED_1000:
458 ctrl |= PHY_CT_SP1000;
459 reg |= GM_GPCR_SPEED_1000;
460 break;
461 case SPEED_100:
462 ctrl |= PHY_CT_SP100;
463 reg |= GM_GPCR_SPEED_100;
464 break;
465 }
466
467 if (sky2->duplex == DUPLEX_FULL) {
468 reg |= GM_GPCR_DUP_FULL;
469 ctrl |= PHY_CT_DUP_MD;
470 } else if (sky2->speed < SPEED_1000)
471 sky2->flow_mode = FC_NONE;
472
473
474 reg |= gm_fc_disable[sky2->flow_mode];
475
476 /* Forward pause packets to GMAC? */
477 if (sky2->flow_mode & FC_RX)
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
479 else
480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
481 }
482
483 gma_write16(hw, port, GM_GP_CTRL, reg);
484
485 if (hw->flags & SKY2_HW_GIGABIT)
486 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
487
488 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
489 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
490
491 /* Setup Phy LED's */
492 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
493 ledover = 0;
494
495 switch (hw->chip_id) {
496 case CHIP_ID_YUKON_FE:
497 /* on 88E3082 these bits are at 11..9 (shifted left) */
498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
499
500 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
501
502 /* delete ACT LED control bits */
503 ctrl &= ~PHY_M_FELP_LED1_MSK;
504 /* change ACT LED control to blink mode */
505 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
506 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
507 break;
508
509 case CHIP_ID_YUKON_FE_P:
510 /* Enable Link Partner Next Page */
511 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
512 ctrl |= PHY_M_PC_ENA_LIP_NP;
513
514 /* disable Energy Detect and enable scrambler */
515 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
516 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
517
518 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
519 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
520 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
521 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
522
523 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
524 break;
525
526 case CHIP_ID_YUKON_XL:
527 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
528
529 /* select page 3 to access LED control register */
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
531
532 /* set LED Function Control register */
533 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
534 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
535 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
536 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
537 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
538
539 /* set Polarity Control register */
540 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
541 (PHY_M_POLC_LS1_P_MIX(4) |
542 PHY_M_POLC_IS0_P_MIX(4) |
543 PHY_M_POLC_LOS_CTRL(2) |
544 PHY_M_POLC_INIT_CTRL(2) |
545 PHY_M_POLC_STA1_CTRL(2) |
546 PHY_M_POLC_STA0_CTRL(2)));
547
548 /* restore page register */
549 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
550 break;
551
552 case CHIP_ID_YUKON_EC_U:
553 case CHIP_ID_YUKON_EX:
554 case CHIP_ID_YUKON_SUPR:
555 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
556
557 /* select page 3 to access LED control register */
558 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
559
560 /* set LED Function Control register */
561 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
562 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
563 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
564 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
565 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
566
567 /* set Blink Rate in LED Timer Control Register */
568 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
569 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
570 /* restore page register */
571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
572 break;
573
574 default:
575 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
576 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
577
578 /* turn off the Rx LED (LED_RX) */
579 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
580 }
581
582 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
583 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
584 /* apply fixes in PHY AFE */
585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
586
587 /* increase differential signal amplitude in 10BASE-T */
588 gm_phy_write(hw, port, 0x18, 0xaa99);
589 gm_phy_write(hw, port, 0x17, 0x2011);
590
591 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
592 gm_phy_write(hw, port, 0x18, 0xa204);
593 gm_phy_write(hw, port, 0x17, 0x2002);
594
595 /* set page register to 0 */
596 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
597 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
598 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
599 /* apply workaround for integrated resistors calibration */
600 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
601 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
602 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
603 /* no effect on Yukon-XL */
604 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
605
606 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
607 /* turn on 100 Mbps LED (LED_LINK100) */
608 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
609 }
610
611 if (ledover)
612 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
613
614 }
615
616 /* Enable phy interrupt on auto-negotiation complete (or link up) */
617 if (sky2->autoneg == AUTONEG_ENABLE)
618 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
619 else
620 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
621 }
622
623 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
624 {
625 u32 reg1;
626 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
627 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
628
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
630 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
631 /* Turn on/off phy power saving */
632 if (onoff)
633 reg1 &= ~phy_power[port];
634 else
635 reg1 |= phy_power[port];
636
637 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
638 reg1 |= coma_mode[port];
639
640 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
641 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
642 sky2_pci_read32(hw, PCI_DEV_REG1);
643
644 udelay(100);
645 }
646
647 /* Force a renegotiation */
648 static void sky2_phy_reinit(struct sky2_port *sky2)
649 {
650 spin_lock_bh(&sky2->phy_lock);
651 sky2_phy_init(sky2->hw, sky2->port);
652 spin_unlock_bh(&sky2->phy_lock);
653 }
654
655 /* Put device in state to listen for Wake On Lan */
656 static void sky2_wol_init(struct sky2_port *sky2)
657 {
658 struct sky2_hw *hw = sky2->hw;
659 unsigned port = sky2->port;
660 enum flow_control save_mode;
661 u16 ctrl;
662 u32 reg1;
663
664 /* Bring hardware out of reset */
665 sky2_write16(hw, B0_CTST, CS_RST_CLR);
666 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
667
668 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
669 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
670
671 /* Force to 10/100
672 * sky2_reset will re-enable on resume
673 */
674 save_mode = sky2->flow_mode;
675 ctrl = sky2->advertising;
676
677 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
678 sky2->flow_mode = FC_NONE;
679 sky2_phy_power(hw, port, 1);
680 sky2_phy_reinit(sky2);
681
682 sky2->flow_mode = save_mode;
683 sky2->advertising = ctrl;
684
685 /* Set GMAC to no flow control and auto update for speed/duplex */
686 gma_write16(hw, port, GM_GP_CTRL,
687 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
688 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
689
690 /* Set WOL address */
691 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
692 sky2->netdev->dev_addr, ETH_ALEN);
693
694 /* Turn on appropriate WOL control bits */
695 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
696 ctrl = 0;
697 if (sky2->wol & WAKE_PHY)
698 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
699 else
700 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
701
702 if (sky2->wol & WAKE_MAGIC)
703 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
704 else
705 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
706
707 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
708 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
709
710 /* Turn on legacy PCI-Express PME mode */
711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
712 reg1 |= PCI_Y2_PME_LEGACY;
713 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
714
715 /* block receiver */
716 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
717
718 }
719
720 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
721 {
722 struct net_device *dev = hw->dev[port];
723
724 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
725 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
726 hw->chip_id == CHIP_ID_YUKON_FE_P ||
727 hw->chip_id == CHIP_ID_YUKON_SUPR) {
728 /* Yukon-Extreme B0 and further Extreme devices */
729 /* enable Store & Forward mode for TX */
730
731 if (dev->mtu <= ETH_DATA_LEN)
732 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
733 TX_JUMBO_DIS | TX_STFW_ENA);
734
735 else
736 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
737 TX_JUMBO_ENA| TX_STFW_ENA);
738 } else {
739 if (dev->mtu <= ETH_DATA_LEN)
740 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
741 else {
742 /* set Tx GMAC FIFO Almost Empty Threshold */
743 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
744 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
745
746 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
747
748 /* Can't do offload because of lack of store/forward */
749 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
750 }
751 }
752 }
753
754 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
755 {
756 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
757 u16 reg;
758 u32 rx_reg;
759 int i;
760 const u8 *addr = hw->dev[port]->dev_addr;
761
762 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
763 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
764
765 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
766
767 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
768 /* WA DEV_472 -- looks like crossed wires on port 2 */
769 /* clear GMAC 1 Control reset */
770 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
771 do {
772 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
773 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
774 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
775 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
776 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
777 }
778
779 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
780
781 /* Enable Transmit FIFO Underrun */
782 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
783
784 spin_lock_bh(&sky2->phy_lock);
785 sky2_phy_init(hw, port);
786 spin_unlock_bh(&sky2->phy_lock);
787
788 /* MIB clear */
789 reg = gma_read16(hw, port, GM_PHY_ADDR);
790 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
791
792 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
793 gma_read16(hw, port, i);
794 gma_write16(hw, port, GM_PHY_ADDR, reg);
795
796 /* transmit control */
797 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
798
799 /* receive control reg: unicast + multicast + no FCS */
800 gma_write16(hw, port, GM_RX_CTRL,
801 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
802
803 /* transmit flow control */
804 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
805
806 /* transmit parameter */
807 gma_write16(hw, port, GM_TX_PARAM,
808 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
809 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
810 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
811 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
812
813 /* serial mode register */
814 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
815 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
816
817 if (hw->dev[port]->mtu > ETH_DATA_LEN)
818 reg |= GM_SMOD_JUMBO_ENA;
819
820 gma_write16(hw, port, GM_SERIAL_MODE, reg);
821
822 /* virtual address for data */
823 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
824
825 /* physical address: used for pause frames */
826 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
827
828 /* ignore counter overflows */
829 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
830 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
831 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
832
833 /* Configure Rx MAC FIFO */
834 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
835 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
836 if (hw->chip_id == CHIP_ID_YUKON_EX ||
837 hw->chip_id == CHIP_ID_YUKON_FE_P)
838 rx_reg |= GMF_RX_OVER_ON;
839
840 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
841
842 if (hw->chip_id == CHIP_ID_YUKON_XL) {
843 /* Hardware errata - clear flush mask */
844 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
845 } else {
846 /* Flush Rx MAC FIFO on any flow control or error */
847 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
848 }
849
850 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
851 reg = RX_GMF_FL_THR_DEF + 1;
852 /* Another magic mystery workaround from sk98lin */
853 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
854 hw->chip_rev == CHIP_REV_YU_FE2_A0)
855 reg = 0x178;
856 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
857
858 /* Configure Tx MAC FIFO */
859 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
860 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
861
862 /* On chips without ram buffer, pause is controled by MAC level */
863 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
864 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
865 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
866
867 sky2_set_tx_stfwd(hw, port);
868 }
869
870 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
871 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
872 /* disable dynamic watermark */
873 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
874 reg &= ~TX_DYN_WM_ENA;
875 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
876 }
877 }
878
879 /* Assign Ram Buffer allocation to queue */
880 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
881 {
882 u32 end;
883
884 /* convert from K bytes to qwords used for hw register */
885 start *= 1024/8;
886 space *= 1024/8;
887 end = start + space - 1;
888
889 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
890 sky2_write32(hw, RB_ADDR(q, RB_START), start);
891 sky2_write32(hw, RB_ADDR(q, RB_END), end);
892 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
893 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
894
895 if (q == Q_R1 || q == Q_R2) {
896 u32 tp = space - space/4;
897
898 /* On receive queue's set the thresholds
899 * give receiver priority when > 3/4 full
900 * send pause when down to 2K
901 */
902 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
903 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
904
905 tp = space - 2048/8;
906 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
907 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
908 } else {
909 /* Enable store & forward on Tx queue's because
910 * Tx FIFO is only 1K on Yukon
911 */
912 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
913 }
914
915 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
916 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
917 }
918
919 /* Setup Bus Memory Interface */
920 static void sky2_qset(struct sky2_hw *hw, u16 q)
921 {
922 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
923 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
924 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
925 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
926 }
927
928 /* Setup prefetch unit registers. This is the interface between
929 * hardware and driver list elements
930 */
931 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
932 u64 addr, u32 last)
933 {
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
935 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
936 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
937 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
938 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
939 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
940
941 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
942 }
943
944 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
945 {
946 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
947
948 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
949 le->ctrl = 0;
950 return le;
951 }
952
953 static void tx_init(struct sky2_port *sky2)
954 {
955 struct sky2_tx_le *le;
956
957 sky2->tx_prod = sky2->tx_cons = 0;
958 sky2->tx_tcpsum = 0;
959 sky2->tx_last_mss = 0;
960
961 le = get_tx_le(sky2);
962 le->addr = 0;
963 le->opcode = OP_ADDR64 | HW_OWNER;
964 }
965
966 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
967 struct sky2_tx_le *le)
968 {
969 return sky2->tx_ring + (le - sky2->tx_le);
970 }
971
972 /* Update chip's next pointer */
973 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
974 {
975 /* Make sure write' to descriptors are complete before we tell hardware */
976 wmb();
977 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
978
979 /* Synchronize I/O on since next processor may write to tail */
980 mmiowb();
981 }
982
983
984 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
985 {
986 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
987 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
988 le->ctrl = 0;
989 return le;
990 }
991
992 /* Build description to hardware for one receive segment */
993 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
994 dma_addr_t map, unsigned len)
995 {
996 struct sky2_rx_le *le;
997
998 if (sizeof(dma_addr_t) > sizeof(u32)) {
999 le = sky2_next_rx(sky2);
1000 le->addr = cpu_to_le32(upper_32_bits(map));
1001 le->opcode = OP_ADDR64 | HW_OWNER;
1002 }
1003
1004 le = sky2_next_rx(sky2);
1005 le->addr = cpu_to_le32((u32) map);
1006 le->length = cpu_to_le16(len);
1007 le->opcode = op | HW_OWNER;
1008 }
1009
1010 /* Build description to hardware for one possibly fragmented skb */
1011 static void sky2_rx_submit(struct sky2_port *sky2,
1012 const struct rx_ring_info *re)
1013 {
1014 int i;
1015
1016 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1017
1018 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1019 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1020 }
1021
1022
1023 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1024 unsigned size)
1025 {
1026 struct sk_buff *skb = re->skb;
1027 int i;
1028
1029 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1030 pci_unmap_len_set(re, data_size, size);
1031
1032 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1033 re->frag_addr[i] = pci_map_page(pdev,
1034 skb_shinfo(skb)->frags[i].page,
1035 skb_shinfo(skb)->frags[i].page_offset,
1036 skb_shinfo(skb)->frags[i].size,
1037 PCI_DMA_FROMDEVICE);
1038 }
1039
1040 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1041 {
1042 struct sk_buff *skb = re->skb;
1043 int i;
1044
1045 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1046 PCI_DMA_FROMDEVICE);
1047
1048 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1049 pci_unmap_page(pdev, re->frag_addr[i],
1050 skb_shinfo(skb)->frags[i].size,
1051 PCI_DMA_FROMDEVICE);
1052 }
1053
1054 /* Tell chip where to start receive checksum.
1055 * Actually has two checksums, but set both same to avoid possible byte
1056 * order problems.
1057 */
1058 static void rx_set_checksum(struct sky2_port *sky2)
1059 {
1060 struct sky2_rx_le *le = sky2_next_rx(sky2);
1061
1062 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1063 le->ctrl = 0;
1064 le->opcode = OP_TCPSTART | HW_OWNER;
1065
1066 sky2_write32(sky2->hw,
1067 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1068 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1069 }
1070
1071 /*
1072 * The RX Stop command will not work for Yukon-2 if the BMU does not
1073 * reach the end of packet and since we can't make sure that we have
1074 * incoming data, we must reset the BMU while it is not doing a DMA
1075 * transfer. Since it is possible that the RX path is still active,
1076 * the RX RAM buffer will be stopped first, so any possible incoming
1077 * data will not trigger a DMA. After the RAM buffer is stopped, the
1078 * BMU is polled until any DMA in progress is ended and only then it
1079 * will be reset.
1080 */
1081 static void sky2_rx_stop(struct sky2_port *sky2)
1082 {
1083 struct sky2_hw *hw = sky2->hw;
1084 unsigned rxq = rxqaddr[sky2->port];
1085 int i;
1086
1087 /* disable the RAM Buffer receive queue */
1088 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1089
1090 for (i = 0; i < 0xffff; i++)
1091 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1092 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1093 goto stopped;
1094
1095 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1096 sky2->netdev->name);
1097 stopped:
1098 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1099
1100 /* reset the Rx prefetch unit */
1101 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1102 mmiowb();
1103 }
1104
1105 /* Clean out receive buffer area, assumes receiver hardware stopped */
1106 static void sky2_rx_clean(struct sky2_port *sky2)
1107 {
1108 unsigned i;
1109
1110 memset(sky2->rx_le, 0, RX_LE_BYTES);
1111 for (i = 0; i < sky2->rx_pending; i++) {
1112 struct rx_ring_info *re = sky2->rx_ring + i;
1113
1114 if (re->skb) {
1115 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1116 kfree_skb(re->skb);
1117 re->skb = NULL;
1118 }
1119 }
1120 }
1121
1122 /* Basic MII support */
1123 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1124 {
1125 struct mii_ioctl_data *data = if_mii(ifr);
1126 struct sky2_port *sky2 = netdev_priv(dev);
1127 struct sky2_hw *hw = sky2->hw;
1128 int err = -EOPNOTSUPP;
1129
1130 if (!netif_running(dev))
1131 return -ENODEV; /* Phy still in reset */
1132
1133 switch (cmd) {
1134 case SIOCGMIIPHY:
1135 data->phy_id = PHY_ADDR_MARV;
1136
1137 /* fallthru */
1138 case SIOCGMIIREG: {
1139 u16 val = 0;
1140
1141 spin_lock_bh(&sky2->phy_lock);
1142 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1143 spin_unlock_bh(&sky2->phy_lock);
1144
1145 data->val_out = val;
1146 break;
1147 }
1148
1149 case SIOCSMIIREG:
1150 if (!capable(CAP_NET_ADMIN))
1151 return -EPERM;
1152
1153 spin_lock_bh(&sky2->phy_lock);
1154 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1155 data->val_in);
1156 spin_unlock_bh(&sky2->phy_lock);
1157 break;
1158 }
1159 return err;
1160 }
1161
1162 #ifdef SKY2_VLAN_TAG_USED
1163 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1164 {
1165 if (onoff) {
1166 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1167 RX_VLAN_STRIP_ON);
1168 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1169 TX_VLAN_TAG_ON);
1170 } else {
1171 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1172 RX_VLAN_STRIP_OFF);
1173 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1174 TX_VLAN_TAG_OFF);
1175 }
1176 }
1177
1178 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1179 {
1180 struct sky2_port *sky2 = netdev_priv(dev);
1181 struct sky2_hw *hw = sky2->hw;
1182 u16 port = sky2->port;
1183
1184 netif_tx_lock_bh(dev);
1185 napi_disable(&hw->napi);
1186
1187 sky2->vlgrp = grp;
1188 sky2_set_vlan_mode(hw, port, grp != NULL);
1189
1190 sky2_read32(hw, B0_Y2_SP_LISR);
1191 napi_enable(&hw->napi);
1192 netif_tx_unlock_bh(dev);
1193 }
1194 #endif
1195
1196 /*
1197 * Allocate an skb for receiving. If the MTU is large enough
1198 * make the skb non-linear with a fragment list of pages.
1199 */
1200 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1201 {
1202 struct sk_buff *skb;
1203 int i;
1204
1205 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1206 unsigned char *start;
1207 /*
1208 * Workaround for a bug in FIFO that cause hang
1209 * if the FIFO if the receive buffer is not 64 byte aligned.
1210 * The buffer returned from netdev_alloc_skb is
1211 * aligned except if slab debugging is enabled.
1212 */
1213 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1214 if (!skb)
1215 goto nomem;
1216 start = PTR_ALIGN(skb->data, 8);
1217 skb_reserve(skb, start - skb->data);
1218 } else {
1219 skb = netdev_alloc_skb(sky2->netdev,
1220 sky2->rx_data_size + NET_IP_ALIGN);
1221 if (!skb)
1222 goto nomem;
1223 skb_reserve(skb, NET_IP_ALIGN);
1224 }
1225
1226 for (i = 0; i < sky2->rx_nfrags; i++) {
1227 struct page *page = alloc_page(GFP_ATOMIC);
1228
1229 if (!page)
1230 goto free_partial;
1231 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1232 }
1233
1234 return skb;
1235 free_partial:
1236 kfree_skb(skb);
1237 nomem:
1238 return NULL;
1239 }
1240
1241 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1242 {
1243 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1244 }
1245
1246 /*
1247 * Allocate and setup receiver buffer pool.
1248 * Normal case this ends up creating one list element for skb
1249 * in the receive ring. Worst case if using large MTU and each
1250 * allocation falls on a different 64 bit region, that results
1251 * in 6 list elements per ring entry.
1252 * One element is used for checksum enable/disable, and one
1253 * extra to avoid wrap.
1254 */
1255 static int sky2_rx_start(struct sky2_port *sky2)
1256 {
1257 struct sky2_hw *hw = sky2->hw;
1258 struct rx_ring_info *re;
1259 unsigned rxq = rxqaddr[sky2->port];
1260 unsigned i, size, thresh;
1261
1262 sky2->rx_put = sky2->rx_next = 0;
1263 sky2_qset(hw, rxq);
1264
1265 /* On PCI express lowering the watermark gives better performance */
1266 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1267 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1268
1269 /* These chips have no ram buffer?
1270 * MAC Rx RAM Read is controlled by hardware */
1271 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1272 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1273 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1274 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1275
1276 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1277
1278 if (!(hw->flags & SKY2_HW_NEW_LE))
1279 rx_set_checksum(sky2);
1280
1281 /* Space needed for frame data + headers rounded up */
1282 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1283
1284 /* Stopping point for hardware truncation */
1285 thresh = (size - 8) / sizeof(u32);
1286
1287 sky2->rx_nfrags = size >> PAGE_SHIFT;
1288 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1289
1290 /* Compute residue after pages */
1291 size -= sky2->rx_nfrags << PAGE_SHIFT;
1292
1293 /* Optimize to handle small packets and headers */
1294 if (size < copybreak)
1295 size = copybreak;
1296 if (size < ETH_HLEN)
1297 size = ETH_HLEN;
1298
1299 sky2->rx_data_size = size;
1300
1301 /* Fill Rx ring */
1302 for (i = 0; i < sky2->rx_pending; i++) {
1303 re = sky2->rx_ring + i;
1304
1305 re->skb = sky2_rx_alloc(sky2);
1306 if (!re->skb)
1307 goto nomem;
1308
1309 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1310 sky2_rx_submit(sky2, re);
1311 }
1312
1313 /*
1314 * The receiver hangs if it receives frames larger than the
1315 * packet buffer. As a workaround, truncate oversize frames, but
1316 * the register is limited to 9 bits, so if you do frames > 2052
1317 * you better get the MTU right!
1318 */
1319 if (thresh > 0x1ff)
1320 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1321 else {
1322 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1323 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1324 }
1325
1326 /* Tell chip about available buffers */
1327 sky2_rx_update(sky2, rxq);
1328 return 0;
1329 nomem:
1330 sky2_rx_clean(sky2);
1331 return -ENOMEM;
1332 }
1333
1334 /* Bring up network interface. */
1335 static int sky2_up(struct net_device *dev)
1336 {
1337 struct sky2_port *sky2 = netdev_priv(dev);
1338 struct sky2_hw *hw = sky2->hw;
1339 unsigned port = sky2->port;
1340 u32 imask, ramsize;
1341 int cap, err = -ENOMEM;
1342 struct net_device *otherdev = hw->dev[sky2->port^1];
1343
1344 /*
1345 * On dual port PCI-X card, there is an problem where status
1346 * can be received out of order due to split transactions
1347 */
1348 if (otherdev && netif_running(otherdev) &&
1349 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1350 u16 cmd;
1351
1352 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1353 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1354 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1355
1356 }
1357
1358 if (netif_msg_ifup(sky2))
1359 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1360
1361 netif_carrier_off(dev);
1362
1363 /* must be power of 2 */
1364 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1365 TX_RING_SIZE *
1366 sizeof(struct sky2_tx_le),
1367 &sky2->tx_le_map);
1368 if (!sky2->tx_le)
1369 goto err_out;
1370
1371 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1372 GFP_KERNEL);
1373 if (!sky2->tx_ring)
1374 goto err_out;
1375
1376 tx_init(sky2);
1377
1378 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1379 &sky2->rx_le_map);
1380 if (!sky2->rx_le)
1381 goto err_out;
1382 memset(sky2->rx_le, 0, RX_LE_BYTES);
1383
1384 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1385 GFP_KERNEL);
1386 if (!sky2->rx_ring)
1387 goto err_out;
1388
1389 sky2_phy_power(hw, port, 1);
1390
1391 sky2_mac_init(hw, port);
1392
1393 /* Register is number of 4K blocks on internal RAM buffer. */
1394 ramsize = sky2_read8(hw, B2_E_0) * 4;
1395 if (ramsize > 0) {
1396 u32 rxspace;
1397
1398 hw->flags |= SKY2_HW_RAM_BUFFER;
1399 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1400 if (ramsize < 16)
1401 rxspace = ramsize / 2;
1402 else
1403 rxspace = 8 + (2*(ramsize - 16))/3;
1404
1405 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1406 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1407
1408 /* Make sure SyncQ is disabled */
1409 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1410 RB_RST_SET);
1411 }
1412
1413 sky2_qset(hw, txqaddr[port]);
1414
1415 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1416 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1417 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1418
1419 /* Set almost empty threshold */
1420 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1421 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1422 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1423
1424 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1425 TX_RING_SIZE - 1);
1426
1427 #ifdef SKY2_VLAN_TAG_USED
1428 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1429 #endif
1430
1431 err = sky2_rx_start(sky2);
1432 if (err)
1433 goto err_out;
1434
1435 /* Enable interrupts from phy/mac for port */
1436 imask = sky2_read32(hw, B0_IMSK);
1437 imask |= portirq_msk[port];
1438 sky2_write32(hw, B0_IMSK, imask);
1439
1440 sky2_set_multicast(dev);
1441 return 0;
1442
1443 err_out:
1444 if (sky2->rx_le) {
1445 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1446 sky2->rx_le, sky2->rx_le_map);
1447 sky2->rx_le = NULL;
1448 }
1449 if (sky2->tx_le) {
1450 pci_free_consistent(hw->pdev,
1451 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1452 sky2->tx_le, sky2->tx_le_map);
1453 sky2->tx_le = NULL;
1454 }
1455 kfree(sky2->tx_ring);
1456 kfree(sky2->rx_ring);
1457
1458 sky2->tx_ring = NULL;
1459 sky2->rx_ring = NULL;
1460 return err;
1461 }
1462
1463 /* Modular subtraction in ring */
1464 static inline int tx_dist(unsigned tail, unsigned head)
1465 {
1466 return (head - tail) & (TX_RING_SIZE - 1);
1467 }
1468
1469 /* Number of list elements available for next tx */
1470 static inline int tx_avail(const struct sky2_port *sky2)
1471 {
1472 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1473 }
1474
1475 /* Estimate of number of transmit list elements required */
1476 static unsigned tx_le_req(const struct sk_buff *skb)
1477 {
1478 unsigned count;
1479
1480 count = sizeof(dma_addr_t) / sizeof(u32);
1481 count += skb_shinfo(skb)->nr_frags * count;
1482
1483 if (skb_is_gso(skb))
1484 ++count;
1485
1486 if (skb->ip_summed == CHECKSUM_PARTIAL)
1487 ++count;
1488
1489 return count;
1490 }
1491
1492 /*
1493 * Put one packet in ring for transmit.
1494 * A single packet can generate multiple list elements, and
1495 * the number of ring elements will probably be less than the number
1496 * of list elements used.
1497 */
1498 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1499 {
1500 struct sky2_port *sky2 = netdev_priv(dev);
1501 struct sky2_hw *hw = sky2->hw;
1502 struct sky2_tx_le *le = NULL;
1503 struct tx_ring_info *re;
1504 unsigned i, len;
1505 dma_addr_t mapping;
1506 u16 mss;
1507 u8 ctrl;
1508
1509 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1510 return NETDEV_TX_BUSY;
1511
1512 if (unlikely(netif_msg_tx_queued(sky2)))
1513 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1514 dev->name, sky2->tx_prod, skb->len);
1515
1516 len = skb_headlen(skb);
1517 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1518
1519 /* Send high bits if needed */
1520 if (sizeof(dma_addr_t) > sizeof(u32)) {
1521 le = get_tx_le(sky2);
1522 le->addr = cpu_to_le32(upper_32_bits(mapping));
1523 le->opcode = OP_ADDR64 | HW_OWNER;
1524 }
1525
1526 /* Check for TCP Segmentation Offload */
1527 mss = skb_shinfo(skb)->gso_size;
1528 if (mss != 0) {
1529
1530 if (!(hw->flags & SKY2_HW_NEW_LE))
1531 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1532
1533 if (mss != sky2->tx_last_mss) {
1534 le = get_tx_le(sky2);
1535 le->addr = cpu_to_le32(mss);
1536
1537 if (hw->flags & SKY2_HW_NEW_LE)
1538 le->opcode = OP_MSS | HW_OWNER;
1539 else
1540 le->opcode = OP_LRGLEN | HW_OWNER;
1541 sky2->tx_last_mss = mss;
1542 }
1543 }
1544
1545 ctrl = 0;
1546 #ifdef SKY2_VLAN_TAG_USED
1547 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1548 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1549 if (!le) {
1550 le = get_tx_le(sky2);
1551 le->addr = 0;
1552 le->opcode = OP_VLAN|HW_OWNER;
1553 } else
1554 le->opcode |= OP_VLAN;
1555 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1556 ctrl |= INS_VLAN;
1557 }
1558 #endif
1559
1560 /* Handle TCP checksum offload */
1561 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1562 /* On Yukon EX (some versions) encoding change. */
1563 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1564 ctrl |= CALSUM; /* auto checksum */
1565 else {
1566 const unsigned offset = skb_transport_offset(skb);
1567 u32 tcpsum;
1568
1569 tcpsum = offset << 16; /* sum start */
1570 tcpsum |= offset + skb->csum_offset; /* sum write */
1571
1572 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1573 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1574 ctrl |= UDPTCP;
1575
1576 if (tcpsum != sky2->tx_tcpsum) {
1577 sky2->tx_tcpsum = tcpsum;
1578
1579 le = get_tx_le(sky2);
1580 le->addr = cpu_to_le32(tcpsum);
1581 le->length = 0; /* initial checksum value */
1582 le->ctrl = 1; /* one packet */
1583 le->opcode = OP_TCPLISW | HW_OWNER;
1584 }
1585 }
1586 }
1587
1588 le = get_tx_le(sky2);
1589 le->addr = cpu_to_le32((u32) mapping);
1590 le->length = cpu_to_le16(len);
1591 le->ctrl = ctrl;
1592 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1593
1594 re = tx_le_re(sky2, le);
1595 re->skb = skb;
1596 pci_unmap_addr_set(re, mapaddr, mapping);
1597 pci_unmap_len_set(re, maplen, len);
1598
1599 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1600 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1601
1602 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1603 frag->size, PCI_DMA_TODEVICE);
1604
1605 if (sizeof(dma_addr_t) > sizeof(u32)) {
1606 le = get_tx_le(sky2);
1607 le->addr = cpu_to_le32(upper_32_bits(mapping));
1608 le->ctrl = 0;
1609 le->opcode = OP_ADDR64 | HW_OWNER;
1610 }
1611
1612 le = get_tx_le(sky2);
1613 le->addr = cpu_to_le32((u32) mapping);
1614 le->length = cpu_to_le16(frag->size);
1615 le->ctrl = ctrl;
1616 le->opcode = OP_BUFFER | HW_OWNER;
1617
1618 re = tx_le_re(sky2, le);
1619 re->skb = skb;
1620 pci_unmap_addr_set(re, mapaddr, mapping);
1621 pci_unmap_len_set(re, maplen, frag->size);
1622 }
1623
1624 le->ctrl |= EOP;
1625
1626 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1627 netif_stop_queue(dev);
1628
1629 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1630
1631 dev->trans_start = jiffies;
1632 return NETDEV_TX_OK;
1633 }
1634
1635 /*
1636 * Free ring elements from starting at tx_cons until "done"
1637 *
1638 * NB: the hardware will tell us about partial completion of multi-part
1639 * buffers so make sure not to free skb to early.
1640 */
1641 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1642 {
1643 struct net_device *dev = sky2->netdev;
1644 struct pci_dev *pdev = sky2->hw->pdev;
1645 unsigned idx;
1646
1647 BUG_ON(done >= TX_RING_SIZE);
1648
1649 for (idx = sky2->tx_cons; idx != done;
1650 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1651 struct sky2_tx_le *le = sky2->tx_le + idx;
1652 struct tx_ring_info *re = sky2->tx_ring + idx;
1653
1654 switch(le->opcode & ~HW_OWNER) {
1655 case OP_LARGESEND:
1656 case OP_PACKET:
1657 pci_unmap_single(pdev,
1658 pci_unmap_addr(re, mapaddr),
1659 pci_unmap_len(re, maplen),
1660 PCI_DMA_TODEVICE);
1661 break;
1662 case OP_BUFFER:
1663 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1664 pci_unmap_len(re, maplen),
1665 PCI_DMA_TODEVICE);
1666 break;
1667 }
1668
1669 if (le->ctrl & EOP) {
1670 if (unlikely(netif_msg_tx_done(sky2)))
1671 printk(KERN_DEBUG "%s: tx done %u\n",
1672 dev->name, idx);
1673
1674 dev->stats.tx_packets++;
1675 dev->stats.tx_bytes += re->skb->len;
1676
1677 dev_kfree_skb_any(re->skb);
1678 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1679 }
1680 }
1681
1682 sky2->tx_cons = idx;
1683 smp_mb();
1684
1685 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1686 netif_wake_queue(dev);
1687 }
1688
1689 /* Cleanup all untransmitted buffers, assume transmitter not running */
1690 static void sky2_tx_clean(struct net_device *dev)
1691 {
1692 struct sky2_port *sky2 = netdev_priv(dev);
1693
1694 netif_tx_lock_bh(dev);
1695 sky2_tx_complete(sky2, sky2->tx_prod);
1696 netif_tx_unlock_bh(dev);
1697 }
1698
1699 /* Network shutdown */
1700 static int sky2_down(struct net_device *dev)
1701 {
1702 struct sky2_port *sky2 = netdev_priv(dev);
1703 struct sky2_hw *hw = sky2->hw;
1704 unsigned port = sky2->port;
1705 u16 ctrl;
1706 u32 imask;
1707
1708 /* Never really got started! */
1709 if (!sky2->tx_le)
1710 return 0;
1711
1712 if (netif_msg_ifdown(sky2))
1713 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1714
1715 /* Stop more packets from being queued */
1716 netif_stop_queue(dev);
1717
1718 /* Disable port IRQ */
1719 imask = sky2_read32(hw, B0_IMSK);
1720 imask &= ~portirq_msk[port];
1721 sky2_write32(hw, B0_IMSK, imask);
1722
1723 synchronize_irq(hw->pdev->irq);
1724
1725 sky2_gmac_reset(hw, port);
1726
1727 /* Stop transmitter */
1728 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1729 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1730
1731 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1732 RB_RST_SET | RB_DIS_OP_MD);
1733
1734 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1735 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1736 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1737
1738 /* Make sure no packets are pending */
1739 napi_synchronize(&hw->napi);
1740
1741 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1742
1743 /* Workaround shared GMAC reset */
1744 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1745 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1746 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1747
1748 /* Disable Force Sync bit and Enable Alloc bit */
1749 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1750 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1751
1752 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1753 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1754 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1755
1756 /* Reset the PCI FIFO of the async Tx queue */
1757 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1758 BMU_RST_SET | BMU_FIFO_RST);
1759
1760 /* Reset the Tx prefetch units */
1761 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1762 PREF_UNIT_RST_SET);
1763
1764 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1765
1766 sky2_rx_stop(sky2);
1767
1768 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1769 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1770
1771 sky2_phy_power(hw, port, 0);
1772
1773 netif_carrier_off(dev);
1774
1775 /* turn off LED's */
1776 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1777
1778 sky2_tx_clean(dev);
1779 sky2_rx_clean(sky2);
1780
1781 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1782 sky2->rx_le, sky2->rx_le_map);
1783 kfree(sky2->rx_ring);
1784
1785 pci_free_consistent(hw->pdev,
1786 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1787 sky2->tx_le, sky2->tx_le_map);
1788 kfree(sky2->tx_ring);
1789
1790 sky2->tx_le = NULL;
1791 sky2->rx_le = NULL;
1792
1793 sky2->rx_ring = NULL;
1794 sky2->tx_ring = NULL;
1795
1796 return 0;
1797 }
1798
1799 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1800 {
1801 if (hw->flags & SKY2_HW_FIBRE_PHY)
1802 return SPEED_1000;
1803
1804 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1805 if (aux & PHY_M_PS_SPEED_100)
1806 return SPEED_100;
1807 else
1808 return SPEED_10;
1809 }
1810
1811 switch (aux & PHY_M_PS_SPEED_MSK) {
1812 case PHY_M_PS_SPEED_1000:
1813 return SPEED_1000;
1814 case PHY_M_PS_SPEED_100:
1815 return SPEED_100;
1816 default:
1817 return SPEED_10;
1818 }
1819 }
1820
1821 static void sky2_link_up(struct sky2_port *sky2)
1822 {
1823 struct sky2_hw *hw = sky2->hw;
1824 unsigned port = sky2->port;
1825 u16 reg;
1826 static const char *fc_name[] = {
1827 [FC_NONE] = "none",
1828 [FC_TX] = "tx",
1829 [FC_RX] = "rx",
1830 [FC_BOTH] = "both",
1831 };
1832
1833 /* enable Rx/Tx */
1834 reg = gma_read16(hw, port, GM_GP_CTRL);
1835 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1836 gma_write16(hw, port, GM_GP_CTRL, reg);
1837
1838 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1839
1840 netif_carrier_on(sky2->netdev);
1841
1842 mod_timer(&hw->watchdog_timer, jiffies + 1);
1843
1844 /* Turn on link LED */
1845 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1846 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1847
1848 if (netif_msg_link(sky2))
1849 printk(KERN_INFO PFX
1850 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1851 sky2->netdev->name, sky2->speed,
1852 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1853 fc_name[sky2->flow_status]);
1854 }
1855
1856 static void sky2_link_down(struct sky2_port *sky2)
1857 {
1858 struct sky2_hw *hw = sky2->hw;
1859 unsigned port = sky2->port;
1860 u16 reg;
1861
1862 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1863
1864 reg = gma_read16(hw, port, GM_GP_CTRL);
1865 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1866 gma_write16(hw, port, GM_GP_CTRL, reg);
1867
1868 netif_carrier_off(sky2->netdev);
1869
1870 /* Turn on link LED */
1871 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1872
1873 if (netif_msg_link(sky2))
1874 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1875
1876 sky2_phy_init(hw, port);
1877 }
1878
1879 static enum flow_control sky2_flow(int rx, int tx)
1880 {
1881 if (rx)
1882 return tx ? FC_BOTH : FC_RX;
1883 else
1884 return tx ? FC_TX : FC_NONE;
1885 }
1886
1887 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1888 {
1889 struct sky2_hw *hw = sky2->hw;
1890 unsigned port = sky2->port;
1891 u16 advert, lpa;
1892
1893 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1894 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1895 if (lpa & PHY_M_AN_RF) {
1896 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1897 return -1;
1898 }
1899
1900 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1901 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1902 sky2->netdev->name);
1903 return -1;
1904 }
1905
1906 sky2->speed = sky2_phy_speed(hw, aux);
1907 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1908
1909 /* Since the pause result bits seem to in different positions on
1910 * different chips. look at registers.
1911 */
1912 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1913 /* Shift for bits in fiber PHY */
1914 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1915 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1916
1917 if (advert & ADVERTISE_1000XPAUSE)
1918 advert |= ADVERTISE_PAUSE_CAP;
1919 if (advert & ADVERTISE_1000XPSE_ASYM)
1920 advert |= ADVERTISE_PAUSE_ASYM;
1921 if (lpa & LPA_1000XPAUSE)
1922 lpa |= LPA_PAUSE_CAP;
1923 if (lpa & LPA_1000XPAUSE_ASYM)
1924 lpa |= LPA_PAUSE_ASYM;
1925 }
1926
1927 sky2->flow_status = FC_NONE;
1928 if (advert & ADVERTISE_PAUSE_CAP) {
1929 if (lpa & LPA_PAUSE_CAP)
1930 sky2->flow_status = FC_BOTH;
1931 else if (advert & ADVERTISE_PAUSE_ASYM)
1932 sky2->flow_status = FC_RX;
1933 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1934 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1935 sky2->flow_status = FC_TX;
1936 }
1937
1938 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1939 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1940 sky2->flow_status = FC_NONE;
1941
1942 if (sky2->flow_status & FC_TX)
1943 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1944 else
1945 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1946
1947 return 0;
1948 }
1949
1950 /* Interrupt from PHY */
1951 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1952 {
1953 struct net_device *dev = hw->dev[port];
1954 struct sky2_port *sky2 = netdev_priv(dev);
1955 u16 istatus, phystat;
1956
1957 if (!netif_running(dev))
1958 return;
1959
1960 spin_lock(&sky2->phy_lock);
1961 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1962 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1963
1964 if (netif_msg_intr(sky2))
1965 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1966 sky2->netdev->name, istatus, phystat);
1967
1968 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1969 if (sky2_autoneg_done(sky2, phystat) == 0)
1970 sky2_link_up(sky2);
1971 goto out;
1972 }
1973
1974 if (istatus & PHY_M_IS_LSP_CHANGE)
1975 sky2->speed = sky2_phy_speed(hw, phystat);
1976
1977 if (istatus & PHY_M_IS_DUP_CHANGE)
1978 sky2->duplex =
1979 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1980
1981 if (istatus & PHY_M_IS_LST_CHANGE) {
1982 if (phystat & PHY_M_PS_LINK_UP)
1983 sky2_link_up(sky2);
1984 else
1985 sky2_link_down(sky2);
1986 }
1987 out:
1988 spin_unlock(&sky2->phy_lock);
1989 }
1990
1991 /* Transmit timeout is only called if we are running, carrier is up
1992 * and tx queue is full (stopped).
1993 */
1994 static void sky2_tx_timeout(struct net_device *dev)
1995 {
1996 struct sky2_port *sky2 = netdev_priv(dev);
1997 struct sky2_hw *hw = sky2->hw;
1998
1999 if (netif_msg_timer(sky2))
2000 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2001
2002 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2003 dev->name, sky2->tx_cons, sky2->tx_prod,
2004 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2005 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2006
2007 /* can't restart safely under softirq */
2008 schedule_work(&hw->restart_work);
2009 }
2010
2011 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2012 {
2013 struct sky2_port *sky2 = netdev_priv(dev);
2014 struct sky2_hw *hw = sky2->hw;
2015 unsigned port = sky2->port;
2016 int err;
2017 u16 ctl, mode;
2018 u32 imask;
2019
2020 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2021 return -EINVAL;
2022
2023 if (new_mtu > ETH_DATA_LEN &&
2024 (hw->chip_id == CHIP_ID_YUKON_FE ||
2025 hw->chip_id == CHIP_ID_YUKON_FE_P))
2026 return -EINVAL;
2027
2028 if (!netif_running(dev)) {
2029 dev->mtu = new_mtu;
2030 return 0;
2031 }
2032
2033 imask = sky2_read32(hw, B0_IMSK);
2034 sky2_write32(hw, B0_IMSK, 0);
2035
2036 dev->trans_start = jiffies; /* prevent tx timeout */
2037 netif_stop_queue(dev);
2038 napi_disable(&hw->napi);
2039
2040 synchronize_irq(hw->pdev->irq);
2041
2042 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2043 sky2_set_tx_stfwd(hw, port);
2044
2045 ctl = gma_read16(hw, port, GM_GP_CTRL);
2046 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2047 sky2_rx_stop(sky2);
2048 sky2_rx_clean(sky2);
2049
2050 dev->mtu = new_mtu;
2051
2052 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2053 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2054
2055 if (dev->mtu > ETH_DATA_LEN)
2056 mode |= GM_SMOD_JUMBO_ENA;
2057
2058 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2059
2060 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2061
2062 err = sky2_rx_start(sky2);
2063 sky2_write32(hw, B0_IMSK, imask);
2064
2065 sky2_read32(hw, B0_Y2_SP_LISR);
2066 napi_enable(&hw->napi);
2067
2068 if (err)
2069 dev_close(dev);
2070 else {
2071 gma_write16(hw, port, GM_GP_CTRL, ctl);
2072
2073 netif_wake_queue(dev);
2074 }
2075
2076 return err;
2077 }
2078
2079 /* For small just reuse existing skb for next receive */
2080 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2081 const struct rx_ring_info *re,
2082 unsigned length)
2083 {
2084 struct sk_buff *skb;
2085
2086 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2087 if (likely(skb)) {
2088 skb_reserve(skb, 2);
2089 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2090 length, PCI_DMA_FROMDEVICE);
2091 skb_copy_from_linear_data(re->skb, skb->data, length);
2092 skb->ip_summed = re->skb->ip_summed;
2093 skb->csum = re->skb->csum;
2094 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2095 length, PCI_DMA_FROMDEVICE);
2096 re->skb->ip_summed = CHECKSUM_NONE;
2097 skb_put(skb, length);
2098 }
2099 return skb;
2100 }
2101
2102 /* Adjust length of skb with fragments to match received data */
2103 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2104 unsigned int length)
2105 {
2106 int i, num_frags;
2107 unsigned int size;
2108
2109 /* put header into skb */
2110 size = min(length, hdr_space);
2111 skb->tail += size;
2112 skb->len += size;
2113 length -= size;
2114
2115 num_frags = skb_shinfo(skb)->nr_frags;
2116 for (i = 0; i < num_frags; i++) {
2117 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2118
2119 if (length == 0) {
2120 /* don't need this page */
2121 __free_page(frag->page);
2122 --skb_shinfo(skb)->nr_frags;
2123 } else {
2124 size = min(length, (unsigned) PAGE_SIZE);
2125
2126 frag->size = size;
2127 skb->data_len += size;
2128 skb->truesize += size;
2129 skb->len += size;
2130 length -= size;
2131 }
2132 }
2133 }
2134
2135 /* Normal packet - take skb from ring element and put in a new one */
2136 static struct sk_buff *receive_new(struct sky2_port *sky2,
2137 struct rx_ring_info *re,
2138 unsigned int length)
2139 {
2140 struct sk_buff *skb, *nskb;
2141 unsigned hdr_space = sky2->rx_data_size;
2142
2143 /* Don't be tricky about reusing pages (yet) */
2144 nskb = sky2_rx_alloc(sky2);
2145 if (unlikely(!nskb))
2146 return NULL;
2147
2148 skb = re->skb;
2149 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2150
2151 prefetch(skb->data);
2152 re->skb = nskb;
2153 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2154
2155 if (skb_shinfo(skb)->nr_frags)
2156 skb_put_frags(skb, hdr_space, length);
2157 else
2158 skb_put(skb, length);
2159 return skb;
2160 }
2161
2162 /*
2163 * Receive one packet.
2164 * For larger packets, get new buffer.
2165 */
2166 static struct sk_buff *sky2_receive(struct net_device *dev,
2167 u16 length, u32 status)
2168 {
2169 struct sky2_port *sky2 = netdev_priv(dev);
2170 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2171 struct sk_buff *skb = NULL;
2172 u16 count = (status & GMR_FS_LEN) >> 16;
2173
2174 #ifdef SKY2_VLAN_TAG_USED
2175 /* Account for vlan tag */
2176 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2177 count -= VLAN_HLEN;
2178 #endif
2179
2180 if (unlikely(netif_msg_rx_status(sky2)))
2181 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2182 dev->name, sky2->rx_next, status, length);
2183
2184 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2185 prefetch(sky2->rx_ring + sky2->rx_next);
2186
2187 /* This chip has hardware problems that generates bogus status.
2188 * So do only marginal checking and expect higher level protocols
2189 * to handle crap frames.
2190 */
2191 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2192 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2193 length != count)
2194 goto okay;
2195
2196 if (status & GMR_FS_ANY_ERR)
2197 goto error;
2198
2199 if (!(status & GMR_FS_RX_OK))
2200 goto resubmit;
2201
2202 /* if length reported by DMA does not match PHY, packet was truncated */
2203 if (length != count)
2204 goto len_error;
2205
2206 okay:
2207 if (length < copybreak)
2208 skb = receive_copy(sky2, re, length);
2209 else
2210 skb = receive_new(sky2, re, length);
2211 resubmit:
2212 sky2_rx_submit(sky2, re);
2213
2214 return skb;
2215
2216 len_error:
2217 /* Truncation of overlength packets
2218 causes PHY length to not match MAC length */
2219 ++dev->stats.rx_length_errors;
2220 if (netif_msg_rx_err(sky2) && net_ratelimit())
2221 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2222 dev->name, status, length);
2223 goto resubmit;
2224
2225 error:
2226 ++dev->stats.rx_errors;
2227 if (status & GMR_FS_RX_FF_OV) {
2228 dev->stats.rx_over_errors++;
2229 goto resubmit;
2230 }
2231
2232 if (netif_msg_rx_err(sky2) && net_ratelimit())
2233 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2234 dev->name, status, length);
2235
2236 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2237 dev->stats.rx_length_errors++;
2238 if (status & GMR_FS_FRAGMENT)
2239 dev->stats.rx_frame_errors++;
2240 if (status & GMR_FS_CRC_ERR)
2241 dev->stats.rx_crc_errors++;
2242
2243 goto resubmit;
2244 }
2245
2246 /* Transmit complete */
2247 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2248 {
2249 struct sky2_port *sky2 = netdev_priv(dev);
2250
2251 if (netif_running(dev)) {
2252 netif_tx_lock(dev);
2253 sky2_tx_complete(sky2, last);
2254 netif_tx_unlock(dev);
2255 }
2256 }
2257
2258 /* Process status response ring */
2259 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2260 {
2261 int work_done = 0;
2262 unsigned rx[2] = { 0, 0 };
2263
2264 rmb();
2265 do {
2266 struct sky2_port *sky2;
2267 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2268 unsigned port;
2269 struct net_device *dev;
2270 struct sk_buff *skb;
2271 u32 status;
2272 u16 length;
2273 u8 opcode = le->opcode;
2274
2275 if (!(opcode & HW_OWNER))
2276 break;
2277
2278 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2279
2280 port = le->css & CSS_LINK_BIT;
2281 dev = hw->dev[port];
2282 sky2 = netdev_priv(dev);
2283 length = le16_to_cpu(le->length);
2284 status = le32_to_cpu(le->status);
2285
2286 le->opcode = 0;
2287 switch (opcode & ~HW_OWNER) {
2288 case OP_RXSTAT:
2289 ++rx[port];
2290 skb = sky2_receive(dev, length, status);
2291 if (unlikely(!skb)) {
2292 dev->stats.rx_dropped++;
2293 break;
2294 }
2295
2296 /* This chip reports checksum status differently */
2297 if (hw->flags & SKY2_HW_NEW_LE) {
2298 if (sky2->rx_csum &&
2299 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2300 (le->css & CSS_TCPUDPCSOK))
2301 skb->ip_summed = CHECKSUM_UNNECESSARY;
2302 else
2303 skb->ip_summed = CHECKSUM_NONE;
2304 }
2305
2306 skb->protocol = eth_type_trans(skb, dev);
2307 dev->stats.rx_packets++;
2308 dev->stats.rx_bytes += skb->len;
2309 dev->last_rx = jiffies;
2310
2311 #ifdef SKY2_VLAN_TAG_USED
2312 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2313 vlan_hwaccel_receive_skb(skb,
2314 sky2->vlgrp,
2315 be16_to_cpu(sky2->rx_tag));
2316 } else
2317 #endif
2318 netif_receive_skb(skb);
2319
2320 /* Stop after net poll weight */
2321 if (++work_done >= to_do)
2322 goto exit_loop;
2323 break;
2324
2325 #ifdef SKY2_VLAN_TAG_USED
2326 case OP_RXVLAN:
2327 sky2->rx_tag = length;
2328 break;
2329
2330 case OP_RXCHKSVLAN:
2331 sky2->rx_tag = length;
2332 /* fall through */
2333 #endif
2334 case OP_RXCHKS:
2335 if (!sky2->rx_csum)
2336 break;
2337
2338 /* If this happens then driver assuming wrong format */
2339 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2340 if (net_ratelimit())
2341 printk(KERN_NOTICE "%s: unexpected"
2342 " checksum status\n",
2343 dev->name);
2344 break;
2345 }
2346
2347 /* Both checksum counters are programmed to start at
2348 * the same offset, so unless there is a problem they
2349 * should match. This failure is an early indication that
2350 * hardware receive checksumming won't work.
2351 */
2352 if (likely(status >> 16 == (status & 0xffff))) {
2353 skb = sky2->rx_ring[sky2->rx_next].skb;
2354 skb->ip_summed = CHECKSUM_COMPLETE;
2355 skb->csum = status & 0xffff;
2356 } else {
2357 printk(KERN_NOTICE PFX "%s: hardware receive "
2358 "checksum problem (status = %#x)\n",
2359 dev->name, status);
2360 sky2->rx_csum = 0;
2361 sky2_write32(sky2->hw,
2362 Q_ADDR(rxqaddr[port], Q_CSR),
2363 BMU_DIS_RX_CHKSUM);
2364 }
2365 break;
2366
2367 case OP_TXINDEXLE:
2368 /* TX index reports status for both ports */
2369 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2370 sky2_tx_done(hw->dev[0], status & 0xfff);
2371 if (hw->dev[1])
2372 sky2_tx_done(hw->dev[1],
2373 ((status >> 24) & 0xff)
2374 | (u16)(length & 0xf) << 8);
2375 break;
2376
2377 default:
2378 if (net_ratelimit())
2379 printk(KERN_WARNING PFX
2380 "unknown status opcode 0x%x\n", opcode);
2381 }
2382 } while (hw->st_idx != idx);
2383
2384 /* Fully processed status ring so clear irq */
2385 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2386
2387 exit_loop:
2388 if (rx[0])
2389 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2390
2391 if (rx[1])
2392 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2393
2394 return work_done;
2395 }
2396
2397 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2398 {
2399 struct net_device *dev = hw->dev[port];
2400
2401 if (net_ratelimit())
2402 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2403 dev->name, status);
2404
2405 if (status & Y2_IS_PAR_RD1) {
2406 if (net_ratelimit())
2407 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2408 dev->name);
2409 /* Clear IRQ */
2410 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2411 }
2412
2413 if (status & Y2_IS_PAR_WR1) {
2414 if (net_ratelimit())
2415 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2416 dev->name);
2417
2418 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2419 }
2420
2421 if (status & Y2_IS_PAR_MAC1) {
2422 if (net_ratelimit())
2423 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2424 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2425 }
2426
2427 if (status & Y2_IS_PAR_RX1) {
2428 if (net_ratelimit())
2429 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2430 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2431 }
2432
2433 if (status & Y2_IS_TCP_TXA1) {
2434 if (net_ratelimit())
2435 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2436 dev->name);
2437 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2438 }
2439 }
2440
2441 static void sky2_hw_intr(struct sky2_hw *hw)
2442 {
2443 struct pci_dev *pdev = hw->pdev;
2444 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2445 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2446
2447 status &= hwmsk;
2448
2449 if (status & Y2_IS_TIST_OV)
2450 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2451
2452 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2453 u16 pci_err;
2454
2455 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2456 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2457 if (net_ratelimit())
2458 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2459 pci_err);
2460
2461 sky2_pci_write16(hw, PCI_STATUS,
2462 pci_err | PCI_STATUS_ERROR_BITS);
2463 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2464 }
2465
2466 if (status & Y2_IS_PCI_EXP) {
2467 /* PCI-Express uncorrectable Error occurred */
2468 u32 err;
2469
2470 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2471 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2472 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2473 0xfffffffful);
2474 if (net_ratelimit())
2475 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2476
2477 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2478 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2479 }
2480
2481 if (status & Y2_HWE_L1_MASK)
2482 sky2_hw_error(hw, 0, status);
2483 status >>= 8;
2484 if (status & Y2_HWE_L1_MASK)
2485 sky2_hw_error(hw, 1, status);
2486 }
2487
2488 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2489 {
2490 struct net_device *dev = hw->dev[port];
2491 struct sky2_port *sky2 = netdev_priv(dev);
2492 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2493
2494 if (netif_msg_intr(sky2))
2495 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2496 dev->name, status);
2497
2498 if (status & GM_IS_RX_CO_OV)
2499 gma_read16(hw, port, GM_RX_IRQ_SRC);
2500
2501 if (status & GM_IS_TX_CO_OV)
2502 gma_read16(hw, port, GM_TX_IRQ_SRC);
2503
2504 if (status & GM_IS_RX_FF_OR) {
2505 ++dev->stats.rx_fifo_errors;
2506 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2507 }
2508
2509 if (status & GM_IS_TX_FF_UR) {
2510 ++dev->stats.tx_fifo_errors;
2511 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2512 }
2513 }
2514
2515 /* This should never happen it is a bug. */
2516 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2517 u16 q, unsigned ring_size)
2518 {
2519 struct net_device *dev = hw->dev[port];
2520 struct sky2_port *sky2 = netdev_priv(dev);
2521 unsigned idx;
2522 const u64 *le = (q == Q_R1 || q == Q_R2)
2523 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2524
2525 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2526 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2527 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2528 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2529
2530 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2531 }
2532
2533 static int sky2_rx_hung(struct net_device *dev)
2534 {
2535 struct sky2_port *sky2 = netdev_priv(dev);
2536 struct sky2_hw *hw = sky2->hw;
2537 unsigned port = sky2->port;
2538 unsigned rxq = rxqaddr[port];
2539 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2540 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2541 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2542 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2543
2544 /* If idle and MAC or PCI is stuck */
2545 if (sky2->check.last == dev->last_rx &&
2546 ((mac_rp == sky2->check.mac_rp &&
2547 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2548 /* Check if the PCI RX hang */
2549 (fifo_rp == sky2->check.fifo_rp &&
2550 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2551 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2552 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2553 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2554 return 1;
2555 } else {
2556 sky2->check.last = dev->last_rx;
2557 sky2->check.mac_rp = mac_rp;
2558 sky2->check.mac_lev = mac_lev;
2559 sky2->check.fifo_rp = fifo_rp;
2560 sky2->check.fifo_lev = fifo_lev;
2561 return 0;
2562 }
2563 }
2564
2565 static void sky2_watchdog(unsigned long arg)
2566 {
2567 struct sky2_hw *hw = (struct sky2_hw *) arg;
2568
2569 /* Check for lost IRQ once a second */
2570 if (sky2_read32(hw, B0_ISRC)) {
2571 napi_schedule(&hw->napi);
2572 } else {
2573 int i, active = 0;
2574
2575 for (i = 0; i < hw->ports; i++) {
2576 struct net_device *dev = hw->dev[i];
2577 if (!netif_running(dev))
2578 continue;
2579 ++active;
2580
2581 /* For chips with Rx FIFO, check if stuck */
2582 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2583 sky2_rx_hung(dev)) {
2584 pr_info(PFX "%s: receiver hang detected\n",
2585 dev->name);
2586 schedule_work(&hw->restart_work);
2587 return;
2588 }
2589 }
2590
2591 if (active == 0)
2592 return;
2593 }
2594
2595 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2596 }
2597
2598 /* Hardware/software error handling */
2599 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2600 {
2601 if (net_ratelimit())
2602 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2603
2604 if (status & Y2_IS_HW_ERR)
2605 sky2_hw_intr(hw);
2606
2607 if (status & Y2_IS_IRQ_MAC1)
2608 sky2_mac_intr(hw, 0);
2609
2610 if (status & Y2_IS_IRQ_MAC2)
2611 sky2_mac_intr(hw, 1);
2612
2613 if (status & Y2_IS_CHK_RX1)
2614 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2615
2616 if (status & Y2_IS_CHK_RX2)
2617 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2618
2619 if (status & Y2_IS_CHK_TXA1)
2620 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2621
2622 if (status & Y2_IS_CHK_TXA2)
2623 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2624 }
2625
2626 static int sky2_poll(struct napi_struct *napi, int work_limit)
2627 {
2628 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2629 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2630 int work_done = 0;
2631 u16 idx;
2632
2633 if (unlikely(status & Y2_IS_ERROR))
2634 sky2_err_intr(hw, status);
2635
2636 if (status & Y2_IS_IRQ_PHY1)
2637 sky2_phy_intr(hw, 0);
2638
2639 if (status & Y2_IS_IRQ_PHY2)
2640 sky2_phy_intr(hw, 1);
2641
2642 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2643 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2644
2645 if (work_done >= work_limit)
2646 goto done;
2647 }
2648
2649 /* Bug/Errata workaround?
2650 * Need to kick the TX irq moderation timer.
2651 */
2652 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2653 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2654 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2655 }
2656 napi_complete(napi);
2657 sky2_read32(hw, B0_Y2_SP_LISR);
2658 done:
2659
2660 return work_done;
2661 }
2662
2663 static irqreturn_t sky2_intr(int irq, void *dev_id)
2664 {
2665 struct sky2_hw *hw = dev_id;
2666 u32 status;
2667
2668 /* Reading this mask interrupts as side effect */
2669 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2670 if (status == 0 || status == ~0)
2671 return IRQ_NONE;
2672
2673 prefetch(&hw->st_le[hw->st_idx]);
2674
2675 napi_schedule(&hw->napi);
2676
2677 return IRQ_HANDLED;
2678 }
2679
2680 #ifdef CONFIG_NET_POLL_CONTROLLER
2681 static void sky2_netpoll(struct net_device *dev)
2682 {
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684
2685 napi_schedule(&sky2->hw->napi);
2686 }
2687 #endif
2688
2689 /* Chip internal frequency for clock calculations */
2690 static u32 sky2_mhz(const struct sky2_hw *hw)
2691 {
2692 switch (hw->chip_id) {
2693 case CHIP_ID_YUKON_EC:
2694 case CHIP_ID_YUKON_EC_U:
2695 case CHIP_ID_YUKON_EX:
2696 case CHIP_ID_YUKON_SUPR:
2697 return 125;
2698
2699 case CHIP_ID_YUKON_FE:
2700 return 100;
2701
2702 case CHIP_ID_YUKON_FE_P:
2703 return 50;
2704
2705 case CHIP_ID_YUKON_XL:
2706 return 156;
2707
2708 default:
2709 BUG();
2710 }
2711 }
2712
2713 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2714 {
2715 return sky2_mhz(hw) * us;
2716 }
2717
2718 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2719 {
2720 return clk / sky2_mhz(hw);
2721 }
2722
2723
2724 static int __devinit sky2_init(struct sky2_hw *hw)
2725 {
2726 u8 t8;
2727
2728 /* Enable all clocks and check for bad PCI access */
2729 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2730
2731 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2732
2733 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2734 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2735
2736 switch(hw->chip_id) {
2737 case CHIP_ID_YUKON_XL:
2738 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2739 break;
2740
2741 case CHIP_ID_YUKON_EC_U:
2742 hw->flags = SKY2_HW_GIGABIT
2743 | SKY2_HW_NEWER_PHY
2744 | SKY2_HW_ADV_POWER_CTL;
2745 break;
2746
2747 case CHIP_ID_YUKON_EX:
2748 hw->flags = SKY2_HW_GIGABIT
2749 | SKY2_HW_NEWER_PHY
2750 | SKY2_HW_NEW_LE
2751 | SKY2_HW_ADV_POWER_CTL;
2752
2753 /* New transmit checksum */
2754 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2755 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2756 break;
2757
2758 case CHIP_ID_YUKON_EC:
2759 /* This rev is really old, and requires untested workarounds */
2760 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2761 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2762 return -EOPNOTSUPP;
2763 }
2764 hw->flags = SKY2_HW_GIGABIT;
2765 break;
2766
2767 case CHIP_ID_YUKON_FE:
2768 break;
2769
2770 case CHIP_ID_YUKON_FE_P:
2771 hw->flags = SKY2_HW_NEWER_PHY
2772 | SKY2_HW_NEW_LE
2773 | SKY2_HW_AUTO_TX_SUM
2774 | SKY2_HW_ADV_POWER_CTL;
2775 break;
2776
2777 case CHIP_ID_YUKON_SUPR:
2778 hw->flags = SKY2_HW_GIGABIT
2779 | SKY2_HW_NEWER_PHY
2780 | SKY2_HW_NEW_LE
2781 | SKY2_HW_AUTO_TX_SUM
2782 | SKY2_HW_ADV_POWER_CTL;
2783 break;
2784
2785 default:
2786 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2787 hw->chip_id);
2788 return -EOPNOTSUPP;
2789 }
2790
2791 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2792 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2793 hw->flags |= SKY2_HW_FIBRE_PHY;
2794
2795
2796 hw->ports = 1;
2797 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2798 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2799 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2800 ++hw->ports;
2801 }
2802
2803 return 0;
2804 }
2805
2806 static void sky2_reset(struct sky2_hw *hw)
2807 {
2808 struct pci_dev *pdev = hw->pdev;
2809 u16 status;
2810 int i, cap;
2811 u32 hwe_mask = Y2_HWE_ALL_MASK;
2812
2813 /* disable ASF */
2814 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2815 status = sky2_read16(hw, HCU_CCSR);
2816 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2817 HCU_CCSR_UC_STATE_MSK);
2818 sky2_write16(hw, HCU_CCSR, status);
2819 } else
2820 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2821 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2822
2823 /* do a SW reset */
2824 sky2_write8(hw, B0_CTST, CS_RST_SET);
2825 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2826
2827 /* allow writes to PCI config */
2828 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2829
2830 /* clear PCI errors, if any */
2831 status = sky2_pci_read16(hw, PCI_STATUS);
2832 status |= PCI_STATUS_ERROR_BITS;
2833 sky2_pci_write16(hw, PCI_STATUS, status);
2834
2835 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2836
2837 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2838 if (cap) {
2839 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2840 0xfffffffful);
2841
2842 /* If error bit is stuck on ignore it */
2843 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2844 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2845 else
2846 hwe_mask |= Y2_IS_PCI_EXP;
2847 }
2848
2849 sky2_power_on(hw);
2850 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2851
2852 for (i = 0; i < hw->ports; i++) {
2853 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2854 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2855
2856 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2857 hw->chip_id == CHIP_ID_YUKON_SUPR)
2858 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2859 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2860 | GMC_BYP_RETR_ON);
2861 }
2862
2863 /* Clear I2C IRQ noise */
2864 sky2_write32(hw, B2_I2C_IRQ, 1);
2865
2866 /* turn off hardware timer (unused) */
2867 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2868 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2869
2870 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2871
2872 /* Turn off descriptor polling */
2873 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2874
2875 /* Turn off receive timestamp */
2876 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2877 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2878
2879 /* enable the Tx Arbiters */
2880 for (i = 0; i < hw->ports; i++)
2881 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2882
2883 /* Initialize ram interface */
2884 for (i = 0; i < hw->ports; i++) {
2885 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2886
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2888 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2889 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2890 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2891 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2892 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2893 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2894 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2895 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2896 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2897 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2898 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2899 }
2900
2901 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2902
2903 for (i = 0; i < hw->ports; i++)
2904 sky2_gmac_reset(hw, i);
2905
2906 memset(hw->st_le, 0, STATUS_LE_BYTES);
2907 hw->st_idx = 0;
2908
2909 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2910 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2911
2912 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2913 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2914
2915 /* Set the list last index */
2916 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2917
2918 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2919 sky2_write8(hw, STAT_FIFO_WM, 16);
2920
2921 /* set Status-FIFO ISR watermark */
2922 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2923 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2924 else
2925 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2926
2927 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2928 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2929 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2930
2931 /* enable status unit */
2932 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2933
2934 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2935 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2936 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2937 }
2938
2939 static void sky2_restart(struct work_struct *work)
2940 {
2941 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2942 struct net_device *dev;
2943 int i, err;
2944
2945 rtnl_lock();
2946 for (i = 0; i < hw->ports; i++) {
2947 dev = hw->dev[i];
2948 if (netif_running(dev))
2949 sky2_down(dev);
2950 }
2951
2952 napi_disable(&hw->napi);
2953 sky2_write32(hw, B0_IMSK, 0);
2954 sky2_reset(hw);
2955 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2956 napi_enable(&hw->napi);
2957
2958 for (i = 0; i < hw->ports; i++) {
2959 dev = hw->dev[i];
2960 if (netif_running(dev)) {
2961 err = sky2_up(dev);
2962 if (err) {
2963 printk(KERN_INFO PFX "%s: could not restart %d\n",
2964 dev->name, err);
2965 dev_close(dev);
2966 }
2967 }
2968 }
2969
2970 rtnl_unlock();
2971 }
2972
2973 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2974 {
2975 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2976 }
2977
2978 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2979 {
2980 const struct sky2_port *sky2 = netdev_priv(dev);
2981
2982 wol->supported = sky2_wol_supported(sky2->hw);
2983 wol->wolopts = sky2->wol;
2984 }
2985
2986 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2987 {
2988 struct sky2_port *sky2 = netdev_priv(dev);
2989 struct sky2_hw *hw = sky2->hw;
2990
2991 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2992 return -EOPNOTSUPP;
2993
2994 sky2->wol = wol->wolopts;
2995
2996 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2997 hw->chip_id == CHIP_ID_YUKON_EX ||
2998 hw->chip_id == CHIP_ID_YUKON_FE_P)
2999 sky2_write32(hw, B0_CTST, sky2->wol
3000 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3001
3002 if (!netif_running(dev))
3003 sky2_wol_init(sky2);
3004 return 0;
3005 }
3006
3007 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3008 {
3009 if (sky2_is_copper(hw)) {
3010 u32 modes = SUPPORTED_10baseT_Half
3011 | SUPPORTED_10baseT_Full
3012 | SUPPORTED_100baseT_Half
3013 | SUPPORTED_100baseT_Full
3014 | SUPPORTED_Autoneg | SUPPORTED_TP;
3015
3016 if (hw->flags & SKY2_HW_GIGABIT)
3017 modes |= SUPPORTED_1000baseT_Half
3018 | SUPPORTED_1000baseT_Full;
3019 return modes;
3020 } else
3021 return SUPPORTED_1000baseT_Half
3022 | SUPPORTED_1000baseT_Full
3023 | SUPPORTED_Autoneg
3024 | SUPPORTED_FIBRE;
3025 }
3026
3027 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3028 {
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
3031
3032 ecmd->transceiver = XCVR_INTERNAL;
3033 ecmd->supported = sky2_supported_modes(hw);
3034 ecmd->phy_address = PHY_ADDR_MARV;
3035 if (sky2_is_copper(hw)) {
3036 ecmd->port = PORT_TP;
3037 ecmd->speed = sky2->speed;
3038 } else {
3039 ecmd->speed = SPEED_1000;
3040 ecmd->port = PORT_FIBRE;
3041 }
3042
3043 ecmd->advertising = sky2->advertising;
3044 ecmd->autoneg = sky2->autoneg;
3045 ecmd->duplex = sky2->duplex;
3046 return 0;
3047 }
3048
3049 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3050 {
3051 struct sky2_port *sky2 = netdev_priv(dev);
3052 const struct sky2_hw *hw = sky2->hw;
3053 u32 supported = sky2_supported_modes(hw);
3054
3055 if (ecmd->autoneg == AUTONEG_ENABLE) {
3056 ecmd->advertising = supported;
3057 sky2->duplex = -1;
3058 sky2->speed = -1;
3059 } else {
3060 u32 setting;
3061
3062 switch (ecmd->speed) {
3063 case SPEED_1000:
3064 if (ecmd->duplex == DUPLEX_FULL)
3065 setting = SUPPORTED_1000baseT_Full;
3066 else if (ecmd->duplex == DUPLEX_HALF)
3067 setting = SUPPORTED_1000baseT_Half;
3068 else
3069 return -EINVAL;
3070 break;
3071 case SPEED_100:
3072 if (ecmd->duplex == DUPLEX_FULL)
3073 setting = SUPPORTED_100baseT_Full;
3074 else if (ecmd->duplex == DUPLEX_HALF)
3075 setting = SUPPORTED_100baseT_Half;
3076 else
3077 return -EINVAL;
3078 break;
3079
3080 case SPEED_10:
3081 if (ecmd->duplex == DUPLEX_FULL)
3082 setting = SUPPORTED_10baseT_Full;
3083 else if (ecmd->duplex == DUPLEX_HALF)
3084 setting = SUPPORTED_10baseT_Half;
3085 else
3086 return -EINVAL;
3087 break;
3088 default:
3089 return -EINVAL;
3090 }
3091
3092 if ((setting & supported) == 0)
3093 return -EINVAL;
3094
3095 sky2->speed = ecmd->speed;
3096 sky2->duplex = ecmd->duplex;
3097 }
3098
3099 sky2->autoneg = ecmd->autoneg;
3100 sky2->advertising = ecmd->advertising;
3101
3102 if (netif_running(dev)) {
3103 sky2_phy_reinit(sky2);
3104 sky2_set_multicast(dev);
3105 }
3106
3107 return 0;
3108 }
3109
3110 static void sky2_get_drvinfo(struct net_device *dev,
3111 struct ethtool_drvinfo *info)
3112 {
3113 struct sky2_port *sky2 = netdev_priv(dev);
3114
3115 strcpy(info->driver, DRV_NAME);
3116 strcpy(info->version, DRV_VERSION);
3117 strcpy(info->fw_version, "N/A");
3118 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3119 }
3120
3121 static const struct sky2_stat {
3122 char name[ETH_GSTRING_LEN];
3123 u16 offset;
3124 } sky2_stats[] = {
3125 { "tx_bytes", GM_TXO_OK_HI },
3126 { "rx_bytes", GM_RXO_OK_HI },
3127 { "tx_broadcast", GM_TXF_BC_OK },
3128 { "rx_broadcast", GM_RXF_BC_OK },
3129 { "tx_multicast", GM_TXF_MC_OK },
3130 { "rx_multicast", GM_RXF_MC_OK },
3131 { "tx_unicast", GM_TXF_UC_OK },
3132 { "rx_unicast", GM_RXF_UC_OK },
3133 { "tx_mac_pause", GM_TXF_MPAUSE },
3134 { "rx_mac_pause", GM_RXF_MPAUSE },
3135 { "collisions", GM_TXF_COL },
3136 { "late_collision",GM_TXF_LAT_COL },
3137 { "aborted", GM_TXF_ABO_COL },
3138 { "single_collisions", GM_TXF_SNG_COL },
3139 { "multi_collisions", GM_TXF_MUL_COL },
3140
3141 { "rx_short", GM_RXF_SHT },
3142 { "rx_runt", GM_RXE_FRAG },
3143 { "rx_64_byte_packets", GM_RXF_64B },
3144 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3145 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3146 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3147 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3148 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3149 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3150 { "rx_too_long", GM_RXF_LNG_ERR },
3151 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3152 { "rx_jabber", GM_RXF_JAB_PKT },
3153 { "rx_fcs_error", GM_RXF_FCS_ERR },
3154
3155 { "tx_64_byte_packets", GM_TXF_64B },
3156 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3157 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3158 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3159 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3160 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3161 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3162 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3163 };
3164
3165 static u32 sky2_get_rx_csum(struct net_device *dev)
3166 {
3167 struct sky2_port *sky2 = netdev_priv(dev);
3168
3169 return sky2->rx_csum;
3170 }
3171
3172 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3173 {
3174 struct sky2_port *sky2 = netdev_priv(dev);
3175
3176 sky2->rx_csum = data;
3177
3178 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3179 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3180
3181 return 0;
3182 }
3183
3184 static u32 sky2_get_msglevel(struct net_device *netdev)
3185 {
3186 struct sky2_port *sky2 = netdev_priv(netdev);
3187 return sky2->msg_enable;
3188 }
3189
3190 static int sky2_nway_reset(struct net_device *dev)
3191 {
3192 struct sky2_port *sky2 = netdev_priv(dev);
3193
3194 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3195 return -EINVAL;
3196
3197 sky2_phy_reinit(sky2);
3198 sky2_set_multicast(dev);
3199
3200 return 0;
3201 }
3202
3203 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3204 {
3205 struct sky2_hw *hw = sky2->hw;
3206 unsigned port = sky2->port;
3207 int i;
3208
3209 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3210 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3211 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3212 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3213
3214 for (i = 2; i < count; i++)
3215 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3216 }
3217
3218 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3219 {
3220 struct sky2_port *sky2 = netdev_priv(netdev);
3221 sky2->msg_enable = value;
3222 }
3223
3224 static int sky2_get_sset_count(struct net_device *dev, int sset)
3225 {
3226 switch (sset) {
3227 case ETH_SS_STATS:
3228 return ARRAY_SIZE(sky2_stats);
3229 default:
3230 return -EOPNOTSUPP;
3231 }
3232 }
3233
3234 static void sky2_get_ethtool_stats(struct net_device *dev,
3235 struct ethtool_stats *stats, u64 * data)
3236 {
3237 struct sky2_port *sky2 = netdev_priv(dev);
3238
3239 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3240 }
3241
3242 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3243 {
3244 int i;
3245
3246 switch (stringset) {
3247 case ETH_SS_STATS:
3248 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3249 memcpy(data + i * ETH_GSTRING_LEN,
3250 sky2_stats[i].name, ETH_GSTRING_LEN);
3251 break;
3252 }
3253 }
3254
3255 static int sky2_set_mac_address(struct net_device *dev, void *p)
3256 {
3257 struct sky2_port *sky2 = netdev_priv(dev);
3258 struct sky2_hw *hw = sky2->hw;
3259 unsigned port = sky2->port;
3260 const struct sockaddr *addr = p;
3261
3262 if (!is_valid_ether_addr(addr->sa_data))
3263 return -EADDRNOTAVAIL;
3264
3265 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3266 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3267 dev->dev_addr, ETH_ALEN);
3268 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3269 dev->dev_addr, ETH_ALEN);
3270
3271 /* virtual address for data */
3272 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3273
3274 /* physical address: used for pause frames */
3275 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3276
3277 return 0;
3278 }
3279
3280 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3281 {
3282 u32 bit;
3283
3284 bit = ether_crc(ETH_ALEN, addr) & 63;
3285 filter[bit >> 3] |= 1 << (bit & 7);
3286 }
3287
3288 static void sky2_set_multicast(struct net_device *dev)
3289 {
3290 struct sky2_port *sky2 = netdev_priv(dev);
3291 struct sky2_hw *hw = sky2->hw;
3292 unsigned port = sky2->port;
3293 struct dev_mc_list *list = dev->mc_list;
3294 u16 reg;
3295 u8 filter[8];
3296 int rx_pause;
3297 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3298
3299 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3300 memset(filter, 0, sizeof(filter));
3301
3302 reg = gma_read16(hw, port, GM_RX_CTRL);
3303 reg |= GM_RXCR_UCF_ENA;
3304
3305 if (dev->flags & IFF_PROMISC) /* promiscuous */
3306 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3307 else if (dev->flags & IFF_ALLMULTI)
3308 memset(filter, 0xff, sizeof(filter));
3309 else if (dev->mc_count == 0 && !rx_pause)
3310 reg &= ~GM_RXCR_MCF_ENA;
3311 else {
3312 int i;
3313 reg |= GM_RXCR_MCF_ENA;
3314
3315 if (rx_pause)
3316 sky2_add_filter(filter, pause_mc_addr);
3317
3318 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3319 sky2_add_filter(filter, list->dmi_addr);
3320 }
3321
3322 gma_write16(hw, port, GM_MC_ADDR_H1,
3323 (u16) filter[0] | ((u16) filter[1] << 8));
3324 gma_write16(hw, port, GM_MC_ADDR_H2,
3325 (u16) filter[2] | ((u16) filter[3] << 8));
3326 gma_write16(hw, port, GM_MC_ADDR_H3,
3327 (u16) filter[4] | ((u16) filter[5] << 8));
3328 gma_write16(hw, port, GM_MC_ADDR_H4,
3329 (u16) filter[6] | ((u16) filter[7] << 8));
3330
3331 gma_write16(hw, port, GM_RX_CTRL, reg);
3332 }
3333
3334 /* Can have one global because blinking is controlled by
3335 * ethtool and that is always under RTNL mutex
3336 */
3337 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3338 {
3339 struct sky2_hw *hw = sky2->hw;
3340 unsigned port = sky2->port;
3341
3342 spin_lock_bh(&sky2->phy_lock);
3343 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3344 hw->chip_id == CHIP_ID_YUKON_EX ||
3345 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3346 u16 pg;
3347 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3349
3350 switch (mode) {
3351 case MO_LED_OFF:
3352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3353 PHY_M_LEDC_LOS_CTRL(8) |
3354 PHY_M_LEDC_INIT_CTRL(8) |
3355 PHY_M_LEDC_STA1_CTRL(8) |
3356 PHY_M_LEDC_STA0_CTRL(8));
3357 break;
3358 case MO_LED_ON:
3359 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3360 PHY_M_LEDC_LOS_CTRL(9) |
3361 PHY_M_LEDC_INIT_CTRL(9) |
3362 PHY_M_LEDC_STA1_CTRL(9) |
3363 PHY_M_LEDC_STA0_CTRL(9));
3364 break;
3365 case MO_LED_BLINK:
3366 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3367 PHY_M_LEDC_LOS_CTRL(0xa) |
3368 PHY_M_LEDC_INIT_CTRL(0xa) |
3369 PHY_M_LEDC_STA1_CTRL(0xa) |
3370 PHY_M_LEDC_STA0_CTRL(0xa));
3371 break;
3372 case MO_LED_NORM:
3373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3374 PHY_M_LEDC_LOS_CTRL(1) |
3375 PHY_M_LEDC_INIT_CTRL(8) |
3376 PHY_M_LEDC_STA1_CTRL(7) |
3377 PHY_M_LEDC_STA0_CTRL(7));
3378 }
3379
3380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3381 } else
3382 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3383 PHY_M_LED_MO_DUP(mode) |
3384 PHY_M_LED_MO_10(mode) |
3385 PHY_M_LED_MO_100(mode) |
3386 PHY_M_LED_MO_1000(mode) |
3387 PHY_M_LED_MO_RX(mode) |
3388 PHY_M_LED_MO_TX(mode));
3389
3390 spin_unlock_bh(&sky2->phy_lock);
3391 }
3392
3393 /* blink LED's for finding board */
3394 static int sky2_phys_id(struct net_device *dev, u32 data)
3395 {
3396 struct sky2_port *sky2 = netdev_priv(dev);
3397 unsigned int i;
3398
3399 if (data == 0)
3400 data = UINT_MAX;
3401
3402 for (i = 0; i < data; i++) {
3403 sky2_led(sky2, MO_LED_ON);
3404 if (msleep_interruptible(500))
3405 break;
3406 sky2_led(sky2, MO_LED_OFF);
3407 if (msleep_interruptible(500))
3408 break;
3409 }
3410 sky2_led(sky2, MO_LED_NORM);
3411
3412 return 0;
3413 }
3414
3415 static void sky2_get_pauseparam(struct net_device *dev,
3416 struct ethtool_pauseparam *ecmd)
3417 {
3418 struct sky2_port *sky2 = netdev_priv(dev);
3419
3420 switch (sky2->flow_mode) {
3421 case FC_NONE:
3422 ecmd->tx_pause = ecmd->rx_pause = 0;
3423 break;
3424 case FC_TX:
3425 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3426 break;
3427 case FC_RX:
3428 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3429 break;
3430 case FC_BOTH:
3431 ecmd->tx_pause = ecmd->rx_pause = 1;
3432 }
3433
3434 ecmd->autoneg = sky2->autoneg;
3435 }
3436
3437 static int sky2_set_pauseparam(struct net_device *dev,
3438 struct ethtool_pauseparam *ecmd)
3439 {
3440 struct sky2_port *sky2 = netdev_priv(dev);
3441
3442 sky2->autoneg = ecmd->autoneg;
3443 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3444
3445 if (netif_running(dev))
3446 sky2_phy_reinit(sky2);
3447
3448 return 0;
3449 }
3450
3451 static int sky2_get_coalesce(struct net_device *dev,
3452 struct ethtool_coalesce *ecmd)
3453 {
3454 struct sky2_port *sky2 = netdev_priv(dev);
3455 struct sky2_hw *hw = sky2->hw;
3456
3457 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3458 ecmd->tx_coalesce_usecs = 0;
3459 else {
3460 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3461 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3462 }
3463 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3464
3465 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3466 ecmd->rx_coalesce_usecs = 0;
3467 else {
3468 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3469 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3470 }
3471 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3472
3473 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3474 ecmd->rx_coalesce_usecs_irq = 0;
3475 else {
3476 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3477 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3478 }
3479
3480 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3481
3482 return 0;
3483 }
3484
3485 /* Note: this affect both ports */
3486 static int sky2_set_coalesce(struct net_device *dev,
3487 struct ethtool_coalesce *ecmd)
3488 {
3489 struct sky2_port *sky2 = netdev_priv(dev);
3490 struct sky2_hw *hw = sky2->hw;
3491 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3492
3493 if (ecmd->tx_coalesce_usecs > tmax ||
3494 ecmd->rx_coalesce_usecs > tmax ||
3495 ecmd->rx_coalesce_usecs_irq > tmax)
3496 return -EINVAL;
3497
3498 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3499 return -EINVAL;
3500 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3501 return -EINVAL;
3502 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3503 return -EINVAL;
3504
3505 if (ecmd->tx_coalesce_usecs == 0)
3506 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3507 else {
3508 sky2_write32(hw, STAT_TX_TIMER_INI,
3509 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3510 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3511 }
3512 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3513
3514 if (ecmd->rx_coalesce_usecs == 0)
3515 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3516 else {
3517 sky2_write32(hw, STAT_LEV_TIMER_INI,
3518 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3519 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3520 }
3521 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3522
3523 if (ecmd->rx_coalesce_usecs_irq == 0)
3524 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3525 else {
3526 sky2_write32(hw, STAT_ISR_TIMER_INI,
3527 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3528 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3529 }
3530 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3531 return 0;
3532 }
3533
3534 static void sky2_get_ringparam(struct net_device *dev,
3535 struct ethtool_ringparam *ering)
3536 {
3537 struct sky2_port *sky2 = netdev_priv(dev);
3538
3539 ering->rx_max_pending = RX_MAX_PENDING;
3540 ering->rx_mini_max_pending = 0;
3541 ering->rx_jumbo_max_pending = 0;
3542 ering->tx_max_pending = TX_RING_SIZE - 1;
3543
3544 ering->rx_pending = sky2->rx_pending;
3545 ering->rx_mini_pending = 0;
3546 ering->rx_jumbo_pending = 0;
3547 ering->tx_pending = sky2->tx_pending;
3548 }
3549
3550 static int sky2_set_ringparam(struct net_device *dev,
3551 struct ethtool_ringparam *ering)
3552 {
3553 struct sky2_port *sky2 = netdev_priv(dev);
3554 int err = 0;
3555
3556 if (ering->rx_pending > RX_MAX_PENDING ||
3557 ering->rx_pending < 8 ||
3558 ering->tx_pending < MAX_SKB_TX_LE ||
3559 ering->tx_pending > TX_RING_SIZE - 1)
3560 return -EINVAL;
3561
3562 if (netif_running(dev))
3563 sky2_down(dev);
3564
3565 sky2->rx_pending = ering->rx_pending;
3566 sky2->tx_pending = ering->tx_pending;
3567
3568 if (netif_running(dev)) {
3569 err = sky2_up(dev);
3570 if (err)
3571 dev_close(dev);
3572 }
3573
3574 return err;
3575 }
3576
3577 static int sky2_get_regs_len(struct net_device *dev)
3578 {
3579 return 0x4000;
3580 }
3581
3582 /*
3583 * Returns copy of control register region
3584 * Note: ethtool_get_regs always provides full size (16k) buffer
3585 */
3586 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3587 void *p)
3588 {
3589 const struct sky2_port *sky2 = netdev_priv(dev);
3590 const void __iomem *io = sky2->hw->regs;
3591 unsigned int b;
3592
3593 regs->version = 1;
3594
3595 for (b = 0; b < 128; b++) {
3596 /* This complicated switch statement is to make sure and
3597 * only access regions that are unreserved.
3598 * Some blocks are only valid on dual port cards.
3599 * and block 3 has some special diagnostic registers that
3600 * are poison.
3601 */
3602 switch (b) {
3603 case 3:
3604 /* skip diagnostic ram region */
3605 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3606 break;
3607
3608 /* dual port cards only */
3609 case 5: /* Tx Arbiter 2 */
3610 case 9: /* RX2 */
3611 case 14 ... 15: /* TX2 */
3612 case 17: case 19: /* Ram Buffer 2 */
3613 case 22 ... 23: /* Tx Ram Buffer 2 */
3614 case 25: /* Rx MAC Fifo 1 */
3615 case 27: /* Tx MAC Fifo 2 */
3616 case 31: /* GPHY 2 */
3617 case 40 ... 47: /* Pattern Ram 2 */
3618 case 52: case 54: /* TCP Segmentation 2 */
3619 case 112 ... 116: /* GMAC 2 */
3620 if (sky2->hw->ports == 1)
3621 goto reserved;
3622 /* fall through */
3623 case 0: /* Control */
3624 case 2: /* Mac address */
3625 case 4: /* Tx Arbiter 1 */
3626 case 7: /* PCI express reg */
3627 case 8: /* RX1 */
3628 case 12 ... 13: /* TX1 */
3629 case 16: case 18:/* Rx Ram Buffer 1 */
3630 case 20 ... 21: /* Tx Ram Buffer 1 */
3631 case 24: /* Rx MAC Fifo 1 */
3632 case 26: /* Tx MAC Fifo 1 */
3633 case 28 ... 29: /* Descriptor and status unit */
3634 case 30: /* GPHY 1*/
3635 case 32 ... 39: /* Pattern Ram 1 */
3636 case 48: case 50: /* TCP Segmentation 1 */
3637 case 56 ... 60: /* PCI space */
3638 case 80 ... 84: /* GMAC 1 */
3639 memcpy_fromio(p, io, 128);
3640 break;
3641 default:
3642 reserved:
3643 memset(p, 0, 128);
3644 }
3645
3646 p += 128;
3647 io += 128;
3648 }
3649 }
3650
3651 /* In order to do Jumbo packets on these chips, need to turn off the
3652 * transmit store/forward. Therefore checksum offload won't work.
3653 */
3654 static int no_tx_offload(struct net_device *dev)
3655 {
3656 const struct sky2_port *sky2 = netdev_priv(dev);
3657 const struct sky2_hw *hw = sky2->hw;
3658
3659 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3660 }
3661
3662 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3663 {
3664 if (data && no_tx_offload(dev))
3665 return -EINVAL;
3666
3667 return ethtool_op_set_tx_csum(dev, data);
3668 }
3669
3670
3671 static int sky2_set_tso(struct net_device *dev, u32 data)
3672 {
3673 if (data && no_tx_offload(dev))
3674 return -EINVAL;
3675
3676 return ethtool_op_set_tso(dev, data);
3677 }
3678
3679 static int sky2_get_eeprom_len(struct net_device *dev)
3680 {
3681 struct sky2_port *sky2 = netdev_priv(dev);
3682 struct sky2_hw *hw = sky2->hw;
3683 u16 reg2;
3684
3685 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3686 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3687 }
3688
3689 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3690 {
3691 u32 val;
3692
3693 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3694
3695 do {
3696 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3697 } while (!(offset & PCI_VPD_ADDR_F));
3698
3699 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3700 return val;
3701 }
3702
3703 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3704 {
3705 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3706 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3707 do {
3708 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3709 } while (offset & PCI_VPD_ADDR_F);
3710 }
3711
3712 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3713 u8 *data)
3714 {
3715 struct sky2_port *sky2 = netdev_priv(dev);
3716 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3717 int length = eeprom->len;
3718 u16 offset = eeprom->offset;
3719
3720 if (!cap)
3721 return -EINVAL;
3722
3723 eeprom->magic = SKY2_EEPROM_MAGIC;
3724
3725 while (length > 0) {
3726 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3727 int n = min_t(int, length, sizeof(val));
3728
3729 memcpy(data, &val, n);
3730 length -= n;
3731 data += n;
3732 offset += n;
3733 }
3734 return 0;
3735 }
3736
3737 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3738 u8 *data)
3739 {
3740 struct sky2_port *sky2 = netdev_priv(dev);
3741 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3742 int length = eeprom->len;
3743 u16 offset = eeprom->offset;
3744
3745 if (!cap)
3746 return -EINVAL;
3747
3748 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3749 return -EINVAL;
3750
3751 while (length > 0) {
3752 u32 val;
3753 int n = min_t(int, length, sizeof(val));
3754
3755 if (n < sizeof(val))
3756 val = sky2_vpd_read(sky2->hw, cap, offset);
3757 memcpy(&val, data, n);
3758
3759 sky2_vpd_write(sky2->hw, cap, offset, val);
3760
3761 length -= n;
3762 data += n;
3763 offset += n;
3764 }
3765 return 0;
3766 }
3767
3768
3769 static const struct ethtool_ops sky2_ethtool_ops = {
3770 .get_settings = sky2_get_settings,
3771 .set_settings = sky2_set_settings,
3772 .get_drvinfo = sky2_get_drvinfo,
3773 .get_wol = sky2_get_wol,
3774 .set_wol = sky2_set_wol,
3775 .get_msglevel = sky2_get_msglevel,
3776 .set_msglevel = sky2_set_msglevel,
3777 .nway_reset = sky2_nway_reset,
3778 .get_regs_len = sky2_get_regs_len,
3779 .get_regs = sky2_get_regs,
3780 .get_link = ethtool_op_get_link,
3781 .get_eeprom_len = sky2_get_eeprom_len,
3782 .get_eeprom = sky2_get_eeprom,
3783 .set_eeprom = sky2_set_eeprom,
3784 .set_sg = ethtool_op_set_sg,
3785 .set_tx_csum = sky2_set_tx_csum,
3786 .set_tso = sky2_set_tso,
3787 .get_rx_csum = sky2_get_rx_csum,
3788 .set_rx_csum = sky2_set_rx_csum,
3789 .get_strings = sky2_get_strings,
3790 .get_coalesce = sky2_get_coalesce,
3791 .set_coalesce = sky2_set_coalesce,
3792 .get_ringparam = sky2_get_ringparam,
3793 .set_ringparam = sky2_set_ringparam,
3794 .get_pauseparam = sky2_get_pauseparam,
3795 .set_pauseparam = sky2_set_pauseparam,
3796 .phys_id = sky2_phys_id,
3797 .get_sset_count = sky2_get_sset_count,
3798 .get_ethtool_stats = sky2_get_ethtool_stats,
3799 };
3800
3801 #ifdef CONFIG_SKY2_DEBUG
3802
3803 static struct dentry *sky2_debug;
3804
3805 static int sky2_debug_show(struct seq_file *seq, void *v)
3806 {
3807 struct net_device *dev = seq->private;
3808 const struct sky2_port *sky2 = netdev_priv(dev);
3809 struct sky2_hw *hw = sky2->hw;
3810 unsigned port = sky2->port;
3811 unsigned idx, last;
3812 int sop;
3813
3814 if (!netif_running(dev))
3815 return -ENETDOWN;
3816
3817 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3818 sky2_read32(hw, B0_ISRC),
3819 sky2_read32(hw, B0_IMSK),
3820 sky2_read32(hw, B0_Y2_SP_ICR));
3821
3822 napi_disable(&hw->napi);
3823 last = sky2_read16(hw, STAT_PUT_IDX);
3824
3825 if (hw->st_idx == last)
3826 seq_puts(seq, "Status ring (empty)\n");
3827 else {
3828 seq_puts(seq, "Status ring\n");
3829 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3830 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3831 const struct sky2_status_le *le = hw->st_le + idx;
3832 seq_printf(seq, "[%d] %#x %d %#x\n",
3833 idx, le->opcode, le->length, le->status);
3834 }
3835 seq_puts(seq, "\n");
3836 }
3837
3838 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3839 sky2->tx_cons, sky2->tx_prod,
3840 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3841 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3842
3843 /* Dump contents of tx ring */
3844 sop = 1;
3845 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3846 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3847 const struct sky2_tx_le *le = sky2->tx_le + idx;
3848 u32 a = le32_to_cpu(le->addr);
3849
3850 if (sop)
3851 seq_printf(seq, "%u:", idx);
3852 sop = 0;
3853
3854 switch(le->opcode & ~HW_OWNER) {
3855 case OP_ADDR64:
3856 seq_printf(seq, " %#x:", a);
3857 break;
3858 case OP_LRGLEN:
3859 seq_printf(seq, " mtu=%d", a);
3860 break;
3861 case OP_VLAN:
3862 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3863 break;
3864 case OP_TCPLISW:
3865 seq_printf(seq, " csum=%#x", a);
3866 break;
3867 case OP_LARGESEND:
3868 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3869 break;
3870 case OP_PACKET:
3871 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3872 break;
3873 case OP_BUFFER:
3874 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3875 break;
3876 default:
3877 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3878 a, le16_to_cpu(le->length));
3879 }
3880
3881 if (le->ctrl & EOP) {
3882 seq_putc(seq, '\n');
3883 sop = 1;
3884 }
3885 }
3886
3887 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3888 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3889 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3890 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3891
3892 sky2_read32(hw, B0_Y2_SP_LISR);
3893 napi_enable(&hw->napi);
3894 return 0;
3895 }
3896
3897 static int sky2_debug_open(struct inode *inode, struct file *file)
3898 {
3899 return single_open(file, sky2_debug_show, inode->i_private);
3900 }
3901
3902 static const struct file_operations sky2_debug_fops = {
3903 .owner = THIS_MODULE,
3904 .open = sky2_debug_open,
3905 .read = seq_read,
3906 .llseek = seq_lseek,
3907 .release = single_release,
3908 };
3909
3910 /*
3911 * Use network device events to create/remove/rename
3912 * debugfs file entries
3913 */
3914 static int sky2_device_event(struct notifier_block *unused,
3915 unsigned long event, void *ptr)
3916 {
3917 struct net_device *dev = ptr;
3918 struct sky2_port *sky2 = netdev_priv(dev);
3919
3920 if (dev->open != sky2_up || !sky2_debug)
3921 return NOTIFY_DONE;
3922
3923 switch(event) {
3924 case NETDEV_CHANGENAME:
3925 if (sky2->debugfs) {
3926 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3927 sky2_debug, dev->name);
3928 }
3929 break;
3930
3931 case NETDEV_GOING_DOWN:
3932 if (sky2->debugfs) {
3933 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3934 dev->name);
3935 debugfs_remove(sky2->debugfs);
3936 sky2->debugfs = NULL;
3937 }
3938 break;
3939
3940 case NETDEV_UP:
3941 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3942 sky2_debug, dev,
3943 &sky2_debug_fops);
3944 if (IS_ERR(sky2->debugfs))
3945 sky2->debugfs = NULL;
3946 }
3947
3948 return NOTIFY_DONE;
3949 }
3950
3951 static struct notifier_block sky2_notifier = {
3952 .notifier_call = sky2_device_event,
3953 };
3954
3955
3956 static __init void sky2_debug_init(void)
3957 {
3958 struct dentry *ent;
3959
3960 ent = debugfs_create_dir("sky2", NULL);
3961 if (!ent || IS_ERR(ent))
3962 return;
3963
3964 sky2_debug = ent;
3965 register_netdevice_notifier(&sky2_notifier);
3966 }
3967
3968 static __exit void sky2_debug_cleanup(void)
3969 {
3970 if (sky2_debug) {
3971 unregister_netdevice_notifier(&sky2_notifier);
3972 debugfs_remove(sky2_debug);
3973 sky2_debug = NULL;
3974 }
3975 }
3976
3977 #else
3978 #define sky2_debug_init()
3979 #define sky2_debug_cleanup()
3980 #endif
3981
3982
3983 /* Initialize network device */
3984 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3985 unsigned port,
3986 int highmem, int wol)
3987 {
3988 struct sky2_port *sky2;
3989 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3990
3991 if (!dev) {
3992 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3993 return NULL;
3994 }
3995
3996 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3997 dev->irq = hw->pdev->irq;
3998 dev->open = sky2_up;
3999 dev->stop = sky2_down;
4000 dev->do_ioctl = sky2_ioctl;
4001 dev->hard_start_xmit = sky2_xmit_frame;
4002 dev->set_multicast_list = sky2_set_multicast;
4003 dev->set_mac_address = sky2_set_mac_address;
4004 dev->change_mtu = sky2_change_mtu;
4005 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4006 dev->tx_timeout = sky2_tx_timeout;
4007 dev->watchdog_timeo = TX_WATCHDOG;
4008 #ifdef CONFIG_NET_POLL_CONTROLLER
4009 if (port == 0)
4010 dev->poll_controller = sky2_netpoll;
4011 #endif
4012
4013 sky2 = netdev_priv(dev);
4014 sky2->netdev = dev;
4015 sky2->hw = hw;
4016 sky2->msg_enable = netif_msg_init(debug, default_msg);
4017
4018 /* Auto speed and flow control */
4019 sky2->autoneg = AUTONEG_ENABLE;
4020 sky2->flow_mode = FC_BOTH;
4021
4022 sky2->duplex = -1;
4023 sky2->speed = -1;
4024 sky2->advertising = sky2_supported_modes(hw);
4025 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4026 sky2->wol = wol;
4027
4028 spin_lock_init(&sky2->phy_lock);
4029 sky2->tx_pending = TX_DEF_PENDING;
4030 sky2->rx_pending = RX_DEF_PENDING;
4031
4032 hw->dev[port] = dev;
4033
4034 sky2->port = port;
4035
4036 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4037 if (highmem)
4038 dev->features |= NETIF_F_HIGHDMA;
4039
4040 #ifdef SKY2_VLAN_TAG_USED
4041 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4042 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4043 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4044 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4045 dev->vlan_rx_register = sky2_vlan_rx_register;
4046 }
4047 #endif
4048
4049 /* read the mac address */
4050 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4051 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4052
4053 return dev;
4054 }
4055
4056 static void __devinit sky2_show_addr(struct net_device *dev)
4057 {
4058 const struct sky2_port *sky2 = netdev_priv(dev);
4059 DECLARE_MAC_BUF(mac);
4060
4061 if (netif_msg_probe(sky2))
4062 printk(KERN_INFO PFX "%s: addr %s\n",
4063 dev->name, print_mac(mac, dev->dev_addr));
4064 }
4065
4066 /* Handle software interrupt used during MSI test */
4067 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4068 {
4069 struct sky2_hw *hw = dev_id;
4070 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4071
4072 if (status == 0)
4073 return IRQ_NONE;
4074
4075 if (status & Y2_IS_IRQ_SW) {
4076 hw->flags |= SKY2_HW_USE_MSI;
4077 wake_up(&hw->msi_wait);
4078 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4079 }
4080 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4081
4082 return IRQ_HANDLED;
4083 }
4084
4085 /* Test interrupt path by forcing a a software IRQ */
4086 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4087 {
4088 struct pci_dev *pdev = hw->pdev;
4089 int err;
4090
4091 init_waitqueue_head (&hw->msi_wait);
4092
4093 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4094
4095 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4096 if (err) {
4097 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4098 return err;
4099 }
4100
4101 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4102 sky2_read8(hw, B0_CTST);
4103
4104 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4105
4106 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4107 /* MSI test failed, go back to INTx mode */
4108 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4109 "switching to INTx mode.\n");
4110
4111 err = -EOPNOTSUPP;
4112 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4113 }
4114
4115 sky2_write32(hw, B0_IMSK, 0);
4116 sky2_read32(hw, B0_IMSK);
4117
4118 free_irq(pdev->irq, hw);
4119
4120 return err;
4121 }
4122
4123 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4124 {
4125 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4126 u16 value;
4127
4128 if (!pm)
4129 return 0;
4130 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4131 return 0;
4132 return value & PCI_PM_CTRL_PME_ENABLE;
4133 }
4134
4135 static int __devinit sky2_probe(struct pci_dev *pdev,
4136 const struct pci_device_id *ent)
4137 {
4138 struct net_device *dev;
4139 struct sky2_hw *hw;
4140 int err, using_dac = 0, wol_default;
4141
4142 err = pci_enable_device(pdev);
4143 if (err) {
4144 dev_err(&pdev->dev, "cannot enable PCI device\n");
4145 goto err_out;
4146 }
4147
4148 err = pci_request_regions(pdev, DRV_NAME);
4149 if (err) {
4150 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4151 goto err_out_disable;
4152 }
4153
4154 pci_set_master(pdev);
4155
4156 if (sizeof(dma_addr_t) > sizeof(u32) &&
4157 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4158 using_dac = 1;
4159 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4160 if (err < 0) {
4161 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4162 "for consistent allocations\n");
4163 goto err_out_free_regions;
4164 }
4165 } else {
4166 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4167 if (err) {
4168 dev_err(&pdev->dev, "no usable DMA configuration\n");
4169 goto err_out_free_regions;
4170 }
4171 }
4172
4173 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4174
4175 err = -ENOMEM;
4176 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4177 if (!hw) {
4178 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4179 goto err_out_free_regions;
4180 }
4181
4182 hw->pdev = pdev;
4183
4184 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4185 if (!hw->regs) {
4186 dev_err(&pdev->dev, "cannot map device registers\n");
4187 goto err_out_free_hw;
4188 }
4189
4190 #ifdef __BIG_ENDIAN
4191 /* The sk98lin vendor driver uses hardware byte swapping but
4192 * this driver uses software swapping.
4193 */
4194 {
4195 u32 reg;
4196 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4197 reg &= ~PCI_REV_DESC;
4198 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4199 }
4200 #endif
4201
4202 /* ring for status responses */
4203 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4204 if (!hw->st_le)
4205 goto err_out_iounmap;
4206
4207 err = sky2_init(hw);
4208 if (err)
4209 goto err_out_iounmap;
4210
4211 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4212 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4213 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4214 hw->chip_id, hw->chip_rev);
4215
4216 sky2_reset(hw);
4217
4218 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4219 if (!dev) {
4220 err = -ENOMEM;
4221 goto err_out_free_pci;
4222 }
4223
4224 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4225 err = sky2_test_msi(hw);
4226 if (err == -EOPNOTSUPP)
4227 pci_disable_msi(pdev);
4228 else if (err)
4229 goto err_out_free_netdev;
4230 }
4231
4232 err = register_netdev(dev);
4233 if (err) {
4234 dev_err(&pdev->dev, "cannot register net device\n");
4235 goto err_out_free_netdev;
4236 }
4237
4238 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4239
4240 err = request_irq(pdev->irq, sky2_intr,
4241 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4242 dev->name, hw);
4243 if (err) {
4244 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4245 goto err_out_unregister;
4246 }
4247 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4248 napi_enable(&hw->napi);
4249
4250 sky2_show_addr(dev);
4251
4252 if (hw->ports > 1) {
4253 struct net_device *dev1;
4254
4255 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4256 if (!dev1)
4257 dev_warn(&pdev->dev, "allocation for second device failed\n");
4258 else if ((err = register_netdev(dev1))) {
4259 dev_warn(&pdev->dev,
4260 "register of second port failed (%d)\n", err);
4261 hw->dev[1] = NULL;
4262 free_netdev(dev1);
4263 } else
4264 sky2_show_addr(dev1);
4265 }
4266
4267 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4268 INIT_WORK(&hw->restart_work, sky2_restart);
4269
4270 pci_set_drvdata(pdev, hw);
4271
4272 return 0;
4273
4274 err_out_unregister:
4275 if (hw->flags & SKY2_HW_USE_MSI)
4276 pci_disable_msi(pdev);
4277 unregister_netdev(dev);
4278 err_out_free_netdev:
4279 free_netdev(dev);
4280 err_out_free_pci:
4281 sky2_write8(hw, B0_CTST, CS_RST_SET);
4282 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4283 err_out_iounmap:
4284 iounmap(hw->regs);
4285 err_out_free_hw:
4286 kfree(hw);
4287 err_out_free_regions:
4288 pci_release_regions(pdev);
4289 err_out_disable:
4290 pci_disable_device(pdev);
4291 err_out:
4292 pci_set_drvdata(pdev, NULL);
4293 return err;
4294 }
4295
4296 static void __devexit sky2_remove(struct pci_dev *pdev)
4297 {
4298 struct sky2_hw *hw = pci_get_drvdata(pdev);
4299 int i;
4300
4301 if (!hw)
4302 return;
4303
4304 del_timer_sync(&hw->watchdog_timer);
4305 cancel_work_sync(&hw->restart_work);
4306
4307 for (i = hw->ports-1; i >= 0; --i)
4308 unregister_netdev(hw->dev[i]);
4309
4310 sky2_write32(hw, B0_IMSK, 0);
4311
4312 sky2_power_aux(hw);
4313
4314 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4315 sky2_write8(hw, B0_CTST, CS_RST_SET);
4316 sky2_read8(hw, B0_CTST);
4317
4318 free_irq(pdev->irq, hw);
4319 if (hw->flags & SKY2_HW_USE_MSI)
4320 pci_disable_msi(pdev);
4321 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4322 pci_release_regions(pdev);
4323 pci_disable_device(pdev);
4324
4325 for (i = hw->ports-1; i >= 0; --i)
4326 free_netdev(hw->dev[i]);
4327
4328 iounmap(hw->regs);
4329 kfree(hw);
4330
4331 pci_set_drvdata(pdev, NULL);
4332 }
4333
4334 #ifdef CONFIG_PM
4335 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4336 {
4337 struct sky2_hw *hw = pci_get_drvdata(pdev);
4338 int i, wol = 0;
4339
4340 if (!hw)
4341 return 0;
4342
4343 del_timer_sync(&hw->watchdog_timer);
4344 cancel_work_sync(&hw->restart_work);
4345
4346 for (i = 0; i < hw->ports; i++) {
4347 struct net_device *dev = hw->dev[i];
4348 struct sky2_port *sky2 = netdev_priv(dev);
4349
4350 netif_device_detach(dev);
4351 if (netif_running(dev))
4352 sky2_down(dev);
4353
4354 if (sky2->wol)
4355 sky2_wol_init(sky2);
4356
4357 wol |= sky2->wol;
4358 }
4359
4360 sky2_write32(hw, B0_IMSK, 0);
4361 napi_disable(&hw->napi);
4362 sky2_power_aux(hw);
4363
4364 pci_save_state(pdev);
4365 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4366 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4367
4368 return 0;
4369 }
4370
4371 static int sky2_resume(struct pci_dev *pdev)
4372 {
4373 struct sky2_hw *hw = pci_get_drvdata(pdev);
4374 int i, err;
4375
4376 if (!hw)
4377 return 0;
4378
4379 err = pci_set_power_state(pdev, PCI_D0);
4380 if (err)
4381 goto out;
4382
4383 err = pci_restore_state(pdev);
4384 if (err)
4385 goto out;
4386
4387 pci_enable_wake(pdev, PCI_D0, 0);
4388
4389 /* Re-enable all clocks */
4390 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4391 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4392 hw->chip_id == CHIP_ID_YUKON_FE_P)
4393 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4394
4395 sky2_reset(hw);
4396 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4397 napi_enable(&hw->napi);
4398
4399 for (i = 0; i < hw->ports; i++) {
4400 struct net_device *dev = hw->dev[i];
4401
4402 netif_device_attach(dev);
4403 if (netif_running(dev)) {
4404 err = sky2_up(dev);
4405 if (err) {
4406 printk(KERN_ERR PFX "%s: could not up: %d\n",
4407 dev->name, err);
4408 rtnl_lock();
4409 dev_close(dev);
4410 rtnl_unlock();
4411 goto out;
4412 }
4413 }
4414 }
4415
4416 return 0;
4417 out:
4418 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4419 pci_disable_device(pdev);
4420 return err;
4421 }
4422 #endif
4423
4424 static void sky2_shutdown(struct pci_dev *pdev)
4425 {
4426 struct sky2_hw *hw = pci_get_drvdata(pdev);
4427 int i, wol = 0;
4428
4429 if (!hw)
4430 return;
4431
4432 del_timer_sync(&hw->watchdog_timer);
4433
4434 for (i = 0; i < hw->ports; i++) {
4435 struct net_device *dev = hw->dev[i];
4436 struct sky2_port *sky2 = netdev_priv(dev);
4437
4438 if (sky2->wol) {
4439 wol = 1;
4440 sky2_wol_init(sky2);
4441 }
4442 }
4443
4444 if (wol)
4445 sky2_power_aux(hw);
4446
4447 pci_enable_wake(pdev, PCI_D3hot, wol);
4448 pci_enable_wake(pdev, PCI_D3cold, wol);
4449
4450 pci_disable_device(pdev);
4451 pci_set_power_state(pdev, PCI_D3hot);
4452
4453 }
4454
4455 static struct pci_driver sky2_driver = {
4456 .name = DRV_NAME,
4457 .id_table = sky2_id_table,
4458 .probe = sky2_probe,
4459 .remove = __devexit_p(sky2_remove),
4460 #ifdef CONFIG_PM
4461 .suspend = sky2_suspend,
4462 .resume = sky2_resume,
4463 #endif
4464 .shutdown = sky2_shutdown,
4465 };
4466
4467 static int __init sky2_init_module(void)
4468 {
4469 sky2_debug_init();
4470 return pci_register_driver(&sky2_driver);
4471 }
4472
4473 static void __exit sky2_cleanup_module(void)
4474 {
4475 pci_unregister_driver(&sky2_driver);
4476 sky2_debug_cleanup();
4477 }
4478
4479 module_init(sky2_init_module);
4480 module_exit(sky2_cleanup_module);
4481
4482 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4483 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4484 MODULE_LICENSE("GPL");
4485 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support