?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: R8A7740 supports packet shecksumming
[linux/fpc-iii.git] / drivers / iommu / mtk_iommu.c
blob1479c76ece9ec31793ec4d0f78a5611d3f09a6cb
1 /*
2 * Copyright (c) 2015-2016 MediaTek Inc.
3 * Author: Yong Wu <yong.wu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14 #include <linux/bootmem.h>
15 #include <linux/bug.h>
16 #include <linux/clk.h>
17 #include <linux/component.h>
18 #include <linux/device.h>
19 #include <linux/dma-iommu.h>
20 #include <linux/err.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/iommu.h>
24 #include <linux/iopoll.h>
25 #include <linux/list.h>
26 #include <linux/of_address.h>
27 #include <linux/of_iommu.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <asm/barrier.h>
34 #include <dt-bindings/memory/mt8173-larb-port.h>
35 #include <soc/mediatek/smi.h>
36
37 #include "mtk_iommu.h"
38
39 #define REG_MMU_PT_BASE_ADDR 0x000
40
41 #define REG_MMU_INVALIDATE 0x020
42 #define F_ALL_INVLD 0x2
43 #define F_MMU_INV_RANGE 0x1
44
45 #define REG_MMU_INVLD_START_A 0x024
46 #define REG_MMU_INVLD_END_A 0x028
47
48 #define REG_MMU_INV_SEL 0x038
49 #define F_INVLD_EN0 BIT(0)
50 #define F_INVLD_EN1 BIT(1)
51
52 #define REG_MMU_STANDARD_AXI_MODE 0x048
53 #define REG_MMU_DCM_DIS 0x050
54
55 #define REG_MMU_CTRL_REG 0x110
56 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
57 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
58
59 #define REG_MMU_IVRP_PADDR 0x114
60 #define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
61
62 #define REG_MMU_INT_CONTROL0 0x120
63 #define F_L2_MULIT_HIT_EN BIT(0)
64 #define F_TABLE_WALK_FAULT_INT_EN BIT(1)
65 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
66 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
67 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
68 #define F_MISS_FIFO_ERR_INT_EN BIT(6)
69 #define F_INT_CLR_BIT BIT(12)
70
71 #define REG_MMU_INT_MAIN_CONTROL 0x124
72 #define F_INT_TRANSLATION_FAULT BIT(0)
73 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
74 #define F_INT_INVALID_PA_FAULT BIT(2)
75 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
76 #define F_INT_TLB_MISS_FAULT BIT(4)
77 #define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
78 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
79
80 #define REG_MMU_CPE_DONE 0x12C
81
82 #define REG_MMU_FAULT_ST1 0x134
83
84 #define REG_MMU_FAULT_VA 0x13c
85 #define F_MMU_FAULT_VA_MSK 0xfffff000
86 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
87 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
88
89 #define REG_MMU_INVLD_PA 0x140
90 #define REG_MMU_INT_ID 0x150
91 #define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
92 #define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
93
94 #define MTK_PROTECT_PA_ALIGN 128
95
96 struct mtk_iommu_domain {
97 spinlock_t pgtlock; /* lock for page table */
98
99 struct io_pgtable_cfg cfg;
100 struct io_pgtable_ops *iop;
101
102 struct iommu_domain domain;
103 };
104
105 static struct iommu_ops mtk_iommu_ops;
106
107 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
108 {
109 return container_of(dom, struct mtk_iommu_domain, domain);
110 }
111
112 static void mtk_iommu_tlb_flush_all(void *cookie)
113 {
114 struct mtk_iommu_data *data = cookie;
115
116 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
117 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
118 wmb(); /* Make sure the tlb flush all done */
119 }
120
121 static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
122 size_t granule, bool leaf,
123 void *cookie)
124 {
125 struct mtk_iommu_data *data = cookie;
126
127 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
128
129 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
130 writel_relaxed(iova + size - 1, data->base + REG_MMU_INVLD_END_A);
131 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
132 }
133
134 static void mtk_iommu_tlb_sync(void *cookie)
135 {
136 struct mtk_iommu_data *data = cookie;
137 int ret;
138 u32 tmp;
139
140 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, tmp,
141 tmp != 0, 10, 100000);
142 if (ret) {
143 dev_warn(data->dev,
144 "Partial TLB flush timed out, falling back to full flush\n");
145 mtk_iommu_tlb_flush_all(cookie);
146 }
147 /* Clear the CPE status */
148 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
149 }
150
151 static const struct iommu_gather_ops mtk_iommu_gather_ops = {
152 .tlb_flush_all = mtk_iommu_tlb_flush_all,
153 .tlb_add_flush = mtk_iommu_tlb_add_flush_nosync,
154 .tlb_sync = mtk_iommu_tlb_sync,
155 };
156
157 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
158 {
159 struct mtk_iommu_data *data = dev_id;
160 struct mtk_iommu_domain *dom = data->m4u_dom;
161 u32 int_state, regval, fault_iova, fault_pa;
162 unsigned int fault_larb, fault_port;
163 bool layer, write;
164
165 /* Read error info from registers */
166 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
167 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
168 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
169 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
170 fault_iova &= F_MMU_FAULT_VA_MSK;
171 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
172 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
173 fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
174 fault_port = F_MMU0_INT_ID_PORT_ID(regval);
175
176 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
177 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
178 dev_err_ratelimited(
179 data->dev,
180 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
181 int_state, fault_iova, fault_pa, fault_larb, fault_port,
182 layer, write ? "write" : "read");
183 }
184
185 /* Interrupt clear */
186 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
187 regval |= F_INT_CLR_BIT;
188 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
189
190 mtk_iommu_tlb_flush_all(data);
191
192 return IRQ_HANDLED;
193 }
194
195 static void mtk_iommu_config(struct mtk_iommu_data *data,
196 struct device *dev, bool enable)
197 {
198 struct mtk_smi_larb_iommu *larb_mmu;
199 unsigned int larbid, portid;
200 struct iommu_fwspec *fwspec = dev->iommu_fwspec;
201 int i;
202
203 for (i = 0; i < fwspec->num_ids; ++i) {
204 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
205 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
206 larb_mmu = &data->smi_imu.larb_imu[larbid];
207
208 dev_dbg(dev, "%s iommu port: %d\n",
209 enable ? "enable" : "disable", portid);
210
211 if (enable)
212 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
213 else
214 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
215 }
216 }
217
218 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
219 {
220 struct mtk_iommu_domain *dom = data->m4u_dom;
221
222 spin_lock_init(&dom->pgtlock);
223
224 dom->cfg = (struct io_pgtable_cfg) {
225 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
226 IO_PGTABLE_QUIRK_NO_PERMS |
227 IO_PGTABLE_QUIRK_TLBI_ON_MAP,
228 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
229 .ias = 32,
230 .oas = 32,
231 .tlb = &mtk_iommu_gather_ops,
232 .iommu_dev = data->dev,
233 };
234
235 if (data->enable_4GB)
236 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB;
237
238 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
239 if (!dom->iop) {
240 dev_err(data->dev, "Failed to alloc io pgtable\n");
241 return -EINVAL;
242 }
243
244 /* Update our support page sizes bitmap */
245 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
246
247 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
248 data->base + REG_MMU_PT_BASE_ADDR);
249 return 0;
250 }
251
252 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
253 {
254 struct mtk_iommu_domain *dom;
255
256 if (type != IOMMU_DOMAIN_DMA)
257 return NULL;
258
259 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
260 if (!dom)
261 return NULL;
262
263 if (iommu_get_dma_cookie(&dom->domain)) {
264 kfree(dom);
265 return NULL;
266 }
267
268 dom->domain.geometry.aperture_start = 0;
269 dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
270 dom->domain.geometry.force_aperture = true;
271
272 return &dom->domain;
273 }
274
275 static void mtk_iommu_domain_free(struct iommu_domain *domain)
276 {
277 iommu_put_dma_cookie(domain);
278 kfree(to_mtk_domain(domain));
279 }
280
281 static int mtk_iommu_attach_device(struct iommu_domain *domain,
282 struct device *dev)
283 {
284 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
285 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
286 int ret;
287
288 if (!data)
289 return -ENODEV;
290
291 if (!data->m4u_dom) {
292 data->m4u_dom = dom;
293 ret = mtk_iommu_domain_finalise(data);
294 if (ret) {
295 data->m4u_dom = NULL;
296 return ret;
297 }
298 } else if (data->m4u_dom != dom) {
299 /* All the client devices should be in the same m4u domain */
300 dev_err(dev, "try to attach into the error iommu domain\n");
301 return -EPERM;
302 }
303
304 mtk_iommu_config(data, dev, true);
305 return 0;
306 }
307
308 static void mtk_iommu_detach_device(struct iommu_domain *domain,
309 struct device *dev)
310 {
311 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
312
313 if (!data)
314 return;
315
316 mtk_iommu_config(data, dev, false);
317 }
318
319 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
320 phys_addr_t paddr, size_t size, int prot)
321 {
322 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
323 unsigned long flags;
324 int ret;
325
326 spin_lock_irqsave(&dom->pgtlock, flags);
327 ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
328 spin_unlock_irqrestore(&dom->pgtlock, flags);
329
330 return ret;
331 }
332
333 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
334 unsigned long iova, size_t size)
335 {
336 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
337 unsigned long flags;
338 size_t unmapsz;
339
340 spin_lock_irqsave(&dom->pgtlock, flags);
341 unmapsz = dom->iop->unmap(dom->iop, iova, size);
342 spin_unlock_irqrestore(&dom->pgtlock, flags);
343
344 return unmapsz;
345 }
346
347 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
348 dma_addr_t iova)
349 {
350 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
351 unsigned long flags;
352 phys_addr_t pa;
353
354 spin_lock_irqsave(&dom->pgtlock, flags);
355 pa = dom->iop->iova_to_phys(dom->iop, iova);
356 spin_unlock_irqrestore(&dom->pgtlock, flags);
357
358 return pa;
359 }
360
361 static int mtk_iommu_add_device(struct device *dev)
362 {
363 struct iommu_group *group;
364
365 if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops)
366 return -ENODEV; /* Not a iommu client device */
367
368 group = iommu_group_get_for_dev(dev);
369 if (IS_ERR(group))
370 return PTR_ERR(group);
371
372 iommu_group_put(group);
373 return 0;
374 }
375
376 static void mtk_iommu_remove_device(struct device *dev)
377 {
378 if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops)
379 return;
380
381 iommu_group_remove_device(dev);
382 iommu_fwspec_free(dev);
383 }
384
385 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
386 {
387 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
388
389 if (!data)
390 return ERR_PTR(-ENODEV);
391
392 /* All the client devices are in the same m4u iommu-group */
393 if (!data->m4u_group) {
394 data->m4u_group = iommu_group_alloc();
395 if (IS_ERR(data->m4u_group))
396 dev_err(dev, "Failed to allocate M4U IOMMU group\n");
397 } else {
398 iommu_group_ref_get(data->m4u_group);
399 }
400 return data->m4u_group;
401 }
402
403 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
404 {
405 struct platform_device *m4updev;
406
407 if (args->args_count != 1) {
408 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
409 args->args_count);
410 return -EINVAL;
411 }
412
413 if (!dev->iommu_fwspec->iommu_priv) {
414 /* Get the m4u device */
415 m4updev = of_find_device_by_node(args->np);
416 if (WARN_ON(!m4updev))
417 return -EINVAL;
418
419 dev->iommu_fwspec->iommu_priv = platform_get_drvdata(m4updev);
420 }
421
422 return iommu_fwspec_add_ids(dev, args->args, 1);
423 }
424
425 static struct iommu_ops mtk_iommu_ops = {
426 .domain_alloc = mtk_iommu_domain_alloc,
427 .domain_free = mtk_iommu_domain_free,
428 .attach_dev = mtk_iommu_attach_device,
429 .detach_dev = mtk_iommu_detach_device,
430 .map = mtk_iommu_map,
431 .unmap = mtk_iommu_unmap,
432 .map_sg = default_iommu_map_sg,
433 .iova_to_phys = mtk_iommu_iova_to_phys,
434 .add_device = mtk_iommu_add_device,
435 .remove_device = mtk_iommu_remove_device,
436 .device_group = mtk_iommu_device_group,
437 .of_xlate = mtk_iommu_of_xlate,
438 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
439 };
440
441 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
442 {
443 u32 regval;
444 int ret;
445
446 ret = clk_prepare_enable(data->bclk);
447 if (ret) {
448 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
449 return ret;
450 }
451
452 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
453 F_MMU_TF_PROTECT_SEL(2);
454 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
455
456 regval = F_L2_MULIT_HIT_EN |
457 F_TABLE_WALK_FAULT_INT_EN |
458 F_PREETCH_FIFO_OVERFLOW_INT_EN |
459 F_MISS_FIFO_OVERFLOW_INT_EN |
460 F_PREFETCH_FIFO_ERR_INT_EN |
461 F_MISS_FIFO_ERR_INT_EN;
462 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
463
464 regval = F_INT_TRANSLATION_FAULT |
465 F_INT_MAIN_MULTI_HIT_FAULT |
466 F_INT_INVALID_PA_FAULT |
467 F_INT_ENTRY_REPLACEMENT_FAULT |
468 F_INT_TLB_MISS_FAULT |
469 F_INT_MISS_TRANSACTION_FIFO_FAULT |
470 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
471 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
472
473 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
474 data->base + REG_MMU_IVRP_PADDR);
475
476 writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
477 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
478
479 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
480 dev_name(data->dev), (void *)data)) {
481 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
482 clk_disable_unprepare(data->bclk);
483 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
484 return -ENODEV;
485 }
486
487 return 0;
488 }
489
490 static const struct component_master_ops mtk_iommu_com_ops = {
491 .bind = mtk_iommu_bind,
492 .unbind = mtk_iommu_unbind,
493 };
494
495 static int mtk_iommu_probe(struct platform_device *pdev)
496 {
497 struct mtk_iommu_data *data;
498 struct device *dev = &pdev->dev;
499 struct resource *res;
500 struct component_match *match = NULL;
501 void *protect;
502 int i, larb_nr, ret;
503
504 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
505 if (!data)
506 return -ENOMEM;
507 data->dev = dev;
508
509 /* Protect memory. HW will access here while translation fault.*/
510 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
511 if (!protect)
512 return -ENOMEM;
513 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
514
515 /* Whether the current dram is over 4GB */
516 data->enable_4GB = !!(max_pfn > (0xffffffffUL >> PAGE_SHIFT));
517
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519 data->base = devm_ioremap_resource(dev, res);
520 if (IS_ERR(data->base))
521 return PTR_ERR(data->base);
522
523 data->irq = platform_get_irq(pdev, 0);
524 if (data->irq < 0)
525 return data->irq;
526
527 data->bclk = devm_clk_get(dev, "bclk");
528 if (IS_ERR(data->bclk))
529 return PTR_ERR(data->bclk);
530
531 larb_nr = of_count_phandle_with_args(dev->of_node,
532 "mediatek,larbs", NULL);
533 if (larb_nr < 0)
534 return larb_nr;
535 data->smi_imu.larb_nr = larb_nr;
536
537 for (i = 0; i < larb_nr; i++) {
538 struct device_node *larbnode;
539 struct platform_device *plarbdev;
540
541 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
542 if (!larbnode)
543 return -EINVAL;
544
545 if (!of_device_is_available(larbnode))
546 continue;
547
548 plarbdev = of_find_device_by_node(larbnode);
549 if (!plarbdev) {
550 plarbdev = of_platform_device_create(
551 larbnode, NULL,
552 platform_bus_type.dev_root);
553 if (!plarbdev) {
554 of_node_put(larbnode);
555 return -EPROBE_DEFER;
556 }
557 }
558 data->smi_imu.larb_imu[i].dev = &plarbdev->dev;
559
560 component_match_add_release(dev, &match, release_of,
561 compare_of, larbnode);
562 }
563
564 platform_set_drvdata(pdev, data);
565
566 ret = mtk_iommu_hw_init(data);
567 if (ret)
568 return ret;
569
570 if (!iommu_present(&platform_bus_type))
571 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
572
573 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
574 }
575
576 static int mtk_iommu_remove(struct platform_device *pdev)
577 {
578 struct mtk_iommu_data *data = platform_get_drvdata(pdev);
579
580 if (iommu_present(&platform_bus_type))
581 bus_set_iommu(&platform_bus_type, NULL);
582
583 free_io_pgtable_ops(data->m4u_dom->iop);
584 clk_disable_unprepare(data->bclk);
585 devm_free_irq(&pdev->dev, data->irq, data);
586 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
587 return 0;
588 }
589
590 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
591 {
592 struct mtk_iommu_data *data = dev_get_drvdata(dev);
593 struct mtk_iommu_suspend_reg *reg = &data->reg;
594 void __iomem *base = data->base;
595
596 reg->standard_axi_mode = readl_relaxed(base +
597 REG_MMU_STANDARD_AXI_MODE);
598 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
599 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
600 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
601 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
602 return 0;
603 }
604
605 static int __maybe_unused mtk_iommu_resume(struct device *dev)
606 {
607 struct mtk_iommu_data *data = dev_get_drvdata(dev);
608 struct mtk_iommu_suspend_reg *reg = &data->reg;
609 void __iomem *base = data->base;
610
611 writel_relaxed(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
612 base + REG_MMU_PT_BASE_ADDR);
613 writel_relaxed(reg->standard_axi_mode,
614 base + REG_MMU_STANDARD_AXI_MODE);
615 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
616 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
617 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
618 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
619 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
620 base + REG_MMU_IVRP_PADDR);
621 return 0;
622 }
623
624 const struct dev_pm_ops mtk_iommu_pm_ops = {
625 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
626 };
627
628 static const struct of_device_id mtk_iommu_of_ids[] = {
629 { .compatible = "mediatek,mt8173-m4u", },
630 {}
631 };
632
633 static struct platform_driver mtk_iommu_driver = {
634 .probe = mtk_iommu_probe,
635 .remove = mtk_iommu_remove,
636 .driver = {
637 .name = "mtk-iommu",
638 .of_match_table = mtk_iommu_of_ids,
639 .pm = &mtk_iommu_pm_ops,
640 }
641 };
642
643 static int mtk_iommu_init_fn(struct device_node *np)
644 {
645 int ret;
646 struct platform_device *pdev;
647
648 pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
649 if (!pdev)
650 return -ENOMEM;
651
652 ret = platform_driver_register(&mtk_iommu_driver);
653 if (ret) {
654 pr_err("%s: Failed to register driver\n", __func__);
655 return ret;
656 }
657
658 of_iommu_set_ops(np, &mtk_iommu_ops);
659 return 0;
660 }
661
662 IOMMU_OF_DECLARE(mtkm4u, "mediatek,mt8173-m4u", mtk_iommu_init_fn);
Linux with added FPC-III support