?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: R8A7740 supports packet shecksumming
[linux/fpc-iii.git] / drivers / media / i2c / adv7604.c
blobd0375cac6a058c2d71720022ba283bd55e912bac
1 /*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30 #include <linux/delay.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/slab.h>
37 #include <linux/v4l2-dv-timings.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/regmap.h>
41
42 #include <media/i2c/adv7604.h>
43 #include <media/cec.h>
44 #include <media/v4l2-ctrls.h>
45 #include <media/v4l2-device.h>
46 #include <media/v4l2-event.h>
47 #include <media/v4l2-dv-timings.h>
48 #include <media/v4l2-of.h>
49
50 static int debug;
51 module_param(debug, int, 0644);
52 MODULE_PARM_DESC(debug, "debug level (0-2)");
53
54 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
55 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
56 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
57 MODULE_LICENSE("GPL");
58
59 /* ADV7604 system clock frequency */
60 #define ADV76XX_FSC (28636360)
61
62 #define ADV76XX_RGB_OUT (1 << 1)
63
64 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
65 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
66 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
67
68 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
69 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
70 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
71 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
72 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
73 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
74
75 #define ADV76XX_OP_CH_SEL_GBR (0 << 5)
76 #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
77 #define ADV76XX_OP_CH_SEL_BGR (2 << 5)
78 #define ADV76XX_OP_CH_SEL_RGB (3 << 5)
79 #define ADV76XX_OP_CH_SEL_BRG (4 << 5)
80 #define ADV76XX_OP_CH_SEL_RBG (5 << 5)
81
82 #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
83
84 #define ADV76XX_MAX_ADDRS (3)
85
86 enum adv76xx_type {
87 ADV7604,
88 ADV7611,
89 ADV7612,
90 };
91
92 struct adv76xx_reg_seq {
93 unsigned int reg;
94 u8 val;
95 };
96
97 struct adv76xx_format_info {
98 u32 code;
99 u8 op_ch_sel;
100 bool rgb_out;
101 bool swap_cb_cr;
102 u8 op_format_sel;
103 };
104
105 struct adv76xx_cfg_read_infoframe {
106 const char *desc;
107 u8 present_mask;
108 u8 head_addr;
109 u8 payload_addr;
110 };
111
112 struct adv76xx_chip_info {
113 enum adv76xx_type type;
114
115 bool has_afe;
116 unsigned int max_port;
117 unsigned int num_dv_ports;
118
119 unsigned int edid_enable_reg;
120 unsigned int edid_status_reg;
121 unsigned int lcf_reg;
122
123 unsigned int cable_det_mask;
124 unsigned int tdms_lock_mask;
125 unsigned int fmt_change_digital_mask;
126 unsigned int cp_csc;
127
128 const struct adv76xx_format_info *formats;
129 unsigned int nformats;
130
131 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
132 void (*setup_irqs)(struct v4l2_subdev *sd);
133 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
134 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
135
136 /* 0 = AFE, 1 = HDMI */
137 const struct adv76xx_reg_seq *recommended_settings[2];
138 unsigned int num_recommended_settings[2];
139
140 unsigned long page_mask;
141
142 /* Masks for timings */
143 unsigned int linewidth_mask;
144 unsigned int field0_height_mask;
145 unsigned int field1_height_mask;
146 unsigned int hfrontporch_mask;
147 unsigned int hsync_mask;
148 unsigned int hbackporch_mask;
149 unsigned int field0_vfrontporch_mask;
150 unsigned int field1_vfrontporch_mask;
151 unsigned int field0_vsync_mask;
152 unsigned int field1_vsync_mask;
153 unsigned int field0_vbackporch_mask;
154 unsigned int field1_vbackporch_mask;
155 };
156
157 /*
158 **********************************************************************
159 *
160 * Arrays with configuration parameters for the ADV7604
161 *
162 **********************************************************************
163 */
164
165 struct adv76xx_state {
166 const struct adv76xx_chip_info *info;
167 struct adv76xx_platform_data pdata;
168
169 struct gpio_desc *hpd_gpio[4];
170 struct gpio_desc *reset_gpio;
171
172 struct v4l2_subdev sd;
173 struct media_pad pads[ADV76XX_PAD_MAX];
174 unsigned int source_pad;
175
176 struct v4l2_ctrl_handler hdl;
177
178 enum adv76xx_pad selected_input;
179
180 struct v4l2_dv_timings timings;
181 const struct adv76xx_format_info *format;
182
183 struct {
184 u8 edid[256];
185 u32 present;
186 unsigned blocks;
187 } edid;
188 u16 spa_port_a[2];
189 struct v4l2_fract aspect_ratio;
190 u32 rgb_quantization_range;
191 struct delayed_work delayed_work_enable_hotplug;
192 bool restart_stdi_once;
193
194 /* CEC */
195 struct cec_adapter *cec_adap;
196 u8 cec_addr[ADV76XX_MAX_ADDRS];
197 u8 cec_valid_addrs;
198 bool cec_enabled_adap;
199
200 /* i2c clients */
201 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
202
203 /* Regmaps */
204 struct regmap *regmap[ADV76XX_PAGE_MAX];
205
206 /* controls */
207 struct v4l2_ctrl *detect_tx_5v_ctrl;
208 struct v4l2_ctrl *analog_sampling_phase_ctrl;
209 struct v4l2_ctrl *free_run_color_manual_ctrl;
210 struct v4l2_ctrl *free_run_color_ctrl;
211 struct v4l2_ctrl *rgb_quantization_range_ctrl;
212 };
213
214 static bool adv76xx_has_afe(struct adv76xx_state *state)
215 {
216 return state->info->has_afe;
217 }
218
219 /* Unsupported timings. This device cannot support 720p30. */
220 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
221 V4L2_DV_BT_CEA_1280X720P30,
222 { }
223 };
224
225 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
226 {
227 int i;
228
229 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
230 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
231 return false;
232 return true;
233 }
234
235 struct adv76xx_video_standards {
236 struct v4l2_dv_timings timings;
237 u8 vid_std;
238 u8 v_freq;
239 };
240
241 /* sorted by number of lines */
242 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
243 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
244 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
245 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
246 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
247 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
248 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
249 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
250 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
251 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
252 /* TODO add 1920x1080P60_RB (CVT timing) */
253 { },
254 };
255
256 /* sorted by number of lines */
257 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
258 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
259 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
260 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
261 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
262 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
263 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
264 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
265 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
266 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
267 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
268 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
269 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
270 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
271 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
272 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
273 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
274 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
275 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
276 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
277 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
278 /* TODO add 1600X1200P60_RB (not a DMT timing) */
279 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
280 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
281 { },
282 };
283
284 /* sorted by number of lines */
285 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
286 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
287 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
288 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
289 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
290 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
291 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
292 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
293 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
294 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
295 { },
296 };
297
298 /* sorted by number of lines */
299 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
300 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
301 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
302 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
303 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
304 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
305 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
306 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
307 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
308 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
309 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
310 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
311 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
312 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
313 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
314 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
315 { },
316 };
317
318 static const struct v4l2_event adv76xx_ev_fmt = {
319 .type = V4L2_EVENT_SOURCE_CHANGE,
320 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
321 };
322
323 /* ----------------------------------------------------------------------- */
324
325 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
326 {
327 return container_of(sd, struct adv76xx_state, sd);
328 }
329
330 static inline unsigned htotal(const struct v4l2_bt_timings *t)
331 {
332 return V4L2_DV_BT_FRAME_WIDTH(t);
333 }
334
335 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
336 {
337 return V4L2_DV_BT_FRAME_HEIGHT(t);
338 }
339
340 /* ----------------------------------------------------------------------- */
341
342 static int adv76xx_read_check(struct adv76xx_state *state,
343 int client_page, u8 reg)
344 {
345 struct i2c_client *client = state->i2c_clients[client_page];
346 int err;
347 unsigned int val;
348
349 err = regmap_read(state->regmap[client_page], reg, &val);
350
351 if (err) {
352 v4l_err(client, "error reading %02x, %02x\n",
353 client->addr, reg);
354 return err;
355 }
356 return val;
357 }
358
359 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
360 * size to one or more registers.
361 *
362 * A value of zero will be returned on success, a negative errno will
363 * be returned in error cases.
364 */
365 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
366 unsigned int init_reg, const void *val,
367 size_t val_len)
368 {
369 struct regmap *regmap = state->regmap[client_page];
370
371 if (val_len > I2C_SMBUS_BLOCK_MAX)
372 val_len = I2C_SMBUS_BLOCK_MAX;
373
374 return regmap_raw_write(regmap, init_reg, val, val_len);
375 }
376
377 /* ----------------------------------------------------------------------- */
378
379 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
380 {
381 struct adv76xx_state *state = to_state(sd);
382
383 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
384 }
385
386 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
387 {
388 struct adv76xx_state *state = to_state(sd);
389
390 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
391 }
392
393 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
394 u8 val)
395 {
396 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
397 }
398
399 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
400 {
401 struct adv76xx_state *state = to_state(sd);
402
403 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
404 }
405
406 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
407 {
408 struct adv76xx_state *state = to_state(sd);
409
410 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
411 }
412
413 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
414 {
415 struct adv76xx_state *state = to_state(sd);
416
417 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
418 }
419
420 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421 {
422 struct adv76xx_state *state = to_state(sd);
423
424 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
425 }
426
427 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
428 u8 val)
429 {
430 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
431 }
432
433 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
434 {
435 struct adv76xx_state *state = to_state(sd);
436
437 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
438 }
439
440 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
441 {
442 struct adv76xx_state *state = to_state(sd);
443
444 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
445 }
446
447 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
448 {
449 struct adv76xx_state *state = to_state(sd);
450
451 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
452 }
453
454 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
455 {
456 struct adv76xx_state *state = to_state(sd);
457
458 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
459 }
460
461 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
462 {
463 struct adv76xx_state *state = to_state(sd);
464
465 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
466 }
467
468 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
469 {
470 struct adv76xx_state *state = to_state(sd);
471
472 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
473 }
474
475 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
476 {
477 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
478 }
479
480 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
481 {
482 struct adv76xx_state *state = to_state(sd);
483
484 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
485 }
486
487 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
488 {
489 struct adv76xx_state *state = to_state(sd);
490
491 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
492 }
493
494 static inline int edid_write_block(struct v4l2_subdev *sd,
495 unsigned int total_len, const u8 *val)
496 {
497 struct adv76xx_state *state = to_state(sd);
498 int err = 0;
499 int i = 0;
500 int len = 0;
501
502 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
503 __func__, total_len);
504
505 while (!err && i < total_len) {
506 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
507 I2C_SMBUS_BLOCK_MAX :
508 (total_len - i);
509
510 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
511 i, val + i, len);
512 i += len;
513 }
514
515 return err;
516 }
517
518 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
519 {
520 unsigned int i;
521
522 for (i = 0; i < state->info->num_dv_ports; ++i)
523 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
524
525 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
526 }
527
528 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
529 {
530 struct delayed_work *dwork = to_delayed_work(work);
531 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
532 delayed_work_enable_hotplug);
533 struct v4l2_subdev *sd = &state->sd;
534
535 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
536
537 adv76xx_set_hpd(state, state->edid.present);
538 }
539
540 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
541 {
542 struct adv76xx_state *state = to_state(sd);
543
544 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
545 }
546
547 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
548 {
549 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
550 }
551
552 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
553 {
554 struct adv76xx_state *state = to_state(sd);
555
556 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
557 }
558
559 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
560 {
561 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
562 }
563
564 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
565 {
566 struct adv76xx_state *state = to_state(sd);
567
568 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
569 }
570
571 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
572 {
573 struct adv76xx_state *state = to_state(sd);
574
575 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
576 }
577
578 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
579 {
580 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
581 }
582
583 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584 {
585 struct adv76xx_state *state = to_state(sd);
586
587 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
588 }
589
590 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
591 {
592 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
593 }
594
595 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
596 {
597 struct adv76xx_state *state = to_state(sd);
598
599 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
600 }
601
602 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
603 {
604 struct adv76xx_state *state = to_state(sd);
605
606 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
607 }
608
609 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
610 #define ADV76XX_REG_SEQ_TERM 0xffff
611
612 #ifdef CONFIG_VIDEO_ADV_DEBUG
613 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
614 {
615 struct adv76xx_state *state = to_state(sd);
616 unsigned int page = reg >> 8;
617 unsigned int val;
618 int err;
619
620 if (!(BIT(page) & state->info->page_mask))
621 return -EINVAL;
622
623 reg &= 0xff;
624 err = regmap_read(state->regmap[page], reg, &val);
625
626 return err ? err : val;
627 }
628 #endif
629
630 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
631 {
632 struct adv76xx_state *state = to_state(sd);
633 unsigned int page = reg >> 8;
634
635 if (!(BIT(page) & state->info->page_mask))
636 return -EINVAL;
637
638 reg &= 0xff;
639
640 return regmap_write(state->regmap[page], reg, val);
641 }
642
643 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
644 const struct adv76xx_reg_seq *reg_seq)
645 {
646 unsigned int i;
647
648 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
649 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
650 }
651
652 /* -----------------------------------------------------------------------------
653 * Format helpers
654 */
655
656 static const struct adv76xx_format_info adv7604_formats[] = {
657 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
658 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
659 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
660 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
661 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
662 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
663 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
664 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
665 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
666 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
667 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
668 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
669 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
670 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
671 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
672 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
673 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
674 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
675 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
677 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
679 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
680 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
681 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
682 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
683 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
684 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
685 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
686 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
687 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
689 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
691 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
693 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
695 };
696
697 static const struct adv76xx_format_info adv7611_formats[] = {
698 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
699 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
700 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
702 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
704 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
705 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
706 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
707 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
708 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
709 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
710 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
711 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
712 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
713 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
714 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
715 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
716 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
718 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
720 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
722 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
724 };
725
726 static const struct adv76xx_format_info adv7612_formats[] = {
727 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
728 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
729 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
730 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
731 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
732 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
733 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
734 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
735 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
736 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
737 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
738 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
739 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
740 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
741 };
742
743 static const struct adv76xx_format_info *
744 adv76xx_format_info(struct adv76xx_state *state, u32 code)
745 {
746 unsigned int i;
747
748 for (i = 0; i < state->info->nformats; ++i) {
749 if (state->info->formats[i].code == code)
750 return &state->info->formats[i];
751 }
752
753 return NULL;
754 }
755
756 /* ----------------------------------------------------------------------- */
757
758 static inline bool is_analog_input(struct v4l2_subdev *sd)
759 {
760 struct adv76xx_state *state = to_state(sd);
761
762 return state->selected_input == ADV7604_PAD_VGA_RGB ||
763 state->selected_input == ADV7604_PAD_VGA_COMP;
764 }
765
766 static inline bool is_digital_input(struct v4l2_subdev *sd)
767 {
768 struct adv76xx_state *state = to_state(sd);
769
770 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
771 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
772 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
773 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
774 }
775
776 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
777 .type = V4L2_DV_BT_656_1120,
778 /* keep this initialization for compatibility with GCC < 4.4.6 */
779 .reserved = { 0 },
780 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
781 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
782 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
783 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
784 V4L2_DV_BT_CAP_CUSTOM)
785 };
786
787 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
788 .type = V4L2_DV_BT_656_1120,
789 /* keep this initialization for compatibility with GCC < 4.4.6 */
790 .reserved = { 0 },
791 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
792 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
793 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
794 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
795 V4L2_DV_BT_CAP_CUSTOM)
796 };
797
798 /*
799 * Return the DV timings capabilities for the requested sink pad. As a special
800 * case, pad value -1 returns the capabilities for the currently selected input.
801 */
802 static const struct v4l2_dv_timings_cap *
803 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
804 {
805 if (pad == -1) {
806 struct adv76xx_state *state = to_state(sd);
807
808 pad = state->selected_input;
809 }
810
811 switch (pad) {
812 case ADV76XX_PAD_HDMI_PORT_A:
813 case ADV7604_PAD_HDMI_PORT_B:
814 case ADV7604_PAD_HDMI_PORT_C:
815 case ADV7604_PAD_HDMI_PORT_D:
816 return &adv76xx_timings_cap_digital;
817
818 case ADV7604_PAD_VGA_RGB:
819 case ADV7604_PAD_VGA_COMP:
820 default:
821 return &adv7604_timings_cap_analog;
822 }
823 }
824
825
826 /* ----------------------------------------------------------------------- */
827
828 #ifdef CONFIG_VIDEO_ADV_DEBUG
829 static void adv76xx_inv_register(struct v4l2_subdev *sd)
830 {
831 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
832 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
833 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
834 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
835 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
836 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
837 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
838 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
839 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
840 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
841 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
842 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
843 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
844 }
845
846 static int adv76xx_g_register(struct v4l2_subdev *sd,
847 struct v4l2_dbg_register *reg)
848 {
849 int ret;
850
851 ret = adv76xx_read_reg(sd, reg->reg);
852 if (ret < 0) {
853 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
854 adv76xx_inv_register(sd);
855 return ret;
856 }
857
858 reg->size = 1;
859 reg->val = ret;
860
861 return 0;
862 }
863
864 static int adv76xx_s_register(struct v4l2_subdev *sd,
865 const struct v4l2_dbg_register *reg)
866 {
867 int ret;
868
869 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
870 if (ret < 0) {
871 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
872 adv76xx_inv_register(sd);
873 return ret;
874 }
875
876 return 0;
877 }
878 #endif
879
880 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
881 {
882 u8 value = io_read(sd, 0x6f);
883
884 return ((value & 0x10) >> 4)
885 | ((value & 0x08) >> 2)
886 | ((value & 0x04) << 0)
887 | ((value & 0x02) << 2);
888 }
889
890 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
891 {
892 u8 value = io_read(sd, 0x6f);
893
894 return value & 1;
895 }
896
897 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
898 {
899 /* Reads CABLE_DET_A_RAW. For input B support, need to
900 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
901 */
902 u8 value = io_read(sd, 0x6f);
903
904 return value & 1;
905 }
906
907 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
908 {
909 struct adv76xx_state *state = to_state(sd);
910 const struct adv76xx_chip_info *info = state->info;
911 u16 cable_det = info->read_cable_det(sd);
912
913 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
914 }
915
916 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
917 u8 prim_mode,
918 const struct adv76xx_video_standards *predef_vid_timings,
919 const struct v4l2_dv_timings *timings)
920 {
921 int i;
922
923 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
924 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
925 is_digital_input(sd) ? 250000 : 1000000, false))
926 continue;
927 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
928 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
929 prim_mode); /* v_freq and prim mode */
930 return 0;
931 }
932
933 return -1;
934 }
935
936 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
937 struct v4l2_dv_timings *timings)
938 {
939 struct adv76xx_state *state = to_state(sd);
940 int err;
941
942 v4l2_dbg(1, debug, sd, "%s", __func__);
943
944 if (adv76xx_has_afe(state)) {
945 /* reset to default values */
946 io_write(sd, 0x16, 0x43);
947 io_write(sd, 0x17, 0x5a);
948 }
949 /* disable embedded syncs for auto graphics mode */
950 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
951 cp_write(sd, 0x8f, 0x00);
952 cp_write(sd, 0x90, 0x00);
953 cp_write(sd, 0xa2, 0x00);
954 cp_write(sd, 0xa3, 0x00);
955 cp_write(sd, 0xa4, 0x00);
956 cp_write(sd, 0xa5, 0x00);
957 cp_write(sd, 0xa6, 0x00);
958 cp_write(sd, 0xa7, 0x00);
959 cp_write(sd, 0xab, 0x00);
960 cp_write(sd, 0xac, 0x00);
961
962 if (is_analog_input(sd)) {
963 err = find_and_set_predefined_video_timings(sd,
964 0x01, adv7604_prim_mode_comp, timings);
965 if (err)
966 err = find_and_set_predefined_video_timings(sd,
967 0x02, adv7604_prim_mode_gr, timings);
968 } else if (is_digital_input(sd)) {
969 err = find_and_set_predefined_video_timings(sd,
970 0x05, adv76xx_prim_mode_hdmi_comp, timings);
971 if (err)
972 err = find_and_set_predefined_video_timings(sd,
973 0x06, adv76xx_prim_mode_hdmi_gr, timings);
974 } else {
975 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
976 __func__, state->selected_input);
977 err = -1;
978 }
979
980
981 return err;
982 }
983
984 static void configure_custom_video_timings(struct v4l2_subdev *sd,
985 const struct v4l2_bt_timings *bt)
986 {
987 struct adv76xx_state *state = to_state(sd);
988 u32 width = htotal(bt);
989 u32 height = vtotal(bt);
990 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
991 u16 cp_start_eav = width - bt->hfrontporch;
992 u16 cp_start_vbi = height - bt->vfrontporch;
993 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
994 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
995 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
996 const u8 pll[2] = {
997 0xc0 | ((width >> 8) & 0x1f),
998 width & 0xff
999 };
1000
1001 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1002
1003 if (is_analog_input(sd)) {
1004 /* auto graphics */
1005 io_write(sd, 0x00, 0x07); /* video std */
1006 io_write(sd, 0x01, 0x02); /* prim mode */
1007 /* enable embedded syncs for auto graphics mode */
1008 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1009
1010 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1011 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1012 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1013 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1014 0x16, pll, 2))
1015 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1016
1017 /* active video - horizontal timing */
1018 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1019 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1020 ((cp_start_eav >> 8) & 0x0f));
1021 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1022
1023 /* active video - vertical timing */
1024 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1025 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1026 ((cp_end_vbi >> 8) & 0xf));
1027 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1028 } else if (is_digital_input(sd)) {
1029 /* set default prim_mode/vid_std for HDMI
1030 according to [REF_03, c. 4.2] */
1031 io_write(sd, 0x00, 0x02); /* video std */
1032 io_write(sd, 0x01, 0x06); /* prim mode */
1033 } else {
1034 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1035 __func__, state->selected_input);
1036 }
1037
1038 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1039 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1040 cp_write(sd, 0xab, (height >> 4) & 0xff);
1041 cp_write(sd, 0xac, (height & 0x0f) << 4);
1042 }
1043
1044 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1045 {
1046 struct adv76xx_state *state = to_state(sd);
1047 u8 offset_buf[4];
1048
1049 if (auto_offset) {
1050 offset_a = 0x3ff;
1051 offset_b = 0x3ff;
1052 offset_c = 0x3ff;
1053 }
1054
1055 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1056 __func__, auto_offset ? "Auto" : "Manual",
1057 offset_a, offset_b, offset_c);
1058
1059 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1060 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1061 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1062 offset_buf[3] = offset_c & 0x0ff;
1063
1064 /* Registers must be written in this order with no i2c access in between */
1065 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1066 0x77, offset_buf, 4))
1067 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1068 }
1069
1070 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1071 {
1072 struct adv76xx_state *state = to_state(sd);
1073 u8 gain_buf[4];
1074 u8 gain_man = 1;
1075 u8 agc_mode_man = 1;
1076
1077 if (auto_gain) {
1078 gain_man = 0;
1079 agc_mode_man = 0;
1080 gain_a = 0x100;
1081 gain_b = 0x100;
1082 gain_c = 0x100;
1083 }
1084
1085 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1086 __func__, auto_gain ? "Auto" : "Manual",
1087 gain_a, gain_b, gain_c);
1088
1089 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1090 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1091 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1092 gain_buf[3] = ((gain_c & 0x0ff));
1093
1094 /* Registers must be written in this order with no i2c access in between */
1095 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1096 0x73, gain_buf, 4))
1097 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1098 }
1099
1100 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1101 {
1102 struct adv76xx_state *state = to_state(sd);
1103 bool rgb_output = io_read(sd, 0x02) & 0x02;
1104 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1105 u8 y = HDMI_COLORSPACE_RGB;
1106
1107 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1108 y = infoframe_read(sd, 0x01) >> 5;
1109
1110 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1111 __func__, state->rgb_quantization_range,
1112 rgb_output, hdmi_signal);
1113
1114 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1115 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1116 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1117
1118 switch (state->rgb_quantization_range) {
1119 case V4L2_DV_RGB_RANGE_AUTO:
1120 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1121 /* Receiving analog RGB signal
1122 * Set RGB full range (0-255) */
1123 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1124 break;
1125 }
1126
1127 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1128 /* Receiving analog YPbPr signal
1129 * Set automode */
1130 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1131 break;
1132 }
1133
1134 if (hdmi_signal) {
1135 /* Receiving HDMI signal
1136 * Set automode */
1137 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1138 break;
1139 }
1140
1141 /* Receiving DVI-D signal
1142 * ADV7604 selects RGB limited range regardless of
1143 * input format (CE/IT) in automatic mode */
1144 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1145 /* RGB limited range (16-235) */
1146 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1147 } else {
1148 /* RGB full range (0-255) */
1149 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1150
1151 if (is_digital_input(sd) && rgb_output) {
1152 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1153 } else {
1154 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1155 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1156 }
1157 }
1158 break;
1159 case V4L2_DV_RGB_RANGE_LIMITED:
1160 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1161 /* YCrCb limited range (16-235) */
1162 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1163 break;
1164 }
1165
1166 if (y != HDMI_COLORSPACE_RGB)
1167 break;
1168
1169 /* RGB limited range (16-235) */
1170 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1171
1172 break;
1173 case V4L2_DV_RGB_RANGE_FULL:
1174 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1175 /* YCrCb full range (0-255) */
1176 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1177 break;
1178 }
1179
1180 if (y != HDMI_COLORSPACE_RGB)
1181 break;
1182
1183 /* RGB full range (0-255) */
1184 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1185
1186 if (is_analog_input(sd) || hdmi_signal)
1187 break;
1188
1189 /* Adjust gain/offset for DVI-D signals only */
1190 if (rgb_output) {
1191 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1192 } else {
1193 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1194 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1195 }
1196 break;
1197 }
1198 }
1199
1200 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1201 {
1202 struct v4l2_subdev *sd =
1203 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1204
1205 struct adv76xx_state *state = to_state(sd);
1206
1207 switch (ctrl->id) {
1208 case V4L2_CID_BRIGHTNESS:
1209 cp_write(sd, 0x3c, ctrl->val);
1210 return 0;
1211 case V4L2_CID_CONTRAST:
1212 cp_write(sd, 0x3a, ctrl->val);
1213 return 0;
1214 case V4L2_CID_SATURATION:
1215 cp_write(sd, 0x3b, ctrl->val);
1216 return 0;
1217 case V4L2_CID_HUE:
1218 cp_write(sd, 0x3d, ctrl->val);
1219 return 0;
1220 case V4L2_CID_DV_RX_RGB_RANGE:
1221 state->rgb_quantization_range = ctrl->val;
1222 set_rgb_quantization_range(sd);
1223 return 0;
1224 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1225 if (!adv76xx_has_afe(state))
1226 return -EINVAL;
1227 /* Set the analog sampling phase. This is needed to find the
1228 best sampling phase for analog video: an application or
1229 driver has to try a number of phases and analyze the picture
1230 quality before settling on the best performing phase. */
1231 afe_write(sd, 0xc8, ctrl->val);
1232 return 0;
1233 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1234 /* Use the default blue color for free running mode,
1235 or supply your own. */
1236 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1237 return 0;
1238 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1239 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1240 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1241 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1242 return 0;
1243 }
1244 return -EINVAL;
1245 }
1246
1247 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1248 {
1249 struct v4l2_subdev *sd =
1250 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1251
1252 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1253 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1254 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1255 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1256 return 0;
1257 }
1258 return -EINVAL;
1259 }
1260
1261 /* ----------------------------------------------------------------------- */
1262
1263 static inline bool no_power(struct v4l2_subdev *sd)
1264 {
1265 /* Entire chip or CP powered off */
1266 return io_read(sd, 0x0c) & 0x24;
1267 }
1268
1269 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1270 {
1271 struct adv76xx_state *state = to_state(sd);
1272
1273 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1274 }
1275
1276 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1277 {
1278 struct adv76xx_state *state = to_state(sd);
1279 const struct adv76xx_chip_info *info = state->info;
1280
1281 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1282 }
1283
1284 static inline bool is_hdmi(struct v4l2_subdev *sd)
1285 {
1286 return hdmi_read(sd, 0x05) & 0x80;
1287 }
1288
1289 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1290 {
1291 struct adv76xx_state *state = to_state(sd);
1292
1293 /*
1294 * Chips without a AFE don't expose registers for the SSPD, so just assume
1295 * that we have a lock.
1296 */
1297 if (adv76xx_has_afe(state))
1298 return false;
1299
1300 /* TODO channel 2 */
1301 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1302 }
1303
1304 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1305 {
1306 /* TODO channel 2 */
1307 return !(cp_read(sd, 0xb1) & 0x80);
1308 }
1309
1310 static inline bool no_signal(struct v4l2_subdev *sd)
1311 {
1312 bool ret;
1313
1314 ret = no_power(sd);
1315
1316 ret |= no_lock_stdi(sd);
1317 ret |= no_lock_sspd(sd);
1318
1319 if (is_digital_input(sd)) {
1320 ret |= no_lock_tmds(sd);
1321 ret |= no_signal_tmds(sd);
1322 }
1323
1324 return ret;
1325 }
1326
1327 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1328 {
1329 struct adv76xx_state *state = to_state(sd);
1330
1331 if (!adv76xx_has_afe(state))
1332 return false;
1333
1334 /* CP has detected a non standard number of lines on the incoming
1335 video compared to what it is configured to receive by s_dv_timings */
1336 return io_read(sd, 0x12) & 0x01;
1337 }
1338
1339 static inline bool in_free_run(struct v4l2_subdev *sd)
1340 {
1341 return cp_read(sd, 0xff) & 0x10;
1342 }
1343
1344 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1345 {
1346 *status = 0;
1347 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1348 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1349 if (!in_free_run(sd) && no_lock_cp(sd))
1350 *status |= is_digital_input(sd) ?
1351 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1352
1353 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1354
1355 return 0;
1356 }
1357
1358 /* ----------------------------------------------------------------------- */
1359
1360 struct stdi_readback {
1361 u16 bl, lcf, lcvs;
1362 u8 hs_pol, vs_pol;
1363 bool interlaced;
1364 };
1365
1366 static int stdi2dv_timings(struct v4l2_subdev *sd,
1367 struct stdi_readback *stdi,
1368 struct v4l2_dv_timings *timings)
1369 {
1370 struct adv76xx_state *state = to_state(sd);
1371 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1372 u32 pix_clk;
1373 int i;
1374
1375 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1376 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1377
1378 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1379 adv76xx_get_dv_timings_cap(sd, -1),
1380 adv76xx_check_dv_timings, NULL))
1381 continue;
1382 if (vtotal(bt) != stdi->lcf + 1)
1383 continue;
1384 if (bt->vsync != stdi->lcvs)
1385 continue;
1386
1387 pix_clk = hfreq * htotal(bt);
1388
1389 if ((pix_clk < bt->pixelclock + 1000000) &&
1390 (pix_clk > bt->pixelclock - 1000000)) {
1391 *timings = v4l2_dv_timings_presets[i];
1392 return 0;
1393 }
1394 }
1395
1396 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1397 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1398 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1399 false, timings))
1400 return 0;
1401 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1402 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1403 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1404 false, state->aspect_ratio, timings))
1405 return 0;
1406
1407 v4l2_dbg(2, debug, sd,
1408 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1409 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1410 stdi->hs_pol, stdi->vs_pol);
1411 return -1;
1412 }
1413
1414
1415 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1416 {
1417 struct adv76xx_state *state = to_state(sd);
1418 const struct adv76xx_chip_info *info = state->info;
1419 u8 polarity;
1420
1421 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1422 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1423 return -1;
1424 }
1425
1426 /* read STDI */
1427 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1428 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1429 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1430 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1431
1432 if (adv76xx_has_afe(state)) {
1433 /* read SSPD */
1434 polarity = cp_read(sd, 0xb5);
1435 if ((polarity & 0x03) == 0x01) {
1436 stdi->hs_pol = polarity & 0x10
1437 ? (polarity & 0x08 ? '+' : '-') : 'x';
1438 stdi->vs_pol = polarity & 0x40
1439 ? (polarity & 0x20 ? '+' : '-') : 'x';
1440 } else {
1441 stdi->hs_pol = 'x';
1442 stdi->vs_pol = 'x';
1443 }
1444 } else {
1445 polarity = hdmi_read(sd, 0x05);
1446 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1447 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1448 }
1449
1450 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1451 v4l2_dbg(2, debug, sd,
1452 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1453 return -1;
1454 }
1455
1456 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1457 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1458 memset(stdi, 0, sizeof(struct stdi_readback));
1459 return -1;
1460 }
1461
1462 v4l2_dbg(2, debug, sd,
1463 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1464 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1465 stdi->hs_pol, stdi->vs_pol,
1466 stdi->interlaced ? "interlaced" : "progressive");
1467
1468 return 0;
1469 }
1470
1471 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1472 struct v4l2_enum_dv_timings *timings)
1473 {
1474 struct adv76xx_state *state = to_state(sd);
1475
1476 if (timings->pad >= state->source_pad)
1477 return -EINVAL;
1478
1479 return v4l2_enum_dv_timings_cap(timings,
1480 adv76xx_get_dv_timings_cap(sd, timings->pad),
1481 adv76xx_check_dv_timings, NULL);
1482 }
1483
1484 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1485 struct v4l2_dv_timings_cap *cap)
1486 {
1487 struct adv76xx_state *state = to_state(sd);
1488 unsigned int pad = cap->pad;
1489
1490 if (cap->pad >= state->source_pad)
1491 return -EINVAL;
1492
1493 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1494 cap->pad = pad;
1495
1496 return 0;
1497 }
1498
1499 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1500 if the format is listed in adv76xx_timings[] */
1501 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1502 struct v4l2_dv_timings *timings)
1503 {
1504 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1505 is_digital_input(sd) ? 250000 : 1000000,
1506 adv76xx_check_dv_timings, NULL);
1507 }
1508
1509 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1510 {
1511 unsigned int freq;
1512 int a, b;
1513
1514 a = hdmi_read(sd, 0x06);
1515 b = hdmi_read(sd, 0x3b);
1516 if (a < 0 || b < 0)
1517 return 0;
1518 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1519
1520 if (is_hdmi(sd)) {
1521 /* adjust for deep color mode */
1522 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1523
1524 freq = freq * 8 / bits_per_channel;
1525 }
1526
1527 return freq;
1528 }
1529
1530 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1531 {
1532 int a, b;
1533
1534 a = hdmi_read(sd, 0x51);
1535 b = hdmi_read(sd, 0x52);
1536 if (a < 0 || b < 0)
1537 return 0;
1538 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1539 }
1540
1541 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1542 struct v4l2_dv_timings *timings)
1543 {
1544 struct adv76xx_state *state = to_state(sd);
1545 const struct adv76xx_chip_info *info = state->info;
1546 struct v4l2_bt_timings *bt = &timings->bt;
1547 struct stdi_readback stdi;
1548
1549 if (!timings)
1550 return -EINVAL;
1551
1552 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1553
1554 if (no_signal(sd)) {
1555 state->restart_stdi_once = true;
1556 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1557 return -ENOLINK;
1558 }
1559
1560 /* read STDI */
1561 if (read_stdi(sd, &stdi)) {
1562 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1563 return -ENOLINK;
1564 }
1565 bt->interlaced = stdi.interlaced ?
1566 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1567
1568 if (is_digital_input(sd)) {
1569 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1570 u8 vic = 0;
1571 u32 w, h;
1572
1573 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1574 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1575
1576 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1577 vic = infoframe_read(sd, 0x04);
1578
1579 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1580 bt->width == w && bt->height == h)
1581 goto found;
1582
1583 timings->type = V4L2_DV_BT_656_1120;
1584
1585 bt->width = w;
1586 bt->height = h;
1587 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1588 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1589 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1590 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1591 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1592 info->field0_vfrontporch_mask) / 2;
1593 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1594 bt->vbackporch = hdmi_read16(sd, 0x32,
1595 info->field0_vbackporch_mask) / 2;
1596 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1597 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1598 if (bt->interlaced == V4L2_DV_INTERLACED) {
1599 bt->height += hdmi_read16(sd, 0x0b,
1600 info->field1_height_mask);
1601 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1602 info->field1_vfrontporch_mask) / 2;
1603 bt->il_vsync = hdmi_read16(sd, 0x30,
1604 info->field1_vsync_mask) / 2;
1605 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1606 info->field1_vbackporch_mask) / 2;
1607 }
1608 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1609 } else {
1610 /* find format
1611 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1612 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1613 */
1614 if (!stdi2dv_timings(sd, &stdi, timings))
1615 goto found;
1616 stdi.lcvs += 1;
1617 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1618 if (!stdi2dv_timings(sd, &stdi, timings))
1619 goto found;
1620 stdi.lcvs -= 2;
1621 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1622 if (stdi2dv_timings(sd, &stdi, timings)) {
1623 /*
1624 * The STDI block may measure wrong values, especially
1625 * for lcvs and lcf. If the driver can not find any
1626 * valid timing, the STDI block is restarted to measure
1627 * the video timings again. The function will return an
1628 * error, but the restart of STDI will generate a new
1629 * STDI interrupt and the format detection process will
1630 * restart.
1631 */
1632 if (state->restart_stdi_once) {
1633 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1634 /* TODO restart STDI for Sync Channel 2 */
1635 /* enter one-shot mode */
1636 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1637 /* trigger STDI restart */
1638 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1639 /* reset to continuous mode */
1640 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1641 state->restart_stdi_once = false;
1642 return -ENOLINK;
1643 }
1644 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1645 return -ERANGE;
1646 }
1647 state->restart_stdi_once = true;
1648 }
1649 found:
1650
1651 if (no_signal(sd)) {
1652 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1653 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1654 return -ENOLINK;
1655 }
1656
1657 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1658 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1659 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1660 __func__, (u32)bt->pixelclock);
1661 return -ERANGE;
1662 }
1663
1664 if (debug > 1)
1665 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1666 timings, true);
1667
1668 return 0;
1669 }
1670
1671 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1672 struct v4l2_dv_timings *timings)
1673 {
1674 struct adv76xx_state *state = to_state(sd);
1675 struct v4l2_bt_timings *bt;
1676 int err;
1677
1678 if (!timings)
1679 return -EINVAL;
1680
1681 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1682 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1683 return 0;
1684 }
1685
1686 bt = &timings->bt;
1687
1688 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1689 adv76xx_check_dv_timings, NULL))
1690 return -ERANGE;
1691
1692 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1693
1694 state->timings = *timings;
1695
1696 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1697
1698 /* Use prim_mode and vid_std when available */
1699 err = configure_predefined_video_timings(sd, timings);
1700 if (err) {
1701 /* custom settings when the video format
1702 does not have prim_mode/vid_std */
1703 configure_custom_video_timings(sd, bt);
1704 }
1705
1706 set_rgb_quantization_range(sd);
1707
1708 if (debug > 1)
1709 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1710 timings, true);
1711 return 0;
1712 }
1713
1714 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1715 struct v4l2_dv_timings *timings)
1716 {
1717 struct adv76xx_state *state = to_state(sd);
1718
1719 *timings = state->timings;
1720 return 0;
1721 }
1722
1723 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1724 {
1725 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1726 }
1727
1728 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1729 {
1730 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1731 }
1732
1733 static void enable_input(struct v4l2_subdev *sd)
1734 {
1735 struct adv76xx_state *state = to_state(sd);
1736
1737 if (is_analog_input(sd)) {
1738 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1739 } else if (is_digital_input(sd)) {
1740 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1741 state->info->set_termination(sd, true);
1742 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1743 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1744 } else {
1745 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1746 __func__, state->selected_input);
1747 }
1748 }
1749
1750 static void disable_input(struct v4l2_subdev *sd)
1751 {
1752 struct adv76xx_state *state = to_state(sd);
1753
1754 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1755 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1756 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1757 state->info->set_termination(sd, false);
1758 }
1759
1760 static void select_input(struct v4l2_subdev *sd)
1761 {
1762 struct adv76xx_state *state = to_state(sd);
1763 const struct adv76xx_chip_info *info = state->info;
1764
1765 if (is_analog_input(sd)) {
1766 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1767
1768 afe_write(sd, 0x00, 0x08); /* power up ADC */
1769 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1770 afe_write(sd, 0xc8, 0x00); /* phase control */
1771 } else if (is_digital_input(sd)) {
1772 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1773
1774 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1775
1776 if (adv76xx_has_afe(state)) {
1777 afe_write(sd, 0x00, 0xff); /* power down ADC */
1778 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1779 afe_write(sd, 0xc8, 0x40); /* phase control */
1780 }
1781
1782 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1783 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1784 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1785 } else {
1786 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1787 __func__, state->selected_input);
1788 }
1789 }
1790
1791 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1792 u32 input, u32 output, u32 config)
1793 {
1794 struct adv76xx_state *state = to_state(sd);
1795
1796 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1797 __func__, input, state->selected_input);
1798
1799 if (input == state->selected_input)
1800 return 0;
1801
1802 if (input > state->info->max_port)
1803 return -EINVAL;
1804
1805 state->selected_input = input;
1806
1807 disable_input(sd);
1808 select_input(sd);
1809 enable_input(sd);
1810
1811 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1812
1813 return 0;
1814 }
1815
1816 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1817 struct v4l2_subdev_pad_config *cfg,
1818 struct v4l2_subdev_mbus_code_enum *code)
1819 {
1820 struct adv76xx_state *state = to_state(sd);
1821
1822 if (code->index >= state->info->nformats)
1823 return -EINVAL;
1824
1825 code->code = state->info->formats[code->index].code;
1826
1827 return 0;
1828 }
1829
1830 static void adv76xx_fill_format(struct adv76xx_state *state,
1831 struct v4l2_mbus_framefmt *format)
1832 {
1833 memset(format, 0, sizeof(*format));
1834
1835 format->width = state->timings.bt.width;
1836 format->height = state->timings.bt.height;
1837 format->field = V4L2_FIELD_NONE;
1838 format->colorspace = V4L2_COLORSPACE_SRGB;
1839
1840 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1841 format->colorspace = (state->timings.bt.height <= 576) ?
1842 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1843 }
1844
1845 /*
1846 * Compute the op_ch_sel value required to obtain on the bus the component order
1847 * corresponding to the selected format taking into account bus reordering
1848 * applied by the board at the output of the device.
1849 *
1850 * The following table gives the op_ch_value from the format component order
1851 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1852 * adv76xx_bus_order value in row).
1853 *
1854 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1855 * ----------+-------------------------------------------------
1856 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1857 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1858 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1859 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1860 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1861 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1862 */
1863 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1864 {
1865 #define _SEL(a,b,c,d,e,f) { \
1866 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1867 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1868 #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1869
1870 static const unsigned int op_ch_sel[6][6] = {
1871 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1872 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1873 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1874 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1875 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1876 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1877 };
1878
1879 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1880 }
1881
1882 static void adv76xx_setup_format(struct adv76xx_state *state)
1883 {
1884 struct v4l2_subdev *sd = &state->sd;
1885
1886 io_write_clr_set(sd, 0x02, 0x02,
1887 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1888 io_write(sd, 0x03, state->format->op_format_sel |
1889 state->pdata.op_format_mode_sel);
1890 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1891 io_write_clr_set(sd, 0x05, 0x01,
1892 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1893 set_rgb_quantization_range(sd);
1894 }
1895
1896 static int adv76xx_get_format(struct v4l2_subdev *sd,
1897 struct v4l2_subdev_pad_config *cfg,
1898 struct v4l2_subdev_format *format)
1899 {
1900 struct adv76xx_state *state = to_state(sd);
1901
1902 if (format->pad != state->source_pad)
1903 return -EINVAL;
1904
1905 adv76xx_fill_format(state, &format->format);
1906
1907 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1908 struct v4l2_mbus_framefmt *fmt;
1909
1910 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1911 format->format.code = fmt->code;
1912 } else {
1913 format->format.code = state->format->code;
1914 }
1915
1916 return 0;
1917 }
1918
1919 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1920 struct v4l2_subdev_pad_config *cfg,
1921 struct v4l2_subdev_selection *sel)
1922 {
1923 struct adv76xx_state *state = to_state(sd);
1924
1925 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1926 return -EINVAL;
1927 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1928 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1929 return -EINVAL;
1930
1931 sel->r.left = 0;
1932 sel->r.top = 0;
1933 sel->r.width = state->timings.bt.width;
1934 sel->r.height = state->timings.bt.height;
1935
1936 return 0;
1937 }
1938
1939 static int adv76xx_set_format(struct v4l2_subdev *sd,
1940 struct v4l2_subdev_pad_config *cfg,
1941 struct v4l2_subdev_format *format)
1942 {
1943 struct adv76xx_state *state = to_state(sd);
1944 const struct adv76xx_format_info *info;
1945
1946 if (format->pad != state->source_pad)
1947 return -EINVAL;
1948
1949 info = adv76xx_format_info(state, format->format.code);
1950 if (info == NULL)
1951 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1952
1953 adv76xx_fill_format(state, &format->format);
1954 format->format.code = info->code;
1955
1956 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1957 struct v4l2_mbus_framefmt *fmt;
1958
1959 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1960 fmt->code = format->format.code;
1961 } else {
1962 state->format = info;
1963 adv76xx_setup_format(state);
1964 }
1965
1966 return 0;
1967 }
1968
1969 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1970 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1971 {
1972 struct adv76xx_state *state = to_state(sd);
1973
1974 if ((cec_read(sd, 0x11) & 0x01) == 0) {
1975 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1976 return;
1977 }
1978
1979 if (tx_raw_status & 0x02) {
1980 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
1981 __func__);
1982 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
1983 1, 0, 0, 0);
1984 }
1985 if (tx_raw_status & 0x04) {
1986 u8 status;
1987 u8 nack_cnt;
1988 u8 low_drive_cnt;
1989
1990 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
1991 /*
1992 * We set this status bit since this hardware performs
1993 * retransmissions.
1994 */
1995 status = CEC_TX_STATUS_MAX_RETRIES;
1996 nack_cnt = cec_read(sd, 0x14) & 0xf;
1997 if (nack_cnt)
1998 status |= CEC_TX_STATUS_NACK;
1999 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2000 if (low_drive_cnt)
2001 status |= CEC_TX_STATUS_LOW_DRIVE;
2002 cec_transmit_done(state->cec_adap, status,
2003 0, nack_cnt, low_drive_cnt, 0);
2004 return;
2005 }
2006 if (tx_raw_status & 0x01) {
2007 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2008 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2009 return;
2010 }
2011 }
2012
2013 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2014 {
2015 struct adv76xx_state *state = to_state(sd);
2016 u8 cec_irq;
2017
2018 /* cec controller */
2019 cec_irq = io_read(sd, 0x4d) & 0x0f;
2020 if (!cec_irq)
2021 return;
2022
2023 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2024 adv76xx_cec_tx_raw_status(sd, cec_irq);
2025 if (cec_irq & 0x08) {
2026 struct cec_msg msg;
2027
2028 msg.len = cec_read(sd, 0x25) & 0x1f;
2029 if (msg.len > 16)
2030 msg.len = 16;
2031
2032 if (msg.len) {
2033 u8 i;
2034
2035 for (i = 0; i < msg.len; i++)
2036 msg.msg[i] = cec_read(sd, i + 0x15);
2037 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2038 cec_received_msg(state->cec_adap, &msg);
2039 }
2040 }
2041
2042 /* note: the bit order is swapped between 0x4d and 0x4e */
2043 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2044 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2045 io_write(sd, 0x4e, cec_irq);
2046
2047 if (handled)
2048 *handled = true;
2049 }
2050
2051 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2052 {
2053 struct adv76xx_state *state = adap->priv;
2054 struct v4l2_subdev *sd = &state->sd;
2055
2056 if (!state->cec_enabled_adap && enable) {
2057 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2058 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2059 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2060 /* enabled irqs: */
2061 /* tx: ready */
2062 /* tx: arbitration lost */
2063 /* tx: retry timeout */
2064 /* rx: ready */
2065 io_write_clr_set(sd, 0x50, 0x0f, 0x0f);
2066 cec_write(sd, 0x26, 0x01); /* enable rx */
2067 } else if (state->cec_enabled_adap && !enable) {
2068 /* disable cec interrupts */
2069 io_write_clr_set(sd, 0x50, 0x0f, 0x00);
2070 /* disable address mask 1-3 */
2071 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2072 /* power down cec section */
2073 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2074 state->cec_valid_addrs = 0;
2075 }
2076 state->cec_enabled_adap = enable;
2077 adv76xx_s_detect_tx_5v_ctrl(sd);
2078 return 0;
2079 }
2080
2081 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2082 {
2083 struct adv76xx_state *state = adap->priv;
2084 struct v4l2_subdev *sd = &state->sd;
2085 unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2086
2087 if (!state->cec_enabled_adap)
2088 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2089
2090 if (addr == CEC_LOG_ADDR_INVALID) {
2091 cec_write_clr_set(sd, 0x27, 0x70, 0);
2092 state->cec_valid_addrs = 0;
2093 return 0;
2094 }
2095
2096 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2097 bool is_valid = state->cec_valid_addrs & (1 << i);
2098
2099 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2100 free_idx = i;
2101 if (is_valid && state->cec_addr[i] == addr)
2102 return 0;
2103 }
2104 if (i == ADV76XX_MAX_ADDRS) {
2105 i = free_idx;
2106 if (i == ADV76XX_MAX_ADDRS)
2107 return -ENXIO;
2108 }
2109 state->cec_addr[i] = addr;
2110 state->cec_valid_addrs |= 1 << i;
2111
2112 switch (i) {
2113 case 0:
2114 /* enable address mask 0 */
2115 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2116 /* set address for mask 0 */
2117 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2118 break;
2119 case 1:
2120 /* enable address mask 1 */
2121 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2122 /* set address for mask 1 */
2123 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2124 break;
2125 case 2:
2126 /* enable address mask 2 */
2127 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2128 /* set address for mask 1 */
2129 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2130 break;
2131 }
2132 return 0;
2133 }
2134
2135 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2136 u32 signal_free_time, struct cec_msg *msg)
2137 {
2138 struct adv76xx_state *state = adap->priv;
2139 struct v4l2_subdev *sd = &state->sd;
2140 u8 len = msg->len;
2141 unsigned int i;
2142
2143 /*
2144 * The number of retries is the number of attempts - 1, but retry
2145 * at least once. It's not clear if a value of 0 is allowed, so
2146 * let's do at least one retry.
2147 */
2148 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2149
2150 if (len > 16) {
2151 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2152 return -EINVAL;
2153 }
2154
2155 /* write data */
2156 for (i = 0; i < len; i++)
2157 cec_write(sd, i, msg->msg[i]);
2158
2159 /* set length (data + header) */
2160 cec_write(sd, 0x10, len);
2161 /* start transmit, enable tx */
2162 cec_write(sd, 0x11, 0x01);
2163 return 0;
2164 }
2165
2166 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2167 .adap_enable = adv76xx_cec_adap_enable,
2168 .adap_log_addr = adv76xx_cec_adap_log_addr,
2169 .adap_transmit = adv76xx_cec_adap_transmit,
2170 };
2171 #endif
2172
2173 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2174 {
2175 struct adv76xx_state *state = to_state(sd);
2176 const struct adv76xx_chip_info *info = state->info;
2177 const u8 irq_reg_0x43 = io_read(sd, 0x43);
2178 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2179 const u8 irq_reg_0x70 = io_read(sd, 0x70);
2180 u8 fmt_change_digital;
2181 u8 fmt_change;
2182 u8 tx_5v;
2183
2184 if (irq_reg_0x43)
2185 io_write(sd, 0x44, irq_reg_0x43);
2186 if (irq_reg_0x70)
2187 io_write(sd, 0x71, irq_reg_0x70);
2188 if (irq_reg_0x6b)
2189 io_write(sd, 0x6c, irq_reg_0x6b);
2190
2191 v4l2_dbg(2, debug, sd, "%s: ", __func__);
2192
2193 /* format change */
2194 fmt_change = irq_reg_0x43 & 0x98;
2195 fmt_change_digital = is_digital_input(sd)
2196 ? irq_reg_0x6b & info->fmt_change_digital_mask
2197 : 0;
2198
2199 if (fmt_change || fmt_change_digital) {
2200 v4l2_dbg(1, debug, sd,
2201 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2202 __func__, fmt_change, fmt_change_digital);
2203
2204 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2205
2206 if (handled)
2207 *handled = true;
2208 }
2209 /* HDMI/DVI mode */
2210 if (irq_reg_0x6b & 0x01) {
2211 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2212 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2213 set_rgb_quantization_range(sd);
2214 if (handled)
2215 *handled = true;
2216 }
2217
2218 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2219 /* cec */
2220 adv76xx_cec_isr(sd, handled);
2221 #endif
2222
2223 /* tx 5v detect */
2224 tx_5v = irq_reg_0x70 & info->cable_det_mask;
2225 if (tx_5v) {
2226 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2227 adv76xx_s_detect_tx_5v_ctrl(sd);
2228 if (handled)
2229 *handled = true;
2230 }
2231 return 0;
2232 }
2233
2234 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2235 {
2236 struct adv76xx_state *state = to_state(sd);
2237 u8 *data = NULL;
2238
2239 memset(edid->reserved, 0, sizeof(edid->reserved));
2240
2241 switch (edid->pad) {
2242 case ADV76XX_PAD_HDMI_PORT_A:
2243 case ADV7604_PAD_HDMI_PORT_B:
2244 case ADV7604_PAD_HDMI_PORT_C:
2245 case ADV7604_PAD_HDMI_PORT_D:
2246 if (state->edid.present & (1 << edid->pad))
2247 data = state->edid.edid;
2248 break;
2249 default:
2250 return -EINVAL;
2251 }
2252
2253 if (edid->start_block == 0 && edid->blocks == 0) {
2254 edid->blocks = data ? state->edid.blocks : 0;
2255 return 0;
2256 }
2257
2258 if (data == NULL)
2259 return -ENODATA;
2260
2261 if (edid->start_block >= state->edid.blocks)
2262 return -EINVAL;
2263
2264 if (edid->start_block + edid->blocks > state->edid.blocks)
2265 edid->blocks = state->edid.blocks - edid->start_block;
2266
2267 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2268
2269 return 0;
2270 }
2271
2272 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2273 {
2274 struct adv76xx_state *state = to_state(sd);
2275 const struct adv76xx_chip_info *info = state->info;
2276 unsigned int spa_loc;
2277 u16 pa;
2278 int err;
2279 int i;
2280
2281 memset(edid->reserved, 0, sizeof(edid->reserved));
2282
2283 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2284 return -EINVAL;
2285 if (edid->start_block != 0)
2286 return -EINVAL;
2287 if (edid->blocks == 0) {
2288 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2289 state->edid.present &= ~(1 << edid->pad);
2290 adv76xx_set_hpd(state, state->edid.present);
2291 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2292
2293 /* Fall back to a 16:9 aspect ratio */
2294 state->aspect_ratio.numerator = 16;
2295 state->aspect_ratio.denominator = 9;
2296
2297 if (!state->edid.present)
2298 state->edid.blocks = 0;
2299
2300 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2301 __func__, edid->pad, state->edid.present);
2302 return 0;
2303 }
2304 if (edid->blocks > 2) {
2305 edid->blocks = 2;
2306 return -E2BIG;
2307 }
2308 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2309 err = cec_phys_addr_validate(pa, &pa, NULL);
2310 if (err)
2311 return err;
2312
2313 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2314 __func__, edid->pad, state->edid.present);
2315
2316 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2317 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2318 adv76xx_set_hpd(state, 0);
2319 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2320
2321 /*
2322 * Return an error if no location of the source physical address
2323 * was found.
2324 */
2325 if (spa_loc == 0)
2326 return -EINVAL;
2327
2328 switch (edid->pad) {
2329 case ADV76XX_PAD_HDMI_PORT_A:
2330 state->spa_port_a[0] = edid->edid[spa_loc];
2331 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2332 break;
2333 case ADV7604_PAD_HDMI_PORT_B:
2334 rep_write(sd, 0x70, edid->edid[spa_loc]);
2335 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2336 break;
2337 case ADV7604_PAD_HDMI_PORT_C:
2338 rep_write(sd, 0x72, edid->edid[spa_loc]);
2339 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2340 break;
2341 case ADV7604_PAD_HDMI_PORT_D:
2342 rep_write(sd, 0x74, edid->edid[spa_loc]);
2343 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2344 break;
2345 default:
2346 return -EINVAL;
2347 }
2348
2349 if (info->type == ADV7604) {
2350 rep_write(sd, 0x76, spa_loc & 0xff);
2351 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2352 } else {
2353 /* ADV7612 Software Manual Rev. A, p. 15 */
2354 rep_write(sd, 0x70, spa_loc & 0xff);
2355 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2356 }
2357
2358 edid->edid[spa_loc] = state->spa_port_a[0];
2359 edid->edid[spa_loc + 1] = state->spa_port_a[1];
2360
2361 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2362 state->edid.blocks = edid->blocks;
2363 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2364 edid->edid[0x16]);
2365 state->edid.present |= 1 << edid->pad;
2366
2367 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2368 if (err < 0) {
2369 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2370 return err;
2371 }
2372
2373 /* adv76xx calculates the checksums and enables I2C access to internal
2374 EDID RAM from DDC port. */
2375 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2376
2377 for (i = 0; i < 1000; i++) {
2378 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2379 break;
2380 mdelay(1);
2381 }
2382 if (i == 1000) {
2383 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2384 return -EIO;
2385 }
2386 cec_s_phys_addr(state->cec_adap, pa, false);
2387
2388 /* enable hotplug after 100 ms */
2389 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2390 return 0;
2391 }
2392
2393 /*********** avi info frame CEA-861-E **************/
2394
2395 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2396 { "AVI", 0x01, 0xe0, 0x00 },
2397 { "Audio", 0x02, 0xe3, 0x1c },
2398 { "SDP", 0x04, 0xe6, 0x2a },
2399 { "Vendor", 0x10, 0xec, 0x54 }
2400 };
2401
2402 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2403 union hdmi_infoframe *frame)
2404 {
2405 uint8_t buffer[32];
2406 u8 len;
2407 int i;
2408
2409 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2410 v4l2_info(sd, "%s infoframe not received\n",
2411 adv76xx_cri[index].desc);
2412 return -ENOENT;
2413 }
2414
2415 for (i = 0; i < 3; i++)
2416 buffer[i] = infoframe_read(sd,
2417 adv76xx_cri[index].head_addr + i);
2418
2419 len = buffer[2] + 1;
2420
2421 if (len + 3 > sizeof(buffer)) {
2422 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2423 adv76xx_cri[index].desc, len);
2424 return -ENOENT;
2425 }
2426
2427 for (i = 0; i < len; i++)
2428 buffer[i + 3] = infoframe_read(sd,
2429 adv76xx_cri[index].payload_addr + i);
2430
2431 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2432 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2433 adv76xx_cri[index].desc);
2434 return -ENOENT;
2435 }
2436 return 0;
2437 }
2438
2439 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2440 {
2441 int i;
2442
2443 if (!is_hdmi(sd)) {
2444 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2445 return;
2446 }
2447
2448 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2449 union hdmi_infoframe frame;
2450 struct i2c_client *client = v4l2_get_subdevdata(sd);
2451
2452 if (adv76xx_read_infoframe(sd, i, &frame))
2453 return;
2454 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2455 }
2456 }
2457
2458 static int adv76xx_log_status(struct v4l2_subdev *sd)
2459 {
2460 struct adv76xx_state *state = to_state(sd);
2461 const struct adv76xx_chip_info *info = state->info;
2462 struct v4l2_dv_timings timings;
2463 struct stdi_readback stdi;
2464 u8 reg_io_0x02 = io_read(sd, 0x02);
2465 u8 edid_enabled;
2466 u8 cable_det;
2467
2468 static const char * const csc_coeff_sel_rb[16] = {
2469 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2470 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2471 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2472 "reserved", "reserved", "reserved", "reserved", "manual"
2473 };
2474 static const char * const input_color_space_txt[16] = {
2475 "RGB limited range (16-235)", "RGB full range (0-255)",
2476 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2477 "xvYCC Bt.601", "xvYCC Bt.709",
2478 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2479 "invalid", "invalid", "invalid", "invalid", "invalid",
2480 "invalid", "invalid", "automatic"
2481 };
2482 static const char * const hdmi_color_space_txt[16] = {
2483 "RGB limited range (16-235)", "RGB full range (0-255)",
2484 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2485 "xvYCC Bt.601", "xvYCC Bt.709",
2486 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2487 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2488 "invalid", "invalid", "invalid"
2489 };
2490 static const char * const rgb_quantization_range_txt[] = {
2491 "Automatic",
2492 "RGB limited range (16-235)",
2493 "RGB full range (0-255)",
2494 };
2495 static const char * const deep_color_mode_txt[4] = {
2496 "8-bits per channel",
2497 "10-bits per channel",
2498 "12-bits per channel",
2499 "16-bits per channel (not supported)"
2500 };
2501
2502 v4l2_info(sd, "-----Chip status-----\n");
2503 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2504 edid_enabled = rep_read(sd, info->edid_status_reg);
2505 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2506 ((edid_enabled & 0x01) ? "Yes" : "No"),
2507 ((edid_enabled & 0x02) ? "Yes" : "No"),
2508 ((edid_enabled & 0x04) ? "Yes" : "No"),
2509 ((edid_enabled & 0x08) ? "Yes" : "No"));
2510 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2511 "enabled" : "disabled");
2512 if (state->cec_enabled_adap) {
2513 int i;
2514
2515 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2516 bool is_valid = state->cec_valid_addrs & (1 << i);
2517
2518 if (is_valid)
2519 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2520 state->cec_addr[i]);
2521 }
2522 }
2523
2524 v4l2_info(sd, "-----Signal status-----\n");
2525 cable_det = info->read_cable_det(sd);
2526 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2527 ((cable_det & 0x01) ? "Yes" : "No"),
2528 ((cable_det & 0x02) ? "Yes" : "No"),
2529 ((cable_det & 0x04) ? "Yes" : "No"),
2530 ((cable_det & 0x08) ? "Yes" : "No"));
2531 v4l2_info(sd, "TMDS signal detected: %s\n",
2532 no_signal_tmds(sd) ? "false" : "true");
2533 v4l2_info(sd, "TMDS signal locked: %s\n",
2534 no_lock_tmds(sd) ? "false" : "true");
2535 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2536 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2537 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2538 v4l2_info(sd, "CP free run: %s\n",
2539 (in_free_run(sd)) ? "on" : "off");
2540 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2541 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2542 (io_read(sd, 0x01) & 0x70) >> 4);
2543
2544 v4l2_info(sd, "-----Video Timings-----\n");
2545 if (read_stdi(sd, &stdi))
2546 v4l2_info(sd, "STDI: not locked\n");
2547 else
2548 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2549 stdi.lcf, stdi.bl, stdi.lcvs,
2550 stdi.interlaced ? "interlaced" : "progressive",
2551 stdi.hs_pol, stdi.vs_pol);
2552 if (adv76xx_query_dv_timings(sd, &timings))
2553 v4l2_info(sd, "No video detected\n");
2554 else
2555 v4l2_print_dv_timings(sd->name, "Detected format: ",
2556 &timings, true);
2557 v4l2_print_dv_timings(sd->name, "Configured format: ",
2558 &state->timings, true);
2559
2560 if (no_signal(sd))
2561 return 0;
2562
2563 v4l2_info(sd, "-----Color space-----\n");
2564 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2565 rgb_quantization_range_txt[state->rgb_quantization_range]);
2566 v4l2_info(sd, "Input color space: %s\n",
2567 input_color_space_txt[reg_io_0x02 >> 4]);
2568 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2569 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2570 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2571 "(16-235)" : "(0-255)",
2572 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2573 v4l2_info(sd, "Color space conversion: %s\n",
2574 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2575
2576 if (!is_digital_input(sd))
2577 return 0;
2578
2579 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2580 v4l2_info(sd, "Digital video port selected: %c\n",
2581 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2582 v4l2_info(sd, "HDCP encrypted content: %s\n",
2583 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2584 v4l2_info(sd, "HDCP keys read: %s%s\n",
2585 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2586 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2587 if (is_hdmi(sd)) {
2588 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2589 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2590 bool audio_mute = io_read(sd, 0x65) & 0x40;
2591
2592 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2593 audio_pll_locked ? "locked" : "not locked",
2594 audio_sample_packet_detect ? "detected" : "not detected",
2595 audio_mute ? "muted" : "enabled");
2596 if (audio_pll_locked && audio_sample_packet_detect) {
2597 v4l2_info(sd, "Audio format: %s\n",
2598 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2599 }
2600 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2601 (hdmi_read(sd, 0x5c) << 8) +
2602 (hdmi_read(sd, 0x5d) & 0xf0));
2603 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2604 (hdmi_read(sd, 0x5e) << 8) +
2605 hdmi_read(sd, 0x5f));
2606 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2607
2608 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2609 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2610
2611 adv76xx_log_infoframes(sd);
2612 }
2613
2614 return 0;
2615 }
2616
2617 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2618 struct v4l2_fh *fh,
2619 struct v4l2_event_subscription *sub)
2620 {
2621 switch (sub->type) {
2622 case V4L2_EVENT_SOURCE_CHANGE:
2623 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2624 case V4L2_EVENT_CTRL:
2625 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2626 default:
2627 return -EINVAL;
2628 }
2629 }
2630
2631 static int adv76xx_registered(struct v4l2_subdev *sd)
2632 {
2633 struct adv76xx_state *state = to_state(sd);
2634 struct i2c_client *client = v4l2_get_subdevdata(sd);
2635 int err;
2636
2637 err = cec_register_adapter(state->cec_adap, &client->dev);
2638 if (err)
2639 cec_delete_adapter(state->cec_adap);
2640 return err;
2641 }
2642
2643 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2644 {
2645 struct adv76xx_state *state = to_state(sd);
2646
2647 cec_unregister_adapter(state->cec_adap);
2648 }
2649
2650 /* ----------------------------------------------------------------------- */
2651
2652 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2653 .s_ctrl = adv76xx_s_ctrl,
2654 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2655 };
2656
2657 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2658 .log_status = adv76xx_log_status,
2659 .interrupt_service_routine = adv76xx_isr,
2660 .subscribe_event = adv76xx_subscribe_event,
2661 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2662 #ifdef CONFIG_VIDEO_ADV_DEBUG
2663 .g_register = adv76xx_g_register,
2664 .s_register = adv76xx_s_register,
2665 #endif
2666 };
2667
2668 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2669 .s_routing = adv76xx_s_routing,
2670 .g_input_status = adv76xx_g_input_status,
2671 .s_dv_timings = adv76xx_s_dv_timings,
2672 .g_dv_timings = adv76xx_g_dv_timings,
2673 .query_dv_timings = adv76xx_query_dv_timings,
2674 };
2675
2676 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2677 .enum_mbus_code = adv76xx_enum_mbus_code,
2678 .get_selection = adv76xx_get_selection,
2679 .get_fmt = adv76xx_get_format,
2680 .set_fmt = adv76xx_set_format,
2681 .get_edid = adv76xx_get_edid,
2682 .set_edid = adv76xx_set_edid,
2683 .dv_timings_cap = adv76xx_dv_timings_cap,
2684 .enum_dv_timings = adv76xx_enum_dv_timings,
2685 };
2686
2687 static const struct v4l2_subdev_ops adv76xx_ops = {
2688 .core = &adv76xx_core_ops,
2689 .video = &adv76xx_video_ops,
2690 .pad = &adv76xx_pad_ops,
2691 };
2692
2693 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2694 .registered = adv76xx_registered,
2695 .unregistered = adv76xx_unregistered,
2696 };
2697
2698 /* -------------------------- custom ctrls ---------------------------------- */
2699
2700 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2701 .ops = &adv76xx_ctrl_ops,
2702 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2703 .name = "Analog Sampling Phase",
2704 .type = V4L2_CTRL_TYPE_INTEGER,
2705 .min = 0,
2706 .max = 0x1f,
2707 .step = 1,
2708 .def = 0,
2709 };
2710
2711 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2712 .ops = &adv76xx_ctrl_ops,
2713 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2714 .name = "Free Running Color, Manual",
2715 .type = V4L2_CTRL_TYPE_BOOLEAN,
2716 .min = false,
2717 .max = true,
2718 .step = 1,
2719 .def = false,
2720 };
2721
2722 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2723 .ops = &adv76xx_ctrl_ops,
2724 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2725 .name = "Free Running Color",
2726 .type = V4L2_CTRL_TYPE_INTEGER,
2727 .min = 0x0,
2728 .max = 0xffffff,
2729 .step = 0x1,
2730 .def = 0x0,
2731 };
2732
2733 /* ----------------------------------------------------------------------- */
2734
2735 static int adv76xx_core_init(struct v4l2_subdev *sd)
2736 {
2737 struct adv76xx_state *state = to_state(sd);
2738 const struct adv76xx_chip_info *info = state->info;
2739 struct adv76xx_platform_data *pdata = &state->pdata;
2740
2741 hdmi_write(sd, 0x48,
2742 (pdata->disable_pwrdnb ? 0x80 : 0) |
2743 (pdata->disable_cable_det_rst ? 0x40 : 0));
2744
2745 disable_input(sd);
2746
2747 if (pdata->default_input >= 0 &&
2748 pdata->default_input < state->source_pad) {
2749 state->selected_input = pdata->default_input;
2750 select_input(sd);
2751 enable_input(sd);
2752 }
2753
2754 /* power */
2755 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2756 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2757 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2758
2759 /* video format */
2760 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2761 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2762 pdata->insert_av_codes << 2 |
2763 pdata->replicate_av_codes << 1);
2764 adv76xx_setup_format(state);
2765
2766 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2767
2768 /* VS, HS polarities */
2769 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2770 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2771
2772 /* Adjust drive strength */
2773 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2774 pdata->dr_str_clk << 2 |
2775 pdata->dr_str_sync);
2776
2777 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2778 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2779 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2780 ADI recommended setting [REF_01, c. 2.3.3] */
2781 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2782 ADI recommended setting [REF_01, c. 2.3.3] */
2783 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2784 for digital formats */
2785
2786 /* HDMI audio */
2787 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2788 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2789 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2790
2791 /* TODO from platform data */
2792 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2793
2794 if (adv76xx_has_afe(state)) {
2795 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2796 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2797 }
2798
2799 /* interrupts */
2800 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2801 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2802 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2803 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2804 info->setup_irqs(sd);
2805
2806 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2807 }
2808
2809 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2810 {
2811 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2812 }
2813
2814 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2815 {
2816 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2817 }
2818
2819 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2820 {
2821 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2822 }
2823
2824 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2825 {
2826 unsigned int i;
2827
2828 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2829 if (state->i2c_clients[i])
2830 i2c_unregister_device(state->i2c_clients[i]);
2831 }
2832 }
2833
2834 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2835 u8 addr, u8 io_reg)
2836 {
2837 struct i2c_client *client = v4l2_get_subdevdata(sd);
2838
2839 if (addr)
2840 io_write(sd, io_reg, addr << 1);
2841 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2842 }
2843
2844 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2845 /* reset ADI recommended settings for HDMI: */
2846 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2847 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2848 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2849 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2850 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2851 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2852 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2853 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2854 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2855 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2856 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2857 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2858 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2859
2860 /* set ADI recommended settings for digitizer */
2861 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2862 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2863 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2864 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2865 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2866 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2867
2868 { ADV76XX_REG_SEQ_TERM, 0 },
2869 };
2870
2871 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2872 /* set ADI recommended settings for HDMI: */
2873 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2874 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2875 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2876 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2877 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2878 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2879 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2880 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2881 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2882 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2883 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2884 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2885
2886 /* reset ADI recommended settings for digitizer */
2887 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2888 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2889 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2890
2891 { ADV76XX_REG_SEQ_TERM, 0 },
2892 };
2893
2894 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2895 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2896 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2897 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2898 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2899 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2900 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2901 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2902 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2903 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2904 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2905 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2906 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2907
2908 { ADV76XX_REG_SEQ_TERM, 0 },
2909 };
2910
2911 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2912 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2913 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2914 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2915 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2916 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2917 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2918 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2919 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2920 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2921 { ADV76XX_REG_SEQ_TERM, 0 },
2922 };
2923
2924 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2925 [ADV7604] = {
2926 .type = ADV7604,
2927 .has_afe = true,
2928 .max_port = ADV7604_PAD_VGA_COMP,
2929 .num_dv_ports = 4,
2930 .edid_enable_reg = 0x77,
2931 .edid_status_reg = 0x7d,
2932 .lcf_reg = 0xb3,
2933 .tdms_lock_mask = 0xe0,
2934 .cable_det_mask = 0x1e,
2935 .fmt_change_digital_mask = 0xc1,
2936 .cp_csc = 0xfc,
2937 .formats = adv7604_formats,
2938 .nformats = ARRAY_SIZE(adv7604_formats),
2939 .set_termination = adv7604_set_termination,
2940 .setup_irqs = adv7604_setup_irqs,
2941 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2942 .read_cable_det = adv7604_read_cable_det,
2943 .recommended_settings = {
2944 [0] = adv7604_recommended_settings_afe,
2945 [1] = adv7604_recommended_settings_hdmi,
2946 },
2947 .num_recommended_settings = {
2948 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2949 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2950 },
2951 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2952 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2953 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2954 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2955 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2956 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2957 BIT(ADV7604_PAGE_VDP),
2958 .linewidth_mask = 0xfff,
2959 .field0_height_mask = 0xfff,
2960 .field1_height_mask = 0xfff,
2961 .hfrontporch_mask = 0x3ff,
2962 .hsync_mask = 0x3ff,
2963 .hbackporch_mask = 0x3ff,
2964 .field0_vfrontporch_mask = 0x1fff,
2965 .field0_vsync_mask = 0x1fff,
2966 .field0_vbackporch_mask = 0x1fff,
2967 .field1_vfrontporch_mask = 0x1fff,
2968 .field1_vsync_mask = 0x1fff,
2969 .field1_vbackporch_mask = 0x1fff,
2970 },
2971 [ADV7611] = {
2972 .type = ADV7611,
2973 .has_afe = false,
2974 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2975 .num_dv_ports = 1,
2976 .edid_enable_reg = 0x74,
2977 .edid_status_reg = 0x76,
2978 .lcf_reg = 0xa3,
2979 .tdms_lock_mask = 0x43,
2980 .cable_det_mask = 0x01,
2981 .fmt_change_digital_mask = 0x03,
2982 .cp_csc = 0xf4,
2983 .formats = adv7611_formats,
2984 .nformats = ARRAY_SIZE(adv7611_formats),
2985 .set_termination = adv7611_set_termination,
2986 .setup_irqs = adv7611_setup_irqs,
2987 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2988 .read_cable_det = adv7611_read_cable_det,
2989 .recommended_settings = {
2990 [1] = adv7611_recommended_settings_hdmi,
2991 },
2992 .num_recommended_settings = {
2993 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2994 },
2995 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2996 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2997 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2998 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2999 .linewidth_mask = 0x1fff,
3000 .field0_height_mask = 0x1fff,
3001 .field1_height_mask = 0x1fff,
3002 .hfrontporch_mask = 0x1fff,
3003 .hsync_mask = 0x1fff,
3004 .hbackporch_mask = 0x1fff,
3005 .field0_vfrontporch_mask = 0x3fff,
3006 .field0_vsync_mask = 0x3fff,
3007 .field0_vbackporch_mask = 0x3fff,
3008 .field1_vfrontporch_mask = 0x3fff,
3009 .field1_vsync_mask = 0x3fff,
3010 .field1_vbackporch_mask = 0x3fff,
3011 },
3012 [ADV7612] = {
3013 .type = ADV7612,
3014 .has_afe = false,
3015 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
3016 .num_dv_ports = 1, /* normally 2 */
3017 .edid_enable_reg = 0x74,
3018 .edid_status_reg = 0x76,
3019 .lcf_reg = 0xa3,
3020 .tdms_lock_mask = 0x43,
3021 .cable_det_mask = 0x01,
3022 .fmt_change_digital_mask = 0x03,
3023 .cp_csc = 0xf4,
3024 .formats = adv7612_formats,
3025 .nformats = ARRAY_SIZE(adv7612_formats),
3026 .set_termination = adv7611_set_termination,
3027 .setup_irqs = adv7612_setup_irqs,
3028 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3029 .read_cable_det = adv7612_read_cable_det,
3030 .recommended_settings = {
3031 [1] = adv7612_recommended_settings_hdmi,
3032 },
3033 .num_recommended_settings = {
3034 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3035 },
3036 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3037 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3038 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3039 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3040 .linewidth_mask = 0x1fff,
3041 .field0_height_mask = 0x1fff,
3042 .field1_height_mask = 0x1fff,
3043 .hfrontporch_mask = 0x1fff,
3044 .hsync_mask = 0x1fff,
3045 .hbackporch_mask = 0x1fff,
3046 .field0_vfrontporch_mask = 0x3fff,
3047 .field0_vsync_mask = 0x3fff,
3048 .field0_vbackporch_mask = 0x3fff,
3049 .field1_vfrontporch_mask = 0x3fff,
3050 .field1_vsync_mask = 0x3fff,
3051 .field1_vbackporch_mask = 0x3fff,
3052 },
3053 };
3054
3055 static const struct i2c_device_id adv76xx_i2c_id[] = {
3056 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3057 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3058 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3059 { }
3060 };
3061 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3062
3063 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3064 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3065 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3066 { }
3067 };
3068 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3069
3070 static int adv76xx_parse_dt(struct adv76xx_state *state)
3071 {
3072 struct v4l2_of_endpoint bus_cfg;
3073 struct device_node *endpoint;
3074 struct device_node *np;
3075 unsigned int flags;
3076 int ret;
3077 u32 v;
3078
3079 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3080
3081 /* Parse the endpoint. */
3082 endpoint = of_graph_get_next_endpoint(np, NULL);
3083 if (!endpoint)
3084 return -EINVAL;
3085
3086 ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg);
3087 if (ret) {
3088 of_node_put(endpoint);
3089 return ret;
3090 }
3091
3092 of_node_put(endpoint);
3093
3094 if (!of_property_read_u32(np, "default-input", &v))
3095 state->pdata.default_input = v;
3096 else
3097 state->pdata.default_input = -1;
3098
3099 flags = bus_cfg.bus.parallel.flags;
3100
3101 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3102 state->pdata.inv_hs_pol = 1;
3103
3104 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3105 state->pdata.inv_vs_pol = 1;
3106
3107 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3108 state->pdata.inv_llc_pol = 1;
3109
3110 if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3111 state->pdata.insert_av_codes = 1;
3112
3113 /* Disable the interrupt for now as no DT-based board uses it. */
3114 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
3115
3116 /* Use the default I2C addresses. */
3117 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
3118 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
3119 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
3120 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
3121 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
3122 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
3123 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
3124 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
3125 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
3126 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
3127 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
3128 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
3129
3130 /* Hardcode the remaining platform data fields. */
3131 state->pdata.disable_pwrdnb = 0;
3132 state->pdata.disable_cable_det_rst = 0;
3133 state->pdata.blank_data = 1;
3134 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3135 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3136
3137 return 0;
3138 }
3139
3140 static const struct regmap_config adv76xx_regmap_cnf[] = {
3141 {
3142 .name = "io",
3143 .reg_bits = 8,
3144 .val_bits = 8,
3145
3146 .max_register = 0xff,
3147 .cache_type = REGCACHE_NONE,
3148 },
3149 {
3150 .name = "avlink",
3151 .reg_bits = 8,
3152 .val_bits = 8,
3153
3154 .max_register = 0xff,
3155 .cache_type = REGCACHE_NONE,
3156 },
3157 {
3158 .name = "cec",
3159 .reg_bits = 8,
3160 .val_bits = 8,
3161
3162 .max_register = 0xff,
3163 .cache_type = REGCACHE_NONE,
3164 },
3165 {
3166 .name = "infoframe",
3167 .reg_bits = 8,
3168 .val_bits = 8,
3169
3170 .max_register = 0xff,
3171 .cache_type = REGCACHE_NONE,
3172 },
3173 {
3174 .name = "esdp",
3175 .reg_bits = 8,
3176 .val_bits = 8,
3177
3178 .max_register = 0xff,
3179 .cache_type = REGCACHE_NONE,
3180 },
3181 {
3182 .name = "epp",
3183 .reg_bits = 8,
3184 .val_bits = 8,
3185
3186 .max_register = 0xff,
3187 .cache_type = REGCACHE_NONE,
3188 },
3189 {
3190 .name = "afe",
3191 .reg_bits = 8,
3192 .val_bits = 8,
3193
3194 .max_register = 0xff,
3195 .cache_type = REGCACHE_NONE,
3196 },
3197 {
3198 .name = "rep",
3199 .reg_bits = 8,
3200 .val_bits = 8,
3201
3202 .max_register = 0xff,
3203 .cache_type = REGCACHE_NONE,
3204 },
3205 {
3206 .name = "edid",
3207 .reg_bits = 8,
3208 .val_bits = 8,
3209
3210 .max_register = 0xff,
3211 .cache_type = REGCACHE_NONE,
3212 },
3213
3214 {
3215 .name = "hdmi",
3216 .reg_bits = 8,
3217 .val_bits = 8,
3218
3219 .max_register = 0xff,
3220 .cache_type = REGCACHE_NONE,
3221 },
3222 {
3223 .name = "test",
3224 .reg_bits = 8,
3225 .val_bits = 8,
3226
3227 .max_register = 0xff,
3228 .cache_type = REGCACHE_NONE,
3229 },
3230 {
3231 .name = "cp",
3232 .reg_bits = 8,
3233 .val_bits = 8,
3234
3235 .max_register = 0xff,
3236 .cache_type = REGCACHE_NONE,
3237 },
3238 {
3239 .name = "vdp",
3240 .reg_bits = 8,
3241 .val_bits = 8,
3242
3243 .max_register = 0xff,
3244 .cache_type = REGCACHE_NONE,
3245 },
3246 };
3247
3248 static int configure_regmap(struct adv76xx_state *state, int region)
3249 {
3250 int err;
3251
3252 if (!state->i2c_clients[region])
3253 return -ENODEV;
3254
3255 state->regmap[region] =
3256 devm_regmap_init_i2c(state->i2c_clients[region],
3257 &adv76xx_regmap_cnf[region]);
3258
3259 if (IS_ERR(state->regmap[region])) {
3260 err = PTR_ERR(state->regmap[region]);
3261 v4l_err(state->i2c_clients[region],
3262 "Error initializing regmap %d with error %d\n",
3263 region, err);
3264 return -EINVAL;
3265 }
3266
3267 return 0;
3268 }
3269
3270 static int configure_regmaps(struct adv76xx_state *state)
3271 {
3272 int i, err;
3273
3274 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3275 err = configure_regmap(state, i);
3276 if (err && (err != -ENODEV))
3277 return err;
3278 }
3279 return 0;
3280 }
3281
3282 static void adv76xx_reset(struct adv76xx_state *state)
3283 {
3284 if (state->reset_gpio) {
3285 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3286 gpiod_set_value_cansleep(state->reset_gpio, 0);
3287 usleep_range(5000, 10000);
3288 gpiod_set_value_cansleep(state->reset_gpio, 1);
3289 /* It is recommended to wait 5 ms after the low pulse before */
3290 /* an I2C write is performed to the ADV76XX. */
3291 usleep_range(5000, 10000);
3292 }
3293 }
3294
3295 static int adv76xx_probe(struct i2c_client *client,
3296 const struct i2c_device_id *id)
3297 {
3298 static const struct v4l2_dv_timings cea640x480 =
3299 V4L2_DV_BT_CEA_640X480P59_94;
3300 struct adv76xx_state *state;
3301 struct v4l2_ctrl_handler *hdl;
3302 struct v4l2_ctrl *ctrl;
3303 struct v4l2_subdev *sd;
3304 unsigned int i;
3305 unsigned int val, val2;
3306 int err;
3307
3308 /* Check if the adapter supports the needed features */
3309 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3310 return -EIO;
3311 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3312 client->addr << 1);
3313
3314 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3315 if (!state) {
3316 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
3317 return -ENOMEM;
3318 }
3319
3320 state->i2c_clients[ADV76XX_PAGE_IO] = client;
3321
3322 /* initialize variables */
3323 state->restart_stdi_once = true;
3324 state->selected_input = ~0;
3325
3326 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3327 const struct of_device_id *oid;
3328
3329 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3330 state->info = oid->data;
3331
3332 err = adv76xx_parse_dt(state);
3333 if (err < 0) {
3334 v4l_err(client, "DT parsing error\n");
3335 return err;
3336 }
3337 } else if (client->dev.platform_data) {
3338 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3339
3340 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3341 state->pdata = *pdata;
3342 } else {
3343 v4l_err(client, "No platform data!\n");
3344 return -ENODEV;
3345 }
3346
3347 /* Request GPIOs. */
3348 for (i = 0; i < state->info->num_dv_ports; ++i) {
3349 state->hpd_gpio[i] =
3350 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3351 GPIOD_OUT_LOW);
3352 if (IS_ERR(state->hpd_gpio[i]))
3353 return PTR_ERR(state->hpd_gpio[i]);
3354
3355 if (state->hpd_gpio[i])
3356 v4l_info(client, "Handling HPD %u GPIO\n", i);
3357 }
3358 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3359 GPIOD_OUT_HIGH);
3360 if (IS_ERR(state->reset_gpio))
3361 return PTR_ERR(state->reset_gpio);
3362
3363 adv76xx_reset(state);
3364
3365 state->timings = cea640x480;
3366 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3367
3368 sd = &state->sd;
3369 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3370 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3371 id->name, i2c_adapter_id(client->adapter),
3372 client->addr);
3373 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3374 sd->internal_ops = &adv76xx_int_ops;
3375
3376 /* Configure IO Regmap region */
3377 err = configure_regmap(state, ADV76XX_PAGE_IO);
3378
3379 if (err) {
3380 v4l2_err(sd, "Error configuring IO regmap region\n");
3381 return -ENODEV;
3382 }
3383
3384 /*
3385 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3386 * identifies the revision, while on ADV7611 it identifies the model as
3387 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3388 */
3389 switch (state->info->type) {
3390 case ADV7604:
3391 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3392 if (err) {
3393 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3394 return -ENODEV;
3395 }
3396 if (val != 0x68) {
3397 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3398 client->addr << 1);
3399 return -ENODEV;
3400 }
3401 break;
3402 case ADV7611:
3403 case ADV7612:
3404 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3405 0xea,
3406 &val);
3407 if (err) {
3408 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3409 return -ENODEV;
3410 }
3411 val2 = val << 8;
3412 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3413 0xeb,
3414 &val);
3415 if (err) {
3416 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3417 return -ENODEV;
3418 }
3419 val |= val2;
3420 if ((state->info->type == ADV7611 && val != 0x2051) ||
3421 (state->info->type == ADV7612 && val != 0x2041)) {
3422 v4l2_err(sd, "not an adv761x on address 0x%x\n",
3423 client->addr << 1);
3424 return -ENODEV;
3425 }
3426 break;
3427 }
3428
3429 /* control handlers */
3430 hdl = &state->hdl;
3431 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3432
3433 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3434 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3435 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3436 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3437 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3438 V4L2_CID_SATURATION, 0, 255, 1, 128);
3439 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3440 V4L2_CID_HUE, 0, 128, 1, 0);
3441 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3442 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3443 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3444 if (ctrl)
3445 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3446
3447 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3448 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3449 (1 << state->info->num_dv_ports) - 1, 0, 0);
3450 state->rgb_quantization_range_ctrl =
3451 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3452 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3453 0, V4L2_DV_RGB_RANGE_AUTO);
3454
3455 /* custom controls */
3456 if (adv76xx_has_afe(state))
3457 state->analog_sampling_phase_ctrl =
3458 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3459 state->free_run_color_manual_ctrl =
3460 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3461 state->free_run_color_ctrl =
3462 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3463
3464 sd->ctrl_handler = hdl;
3465 if (hdl->error) {
3466 err = hdl->error;
3467 goto err_hdl;
3468 }
3469 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3470 err = -ENODEV;
3471 goto err_hdl;
3472 }
3473
3474 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3475 if (!(BIT(i) & state->info->page_mask))
3476 continue;
3477
3478 state->i2c_clients[i] =
3479 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
3480 0xf2 + i);
3481 if (state->i2c_clients[i] == NULL) {
3482 err = -ENOMEM;
3483 v4l2_err(sd, "failed to create i2c client %u\n", i);
3484 goto err_i2c;
3485 }
3486 }
3487
3488 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3489 adv76xx_delayed_work_enable_hotplug);
3490
3491 state->source_pad = state->info->num_dv_ports
3492 + (state->info->has_afe ? 2 : 0);
3493 for (i = 0; i < state->source_pad; ++i)
3494 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3495 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3496
3497 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3498 state->pads);
3499 if (err)
3500 goto err_work_queues;
3501
3502 /* Configure regmaps */
3503 err = configure_regmaps(state);
3504 if (err)
3505 goto err_entity;
3506
3507 err = adv76xx_core_init(sd);
3508 if (err)
3509 goto err_entity;
3510
3511 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3512 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3513 state, dev_name(&client->dev),
3514 CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
3515 CEC_CAP_PASSTHROUGH | CEC_CAP_RC, ADV76XX_MAX_ADDRS);
3516 err = PTR_ERR_OR_ZERO(state->cec_adap);
3517 if (err)
3518 goto err_entity;
3519 #endif
3520
3521 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3522 client->addr << 1, client->adapter->name);
3523
3524 err = v4l2_async_register_subdev(sd);
3525 if (err)
3526 goto err_entity;
3527
3528 return 0;
3529
3530 err_entity:
3531 media_entity_cleanup(&sd->entity);
3532 err_work_queues:
3533 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3534 err_i2c:
3535 adv76xx_unregister_clients(state);
3536 err_hdl:
3537 v4l2_ctrl_handler_free(hdl);
3538 return err;
3539 }
3540
3541 /* ----------------------------------------------------------------------- */
3542
3543 static int adv76xx_remove(struct i2c_client *client)
3544 {
3545 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3546 struct adv76xx_state *state = to_state(sd);
3547
3548 /* disable interrupts */
3549 io_write(sd, 0x40, 0);
3550 io_write(sd, 0x41, 0);
3551 io_write(sd, 0x46, 0);
3552 io_write(sd, 0x6e, 0);
3553 io_write(sd, 0x73, 0);
3554
3555 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3556 v4l2_async_unregister_subdev(sd);
3557 media_entity_cleanup(&sd->entity);
3558 adv76xx_unregister_clients(to_state(sd));
3559 v4l2_ctrl_handler_free(sd->ctrl_handler);
3560 return 0;
3561 }
3562
3563 /* ----------------------------------------------------------------------- */
3564
3565 static struct i2c_driver adv76xx_driver = {
3566 .driver = {
3567 .name = "adv7604",
3568 .of_match_table = of_match_ptr(adv76xx_of_id),
3569 },
3570 .probe = adv76xx_probe,
3571 .remove = adv76xx_remove,
3572 .id_table = adv76xx_i2c_id,
3573 };
3574
3575 module_i2c_driver(adv76xx_driver);
Linux with added FPC-III support