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sh_eth: R8A7740 supports packet shecksumming
[linux/fpc-iii.git] / drivers / media / i2c / tc358743.c
blob1e3a0dd2238cf4aa1c43705ca3493d3652d79967
1 /*
2 * tc358743 - Toshiba HDMI to CSI-2 bridge
3 *
4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
5 * reserved.
6 *
7 * This program is free software; you may redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18 * SOFTWARE.
19 *
20 */
21
22 /*
23 * References (c = chapter, p = page):
24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
31 #include <linux/i2c.h>
32 #include <linux/clk.h>
33 #include <linux/delay.h>
34 #include <linux/gpio/consumer.h>
35 #include <linux/interrupt.h>
36 #include <linux/videodev2.h>
37 #include <linux/workqueue.h>
38 #include <linux/v4l2-dv-timings.h>
39 #include <linux/hdmi.h>
40 #include <media/v4l2-dv-timings.h>
41 #include <media/v4l2-device.h>
42 #include <media/v4l2-ctrls.h>
43 #include <media/v4l2-event.h>
44 #include <media/v4l2-of.h>
45 #include <media/i2c/tc358743.h>
46
47 #include "tc358743_regs.h"
48
49 static int debug;
50 module_param(debug, int, 0644);
51 MODULE_PARM_DESC(debug, "debug level (0-3)");
52
53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
57 MODULE_LICENSE("GPL");
58
59 #define EDID_NUM_BLOCKS_MAX 8
60 #define EDID_BLOCK_SIZE 128
61
62 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
63
64 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
65 .type = V4L2_DV_BT_656_1120,
66 /* keep this initialization for compatibility with GCC < 4.4.6 */
67 .reserved = { 0 },
68 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
69 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
70 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
71 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
72 V4L2_DV_BT_CAP_PROGRESSIVE |
73 V4L2_DV_BT_CAP_REDUCED_BLANKING |
74 V4L2_DV_BT_CAP_CUSTOM)
75 };
76
77 struct tc358743_state {
78 struct tc358743_platform_data pdata;
79 struct v4l2_of_bus_mipi_csi2 bus;
80 struct v4l2_subdev sd;
81 struct media_pad pad;
82 struct v4l2_ctrl_handler hdl;
83 struct i2c_client *i2c_client;
84 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
85 struct mutex confctl_mutex;
86
87 /* controls */
88 struct v4l2_ctrl *detect_tx_5v_ctrl;
89 struct v4l2_ctrl *audio_sampling_rate_ctrl;
90 struct v4l2_ctrl *audio_present_ctrl;
91
92 struct delayed_work delayed_work_enable_hotplug;
93
94 /* edid */
95 u8 edid_blocks_written;
96
97 struct v4l2_dv_timings timings;
98 u32 mbus_fmt_code;
99
100 struct gpio_desc *reset_gpio;
101 };
102
103 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
104 bool cable_connected);
105 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
106
107 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
108 {
109 return container_of(sd, struct tc358743_state, sd);
110 }
111
112 /* --------------- I2C --------------- */
113
114 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
115 {
116 struct tc358743_state *state = to_state(sd);
117 struct i2c_client *client = state->i2c_client;
118 int err;
119 u8 buf[2] = { reg >> 8, reg & 0xff };
120 struct i2c_msg msgs[] = {
121 {
122 .addr = client->addr,
123 .flags = 0,
124 .len = 2,
125 .buf = buf,
126 },
127 {
128 .addr = client->addr,
129 .flags = I2C_M_RD,
130 .len = n,
131 .buf = values,
132 },
133 };
134
135 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
136 if (err != ARRAY_SIZE(msgs)) {
137 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
138 __func__, reg, client->addr);
139 }
140 }
141
142 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
143 {
144 struct tc358743_state *state = to_state(sd);
145 struct i2c_client *client = state->i2c_client;
146 int err, i;
147 struct i2c_msg msg;
148 u8 data[I2C_MAX_XFER_SIZE];
149
150 if ((2 + n) > I2C_MAX_XFER_SIZE) {
151 n = I2C_MAX_XFER_SIZE - 2;
152 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
153 reg, 2 + n);
154 }
155
156 msg.addr = client->addr;
157 msg.buf = data;
158 msg.len = 2 + n;
159 msg.flags = 0;
160
161 data[0] = reg >> 8;
162 data[1] = reg & 0xff;
163
164 for (i = 0; i < n; i++)
165 data[2 + i] = values[i];
166
167 err = i2c_transfer(client->adapter, &msg, 1);
168 if (err != 1) {
169 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
170 __func__, reg, client->addr);
171 return;
172 }
173
174 if (debug < 3)
175 return;
176
177 switch (n) {
178 case 1:
179 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
180 reg, data[2]);
181 break;
182 case 2:
183 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
184 reg, data[3], data[2]);
185 break;
186 case 4:
187 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
188 reg, data[5], data[4], data[3], data[2]);
189 break;
190 default:
191 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
192 n, reg);
193 }
194 }
195
196 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
197 {
198 u8 val;
199
200 i2c_rd(sd, reg, &val, 1);
201
202 return val;
203 }
204
205 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
206 {
207 i2c_wr(sd, reg, &val, 1);
208 }
209
210 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
211 u8 mask, u8 val)
212 {
213 i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
214 }
215
216 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
217 {
218 u16 val;
219
220 i2c_rd(sd, reg, (u8 *)&val, 2);
221
222 return val;
223 }
224
225 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
226 {
227 i2c_wr(sd, reg, (u8 *)&val, 2);
228 }
229
230 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
231 {
232 i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
233 }
234
235 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
236 {
237 u32 val;
238
239 i2c_rd(sd, reg, (u8 *)&val, 4);
240
241 return val;
242 }
243
244 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
245 {
246 i2c_wr(sd, reg, (u8 *)&val, 4);
247 }
248
249 /* --------------- STATUS --------------- */
250
251 static inline bool is_hdmi(struct v4l2_subdev *sd)
252 {
253 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
254 }
255
256 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
257 {
258 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
259 }
260
261 static inline bool no_signal(struct v4l2_subdev *sd)
262 {
263 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
264 }
265
266 static inline bool no_sync(struct v4l2_subdev *sd)
267 {
268 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
269 }
270
271 static inline bool audio_present(struct v4l2_subdev *sd)
272 {
273 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
274 }
275
276 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
277 {
278 static const int code_to_rate[] = {
279 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
280 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
281 };
282
283 /* Register FS_SET is not cleared when the cable is disconnected */
284 if (no_signal(sd))
285 return 0;
286
287 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
288 }
289
290 static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
291 {
292 return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
293 }
294
295 /* --------------- TIMINGS --------------- */
296
297 static inline unsigned fps(const struct v4l2_bt_timings *t)
298 {
299 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
300 return 0;
301
302 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
303 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
304 }
305
306 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
307 struct v4l2_dv_timings *timings)
308 {
309 struct v4l2_bt_timings *bt = &timings->bt;
310 unsigned width, height, frame_width, frame_height, frame_interval, fps;
311
312 memset(timings, 0, sizeof(struct v4l2_dv_timings));
313
314 if (no_signal(sd)) {
315 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
316 return -ENOLINK;
317 }
318 if (no_sync(sd)) {
319 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
320 return -ENOLCK;
321 }
322
323 timings->type = V4L2_DV_BT_656_1120;
324 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
325 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
326
327 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
328 i2c_rd8(sd, DE_WIDTH_H_LO);
329 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
330 i2c_rd8(sd, DE_WIDTH_V_LO);
331 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
332 i2c_rd8(sd, H_SIZE_LO);
333 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
334 i2c_rd8(sd, V_SIZE_LO)) / 2;
335 /* frame interval in milliseconds * 10
336 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
337 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
338 i2c_rd8(sd, FV_CNT_LO);
339 fps = (frame_interval > 0) ?
340 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
341
342 bt->width = width;
343 bt->height = height;
344 bt->vsync = frame_height - height;
345 bt->hsync = frame_width - width;
346 bt->pixelclock = frame_width * frame_height * fps;
347 if (bt->interlaced == V4L2_DV_INTERLACED) {
348 bt->height *= 2;
349 bt->il_vsync = bt->vsync + 1;
350 bt->pixelclock /= 2;
351 }
352
353 return 0;
354 }
355
356 /* --------------- HOTPLUG / HDCP / EDID --------------- */
357
358 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
359 {
360 struct delayed_work *dwork = to_delayed_work(work);
361 struct tc358743_state *state = container_of(dwork,
362 struct tc358743_state, delayed_work_enable_hotplug);
363 struct v4l2_subdev *sd = &state->sd;
364
365 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
366
367 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
368 }
369
370 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
371 {
372 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
373 "enable" : "disable");
374
375 i2c_wr8_and_or(sd, HDCP_REG1,
376 ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
377 MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
378
379 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
380 SET_AUTO_P3_RESET_FRAMES(0x0f));
381
382 /* HDCP is disabled by configuring the receiver as HDCP repeater. The
383 * repeater mode require software support to work, so HDCP
384 * authentication will fail.
385 */
386 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
387 i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
388 enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
389
390 /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
391 * second when HDCP is disabled, but the MAX_EXCED bit is handled
392 * correctly and HDCP is disabled on the HDMI output.
393 */
394 i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
395 enable ? 0 : MASK_MAX_EXCED);
396 i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
397 enable ? 0 : MASK_REPEATER | MASK_READY);
398 }
399
400 static void tc358743_disable_edid(struct v4l2_subdev *sd)
401 {
402 struct tc358743_state *state = to_state(sd);
403
404 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
405
406 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
407
408 /* DDC access to EDID is also disabled when hotplug is disabled. See
409 * register DDC_CTL */
410 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
411 }
412
413 static void tc358743_enable_edid(struct v4l2_subdev *sd)
414 {
415 struct tc358743_state *state = to_state(sd);
416
417 if (state->edid_blocks_written == 0) {
418 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
419 return;
420 }
421
422 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
423
424 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
425 * hotplug is enabled. See register DDC_CTL */
426 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
427
428 tc358743_enable_interrupts(sd, true);
429 tc358743_s_ctrl_detect_tx_5v(sd);
430 }
431
432 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
433 {
434 int i;
435
436 for (i = 0; i < 5; i++)
437 i2c_wr8(sd, BKSV + i, 0);
438 }
439
440 /* --------------- AVI infoframe --------------- */
441
442 static void print_avi_infoframe(struct v4l2_subdev *sd)
443 {
444 struct i2c_client *client = v4l2_get_subdevdata(sd);
445 struct device *dev = &client->dev;
446 union hdmi_infoframe frame;
447 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
448
449 if (!is_hdmi(sd)) {
450 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
451 return;
452 }
453
454 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
455
456 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
457 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
458 return;
459 }
460
461 hdmi_infoframe_log(KERN_INFO, dev, &frame);
462 }
463
464 /* --------------- CTRLS --------------- */
465
466 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
467 {
468 struct tc358743_state *state = to_state(sd);
469
470 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
471 tx_5v_power_present(sd));
472 }
473
474 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
475 {
476 struct tc358743_state *state = to_state(sd);
477
478 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
479 get_audio_sampling_rate(sd));
480 }
481
482 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
483 {
484 struct tc358743_state *state = to_state(sd);
485
486 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
487 audio_present(sd));
488 }
489
490 static int tc358743_update_controls(struct v4l2_subdev *sd)
491 {
492 int ret = 0;
493
494 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
495 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
496 ret |= tc358743_s_ctrl_audio_present(sd);
497
498 return ret;
499 }
500
501 /* --------------- INIT --------------- */
502
503 static void tc358743_reset_phy(struct v4l2_subdev *sd)
504 {
505 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
506
507 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
508 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
509 }
510
511 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
512 {
513 u16 sysctl = i2c_rd16(sd, SYSCTL);
514
515 i2c_wr16(sd, SYSCTL, sysctl | mask);
516 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
517 }
518
519 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
520 {
521 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
522 enable ? MASK_SLEEP : 0);
523 }
524
525 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
526 {
527 struct tc358743_state *state = to_state(sd);
528
529 v4l2_dbg(3, debug, sd, "%s: %sable\n",
530 __func__, enable ? "en" : "dis");
531
532 if (enable) {
533 /* It is critical for CSI receiver to see lane transition
534 * LP11->HS. Set to non-continuous mode to enable clock lane
535 * LP11 state. */
536 i2c_wr32(sd, TXOPTIONCNTRL, 0);
537 /* Set to continuous mode to trigger LP11->HS transition */
538 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
539 /* Unmute video */
540 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
541 } else {
542 /* Mute video so that all data lanes go to LSP11 state.
543 * No data is output to CSI Tx block. */
544 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
545 }
546
547 mutex_lock(&state->confctl_mutex);
548 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
549 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
550 mutex_unlock(&state->confctl_mutex);
551 }
552
553 static void tc358743_set_pll(struct v4l2_subdev *sd)
554 {
555 struct tc358743_state *state = to_state(sd);
556 struct tc358743_platform_data *pdata = &state->pdata;
557 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
558 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
559 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
560 SET_PLL_FBD(pdata->pll_fbd);
561 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
562
563 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
564
565 /* Only rewrite when needed (new value or disabled), since rewriting
566 * triggers another format change event. */
567 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
568 u16 pll_frs;
569
570 if (hsck > 500000000)
571 pll_frs = 0x0;
572 else if (hsck > 250000000)
573 pll_frs = 0x1;
574 else if (hsck > 125000000)
575 pll_frs = 0x2;
576 else
577 pll_frs = 0x3;
578
579 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
580 tc358743_sleep_mode(sd, true);
581 i2c_wr16(sd, PLLCTL0, pllctl0_new);
582 i2c_wr16_and_or(sd, PLLCTL1,
583 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
584 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
585 MASK_PLL_EN));
586 udelay(10); /* REF_02, Sheet "Source HDMI" */
587 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
588 tc358743_sleep_mode(sd, false);
589 }
590 }
591
592 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
593 {
594 struct tc358743_state *state = to_state(sd);
595 struct tc358743_platform_data *pdata = &state->pdata;
596 u32 sys_freq;
597 u32 lockdet_ref;
598 u16 fh_min;
599 u16 fh_max;
600
601 BUG_ON(!(pdata->refclk_hz == 26000000 ||
602 pdata->refclk_hz == 27000000 ||
603 pdata->refclk_hz == 42000000));
604
605 sys_freq = pdata->refclk_hz / 10000;
606 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
607 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
608
609 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
610 (pdata->refclk_hz == 42000000) ?
611 MASK_PHY_SYSCLK_IND : 0x0);
612
613 fh_min = pdata->refclk_hz / 100000;
614 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
615 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
616
617 fh_max = (fh_min * 66) / 10;
618 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
619 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
620
621 lockdet_ref = pdata->refclk_hz / 100;
622 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
623 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
624 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
625
626 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
627 (pdata->refclk_hz == 27000000) ?
628 MASK_NCO_F0_MOD_27MHZ : 0x0);
629 }
630
631 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
632 {
633 struct tc358743_state *state = to_state(sd);
634
635 switch (state->mbus_fmt_code) {
636 case MEDIA_BUS_FMT_UYVY8_1X16:
637 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
638 i2c_wr8_and_or(sd, VOUT_SET2,
639 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
640 MASK_SEL422 | MASK_VOUT_422FIL_100);
641 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
642 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
643 mutex_lock(&state->confctl_mutex);
644 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
645 MASK_YCBCRFMT_422_8_BIT);
646 mutex_unlock(&state->confctl_mutex);
647 break;
648 case MEDIA_BUS_FMT_RGB888_1X24:
649 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
650 i2c_wr8_and_or(sd, VOUT_SET2,
651 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
652 0x00);
653 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
654 MASK_VOUT_COLOR_RGB_FULL);
655 mutex_lock(&state->confctl_mutex);
656 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
657 mutex_unlock(&state->confctl_mutex);
658 break;
659 default:
660 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
661 __func__, state->mbus_fmt_code);
662 }
663 }
664
665 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
666 {
667 struct tc358743_state *state = to_state(sd);
668 struct v4l2_bt_timings *bt = &state->timings.bt;
669 struct tc358743_platform_data *pdata = &state->pdata;
670 u32 bits_pr_pixel =
671 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
672 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
673 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
674
675 return DIV_ROUND_UP(bps, bps_pr_lane);
676 }
677
678 static void tc358743_set_csi(struct v4l2_subdev *sd)
679 {
680 struct tc358743_state *state = to_state(sd);
681 struct tc358743_platform_data *pdata = &state->pdata;
682 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
683
684 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
685
686 tc358743_reset(sd, MASK_CTXRST);
687
688 if (lanes < 1)
689 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
690 if (lanes < 1)
691 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
692 if (lanes < 2)
693 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
694 if (lanes < 3)
695 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
696 if (lanes < 4)
697 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
698
699 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
700 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
701 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
702 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
703 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
704 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
705 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
706 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
707 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
708
709 i2c_wr32(sd, HSTXVREGEN,
710 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
711 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
712 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
713 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
714 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
715
716 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
717 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
718 i2c_wr32(sd, STARTCNTRL, MASK_START);
719 i2c_wr32(sd, CSI_START, MASK_STRT);
720
721 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
722 MASK_ADDRESS_CSI_CONTROL |
723 MASK_CSI_MODE |
724 MASK_TXHSMD |
725 ((lanes == 4) ? MASK_NOL_4 :
726 (lanes == 3) ? MASK_NOL_3 :
727 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
728
729 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
730 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
731 MASK_WCER | MASK_INER);
732
733 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
734 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
735
736 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
737 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
738 }
739
740 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
741 {
742 struct tc358743_state *state = to_state(sd);
743 struct tc358743_platform_data *pdata = &state->pdata;
744
745 /* Default settings from REF_02, sheet "Source HDMI"
746 * and custom settings as platform data */
747 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
748 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
749 SET_FREQ_RANGE_MODE_CYCLES(1));
750 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
751 (pdata->hdmi_phy_auto_reset_tmds_detected ?
752 MASK_PHY_AUTO_RST2 : 0) |
753 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
754 MASK_PHY_AUTO_RST3 : 0) |
755 (pdata->hdmi_phy_auto_reset_tmds_valid ?
756 MASK_PHY_AUTO_RST4 : 0));
757 i2c_wr8(sd, PHY_BIAS, 0x40);
758 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
759 i2c_wr8(sd, AVM_CTL, 45);
760 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
761 pdata->hdmi_detection_delay << 4);
762 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
763 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
764 MASK_H_PI_RST : 0) |
765 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
766 MASK_V_PI_RST : 0));
767 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
768 }
769
770 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
771 {
772 struct tc358743_state *state = to_state(sd);
773
774 /* Default settings from REF_02, sheet "Source HDMI" */
775 i2c_wr8(sd, FORCE_MUTE, 0x00);
776 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
777 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
778 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
779 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
780 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
781 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
782 i2c_wr8(sd, FS_MUTE, 0x00);
783 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
784 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
785 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
786 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
787 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
788 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
789
790 mutex_lock(&state->confctl_mutex);
791 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
792 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
793 mutex_unlock(&state->confctl_mutex);
794 }
795
796 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
797 {
798 /* Default settings from REF_02, sheet "Source HDMI" */
799 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
800 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
801 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
802 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
803 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
804 i2c_wr8(sd, NO_PKT_CLR, 0x53);
805 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
806 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
807 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
808 }
809
810 static void tc358743_initial_setup(struct v4l2_subdev *sd)
811 {
812 struct tc358743_state *state = to_state(sd);
813 struct tc358743_platform_data *pdata = &state->pdata;
814
815 /* CEC and IR are not supported by this driver */
816 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
817 (MASK_CECRST | MASK_IRRST));
818
819 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
820 tc358743_sleep_mode(sd, false);
821
822 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
823
824 tc358743_set_ref_clk(sd);
825
826 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
827 pdata->ddc5v_delay & MASK_DDC5V_MODE);
828 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
829
830 tc358743_set_hdmi_phy(sd);
831 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
832 tc358743_set_hdmi_audio(sd);
833 tc358743_set_hdmi_info_frame_mode(sd);
834
835 /* All CE and IT formats are detected as RGB full range in DVI mode */
836 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
837
838 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
839 MASK_VOUTCOLORMODE_AUTO);
840 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
841 }
842
843 /* --------------- IRQ --------------- */
844
845 static void tc358743_format_change(struct v4l2_subdev *sd)
846 {
847 struct tc358743_state *state = to_state(sd);
848 struct v4l2_dv_timings timings;
849 const struct v4l2_event tc358743_ev_fmt = {
850 .type = V4L2_EVENT_SOURCE_CHANGE,
851 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
852 };
853
854 if (tc358743_get_detected_timings(sd, &timings)) {
855 enable_stream(sd, false);
856
857 v4l2_dbg(1, debug, sd, "%s: No signal\n",
858 __func__);
859 } else {
860 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
861 enable_stream(sd, false);
862
863 if (debug)
864 v4l2_print_dv_timings(sd->name,
865 "tc358743_format_change: New format: ",
866 &timings, false);
867 }
868
869 if (sd->devnode)
870 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
871 }
872
873 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
874 {
875 u16 i;
876
877 /* clear interrupt status registers */
878 for (i = SYS_INT; i <= KEY_INT; i++)
879 i2c_wr8(sd, i, 0xff);
880
881 i2c_wr16(sd, INTSTATUS, 0xffff);
882 }
883
884 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
885 bool cable_connected)
886 {
887 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
888 cable_connected);
889
890 if (cable_connected) {
891 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
892 MASK_M_HDMI_DET) & 0xff);
893 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
894 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
895 MASK_M_AF_UNLOCK) & 0xff);
896 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
897 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
898 } else {
899 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
900 i2c_wr8(sd, CLK_INTM, 0xff);
901 i2c_wr8(sd, CBIT_INTM, 0xff);
902 i2c_wr8(sd, AUDIO_INTM, 0xff);
903 i2c_wr8(sd, MISC_INTM, 0xff);
904 }
905 }
906
907 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
908 bool *handled)
909 {
910 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
911 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
912
913 i2c_wr8(sd, AUDIO_INT, audio_int);
914
915 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
916
917 tc358743_s_ctrl_audio_sampling_rate(sd);
918 tc358743_s_ctrl_audio_present(sd);
919 }
920
921 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
922 {
923 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
924
925 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
926 }
927
928 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
929 bool *handled)
930 {
931 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
932 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
933
934 i2c_wr8(sd, MISC_INT, misc_int);
935
936 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
937
938 if (misc_int & MASK_I_SYNC_CHG) {
939 /* Reset the HDMI PHY to try to trigger proper lock on the
940 * incoming video format. Erase BKSV to prevent that old keys
941 * are used when a new source is connected. */
942 if (no_sync(sd) || no_signal(sd)) {
943 tc358743_reset_phy(sd);
944 tc358743_erase_bksv(sd);
945 }
946
947 tc358743_format_change(sd);
948
949 misc_int &= ~MASK_I_SYNC_CHG;
950 if (handled)
951 *handled = true;
952 }
953
954 if (misc_int) {
955 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
956 __func__, misc_int);
957 }
958 }
959
960 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
961 bool *handled)
962 {
963 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
964 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
965
966 i2c_wr8(sd, CBIT_INT, cbit_int);
967
968 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
969
970 if (cbit_int & MASK_I_CBIT_FS) {
971
972 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
973 __func__);
974 tc358743_s_ctrl_audio_sampling_rate(sd);
975
976 cbit_int &= ~MASK_I_CBIT_FS;
977 if (handled)
978 *handled = true;
979 }
980
981 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
982
983 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
984 __func__);
985 tc358743_s_ctrl_audio_present(sd);
986
987 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
988 if (handled)
989 *handled = true;
990 }
991
992 if (cbit_int) {
993 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
994 __func__, cbit_int);
995 }
996 }
997
998 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
999 {
1000 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1001 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1002
1003 /* Bit 7 and bit 6 are set even when they are masked */
1004 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1005
1006 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1007
1008 if (clk_int & (MASK_I_IN_DE_CHG)) {
1009
1010 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1011 __func__);
1012
1013 /* If the source switch to a new resolution with the same pixel
1014 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1015 * I_SYNC_CHG interrupt is not always triggered, while the
1016 * I_IN_DE_CHG interrupt seems to work fine. Format change
1017 * notifications are only sent when the signal is stable to
1018 * reduce the number of notifications. */
1019 if (!no_signal(sd) && !no_sync(sd))
1020 tc358743_format_change(sd);
1021
1022 clk_int &= ~(MASK_I_IN_DE_CHG);
1023 if (handled)
1024 *handled = true;
1025 }
1026
1027 if (clk_int) {
1028 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1029 __func__, clk_int);
1030 }
1031 }
1032
1033 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1034 {
1035 struct tc358743_state *state = to_state(sd);
1036 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1037 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1038
1039 i2c_wr8(sd, SYS_INT, sys_int);
1040
1041 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1042
1043 if (sys_int & MASK_I_DDC) {
1044 bool tx_5v = tx_5v_power_present(sd);
1045
1046 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1047 __func__, tx_5v ? "yes" : "no");
1048
1049 if (tx_5v) {
1050 tc358743_enable_edid(sd);
1051 } else {
1052 tc358743_enable_interrupts(sd, false);
1053 tc358743_disable_edid(sd);
1054 memset(&state->timings, 0, sizeof(state->timings));
1055 tc358743_erase_bksv(sd);
1056 tc358743_update_controls(sd);
1057 }
1058
1059 sys_int &= ~MASK_I_DDC;
1060 if (handled)
1061 *handled = true;
1062 }
1063
1064 if (sys_int & MASK_I_DVI) {
1065 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1066 __func__);
1067
1068 /* Reset the HDMI PHY to try to trigger proper lock on the
1069 * incoming video format. Erase BKSV to prevent that old keys
1070 * are used when a new source is connected. */
1071 if (no_sync(sd) || no_signal(sd)) {
1072 tc358743_reset_phy(sd);
1073 tc358743_erase_bksv(sd);
1074 }
1075
1076 sys_int &= ~MASK_I_DVI;
1077 if (handled)
1078 *handled = true;
1079 }
1080
1081 if (sys_int & MASK_I_HDMI) {
1082 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1083 __func__);
1084
1085 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1086 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1087
1088 sys_int &= ~MASK_I_HDMI;
1089 if (handled)
1090 *handled = true;
1091 }
1092
1093 if (sys_int) {
1094 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1095 __func__, sys_int);
1096 }
1097 }
1098
1099 /* --------------- CORE OPS --------------- */
1100
1101 static int tc358743_log_status(struct v4l2_subdev *sd)
1102 {
1103 struct tc358743_state *state = to_state(sd);
1104 struct v4l2_dv_timings timings;
1105 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1106 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1107 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1108 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1109 static const char * const input_color_space[] = {
1110 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1111 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1112 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1113
1114 v4l2_info(sd, "-----Chip status-----\n");
1115 v4l2_info(sd, "Chip ID: 0x%02x\n",
1116 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1117 v4l2_info(sd, "Chip revision: 0x%02x\n",
1118 i2c_rd16(sd, CHIPID) & MASK_REVID);
1119 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1120 !!(sysctl & MASK_IRRST),
1121 !!(sysctl & MASK_CECRST),
1122 !!(sysctl & MASK_CTXRST),
1123 !!(sysctl & MASK_HDMIRST));
1124 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1125 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1126 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1127 v4l2_info(sd, "DDC lines enabled: %s\n",
1128 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1129 "yes" : "no");
1130 v4l2_info(sd, "Hotplug enabled: %s\n",
1131 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1132 "yes" : "no");
1133 v4l2_info(sd, "CEC enabled: %s\n",
1134 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1135 v4l2_info(sd, "-----Signal status-----\n");
1136 v4l2_info(sd, "TMDS signal detected: %s\n",
1137 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1138 v4l2_info(sd, "Stable sync signal: %s\n",
1139 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1140 v4l2_info(sd, "PHY PLL locked: %s\n",
1141 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1142 v4l2_info(sd, "PHY DE detected: %s\n",
1143 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1144
1145 if (tc358743_get_detected_timings(sd, &timings)) {
1146 v4l2_info(sd, "No video detected\n");
1147 } else {
1148 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1149 true);
1150 }
1151 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1152 true);
1153
1154 v4l2_info(sd, "-----CSI-TX status-----\n");
1155 v4l2_info(sd, "Lanes needed: %d\n",
1156 tc358743_num_csi_lanes_needed(sd));
1157 v4l2_info(sd, "Lanes in use: %d\n",
1158 tc358743_num_csi_lanes_in_use(sd));
1159 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1160 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1161 "yes" : "no");
1162 v4l2_info(sd, "Transmit mode: %s\n",
1163 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1164 "yes" : "no");
1165 v4l2_info(sd, "Receive mode: %s\n",
1166 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1167 "yes" : "no");
1168 v4l2_info(sd, "Stopped: %s\n",
1169 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1170 "yes" : "no");
1171 v4l2_info(sd, "Color space: %s\n",
1172 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1173 "YCbCr 422 16-bit" :
1174 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1175 "RGB 888 24-bit" : "Unsupported");
1176
1177 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1178 v4l2_info(sd, "HDCP encrypted content: %s\n",
1179 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1180 v4l2_info(sd, "Input color space: %s %s range\n",
1181 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1182 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1183 if (!is_hdmi(sd))
1184 return 0;
1185 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1186 "off");
1187 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1188 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1189 MASK_S_DEEPCOLOR) >> 2]);
1190 print_avi_infoframe(sd);
1191
1192 return 0;
1193 }
1194
1195 #ifdef CONFIG_VIDEO_ADV_DEBUG
1196 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1197 {
1198 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1199 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1200 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1201 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1202 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1203 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1204 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1205 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1206 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1207 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1208 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1209 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1210 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1211 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1212 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1213 v4l2_info(sd, "0x9300- : Reserved\n");
1214 }
1215
1216 static int tc358743_get_reg_size(u16 address)
1217 {
1218 /* REF_01 p. 66-72 */
1219 if (address <= 0x00ff)
1220 return 2;
1221 else if ((address >= 0x0100) && (address <= 0x06FF))
1222 return 4;
1223 else if ((address >= 0x0700) && (address <= 0x84ff))
1224 return 2;
1225 else
1226 return 1;
1227 }
1228
1229 static int tc358743_g_register(struct v4l2_subdev *sd,
1230 struct v4l2_dbg_register *reg)
1231 {
1232 if (reg->reg > 0xffff) {
1233 tc358743_print_register_map(sd);
1234 return -EINVAL;
1235 }
1236
1237 reg->size = tc358743_get_reg_size(reg->reg);
1238
1239 i2c_rd(sd, reg->reg, (u8 *)&reg->val, reg->size);
1240
1241 return 0;
1242 }
1243
1244 static int tc358743_s_register(struct v4l2_subdev *sd,
1245 const struct v4l2_dbg_register *reg)
1246 {
1247 if (reg->reg > 0xffff) {
1248 tc358743_print_register_map(sd);
1249 return -EINVAL;
1250 }
1251
1252 /* It should not be possible for the user to enable HDCP with a simple
1253 * v4l2-dbg command.
1254 *
1255 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1256 * resolved.
1257 */
1258 if (reg->reg == HDCP_MODE ||
1259 reg->reg == HDCP_REG1 ||
1260 reg->reg == HDCP_REG2 ||
1261 reg->reg == HDCP_REG3 ||
1262 reg->reg == BCAPS)
1263 return 0;
1264
1265 i2c_wr(sd, (u16)reg->reg, (u8 *)&reg->val,
1266 tc358743_get_reg_size(reg->reg));
1267
1268 return 0;
1269 }
1270 #endif
1271
1272 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1273 {
1274 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1275
1276 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1277
1278 if (intstatus & MASK_HDMI_INT) {
1279 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1280 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1281
1282 if (hdmi_int0 & MASK_I_MISC)
1283 tc358743_hdmi_misc_int_handler(sd, handled);
1284 if (hdmi_int1 & MASK_I_CBIT)
1285 tc358743_hdmi_cbit_int_handler(sd, handled);
1286 if (hdmi_int1 & MASK_I_CLK)
1287 tc358743_hdmi_clk_int_handler(sd, handled);
1288 if (hdmi_int1 & MASK_I_SYS)
1289 tc358743_hdmi_sys_int_handler(sd, handled);
1290 if (hdmi_int1 & MASK_I_AUD)
1291 tc358743_hdmi_audio_int_handler(sd, handled);
1292
1293 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1294 intstatus &= ~MASK_HDMI_INT;
1295 }
1296
1297 if (intstatus & MASK_CSI_INT) {
1298 u32 csi_int = i2c_rd32(sd, CSI_INT);
1299
1300 if (csi_int & MASK_INTER)
1301 tc358743_csi_err_int_handler(sd, handled);
1302
1303 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1304 intstatus &= ~MASK_CSI_INT;
1305 }
1306
1307 intstatus = i2c_rd16(sd, INTSTATUS);
1308 if (intstatus) {
1309 v4l2_dbg(1, debug, sd,
1310 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1311 __func__, intstatus);
1312 }
1313
1314 return 0;
1315 }
1316
1317 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1318 {
1319 struct tc358743_state *state = dev_id;
1320 bool handled;
1321
1322 tc358743_isr(&state->sd, 0, &handled);
1323
1324 return handled ? IRQ_HANDLED : IRQ_NONE;
1325 }
1326
1327 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1328 struct v4l2_event_subscription *sub)
1329 {
1330 switch (sub->type) {
1331 case V4L2_EVENT_SOURCE_CHANGE:
1332 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1333 case V4L2_EVENT_CTRL:
1334 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1335 default:
1336 return -EINVAL;
1337 }
1338 }
1339
1340 /* --------------- VIDEO OPS --------------- */
1341
1342 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1343 {
1344 *status = 0;
1345 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1346 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1347
1348 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1349
1350 return 0;
1351 }
1352
1353 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1354 struct v4l2_dv_timings *timings)
1355 {
1356 struct tc358743_state *state = to_state(sd);
1357
1358 if (!timings)
1359 return -EINVAL;
1360
1361 if (debug)
1362 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1363 timings, false);
1364
1365 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1366 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1367 return 0;
1368 }
1369
1370 if (!v4l2_valid_dv_timings(timings,
1371 &tc358743_timings_cap, NULL, NULL)) {
1372 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1373 return -ERANGE;
1374 }
1375
1376 state->timings = *timings;
1377
1378 enable_stream(sd, false);
1379 tc358743_set_pll(sd);
1380 tc358743_set_csi(sd);
1381
1382 return 0;
1383 }
1384
1385 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1386 struct v4l2_dv_timings *timings)
1387 {
1388 struct tc358743_state *state = to_state(sd);
1389
1390 *timings = state->timings;
1391
1392 return 0;
1393 }
1394
1395 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1396 struct v4l2_enum_dv_timings *timings)
1397 {
1398 if (timings->pad != 0)
1399 return -EINVAL;
1400
1401 return v4l2_enum_dv_timings_cap(timings,
1402 &tc358743_timings_cap, NULL, NULL);
1403 }
1404
1405 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1406 struct v4l2_dv_timings *timings)
1407 {
1408 int ret;
1409
1410 ret = tc358743_get_detected_timings(sd, timings);
1411 if (ret)
1412 return ret;
1413
1414 if (debug)
1415 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1416 timings, false);
1417
1418 if (!v4l2_valid_dv_timings(timings,
1419 &tc358743_timings_cap, NULL, NULL)) {
1420 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1421 return -ERANGE;
1422 }
1423
1424 return 0;
1425 }
1426
1427 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1428 struct v4l2_dv_timings_cap *cap)
1429 {
1430 if (cap->pad != 0)
1431 return -EINVAL;
1432
1433 *cap = tc358743_timings_cap;
1434
1435 return 0;
1436 }
1437
1438 static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1439 struct v4l2_mbus_config *cfg)
1440 {
1441 cfg->type = V4L2_MBUS_CSI2;
1442
1443 /* Support for non-continuous CSI-2 clock is missing in the driver */
1444 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1445
1446 switch (tc358743_num_csi_lanes_in_use(sd)) {
1447 case 1:
1448 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1449 break;
1450 case 2:
1451 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1452 break;
1453 case 3:
1454 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1455 break;
1456 case 4:
1457 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1458 break;
1459 default:
1460 return -EINVAL;
1461 }
1462
1463 return 0;
1464 }
1465
1466 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1467 {
1468 enable_stream(sd, enable);
1469
1470 return 0;
1471 }
1472
1473 /* --------------- PAD OPS --------------- */
1474
1475 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1476 struct v4l2_subdev_pad_config *cfg,
1477 struct v4l2_subdev_format *format)
1478 {
1479 struct tc358743_state *state = to_state(sd);
1480 u8 vi_rep = i2c_rd8(sd, VI_REP);
1481
1482 if (format->pad != 0)
1483 return -EINVAL;
1484
1485 format->format.code = state->mbus_fmt_code;
1486 format->format.width = state->timings.bt.width;
1487 format->format.height = state->timings.bt.height;
1488 format->format.field = V4L2_FIELD_NONE;
1489
1490 switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1491 case MASK_VOUT_COLOR_RGB_FULL:
1492 case MASK_VOUT_COLOR_RGB_LIMITED:
1493 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1494 break;
1495 case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1496 case MASK_VOUT_COLOR_601_YCBCR_FULL:
1497 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1498 break;
1499 case MASK_VOUT_COLOR_709_YCBCR_FULL:
1500 case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1501 format->format.colorspace = V4L2_COLORSPACE_REC709;
1502 break;
1503 default:
1504 format->format.colorspace = 0;
1505 break;
1506 }
1507
1508 return 0;
1509 }
1510
1511 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1512 struct v4l2_subdev_pad_config *cfg,
1513 struct v4l2_subdev_format *format)
1514 {
1515 struct tc358743_state *state = to_state(sd);
1516
1517 u32 code = format->format.code; /* is overwritten by get_fmt */
1518 int ret = tc358743_get_fmt(sd, cfg, format);
1519
1520 format->format.code = code;
1521
1522 if (ret)
1523 return ret;
1524
1525 switch (code) {
1526 case MEDIA_BUS_FMT_RGB888_1X24:
1527 case MEDIA_BUS_FMT_UYVY8_1X16:
1528 break;
1529 default:
1530 return -EINVAL;
1531 }
1532
1533 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1534 return 0;
1535
1536 state->mbus_fmt_code = format->format.code;
1537
1538 enable_stream(sd, false);
1539 tc358743_set_pll(sd);
1540 tc358743_set_csi(sd);
1541 tc358743_set_csi_color_space(sd);
1542
1543 return 0;
1544 }
1545
1546 static int tc358743_g_edid(struct v4l2_subdev *sd,
1547 struct v4l2_subdev_edid *edid)
1548 {
1549 struct tc358743_state *state = to_state(sd);
1550
1551 memset(edid->reserved, 0, sizeof(edid->reserved));
1552
1553 if (edid->pad != 0)
1554 return -EINVAL;
1555
1556 if (edid->start_block == 0 && edid->blocks == 0) {
1557 edid->blocks = state->edid_blocks_written;
1558 return 0;
1559 }
1560
1561 if (state->edid_blocks_written == 0)
1562 return -ENODATA;
1563
1564 if (edid->start_block >= state->edid_blocks_written ||
1565 edid->blocks == 0)
1566 return -EINVAL;
1567
1568 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1569 edid->blocks = state->edid_blocks_written - edid->start_block;
1570
1571 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1572 edid->blocks * EDID_BLOCK_SIZE);
1573
1574 return 0;
1575 }
1576
1577 static int tc358743_s_edid(struct v4l2_subdev *sd,
1578 struct v4l2_subdev_edid *edid)
1579 {
1580 struct tc358743_state *state = to_state(sd);
1581 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1582 int i;
1583
1584 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1585 __func__, edid->pad, edid->start_block, edid->blocks);
1586
1587 memset(edid->reserved, 0, sizeof(edid->reserved));
1588
1589 if (edid->pad != 0)
1590 return -EINVAL;
1591
1592 if (edid->start_block != 0)
1593 return -EINVAL;
1594
1595 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1596 edid->blocks = EDID_NUM_BLOCKS_MAX;
1597 return -E2BIG;
1598 }
1599
1600 tc358743_disable_edid(sd);
1601
1602 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1603 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1604
1605 if (edid->blocks == 0) {
1606 state->edid_blocks_written = 0;
1607 return 0;
1608 }
1609
1610 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1611 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1612
1613 state->edid_blocks_written = edid->blocks;
1614
1615 if (tx_5v_power_present(sd))
1616 tc358743_enable_edid(sd);
1617
1618 return 0;
1619 }
1620
1621 /* -------------------------------------------------------------------------- */
1622
1623 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1624 .log_status = tc358743_log_status,
1625 #ifdef CONFIG_VIDEO_ADV_DEBUG
1626 .g_register = tc358743_g_register,
1627 .s_register = tc358743_s_register,
1628 #endif
1629 .interrupt_service_routine = tc358743_isr,
1630 .subscribe_event = tc358743_subscribe_event,
1631 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1632 };
1633
1634 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1635 .g_input_status = tc358743_g_input_status,
1636 .s_dv_timings = tc358743_s_dv_timings,
1637 .g_dv_timings = tc358743_g_dv_timings,
1638 .query_dv_timings = tc358743_query_dv_timings,
1639 .g_mbus_config = tc358743_g_mbus_config,
1640 .s_stream = tc358743_s_stream,
1641 };
1642
1643 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1644 .set_fmt = tc358743_set_fmt,
1645 .get_fmt = tc358743_get_fmt,
1646 .get_edid = tc358743_g_edid,
1647 .set_edid = tc358743_s_edid,
1648 .enum_dv_timings = tc358743_enum_dv_timings,
1649 .dv_timings_cap = tc358743_dv_timings_cap,
1650 };
1651
1652 static const struct v4l2_subdev_ops tc358743_ops = {
1653 .core = &tc358743_core_ops,
1654 .video = &tc358743_video_ops,
1655 .pad = &tc358743_pad_ops,
1656 };
1657
1658 /* --------------- CUSTOM CTRLS --------------- */
1659
1660 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1661 .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1662 .name = "Audio sampling rate",
1663 .type = V4L2_CTRL_TYPE_INTEGER,
1664 .min = 0,
1665 .max = 768000,
1666 .step = 1,
1667 .def = 0,
1668 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1669 };
1670
1671 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1672 .id = TC358743_CID_AUDIO_PRESENT,
1673 .name = "Audio present",
1674 .type = V4L2_CTRL_TYPE_BOOLEAN,
1675 .min = 0,
1676 .max = 1,
1677 .step = 1,
1678 .def = 0,
1679 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1680 };
1681
1682 /* --------------- PROBE / REMOVE --------------- */
1683
1684 #ifdef CONFIG_OF
1685 static void tc358743_gpio_reset(struct tc358743_state *state)
1686 {
1687 usleep_range(5000, 10000);
1688 gpiod_set_value(state->reset_gpio, 1);
1689 usleep_range(1000, 2000);
1690 gpiod_set_value(state->reset_gpio, 0);
1691 msleep(20);
1692 }
1693
1694 static int tc358743_probe_of(struct tc358743_state *state)
1695 {
1696 struct device *dev = &state->i2c_client->dev;
1697 struct v4l2_of_endpoint *endpoint;
1698 struct device_node *ep;
1699 struct clk *refclk;
1700 u32 bps_pr_lane;
1701 int ret = -EINVAL;
1702
1703 refclk = devm_clk_get(dev, "refclk");
1704 if (IS_ERR(refclk)) {
1705 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1706 dev_err(dev, "failed to get refclk: %ld\n",
1707 PTR_ERR(refclk));
1708 return PTR_ERR(refclk);
1709 }
1710
1711 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1712 if (!ep) {
1713 dev_err(dev, "missing endpoint node\n");
1714 return -EINVAL;
1715 }
1716
1717 endpoint = v4l2_of_alloc_parse_endpoint(ep);
1718 if (IS_ERR(endpoint)) {
1719 dev_err(dev, "failed to parse endpoint\n");
1720 return PTR_ERR(endpoint);
1721 }
1722
1723 if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1724 endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1725 endpoint->nr_of_link_frequencies == 0) {
1726 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1727 goto free_endpoint;
1728 }
1729
1730 state->bus = endpoint->bus.mipi_csi2;
1731
1732 clk_prepare_enable(refclk);
1733
1734 state->pdata.refclk_hz = clk_get_rate(refclk);
1735 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1736 state->pdata.enable_hdcp = false;
1737 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1738 state->pdata.fifo_level = 16;
1739 /*
1740 * The PLL input clock is obtained by dividing refclk by pll_prd.
1741 * It must be between 6 MHz and 40 MHz, lower frequency is better.
1742 */
1743 switch (state->pdata.refclk_hz) {
1744 case 26000000:
1745 case 27000000:
1746 case 42000000:
1747 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1748 break;
1749 default:
1750 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1751 state->pdata.refclk_hz);
1752 goto disable_clk;
1753 }
1754
1755 /*
1756 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1757 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1758 */
1759 bps_pr_lane = 2 * endpoint->link_frequencies[0];
1760 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1761 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1762 goto disable_clk;
1763 }
1764
1765 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1766 state->pdata.pll_fbd = bps_pr_lane /
1767 state->pdata.refclk_hz * state->pdata.pll_prd;
1768
1769 /*
1770 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1771 * link frequency). In principle it should be possible to calculate
1772 * them based on link frequency and resolution.
1773 */
1774 if (bps_pr_lane != 594000000U)
1775 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1776 state->pdata.lineinitcnt = 0xe80;
1777 state->pdata.lptxtimecnt = 0x003;
1778 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1779 state->pdata.tclk_headercnt = 0x1403;
1780 state->pdata.tclk_trailcnt = 0x00;
1781 /* ths-preparecnt: 3, ths-zerocnt: 1 */
1782 state->pdata.ths_headercnt = 0x0103;
1783 state->pdata.twakeup = 0x4882;
1784 state->pdata.tclk_postcnt = 0x008;
1785 state->pdata.ths_trailcnt = 0x2;
1786 state->pdata.hstxvregcnt = 0;
1787
1788 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1789 GPIOD_OUT_LOW);
1790 if (IS_ERR(state->reset_gpio)) {
1791 dev_err(dev, "failed to get reset gpio\n");
1792 ret = PTR_ERR(state->reset_gpio);
1793 goto disable_clk;
1794 }
1795
1796 if (state->reset_gpio)
1797 tc358743_gpio_reset(state);
1798
1799 ret = 0;
1800 goto free_endpoint;
1801
1802 disable_clk:
1803 clk_disable_unprepare(refclk);
1804 free_endpoint:
1805 v4l2_of_free_endpoint(endpoint);
1806 return ret;
1807 }
1808 #else
1809 static inline int tc358743_probe_of(struct tc358743_state *state)
1810 {
1811 return -ENODEV;
1812 }
1813 #endif
1814
1815 static int tc358743_probe(struct i2c_client *client,
1816 const struct i2c_device_id *id)
1817 {
1818 static struct v4l2_dv_timings default_timing =
1819 V4L2_DV_BT_CEA_640X480P59_94;
1820 struct tc358743_state *state;
1821 struct tc358743_platform_data *pdata = client->dev.platform_data;
1822 struct v4l2_subdev *sd;
1823 int err;
1824
1825 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1826 return -EIO;
1827 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
1828 client->addr << 1, client->adapter->name);
1829
1830 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
1831 GFP_KERNEL);
1832 if (!state)
1833 return -ENOMEM;
1834
1835 state->i2c_client = client;
1836
1837 /* platform data */
1838 if (pdata) {
1839 state->pdata = *pdata;
1840 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1841 } else {
1842 err = tc358743_probe_of(state);
1843 if (err == -ENODEV)
1844 v4l_err(client, "No platform data!\n");
1845 if (err)
1846 return err;
1847 }
1848
1849 sd = &state->sd;
1850 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
1851 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1852
1853 /* i2c access */
1854 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
1855 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
1856 client->addr << 1);
1857 return -ENODEV;
1858 }
1859
1860 /* control handlers */
1861 v4l2_ctrl_handler_init(&state->hdl, 3);
1862
1863 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
1864 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1865
1866 /* custom controls */
1867 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1868 &tc358743_ctrl_audio_sampling_rate, NULL);
1869
1870 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1871 &tc358743_ctrl_audio_present, NULL);
1872
1873 sd->ctrl_handler = &state->hdl;
1874 if (state->hdl.error) {
1875 err = state->hdl.error;
1876 goto err_hdl;
1877 }
1878
1879 if (tc358743_update_controls(sd)) {
1880 err = -ENODEV;
1881 goto err_hdl;
1882 }
1883
1884 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1885 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1886 if (err < 0)
1887 goto err_hdl;
1888
1889 sd->dev = &client->dev;
1890 err = v4l2_async_register_subdev(sd);
1891 if (err < 0)
1892 goto err_hdl;
1893
1894 mutex_init(&state->confctl_mutex);
1895
1896 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
1897 tc358743_delayed_work_enable_hotplug);
1898
1899 tc358743_initial_setup(sd);
1900
1901 tc358743_s_dv_timings(sd, &default_timing);
1902
1903 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1904 tc358743_set_csi_color_space(sd);
1905
1906 tc358743_init_interrupts(sd);
1907
1908 if (state->i2c_client->irq) {
1909 err = devm_request_threaded_irq(&client->dev,
1910 state->i2c_client->irq,
1911 NULL, tc358743_irq_handler,
1912 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1913 "tc358743", state);
1914 if (err)
1915 goto err_work_queues;
1916 }
1917
1918 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
1919 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
1920
1921 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1922 if (err)
1923 goto err_work_queues;
1924
1925 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1926 client->addr << 1, client->adapter->name);
1927
1928 return 0;
1929
1930 err_work_queues:
1931 cancel_delayed_work(&state->delayed_work_enable_hotplug);
1932 mutex_destroy(&state->confctl_mutex);
1933 err_hdl:
1934 media_entity_cleanup(&sd->entity);
1935 v4l2_ctrl_handler_free(&state->hdl);
1936 return err;
1937 }
1938
1939 static int tc358743_remove(struct i2c_client *client)
1940 {
1941 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1942 struct tc358743_state *state = to_state(sd);
1943
1944 cancel_delayed_work(&state->delayed_work_enable_hotplug);
1945 v4l2_async_unregister_subdev(sd);
1946 v4l2_device_unregister_subdev(sd);
1947 mutex_destroy(&state->confctl_mutex);
1948 media_entity_cleanup(&sd->entity);
1949 v4l2_ctrl_handler_free(&state->hdl);
1950
1951 return 0;
1952 }
1953
1954 static struct i2c_device_id tc358743_id[] = {
1955 {"tc358743", 0},
1956 {}
1957 };
1958
1959 MODULE_DEVICE_TABLE(i2c, tc358743_id);
1960
1961 static struct i2c_driver tc358743_driver = {
1962 .driver = {
1963 .name = "tc358743",
1964 },
1965 .probe = tc358743_probe,
1966 .remove = tc358743_remove,
1967 .id_table = tc358743_id,
1968 };
1969
1970 module_i2c_driver(tc358743_driver);
Linux with added FPC-III support