drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2014-2015 Cogent Embedded, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2
   9  * as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13
  14 #include "sh_pfc.h"
  15
  16 /*
  17  * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
  18  * which case they support both 3.3V and 1.8V signalling.
  19  */
  20 #define CPU_ALL_PORT(fn, sfx)                                           \
  21         PORT_GP_32(0, fn, sfx),                                         \
  22         PORT_GP_26(1, fn, sfx),                                         \
  23         PORT_GP_32(2, fn, sfx),                                         \
  24         PORT_GP_32(3, fn, sfx),                                         \
  25         PORT_GP_32(4, fn, sfx),                                         \
  26         PORT_GP_32(5, fn, sfx),                                         \
  27         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  28         PORT_GP_1(6, 24, fn, sfx),                                      \
  29         PORT_GP_1(6, 25, fn, sfx),                                      \
  30         PORT_GP_1(6, 26, fn, sfx),                                      \
  31         PORT_GP_1(6, 27, fn, sfx),                                      \
  32         PORT_GP_1(6, 28, fn, sfx),                                      \
  33         PORT_GP_1(6, 29, fn, sfx),                                      \
  34         PORT_GP_1(6, 30, fn, sfx),                                      \
  35         PORT_GP_1(6, 31, fn, sfx),                                      \
  36         PORT_GP_26(7, fn, sfx)
  37
  38 enum {
  39         PINMUX_RESERVED = 0,
  40
  41         PINMUX_DATA_BEGIN,
  42         GP_ALL(DATA),
  43         PINMUX_DATA_END,
  44
  45         PINMUX_FUNCTION_BEGIN,
  46         GP_ALL(FN),
  47
  48         /* GPSR0 */
  49         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  50         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  51         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  52         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  53         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  54         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  55
  56         /* GPSR1 */
  57         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  58         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  59         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  60         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  61         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  62         FN_IP3_21_20,
  63
  64         /* GPSR2 */
  65         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  66         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  67         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  68         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  69         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  70         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  71         FN_IP6_5_3, FN_IP6_7_6,
  72
  73         /* GPSR3 */
  74         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  75         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  76         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  77         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  78         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  79         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  80         FN_IP9_18_17,
  81
  82         /* GPSR4 */
  83         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  84         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  85         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  86         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  87         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  88         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  89         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  90         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  91
  92         /* GPSR5 */
  93         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  94         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  95         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  96         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  97         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  98         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  99         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
 100
 101         /* GPSR6 */
 102         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
 103         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
 104         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
 105         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
 106         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
 107         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
 108         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
 109         FN_USB1_OVC, FN_DU0_DOTCLKIN,
 110
 111         /* GPSR7 */
 112         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 113         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 114         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 115         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 116         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 117         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 118
 119         /* IPSR0 */
 120         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 121         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 122         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 123         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 124         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 125         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 126
 127         /* IPSR1 */
 128         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 129         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 130         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 131         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 132         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 133         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 134         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 135         FN_A15, FN_BPFCLK_C,
 136         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 137         FN_A17, FN_DACK2_B, FN_SDA0_C,
 138         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 139
 140         /* IPSR2 */
 141         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 142         FN_A20, FN_SPCLK,
 143         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 144         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 145         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 146         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 147         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 148         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 149         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 150         FN_EX_CS1_N, FN_MSIOF2_SCK,
 151         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 152         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 153
 154         /* IPSR3 */
 155         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 156         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 157         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 158         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 159         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 160         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 161         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 162         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 163         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 164         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 165         FN_DACK0, FN_DRACK0, FN_REMOCON,
 166         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 167         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 168         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 169         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 170
 171         /* IPSR4 */
 172         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 173         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 174         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 175         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 176         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 177         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 178         FN_GLO_Q1_D, FN_HCTS1_N_E,
 179         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 180         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 181         FN_SSI_SCK4, FN_GLO_SS_D,
 182         FN_SSI_WS4, FN_GLO_RFON_D,
 183         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 184         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 185         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 186
 187         /* IPSR5 */
 188         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 189         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 190         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 191         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 192         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 193         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 194         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 195         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 196         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 197         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 198         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 199         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 200         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 201         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 202         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 203
 204         /* IPSR6 */
 205         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 206         FN_SCIF_CLK, FN_BPFCLK_E,
 207         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 208         FN_SCIFA2_RXD, FN_FMIN_E,
 209         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 210         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 211         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 212         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 213         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 214         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 215         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 216         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 217         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 218         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 219
 220         /* IPSR7 */
 221         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 222         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 223         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 224         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 225         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 226         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 227         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 228         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 229         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 230         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 231         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 232         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 233         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 234         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 235         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 236         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 237         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 238         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 239
 240         /* IPSR8 */
 241         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 242         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 243         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 244         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 245         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 246         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 247         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 248         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 249         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 250         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 251         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 252         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 253         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 254         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 255         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 256         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 257         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 258
 259         /* IPSR9 */
 260         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 261         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 262         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 263         FN_DU1_DOTCLKOUT0, FN_QCLK,
 264         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 265         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 266         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 267         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 268         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 269         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 270         FN_DU1_DISP, FN_QPOLA,
 271         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 272         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 273         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 274         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 275         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 276         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 277         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 278         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 279
 280         /* IPSR10 */
 281         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 282         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 283         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 284         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 285         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 286         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 287         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 288         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 289         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 290         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 291         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 292         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 293         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 294         FN_TS_SDATA0_C, FN_ATACS11_N,
 295         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 296         FN_TS_SCK0_C, FN_ATAG1_N,
 297         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 298         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 299         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 300
 301         /* IPSR11 */
 302         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 303         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 304         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 305         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 306         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 307         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 308         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 309         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 310         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 311         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 312         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 313         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 314         FN_VI1_DATA7, FN_AVB_MDC,
 315         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 316         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 317
 318         /* IPSR12 */
 319         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 320         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 321         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 322         FN_SCL2_D, FN_MSIOF1_RXD_E,
 323         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 324         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 325         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 326         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 327         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 328         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 329         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 330         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 331         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 332         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 333         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 334         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 335         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 336
 337         /* IPSR13 */
 338         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 339         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 340         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 341         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 342         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 343         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 344         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 345         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 346         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 347         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 348         FN_SCIFA5_TXD_B, FN_TX3_C,
 349         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 350         FN_SCIFA5_RXD_B, FN_RX3_C,
 351         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 352         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 353         FN_SD1_DATA3, FN_IERX_B,
 354         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 355
 356         /* IPSR14 */
 357         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 358         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 359         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 360         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 361         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 362         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 363         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 364         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 365         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 366         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 367         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 368         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 369         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 370         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 371
 372         /* IPSR15 */
 373         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 374         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 375         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 376         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 377         FN_PWM5_B, FN_SCIFA3_TXD_C,
 378         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 379         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 380         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 381         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 382         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 383         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 384         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 385         FN_TCLK2, FN_VI1_DATA3_C,
 386         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 387         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 388
 389         /* IPSR16 */
 390         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 391         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 392         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
 393         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 394         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 395
 396         /* MOD_SEL */
 397         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 398         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 399         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 400         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 401         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 402         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 403         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 404         FN_SEL_QSP_0, FN_SEL_QSP_1,
 405         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 406         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 407         FN_SEL_HSCIF1_4,
 408         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 409         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 410         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 411         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 412         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 413
 414         /* MOD_SEL2 */
 415         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 416         FN_SEL_SCIF0_4,
 417         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 418         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 419         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 420         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 421         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 422         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 423         FN_SEL_ADG_0, FN_SEL_ADG_1,
 424         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 425         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 426         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 427         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 428         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 429         FN_SEL_SIM_0, FN_SEL_SIM_1,
 430         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 431
 432         /* MOD_SEL3 */
 433         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 434         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 435         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 436         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 437         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 438         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 439         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 440         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 441         FN_SEL_MMC_0, FN_SEL_MMC_1,
 442         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 443         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 444         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 445         FN_SEL_IIC1_4,
 446         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 447
 448         /* MOD_SEL4 */
 449         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 450         FN_SEL_SOF1_4,
 451         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 452         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 453         FN_SEL_RAD_0, FN_SEL_RAD_1,
 454         FN_SEL_RCN_0, FN_SEL_RCN_1,
 455         FN_SEL_RSP_0, FN_SEL_RSP_1,
 456         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 457         FN_SEL_SCIF2_4,
 458         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 459         FN_SEL_SOF2_4,
 460         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 461         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 462         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 463         PINMUX_FUNCTION_END,
 464
 465         PINMUX_MARK_BEGIN,
 466
 467         EX_CS0_N_MARK, RD_N_MARK,
 468
 469         AUDIO_CLKA_MARK,
 470
 471         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 472         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 473         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 474
 475         SD1_CLK_MARK,
 476
 477         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 478         DU0_DOTCLKIN_MARK,
 479
 480         /* IPSR0 */
 481         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 482         D6_MARK, D7_MARK, D8_MARK,
 483         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 484         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 485         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 486         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 487         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 488
 489         /* IPSR1 */
 490         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 491         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 492         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 493         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 494         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 495         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 496         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 497         A15_MARK, BPFCLK_C_MARK,
 498         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 499         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 500         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 501
 502         /* IPSR2 */
 503         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 504         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 505         A20_MARK, SPCLK_MARK,
 506         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 507         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 508         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 509         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 510         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 511         RX1_MARK, SCIFA1_RXD_MARK,
 512         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 513         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 514         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 515         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 516         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 517         ATAG0_N_MARK, EX_WAIT1_MARK,
 518
 519         /* IPSR3 */
 520         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 521         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 522         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 523         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 524         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 525         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 526         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 527         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 528         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 529         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 530         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 531         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 532         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 533         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 534         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 535         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 536         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 537         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 538
 539         /* IPSR4 */
 540         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 541         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 542         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 543         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 544         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 545         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 546         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 547         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 548         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 549         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 550         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 551         SSI_SCK4_MARK, GLO_SS_D_MARK,
 552         SSI_WS4_MARK, GLO_RFON_D_MARK,
 553         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 554         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 555         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 556
 557         /* IPSR5 */
 558         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 559         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 560         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 561         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 562         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 563         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 564         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 565         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 566         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 567         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 568         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 569         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 570         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 571         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 572         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 573
 574         /* IPSR6 */
 575         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 576         SCIF_CLK_MARK, BPFCLK_E_MARK,
 577         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 578         SCIFA2_RXD_MARK, FMIN_E_MARK,
 579         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 580         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 581         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 582         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 583         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 584         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 585         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 586         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 587         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 588         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 589         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 590         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 591         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 592         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 593
 594         /* IPSR7 */
 595         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 596         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 597         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 598         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 599         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 600         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 601         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 602         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 603         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 604         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 605         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 606         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 607         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 608         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 609         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 610         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 611         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 612         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 613
 614         /* IPSR8 */
 615         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 616         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 617         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 618         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 619         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 620         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 621         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 622         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 623         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 624         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 625         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 626         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 627         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 628         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 629         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 630         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 631         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 632         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 633
 634         /* IPSR9 */
 635         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 636         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 637         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 638         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 639         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 640         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 641         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 642         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 643         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 644         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 645         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 646         DU1_DISP_MARK, QPOLA_MARK,
 647         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 648         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 649         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 650         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 651         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 652         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 653         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 654         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 655
 656         /* IPSR10 */
 657         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 658         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 659         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 660         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 661         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 662         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 663         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 664         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 665         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 666         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 667         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 668         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 669         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 670         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 671         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 672         TS_SCK0_C_MARK, ATAG1_N_MARK,
 673         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 674         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 675         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 676
 677         /* IPSR11 */
 678         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 679         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 680         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 681         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 682         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 683         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 684         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 685         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 686         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 687         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 688         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 689         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 690         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 691         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 692         VI1_DATA7_MARK, AVB_MDC_MARK,
 693         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 694         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 695
 696         /* IPSR12 */
 697         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 698         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 699         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 700         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 701         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 702         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 703         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 704         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 705         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 706         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 707         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 708         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 709         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 710         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 711         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 712         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 713         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 714         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 715
 716         /* IPSR13 */
 717         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 718         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 719         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 720         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 721         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 722         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 723         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 724         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 725         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 726         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 727         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 728         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 729         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 730         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 731         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 732         SD1_DATA3_MARK, IERX_B_MARK,
 733         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 734
 735         /* IPSR14 */
 736         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 737         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 738         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 739         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 740         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 741         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 742         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 743         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 744         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 745         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 746         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 747         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 748         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 749         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 750         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 751         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 752
 753         /* IPSR15 */
 754         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 755         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 756         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 757         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 758         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 759         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 760         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 761         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 762         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 763         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 764         TCLK1_MARK, VI1_DATA1_C_MARK,
 765         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 766         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 767         TCLK2_MARK, VI1_DATA3_C_MARK,
 768         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 769         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 770         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 771         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 772
 773         /* IPSR16 */
 774         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 775         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 776         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 777         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 778         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
 779         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 780         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 781         PINMUX_MARK_END,
 782 };
 783
 784 static const u16 pinmux_data[] = {
 785         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 786
 787         PINMUX_SINGLE(EX_CS0_N),
 788         PINMUX_SINGLE(RD_N),
 789         PINMUX_SINGLE(AUDIO_CLKA),
 790         PINMUX_SINGLE(VI0_CLK),
 791         PINMUX_SINGLE(VI0_DATA0_VI0_B0),
 792         PINMUX_SINGLE(VI0_DATA1_VI0_B1),
 793         PINMUX_SINGLE(VI0_DATA2_VI0_B2),
 794         PINMUX_SINGLE(VI0_DATA4_VI0_B4),
 795         PINMUX_SINGLE(VI0_DATA5_VI0_B5),
 796         PINMUX_SINGLE(VI0_DATA6_VI0_B6),
 797         PINMUX_SINGLE(VI0_DATA7_VI0_B7),
 798         PINMUX_SINGLE(USB0_PWEN),
 799         PINMUX_SINGLE(USB0_OVC),
 800         PINMUX_SINGLE(USB1_PWEN),
 801         PINMUX_SINGLE(USB1_OVC),
 802         PINMUX_SINGLE(DU0_DOTCLKIN),
 803         PINMUX_SINGLE(SD1_CLK),
 804
 805         /* IPSR0 */
 806         PINMUX_IPSR_GPSR(IP0_0, D0),
 807         PINMUX_IPSR_GPSR(IP0_1, D1),
 808         PINMUX_IPSR_GPSR(IP0_2, D2),
 809         PINMUX_IPSR_GPSR(IP0_3, D3),
 810         PINMUX_IPSR_GPSR(IP0_4, D4),
 811         PINMUX_IPSR_GPSR(IP0_5, D5),
 812         PINMUX_IPSR_GPSR(IP0_6, D6),
 813         PINMUX_IPSR_GPSR(IP0_7, D7),
 814         PINMUX_IPSR_GPSR(IP0_8, D8),
 815         PINMUX_IPSR_GPSR(IP0_9, D9),
 816         PINMUX_IPSR_GPSR(IP0_10, D10),
 817         PINMUX_IPSR_GPSR(IP0_11, D11),
 818         PINMUX_IPSR_GPSR(IP0_12, D12),
 819         PINMUX_IPSR_GPSR(IP0_13, D13),
 820         PINMUX_IPSR_GPSR(IP0_14, D14),
 821         PINMUX_IPSR_GPSR(IP0_15, D15),
 822         PINMUX_IPSR_GPSR(IP0_18_16, A0),
 823         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 824         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 825         PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
 826         PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
 827         PINMUX_IPSR_GPSR(IP0_20_19, A1),
 828         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 829         PINMUX_IPSR_GPSR(IP0_22_21, A2),
 830         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 831         PINMUX_IPSR_GPSR(IP0_24_23, A3),
 832         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 833         PINMUX_IPSR_GPSR(IP0_26_25, A4),
 834         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 835         PINMUX_IPSR_GPSR(IP0_28_27, A5),
 836         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 837         PINMUX_IPSR_GPSR(IP0_30_29, A6),
 838         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 839
 840         /* IPSR1 */
 841         PINMUX_IPSR_GPSR(IP1_1_0, A7),
 842         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 843         PINMUX_IPSR_GPSR(IP1_3_2, A8),
 844         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 845         PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
 846         PINMUX_IPSR_GPSR(IP1_5_4, A9),
 847         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 848         PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
 849         PINMUX_IPSR_GPSR(IP1_7_6, A10),
 850         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 851         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 852         PINMUX_IPSR_GPSR(IP1_10_8, A11),
 853         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 854         PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
 855         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 856         PINMUX_IPSR_GPSR(IP1_13_11, A12),
 857         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
 858         PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
 859         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 860         PINMUX_IPSR_GPSR(IP1_16_14, A13),
 861         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 862         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
 863         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 864         PINMUX_IPSR_GPSR(IP1_19_17, A14),
 865         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 866         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
 867         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
 868         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 869         PINMUX_IPSR_GPSR(IP1_22_20, A15),
 870         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
 871         PINMUX_IPSR_GPSR(IP1_25_23, A16),
 872         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
 873         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
 874         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 875         PINMUX_IPSR_GPSR(IP1_28_26, A17),
 876         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
 877         PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
 878         PINMUX_IPSR_GPSR(IP1_31_29, A18),
 879         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
 880         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 881         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 882
 883         /* IPSR2 */
 884         PINMUX_IPSR_GPSR(IP2_2_0, A19),
 885         PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
 886         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 887         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 888         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
 889         PINMUX_IPSR_GPSR(IP2_2_0, A20),
 890         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
 891         PINMUX_IPSR_GPSR(IP2_6_5, A21),
 892         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 893         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 894         PINMUX_IPSR_GPSR(IP2_9_7, A22),
 895         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
 896         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
 897         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
 898         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 899         PINMUX_IPSR_GPSR(IP2_12_10, A23),
 900         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
 901         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
 902         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
 903         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 904         PINMUX_IPSR_GPSR(IP2_15_13, A24),
 905         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
 906         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
 907         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
 908         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 909         PINMUX_IPSR_GPSR(IP2_18_16, A25),
 910         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
 911         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
 912         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
 913         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
 914         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 915         PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
 916         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 917         PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
 918         PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
 919         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 920         PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
 921         PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
 922         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 923         PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
 924         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 925         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 926         PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
 927         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 928         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 929         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
 930         PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
 931
 932         /* IPSR3 */
 933         PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
 934         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
 935         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 936         PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
 937         PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
 938         PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
 939         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 940         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 941         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 942         PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
 943         PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
 944         PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
 945         PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
 946         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 947         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 948         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 949         PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
 950         PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
 951         PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
 952         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 953         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
 954         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 955         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
 956         PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
 957         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 958         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 959         PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
 960         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 961         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 962         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 963         PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
 964         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 965         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 966         PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
 967         PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
 968         PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
 969         PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
 970         PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
 971         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
 972         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
 973         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 974         PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 975         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 976         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 977         PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
 978         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 979         PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 980         PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 981         PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 982         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 983         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 984         PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 985         PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 986         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 987         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 988         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 989
 990         /* IPSR4 */
 991         PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 992         PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1),
 993         PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1),
 994         PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 995         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 996         PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1),
 997         PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1),
 998         PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
 999         PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1000         PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1001         PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1),
1002         PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1),
1003         PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1004         PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1005         PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1006         PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
1007         PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
1008         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1009         PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1010         PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
1011         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1012         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1013         PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1014         PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
1015         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1016         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1017         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1018         PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1019         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1020         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1021         PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1022         PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1023         PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1024         PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1025         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1026         PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1027         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1028         PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1029         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1030         PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1031         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1032         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1033         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1034         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1035         PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1036
1037         /* IPSR5 */
1038         PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1039         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1040         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1041         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1042         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1043         PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1044         PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1045         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1046         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1047         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1048         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1049         PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1050         PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1051         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1052         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1053         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1054         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1055         PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1056         PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1057         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1058         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1059         PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1060         PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1061         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1062         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1063         PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1064         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1065         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1066         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1067         PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1068         PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1069         PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1070         PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1071         PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1072         PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1073         PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1074         PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1075         PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1076         PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1077         PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1078         PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1079         PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1080         PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1081         PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1082         PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1083         PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1084         PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1085         PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1086         PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1087
1088         /* IPSR6 */
1089         PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1090         PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1091         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1092         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1093         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1094         PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1095         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1096         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1097         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1098         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1099         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1100         PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1101         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1102         PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
1103         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1104         PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1105         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1106         PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1107         PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1108         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1109         PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1110         PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1111         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1112         PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1113         PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1114         PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
1115         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1116         PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1117         PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1118         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1119         PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
1120         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1121         PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1122         PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1123         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1124         PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
1125         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1126         PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1127         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1128         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1129         PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
1130         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1131         PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1132         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1133         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1134         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1135         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1136         PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1137         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1138         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1139         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1140         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1141
1142         /* IPSR7 */
1143         PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1144         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1145         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1146         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1147         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1148         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1149         PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1150         PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1151         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1152         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1153         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1154         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1155         PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1156         PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1157         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1158         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1159         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1160         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1161         PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1162         PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1163         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1164         PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1165         PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1166         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1167         PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1168         PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1169         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1170         PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1171         PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1172         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1173         PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1174         PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1175         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1176         PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1177         PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1178         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1179         PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1180         PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1181         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1182         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1183         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1184         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1185         PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1186         PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1187         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1188         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1189         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1190         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1191         PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1192         PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1193         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1194         PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1195         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1196         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1197
1198         /* IPSR8 */
1199         PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1200         PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1201         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1202         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1203         PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1204         PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1205         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1206         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1207         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1208         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1209         PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1210         PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1211         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1212         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1213         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1214         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1215         PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1216         PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1217         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1218         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1219         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1220         PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1221         PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1222         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1223         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1224         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1225         PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1226         PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1227         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1228         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1229         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1230         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1231         PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1232         PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1233         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1234         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1235         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1236         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1237         PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1238         PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1239         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1240         PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1241         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1242         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1243         PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1244         PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1245         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1246         PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1247         PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1248         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1249         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1250         PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1251         PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1252         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1253         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1254         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1255
1256         /* IPSR9 */
1257         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1258         PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1259         PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
1260         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1261         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1262         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1263         PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1264         PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
1265         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1266         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1267         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1268         PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1269         PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1270         PINMUX_IPSR_GPSR(IP9_7, QCLK),
1271         PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1272         PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1273         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1274         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1275         PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
1276         PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1277         PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1278         PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1279         PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1280         PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1281         PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1282         PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1283         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1284         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1285         PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
1286         PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1287         PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1288         PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1289         PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1290         PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1291         PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1292         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1293         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1294         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1295         PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1296         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1297         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1298         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1299         PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1300         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1301         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1302         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1303         PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1304         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1305         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1306         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1307         PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1308         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1309         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1310         PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1311         PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
1312         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1313         PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
1314         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1315         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1316         PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1317
1318         /* IPSR10 */
1319         PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1320         PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
1321         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1322         PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
1323         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1324         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1325         PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1326         PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1327         PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1328         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1329         PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
1330         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1331         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1332         PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1333         PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1334         PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1335         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1336         PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
1337         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1338         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1339         PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1340         PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1341         PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1342         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1343         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1344         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1345         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1346         PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1347         PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1348         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1349         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1350         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1351         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1352         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1353         PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1354         PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1355         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1356         PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1357         PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1358         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1359         PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1360         PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1361         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1362         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1363         PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1364         PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1365         PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1366         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1367         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1368         PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1369         PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1370         PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1371         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1372         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1373         PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1374         PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1375         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1376         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1377         PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1378         PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1379         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1380         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1381         PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
1382
1383         /* IPSR11 */
1384         PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1385         PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1386         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1387         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1388         PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
1389         PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1390         PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1391         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1392         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1393         PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
1394         PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1395         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1396         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1397         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1398         PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1),
1399         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1400         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1401         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1402         PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1403         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1404         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1405         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1406         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1407         PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1408         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1409         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1410         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1411         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1412         PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1413         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1414         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1415         PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1416         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1417         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1418         PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1419         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1420         PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1421         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1422         PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1423         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1424         PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1425         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1426         PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1427         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1428         PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1429         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1430         PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1431         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1432         PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1433         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1434         PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1435         PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1436         PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1437         PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
1438         PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1439         PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1440         PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
1441
1442         /* IPSR12 */
1443         PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1444         PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1445         PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
1446         PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
1447         PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1448         PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1449         PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
1450         PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
1451         PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1452         PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1453         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1454         PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
1455         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1456         PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1457         PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1458         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1459         PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
1460         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1461         PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1462         PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1463         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1464         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1465         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1466         PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1467         PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1468         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1469         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1470         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1471         PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1472         PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1473         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1474         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1475         PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1476         PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1477         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1478         PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1479         PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1480         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1481         PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1482         PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1483         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1484         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1485         PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1486         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1487         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1488         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1489         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1490         PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1491         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1492         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1493         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1494
1495         /* IPSR13 */
1496         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1497         PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1498         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1499         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1500         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1501         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1502         PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1503         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1504         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1505         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1506         PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1507         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1508         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1509         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1510         PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1511         PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1512         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1513         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1514         PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1515         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1516         PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1517         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1518         PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1519         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1520         PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1521         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1522         PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1523         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1524         PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1525         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1526         PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1527         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1528         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1529         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1530         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1531         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1532         PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1533         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1534         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1535         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1536         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1537         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1538         PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1539         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1540         PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1541         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1542         PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1543         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1544         PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1545         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1546         PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1547         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1548         PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1549         PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1550         PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1551         PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
1552
1553         /* IPSR14 */
1554         PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1555         PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1556         PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
1557         PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1558         PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1559         PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1560         PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1561         PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1562         PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1563         PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1564         PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1565         PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1566         PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1567         PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1568         PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1569         PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1570         PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1571         PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
1572         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1573         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1574         PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1575         PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1576         PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
1577         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1578         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1579         PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1580         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1581         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1582         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1583         PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1584         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1585         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1586         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1587         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1588         PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1589         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1590         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1591         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1592         PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1593         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1594         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1595         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1596         PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1597         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1598         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1599         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1600         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1601         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1602         PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
1603         PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1604         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1605         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1606         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1607         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1608         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1609         PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
1610         PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1611
1612         /* IPSR15 */
1613         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1614         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1615         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1616         PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1617         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1618         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1619         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1620         PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1621         PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1622         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1623         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1624         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1625         PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1626         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1627         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1628         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1629         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1630         PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1631         PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1632         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1633         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1634         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1635         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1636         PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1637         PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1638         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1639         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1640         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1641         PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1642         PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1643         PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1644         PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1645         PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1646         PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1647         PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1648         PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1649         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1650         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1651         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1652         PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1653         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1654         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1655         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1656         PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1657         PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1658         PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1659         PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1660         PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1661         PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1662         PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1663         PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1664
1665         /* IPSR16 */
1666         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1667         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1668         PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1669         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1670         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1671         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1672         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1673         PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1674         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1675         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1676         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1677         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1678         PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1679         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1680         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1681         PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1682         PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1683         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1684         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1685         PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1686         PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1687         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1688 };
1689
1690 static const struct sh_pfc_pin pinmux_pins[] = {
1691         PINMUX_GPIO_GP_ALL(),
1692 };
1693
1694 /* - Audio Clock ------------------------------------------------------------ */
1695 static const unsigned int audio_clk_a_pins[] = {
1696         /* CLK */
1697         RCAR_GP_PIN(2, 28),
1698 };
1699
1700 static const unsigned int audio_clk_a_mux[] = {
1701         AUDIO_CLKA_MARK,
1702 };
1703
1704 static const unsigned int audio_clk_b_pins[] = {
1705         /* CLK */
1706         RCAR_GP_PIN(2, 29),
1707 };
1708
1709 static const unsigned int audio_clk_b_mux[] = {
1710         AUDIO_CLKB_MARK,
1711 };
1712
1713 static const unsigned int audio_clk_b_b_pins[] = {
1714         /* CLK */
1715         RCAR_GP_PIN(7, 20),
1716 };
1717
1718 static const unsigned int audio_clk_b_b_mux[] = {
1719         AUDIO_CLKB_B_MARK,
1720 };
1721
1722 static const unsigned int audio_clk_c_pins[] = {
1723         /* CLK */
1724         RCAR_GP_PIN(2, 30),
1725 };
1726
1727 static const unsigned int audio_clk_c_mux[] = {
1728         AUDIO_CLKC_MARK,
1729 };
1730
1731 static const unsigned int audio_clkout_pins[] = {
1732         /* CLK */
1733         RCAR_GP_PIN(2, 31),
1734 };
1735
1736 static const unsigned int audio_clkout_mux[] = {
1737         AUDIO_CLKOUT_MARK,
1738 };
1739
1740 /* - AVB -------------------------------------------------------------------- */
1741 static const unsigned int avb_link_pins[] = {
1742         RCAR_GP_PIN(5, 14),
1743 };
1744 static const unsigned int avb_link_mux[] = {
1745         AVB_LINK_MARK,
1746 };
1747 static const unsigned int avb_magic_pins[] = {
1748         RCAR_GP_PIN(5, 11),
1749 };
1750 static const unsigned int avb_magic_mux[] = {
1751         AVB_MAGIC_MARK,
1752 };
1753 static const unsigned int avb_phy_int_pins[] = {
1754         RCAR_GP_PIN(5, 16),
1755 };
1756 static const unsigned int avb_phy_int_mux[] = {
1757         AVB_PHY_INT_MARK,
1758 };
1759 static const unsigned int avb_mdio_pins[] = {
1760         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1761 };
1762 static const unsigned int avb_mdio_mux[] = {
1763         AVB_MDC_MARK, AVB_MDIO_MARK,
1764 };
1765 static const unsigned int avb_mii_pins[] = {
1766         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1767         RCAR_GP_PIN(5, 21),
1768
1769         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1770         RCAR_GP_PIN(5, 3),
1771
1772         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1773         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1774         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1775 };
1776 static const unsigned int avb_mii_mux[] = {
1777         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1778         AVB_TXD3_MARK,
1779
1780         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1781         AVB_RXD3_MARK,
1782
1783         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1784         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1785         AVB_TX_CLK_MARK, AVB_COL_MARK,
1786 };
1787 static const unsigned int avb_gmii_pins[] = {
1788         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1789         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1790         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1791
1792         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1793         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1794         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1795
1796         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1797         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1798         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1799         RCAR_GP_PIN(5, 29),
1800 };
1801 static const unsigned int avb_gmii_mux[] = {
1802         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1803         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1804         AVB_TXD6_MARK, AVB_TXD7_MARK,
1805
1806         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1807         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1808         AVB_RXD6_MARK, AVB_RXD7_MARK,
1809
1810         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1811         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1812         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1813         AVB_COL_MARK,
1814 };
1815
1816 /* - CAN -------------------------------------------------------------------- */
1817
1818 static const unsigned int can0_data_pins[] = {
1819         /* TX, RX */
1820         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1821 };
1822
1823 static const unsigned int can0_data_mux[] = {
1824         CAN0_TX_MARK, CAN0_RX_MARK,
1825 };
1826
1827 static const unsigned int can0_data_b_pins[] = {
1828         /* TX, RX */
1829         RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1830 };
1831
1832 static const unsigned int can0_data_b_mux[] = {
1833         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1834 };
1835
1836 static const unsigned int can0_data_c_pins[] = {
1837         /* TX, RX */
1838         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1839 };
1840
1841 static const unsigned int can0_data_c_mux[] = {
1842         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1843 };
1844
1845 static const unsigned int can0_data_d_pins[] = {
1846         /* TX, RX */
1847         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1848 };
1849
1850 static const unsigned int can0_data_d_mux[] = {
1851         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1852 };
1853
1854 static const unsigned int can0_data_e_pins[] = {
1855         /* TX, RX */
1856         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1857 };
1858
1859 static const unsigned int can0_data_e_mux[] = {
1860         CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1861 };
1862
1863 static const unsigned int can0_data_f_pins[] = {
1864         /* TX, RX */
1865         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1866 };
1867
1868 static const unsigned int can0_data_f_mux[] = {
1869         CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1870 };
1871
1872 static const unsigned int can1_data_pins[] = {
1873         /* TX, RX */
1874          RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1875 };
1876
1877 static const unsigned int can1_data_mux[] = {
1878         CAN1_TX_MARK, CAN1_RX_MARK,
1879 };
1880
1881 static const unsigned int can1_data_b_pins[] = {
1882         /* TX, RX */
1883         RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1884 };
1885
1886 static const unsigned int can1_data_b_mux[] = {
1887         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1888 };
1889
1890 static const unsigned int can1_data_c_pins[] = {
1891         /* TX, RX */
1892         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1893 };
1894
1895 static const unsigned int can1_data_c_mux[] = {
1896         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1897 };
1898
1899 static const unsigned int can1_data_d_pins[] = {
1900         /* TX, RX */
1901          RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1902 };
1903
1904 static const unsigned int can1_data_d_mux[] = {
1905         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1906 };
1907
1908 static const unsigned int can_clk_pins[] = {
1909         /* CLK */
1910         RCAR_GP_PIN(7, 2),
1911 };
1912
1913 static const unsigned int can_clk_mux[] = {
1914         CAN_CLK_MARK,
1915 };
1916
1917 static const unsigned int can_clk_b_pins[] = {
1918         /* CLK */
1919         RCAR_GP_PIN(5, 21),
1920 };
1921
1922 static const unsigned int can_clk_b_mux[] = {
1923         CAN_CLK_B_MARK,
1924 };
1925
1926 static const unsigned int can_clk_c_pins[] = {
1927         /* CLK */
1928         RCAR_GP_PIN(4, 30),
1929 };
1930
1931 static const unsigned int can_clk_c_mux[] = {
1932         CAN_CLK_C_MARK,
1933 };
1934
1935 static const unsigned int can_clk_d_pins[] = {
1936         /* CLK */
1937         RCAR_GP_PIN(7, 19),
1938 };
1939
1940 static const unsigned int can_clk_d_mux[] = {
1941         CAN_CLK_D_MARK,
1942 };
1943
1944 /* - DU --------------------------------------------------------------------- */
1945 static const unsigned int du_rgb666_pins[] = {
1946         /* R[7:2], G[7:2], B[7:2] */
1947         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1948         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1949         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1950         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1951         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1952         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1953 };
1954 static const unsigned int du_rgb666_mux[] = {
1955         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1956         DU1_DR3_MARK, DU1_DR2_MARK,
1957         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1958         DU1_DG3_MARK, DU1_DG2_MARK,
1959         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1960         DU1_DB3_MARK, DU1_DB2_MARK,
1961 };
1962 static const unsigned int du_rgb888_pins[] = {
1963         /* R[7:0], G[7:0], B[7:0] */
1964         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1965         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1966         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
1967         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1968         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1969         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
1970         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1971         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1972         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1973 };
1974 static const unsigned int du_rgb888_mux[] = {
1975         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1976         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1977         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1978         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1979         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1980         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1981 };
1982 static const unsigned int du_clk_out_0_pins[] = {
1983         /* CLKOUT */
1984         RCAR_GP_PIN(3, 25),
1985 };
1986 static const unsigned int du_clk_out_0_mux[] = {
1987         DU1_DOTCLKOUT0_MARK
1988 };
1989 static const unsigned int du_clk_out_1_pins[] = {
1990         /* CLKOUT */
1991         RCAR_GP_PIN(3, 26),
1992 };
1993 static const unsigned int du_clk_out_1_mux[] = {
1994         DU1_DOTCLKOUT1_MARK
1995 };
1996 static const unsigned int du_sync_pins[] = {
1997         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1998         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1999 };
2000 static const unsigned int du_sync_mux[] = {
2001         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2002 };
2003 static const unsigned int du_oddf_pins[] = {
2004         /* EXDISP/EXODDF/EXCDE */
2005         RCAR_GP_PIN(3, 29),
2006 };
2007 static const unsigned int du_oddf_mux[] = {
2008         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2009 };
2010 static const unsigned int du_cde_pins[] = {
2011         /* CDE */
2012         RCAR_GP_PIN(3, 31),
2013 };
2014 static const unsigned int du_cde_mux[] = {
2015         DU1_CDE_MARK,
2016 };
2017 static const unsigned int du_disp_pins[] = {
2018         /* DISP */
2019         RCAR_GP_PIN(3, 30),
2020 };
2021 static const unsigned int du_disp_mux[] = {
2022         DU1_DISP_MARK,
2023 };
2024 static const unsigned int du0_clk_in_pins[] = {
2025         /* CLKIN */
2026         RCAR_GP_PIN(6, 31),
2027 };
2028 static const unsigned int du0_clk_in_mux[] = {
2029         DU0_DOTCLKIN_MARK
2030 };
2031 static const unsigned int du1_clk_in_pins[] = {
2032         /* CLKIN */
2033         RCAR_GP_PIN(3, 24),
2034 };
2035 static const unsigned int du1_clk_in_mux[] = {
2036         DU1_DOTCLKIN_MARK
2037 };
2038 static const unsigned int du1_clk_in_b_pins[] = {
2039         /* CLKIN */
2040         RCAR_GP_PIN(7, 19),
2041 };
2042 static const unsigned int du1_clk_in_b_mux[] = {
2043         DU1_DOTCLKIN_B_MARK,
2044 };
2045 static const unsigned int du1_clk_in_c_pins[] = {
2046         /* CLKIN */
2047         RCAR_GP_PIN(7, 20),
2048 };
2049 static const unsigned int du1_clk_in_c_mux[] = {
2050         DU1_DOTCLKIN_C_MARK,
2051 };
2052 /* - ETH -------------------------------------------------------------------- */
2053 static const unsigned int eth_link_pins[] = {
2054         /* LINK */
2055         RCAR_GP_PIN(5, 18),
2056 };
2057 static const unsigned int eth_link_mux[] = {
2058         ETH_LINK_MARK,
2059 };
2060 static const unsigned int eth_magic_pins[] = {
2061         /* MAGIC */
2062         RCAR_GP_PIN(5, 22),
2063 };
2064 static const unsigned int eth_magic_mux[] = {
2065         ETH_MAGIC_MARK,
2066 };
2067 static const unsigned int eth_mdio_pins[] = {
2068         /* MDC, MDIO */
2069         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2070 };
2071 static const unsigned int eth_mdio_mux[] = {
2072         ETH_MDC_MARK, ETH_MDIO_MARK,
2073 };
2074 static const unsigned int eth_rmii_pins[] = {
2075         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2076         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2077         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2078         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2079 };
2080 static const unsigned int eth_rmii_mux[] = {
2081         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2082         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2083 };
2084
2085 /* - HSCIF0 ----------------------------------------------------------------- */
2086 static const unsigned int hscif0_data_pins[] = {
2087         /* RX, TX */
2088         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2089 };
2090 static const unsigned int hscif0_data_mux[] = {
2091         HRX0_MARK, HTX0_MARK,
2092 };
2093 static const unsigned int hscif0_clk_pins[] = {
2094         /* SCK */
2095         RCAR_GP_PIN(7, 2),
2096 };
2097 static const unsigned int hscif0_clk_mux[] = {
2098         HSCK0_MARK,
2099 };
2100 static const unsigned int hscif0_ctrl_pins[] = {
2101         /* RTS, CTS */
2102         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2103 };
2104 static const unsigned int hscif0_ctrl_mux[] = {
2105         HRTS0_N_MARK, HCTS0_N_MARK,
2106 };
2107 static const unsigned int hscif0_data_b_pins[] = {
2108         /* RX, TX */
2109         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2110 };
2111 static const unsigned int hscif0_data_b_mux[] = {
2112         HRX0_B_MARK, HTX0_B_MARK,
2113 };
2114 static const unsigned int hscif0_ctrl_b_pins[] = {
2115         /* RTS, CTS */
2116         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2117 };
2118 static const unsigned int hscif0_ctrl_b_mux[] = {
2119         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2120 };
2121 static const unsigned int hscif0_data_c_pins[] = {
2122         /* RX, TX */
2123         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2124 };
2125 static const unsigned int hscif0_data_c_mux[] = {
2126         HRX0_C_MARK, HTX0_C_MARK,
2127 };
2128 static const unsigned int hscif0_clk_c_pins[] = {
2129         /* SCK */
2130         RCAR_GP_PIN(5, 31),
2131 };
2132 static const unsigned int hscif0_clk_c_mux[] = {
2133         HSCK0_C_MARK,
2134 };
2135 /* - HSCIF1 ----------------------------------------------------------------- */
2136 static const unsigned int hscif1_data_pins[] = {
2137         /* RX, TX */
2138         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2139 };
2140 static const unsigned int hscif1_data_mux[] = {
2141         HRX1_MARK, HTX1_MARK,
2142 };
2143 static const unsigned int hscif1_clk_pins[] = {
2144         /* SCK */
2145         RCAR_GP_PIN(7, 7),
2146 };
2147 static const unsigned int hscif1_clk_mux[] = {
2148         HSCK1_MARK,
2149 };
2150 static const unsigned int hscif1_ctrl_pins[] = {
2151         /* RTS, CTS */
2152         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2153 };
2154 static const unsigned int hscif1_ctrl_mux[] = {
2155         HRTS1_N_MARK, HCTS1_N_MARK,
2156 };
2157 static const unsigned int hscif1_data_b_pins[] = {
2158         /* RX, TX */
2159         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2160 };
2161 static const unsigned int hscif1_data_b_mux[] = {
2162         HRX1_B_MARK, HTX1_B_MARK,
2163 };
2164 static const unsigned int hscif1_data_c_pins[] = {
2165         /* RX, TX */
2166         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2167 };
2168 static const unsigned int hscif1_data_c_mux[] = {
2169         HRX1_C_MARK, HTX1_C_MARK,
2170 };
2171 static const unsigned int hscif1_clk_c_pins[] = {
2172         /* SCK */
2173         RCAR_GP_PIN(7, 16),
2174 };
2175 static const unsigned int hscif1_clk_c_mux[] = {
2176         HSCK1_C_MARK,
2177 };
2178 static const unsigned int hscif1_ctrl_c_pins[] = {
2179         /* RTS, CTS */
2180         RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2181 };
2182 static const unsigned int hscif1_ctrl_c_mux[] = {
2183         HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2184 };
2185 static const unsigned int hscif1_data_d_pins[] = {
2186         /* RX, TX */
2187         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2188 };
2189 static const unsigned int hscif1_data_d_mux[] = {
2190         HRX1_D_MARK, HTX1_D_MARK,
2191 };
2192 static const unsigned int hscif1_data_e_pins[] = {
2193         /* RX, TX */
2194         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2195 };
2196 static const unsigned int hscif1_data_e_mux[] = {
2197         HRX1_C_MARK, HTX1_C_MARK,
2198 };
2199 static const unsigned int hscif1_clk_e_pins[] = {
2200         /* SCK */
2201         RCAR_GP_PIN(2, 6),
2202 };
2203 static const unsigned int hscif1_clk_e_mux[] = {
2204         HSCK1_E_MARK,
2205 };
2206 static const unsigned int hscif1_ctrl_e_pins[] = {
2207         /* RTS, CTS */
2208         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2209 };
2210 static const unsigned int hscif1_ctrl_e_mux[] = {
2211         HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2212 };
2213 /* - HSCIF2 ----------------------------------------------------------------- */
2214 static const unsigned int hscif2_data_pins[] = {
2215         /* RX, TX */
2216         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2217 };
2218 static const unsigned int hscif2_data_mux[] = {
2219         HRX2_MARK, HTX2_MARK,
2220 };
2221 static const unsigned int hscif2_clk_pins[] = {
2222         /* SCK */
2223         RCAR_GP_PIN(4, 15),
2224 };
2225 static const unsigned int hscif2_clk_mux[] = {
2226         HSCK2_MARK,
2227 };
2228 static const unsigned int hscif2_ctrl_pins[] = {
2229         /* RTS, CTS */
2230         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2231 };
2232 static const unsigned int hscif2_ctrl_mux[] = {
2233         HRTS2_N_MARK, HCTS2_N_MARK,
2234 };
2235 static const unsigned int hscif2_data_b_pins[] = {
2236         /* RX, TX */
2237         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2238 };
2239 static const unsigned int hscif2_data_b_mux[] = {
2240         HRX2_B_MARK, HTX2_B_MARK,
2241 };
2242 static const unsigned int hscif2_ctrl_b_pins[] = {
2243         /* RTS, CTS */
2244         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2245 };
2246 static const unsigned int hscif2_ctrl_b_mux[] = {
2247         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2248 };
2249 static const unsigned int hscif2_data_c_pins[] = {
2250         /* RX, TX */
2251         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2252 };
2253 static const unsigned int hscif2_data_c_mux[] = {
2254         HRX2_C_MARK, HTX2_C_MARK,
2255 };
2256 static const unsigned int hscif2_clk_c_pins[] = {
2257         /* SCK */
2258         RCAR_GP_PIN(5, 31),
2259 };
2260 static const unsigned int hscif2_clk_c_mux[] = {
2261         HSCK2_C_MARK,
2262 };
2263 static const unsigned int hscif2_data_d_pins[] = {
2264         /* RX, TX */
2265         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2266 };
2267 static const unsigned int hscif2_data_d_mux[] = {
2268         HRX2_B_MARK, HTX2_D_MARK,
2269 };
2270 /* - I2C0 ------------------------------------------------------------------- */
2271 static const unsigned int i2c0_pins[] = {
2272         /* SCL, SDA */
2273         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2274 };
2275 static const unsigned int i2c0_mux[] = {
2276         SCL0_MARK, SDA0_MARK,
2277 };
2278 static const unsigned int i2c0_b_pins[] = {
2279         /* SCL, SDA */
2280         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2281 };
2282 static const unsigned int i2c0_b_mux[] = {
2283         SCL0_B_MARK, SDA0_B_MARK,
2284 };
2285 static const unsigned int i2c0_c_pins[] = {
2286         /* SCL, SDA */
2287         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2288 };
2289 static const unsigned int i2c0_c_mux[] = {
2290         SCL0_C_MARK, SDA0_C_MARK,
2291 };
2292 /* - I2C1 ------------------------------------------------------------------- */
2293 static const unsigned int i2c1_pins[] = {
2294         /* SCL, SDA */
2295         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2296 };
2297 static const unsigned int i2c1_mux[] = {
2298         SCL1_MARK, SDA1_MARK,
2299 };
2300 static const unsigned int i2c1_b_pins[] = {
2301         /* SCL, SDA */
2302         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2303 };
2304 static const unsigned int i2c1_b_mux[] = {
2305         SCL1_B_MARK, SDA1_B_MARK,
2306 };
2307 static const unsigned int i2c1_c_pins[] = {
2308         /* SCL, SDA */
2309         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2310 };
2311 static const unsigned int i2c1_c_mux[] = {
2312         SCL1_C_MARK, SDA1_C_MARK,
2313 };
2314 static const unsigned int i2c1_d_pins[] = {
2315         /* SCL, SDA */
2316         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2317 };
2318 static const unsigned int i2c1_d_mux[] = {
2319         SCL1_D_MARK, SDA1_D_MARK,
2320 };
2321 static const unsigned int i2c1_e_pins[] = {
2322         /* SCL, SDA */
2323         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2324 };
2325 static const unsigned int i2c1_e_mux[] = {
2326         SCL1_E_MARK, SDA1_E_MARK,
2327 };
2328 /* - I2C2 ------------------------------------------------------------------- */
2329 static const unsigned int i2c2_pins[] = {
2330         /* SCL, SDA */
2331         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2332 };
2333 static const unsigned int i2c2_mux[] = {
2334         SCL2_MARK, SDA2_MARK,
2335 };
2336 static const unsigned int i2c2_b_pins[] = {
2337         /* SCL, SDA */
2338         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2339 };
2340 static const unsigned int i2c2_b_mux[] = {
2341         SCL2_B_MARK, SDA2_B_MARK,
2342 };
2343 static const unsigned int i2c2_c_pins[] = {
2344         /* SCL, SDA */
2345         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2346 };
2347 static const unsigned int i2c2_c_mux[] = {
2348         SCL2_C_MARK, SDA2_C_MARK,
2349 };
2350 static const unsigned int i2c2_d_pins[] = {
2351         /* SCL, SDA */
2352         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2353 };
2354 static const unsigned int i2c2_d_mux[] = {
2355         SCL2_D_MARK, SDA2_D_MARK,
2356 };
2357 /* - I2C3 ------------------------------------------------------------------- */
2358 static const unsigned int i2c3_pins[] = {
2359         /* SCL, SDA */
2360         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2361 };
2362 static const unsigned int i2c3_mux[] = {
2363         SCL3_MARK, SDA3_MARK,
2364 };
2365 static const unsigned int i2c3_b_pins[] = {
2366         /* SCL, SDA */
2367         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2368 };
2369 static const unsigned int i2c3_b_mux[] = {
2370         SCL3_B_MARK, SDA3_B_MARK,
2371 };
2372 static const unsigned int i2c3_c_pins[] = {
2373         /* SCL, SDA */
2374         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2375 };
2376 static const unsigned int i2c3_c_mux[] = {
2377         SCL3_C_MARK, SDA3_C_MARK,
2378 };
2379 static const unsigned int i2c3_d_pins[] = {
2380         /* SCL, SDA */
2381         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2382 };
2383 static const unsigned int i2c3_d_mux[] = {
2384         SCL3_D_MARK, SDA3_D_MARK,
2385 };
2386 /* - I2C4 ------------------------------------------------------------------- */
2387 static const unsigned int i2c4_pins[] = {
2388         /* SCL, SDA */
2389         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2390 };
2391 static const unsigned int i2c4_mux[] = {
2392         SCL4_MARK, SDA4_MARK,
2393 };
2394 static const unsigned int i2c4_b_pins[] = {
2395         /* SCL, SDA */
2396         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2397 };
2398 static const unsigned int i2c4_b_mux[] = {
2399         SCL4_B_MARK, SDA4_B_MARK,
2400 };
2401 static const unsigned int i2c4_c_pins[] = {
2402         /* SCL, SDA */
2403         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2404 };
2405 static const unsigned int i2c4_c_mux[] = {
2406         SCL4_C_MARK, SDA4_C_MARK,
2407 };
2408 /* - I2C7 ------------------------------------------------------------------- */
2409 static const unsigned int i2c7_pins[] = {
2410         /* SCL, SDA */
2411         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2412 };
2413 static const unsigned int i2c7_mux[] = {
2414         SCL7_MARK, SDA7_MARK,
2415 };
2416 static const unsigned int i2c7_b_pins[] = {
2417         /* SCL, SDA */
2418         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2419 };
2420 static const unsigned int i2c7_b_mux[] = {
2421         SCL7_B_MARK, SDA7_B_MARK,
2422 };
2423 static const unsigned int i2c7_c_pins[] = {
2424         /* SCL, SDA */
2425         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2426 };
2427 static const unsigned int i2c7_c_mux[] = {
2428         SCL7_C_MARK, SDA7_C_MARK,
2429 };
2430 /* - I2C8 ------------------------------------------------------------------- */
2431 static const unsigned int i2c8_pins[] = {
2432         /* SCL, SDA */
2433         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2434 };
2435 static const unsigned int i2c8_mux[] = {
2436         SCL8_MARK, SDA8_MARK,
2437 };
2438 static const unsigned int i2c8_b_pins[] = {
2439         /* SCL, SDA */
2440         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2441 };
2442 static const unsigned int i2c8_b_mux[] = {
2443         SCL8_B_MARK, SDA8_B_MARK,
2444 };
2445 static const unsigned int i2c8_c_pins[] = {
2446         /* SCL, SDA */
2447         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2448 };
2449 static const unsigned int i2c8_c_mux[] = {
2450         SCL8_C_MARK, SDA8_C_MARK,
2451 };
2452 /* - INTC ------------------------------------------------------------------- */
2453 static const unsigned int intc_irq0_pins[] = {
2454         /* IRQ */
2455         RCAR_GP_PIN(7, 10),
2456 };
2457 static const unsigned int intc_irq0_mux[] = {
2458         IRQ0_MARK,
2459 };
2460 static const unsigned int intc_irq1_pins[] = {
2461         /* IRQ */
2462         RCAR_GP_PIN(7, 11),
2463 };
2464 static const unsigned int intc_irq1_mux[] = {
2465         IRQ1_MARK,
2466 };
2467 static const unsigned int intc_irq2_pins[] = {
2468         /* IRQ */
2469         RCAR_GP_PIN(7, 12),
2470 };
2471 static const unsigned int intc_irq2_mux[] = {
2472         IRQ2_MARK,
2473 };
2474 static const unsigned int intc_irq3_pins[] = {
2475         /* IRQ */
2476         RCAR_GP_PIN(7, 13),
2477 };
2478 static const unsigned int intc_irq3_mux[] = {
2479         IRQ3_MARK,
2480 };
2481 /* - MLB+ ------------------------------------------------------------------- */
2482 static const unsigned int mlb_3pin_pins[] = {
2483         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2484 };
2485 static const unsigned int mlb_3pin_mux[] = {
2486         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2487 };
2488 /* - MMCIF ------------------------------------------------------------------ */
2489 static const unsigned int mmc_data1_pins[] = {
2490         /* D[0] */
2491         RCAR_GP_PIN(6, 18),
2492 };
2493 static const unsigned int mmc_data1_mux[] = {
2494         MMC_D0_MARK,
2495 };
2496 static const unsigned int mmc_data4_pins[] = {
2497         /* D[0:3] */
2498         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2499         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2500 };
2501 static const unsigned int mmc_data4_mux[] = {
2502         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2503 };
2504 static const unsigned int mmc_data8_pins[] = {
2505         /* D[0:7] */
2506         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2507         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2508         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2509         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2510 };
2511 static const unsigned int mmc_data8_mux[] = {
2512         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2513         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2514 };
2515 static const unsigned int mmc_ctrl_pins[] = {
2516         /* CLK, CMD */
2517         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2518 };
2519 static const unsigned int mmc_ctrl_mux[] = {
2520         MMC_CLK_MARK, MMC_CMD_MARK,
2521 };
2522 /* - MSIOF0 ----------------------------------------------------------------- */
2523 static const unsigned int msiof0_clk_pins[] = {
2524         /* SCK */
2525         RCAR_GP_PIN(6, 24),
2526 };
2527 static const unsigned int msiof0_clk_mux[] = {
2528         MSIOF0_SCK_MARK,
2529 };
2530 static const unsigned int msiof0_sync_pins[] = {
2531         /* SYNC */
2532         RCAR_GP_PIN(6, 25),
2533 };
2534 static const unsigned int msiof0_sync_mux[] = {
2535         MSIOF0_SYNC_MARK,
2536 };
2537 static const unsigned int msiof0_ss1_pins[] = {
2538         /* SS1 */
2539         RCAR_GP_PIN(6, 28),
2540 };
2541 static const unsigned int msiof0_ss1_mux[] = {
2542         MSIOF0_SS1_MARK,
2543 };
2544 static const unsigned int msiof0_ss2_pins[] = {
2545         /* SS2 */
2546         RCAR_GP_PIN(6, 29),
2547 };
2548 static const unsigned int msiof0_ss2_mux[] = {
2549         MSIOF0_SS2_MARK,
2550 };
2551 static const unsigned int msiof0_rx_pins[] = {
2552         /* RXD */
2553         RCAR_GP_PIN(6, 27),
2554 };
2555 static const unsigned int msiof0_rx_mux[] = {
2556         MSIOF0_RXD_MARK,
2557 };
2558 static const unsigned int msiof0_tx_pins[] = {
2559         /* TXD */
2560         RCAR_GP_PIN(6, 26),
2561 };
2562 static const unsigned int msiof0_tx_mux[] = {
2563         MSIOF0_TXD_MARK,
2564 };
2565
2566 static const unsigned int msiof0_clk_b_pins[] = {
2567         /* SCK */
2568         RCAR_GP_PIN(0, 16),
2569 };
2570 static const unsigned int msiof0_clk_b_mux[] = {
2571         MSIOF0_SCK_B_MARK,
2572 };
2573 static const unsigned int msiof0_sync_b_pins[] = {
2574         /* SYNC */
2575         RCAR_GP_PIN(0, 17),
2576 };
2577 static const unsigned int msiof0_sync_b_mux[] = {
2578         MSIOF0_SYNC_B_MARK,
2579 };
2580 static const unsigned int msiof0_ss1_b_pins[] = {
2581         /* SS1 */
2582         RCAR_GP_PIN(0, 18),
2583 };
2584 static const unsigned int msiof0_ss1_b_mux[] = {
2585         MSIOF0_SS1_B_MARK,
2586 };
2587 static const unsigned int msiof0_ss2_b_pins[] = {
2588         /* SS2 */
2589         RCAR_GP_PIN(0, 19),
2590 };
2591 static const unsigned int msiof0_ss2_b_mux[] = {
2592         MSIOF0_SS2_B_MARK,
2593 };
2594 static const unsigned int msiof0_rx_b_pins[] = {
2595         /* RXD */
2596         RCAR_GP_PIN(0, 21),
2597 };
2598 static const unsigned int msiof0_rx_b_mux[] = {
2599         MSIOF0_RXD_B_MARK,
2600 };
2601 static const unsigned int msiof0_tx_b_pins[] = {
2602         /* TXD */
2603         RCAR_GP_PIN(0, 20),
2604 };
2605 static const unsigned int msiof0_tx_b_mux[] = {
2606         MSIOF0_TXD_B_MARK,
2607 };
2608
2609 static const unsigned int msiof0_clk_c_pins[] = {
2610         /* SCK */
2611         RCAR_GP_PIN(5, 26),
2612 };
2613 static const unsigned int msiof0_clk_c_mux[] = {
2614         MSIOF0_SCK_C_MARK,
2615 };
2616 static const unsigned int msiof0_sync_c_pins[] = {
2617         /* SYNC */
2618         RCAR_GP_PIN(5, 25),
2619 };
2620 static const unsigned int msiof0_sync_c_mux[] = {
2621         MSIOF0_SYNC_C_MARK,
2622 };
2623 static const unsigned int msiof0_ss1_c_pins[] = {
2624         /* SS1 */
2625         RCAR_GP_PIN(5, 27),
2626 };
2627 static const unsigned int msiof0_ss1_c_mux[] = {
2628         MSIOF0_SS1_C_MARK,
2629 };
2630 static const unsigned int msiof0_ss2_c_pins[] = {
2631         /* SS2 */
2632         RCAR_GP_PIN(5, 28),
2633 };
2634 static const unsigned int msiof0_ss2_c_mux[] = {
2635         MSIOF0_SS2_C_MARK,
2636 };
2637 static const unsigned int msiof0_rx_c_pins[] = {
2638         /* RXD */
2639         RCAR_GP_PIN(5, 29),
2640 };
2641 static const unsigned int msiof0_rx_c_mux[] = {
2642         MSIOF0_RXD_C_MARK,
2643 };
2644 static const unsigned int msiof0_tx_c_pins[] = {
2645         /* TXD */
2646         RCAR_GP_PIN(5, 30),
2647 };
2648 static const unsigned int msiof0_tx_c_mux[] = {
2649         MSIOF0_TXD_C_MARK,
2650 };
2651 /* - MSIOF1 ----------------------------------------------------------------- */
2652 static const unsigned int msiof1_clk_pins[] = {
2653         /* SCK */
2654         RCAR_GP_PIN(0, 22),
2655 };
2656 static const unsigned int msiof1_clk_mux[] = {
2657         MSIOF1_SCK_MARK,
2658 };
2659 static const unsigned int msiof1_sync_pins[] = {
2660         /* SYNC */
2661         RCAR_GP_PIN(0, 23),
2662 };
2663 static const unsigned int msiof1_sync_mux[] = {
2664         MSIOF1_SYNC_MARK,
2665 };
2666 static const unsigned int msiof1_ss1_pins[] = {
2667         /* SS1 */
2668         RCAR_GP_PIN(0, 24),
2669 };
2670 static const unsigned int msiof1_ss1_mux[] = {
2671         MSIOF1_SS1_MARK,
2672 };
2673 static const unsigned int msiof1_ss2_pins[] = {
2674         /* SS2 */
2675         RCAR_GP_PIN(0, 25),
2676 };
2677 static const unsigned int msiof1_ss2_mux[] = {
2678         MSIOF1_SS2_MARK,
2679 };
2680 static const unsigned int msiof1_rx_pins[] = {
2681         /* RXD */
2682         RCAR_GP_PIN(0, 27),
2683 };
2684 static const unsigned int msiof1_rx_mux[] = {
2685         MSIOF1_RXD_MARK,
2686 };
2687 static const unsigned int msiof1_tx_pins[] = {
2688         /* TXD */
2689         RCAR_GP_PIN(0, 26),
2690 };
2691 static const unsigned int msiof1_tx_mux[] = {
2692         MSIOF1_TXD_MARK,
2693 };
2694
2695 static const unsigned int msiof1_clk_b_pins[] = {
2696         /* SCK */
2697         RCAR_GP_PIN(2, 29),
2698 };
2699 static const unsigned int msiof1_clk_b_mux[] = {
2700         MSIOF1_SCK_B_MARK,
2701 };
2702 static const unsigned int msiof1_sync_b_pins[] = {
2703         /* SYNC */
2704         RCAR_GP_PIN(2, 30),
2705 };
2706 static const unsigned int msiof1_sync_b_mux[] = {
2707         MSIOF1_SYNC_B_MARK,
2708 };
2709 static const unsigned int msiof1_ss1_b_pins[] = {
2710         /* SS1 */
2711         RCAR_GP_PIN(2, 31),
2712 };
2713 static const unsigned int msiof1_ss1_b_mux[] = {
2714         MSIOF1_SS1_B_MARK,
2715 };
2716 static const unsigned int msiof1_ss2_b_pins[] = {
2717         /* SS2 */
2718         RCAR_GP_PIN(7, 16),
2719 };
2720 static const unsigned int msiof1_ss2_b_mux[] = {
2721         MSIOF1_SS2_B_MARK,
2722 };
2723 static const unsigned int msiof1_rx_b_pins[] = {
2724         /* RXD */
2725         RCAR_GP_PIN(7, 18),
2726 };
2727 static const unsigned int msiof1_rx_b_mux[] = {
2728         MSIOF1_RXD_B_MARK,
2729 };
2730 static const unsigned int msiof1_tx_b_pins[] = {
2731         /* TXD */
2732         RCAR_GP_PIN(7, 17),
2733 };
2734 static const unsigned int msiof1_tx_b_mux[] = {
2735         MSIOF1_TXD_B_MARK,
2736 };
2737
2738 static const unsigned int msiof1_clk_c_pins[] = {
2739         /* SCK */
2740         RCAR_GP_PIN(2, 15),
2741 };
2742 static const unsigned int msiof1_clk_c_mux[] = {
2743         MSIOF1_SCK_C_MARK,
2744 };
2745 static const unsigned int msiof1_sync_c_pins[] = {
2746         /* SYNC */
2747         RCAR_GP_PIN(2, 16),
2748 };
2749 static const unsigned int msiof1_sync_c_mux[] = {
2750         MSIOF1_SYNC_C_MARK,
2751 };
2752 static const unsigned int msiof1_rx_c_pins[] = {
2753         /* RXD */
2754         RCAR_GP_PIN(2, 18),
2755 };
2756 static const unsigned int msiof1_rx_c_mux[] = {
2757         MSIOF1_RXD_C_MARK,
2758 };
2759 static const unsigned int msiof1_tx_c_pins[] = {
2760         /* TXD */
2761         RCAR_GP_PIN(2, 17),
2762 };
2763 static const unsigned int msiof1_tx_c_mux[] = {
2764         MSIOF1_TXD_C_MARK,
2765 };
2766
2767 static const unsigned int msiof1_clk_d_pins[] = {
2768         /* SCK */
2769         RCAR_GP_PIN(0, 28),
2770 };
2771 static const unsigned int msiof1_clk_d_mux[] = {
2772         MSIOF1_SCK_D_MARK,
2773 };
2774 static const unsigned int msiof1_sync_d_pins[] = {
2775         /* SYNC */
2776         RCAR_GP_PIN(0, 30),
2777 };
2778 static const unsigned int msiof1_sync_d_mux[] = {
2779         MSIOF1_SYNC_D_MARK,
2780 };
2781 static const unsigned int msiof1_ss1_d_pins[] = {
2782         /* SS1 */
2783         RCAR_GP_PIN(0, 29),
2784 };
2785 static const unsigned int msiof1_ss1_d_mux[] = {
2786         MSIOF1_SS1_D_MARK,
2787 };
2788 static const unsigned int msiof1_rx_d_pins[] = {
2789         /* RXD */
2790         RCAR_GP_PIN(0, 27),
2791 };
2792 static const unsigned int msiof1_rx_d_mux[] = {
2793         MSIOF1_RXD_D_MARK,
2794 };
2795 static const unsigned int msiof1_tx_d_pins[] = {
2796         /* TXD */
2797         RCAR_GP_PIN(0, 26),
2798 };
2799 static const unsigned int msiof1_tx_d_mux[] = {
2800         MSIOF1_TXD_D_MARK,
2801 };
2802
2803 static const unsigned int msiof1_clk_e_pins[] = {
2804         /* SCK */
2805         RCAR_GP_PIN(5, 18),
2806 };
2807 static const unsigned int msiof1_clk_e_mux[] = {
2808         MSIOF1_SCK_E_MARK,
2809 };
2810 static const unsigned int msiof1_sync_e_pins[] = {
2811         /* SYNC */
2812         RCAR_GP_PIN(5, 19),
2813 };
2814 static const unsigned int msiof1_sync_e_mux[] = {
2815         MSIOF1_SYNC_E_MARK,
2816 };
2817 static const unsigned int msiof1_rx_e_pins[] = {
2818         /* RXD */
2819         RCAR_GP_PIN(5, 17),
2820 };
2821 static const unsigned int msiof1_rx_e_mux[] = {
2822         MSIOF1_RXD_E_MARK,
2823 };
2824 static const unsigned int msiof1_tx_e_pins[] = {
2825         /* TXD */
2826         RCAR_GP_PIN(5, 20),
2827 };
2828 static const unsigned int msiof1_tx_e_mux[] = {
2829         MSIOF1_TXD_E_MARK,
2830 };
2831 /* - MSIOF2 ----------------------------------------------------------------- */
2832 static const unsigned int msiof2_clk_pins[] = {
2833         /* SCK */
2834         RCAR_GP_PIN(1, 13),
2835 };
2836 static const unsigned int msiof2_clk_mux[] = {
2837         MSIOF2_SCK_MARK,
2838 };
2839 static const unsigned int msiof2_sync_pins[] = {
2840         /* SYNC */
2841         RCAR_GP_PIN(1, 14),
2842 };
2843 static const unsigned int msiof2_sync_mux[] = {
2844         MSIOF2_SYNC_MARK,
2845 };
2846 static const unsigned int msiof2_ss1_pins[] = {
2847         /* SS1 */
2848         RCAR_GP_PIN(1, 17),
2849 };
2850 static const unsigned int msiof2_ss1_mux[] = {
2851         MSIOF2_SS1_MARK,
2852 };
2853 static const unsigned int msiof2_ss2_pins[] = {
2854         /* SS2 */
2855         RCAR_GP_PIN(1, 18),
2856 };
2857 static const unsigned int msiof2_ss2_mux[] = {
2858         MSIOF2_SS2_MARK,
2859 };
2860 static const unsigned int msiof2_rx_pins[] = {
2861         /* RXD */
2862         RCAR_GP_PIN(1, 16),
2863 };
2864 static const unsigned int msiof2_rx_mux[] = {
2865         MSIOF2_RXD_MARK,
2866 };
2867 static const unsigned int msiof2_tx_pins[] = {
2868         /* TXD */
2869         RCAR_GP_PIN(1, 15),
2870 };
2871 static const unsigned int msiof2_tx_mux[] = {
2872         MSIOF2_TXD_MARK,
2873 };
2874
2875 static const unsigned int msiof2_clk_b_pins[] = {
2876         /* SCK */
2877         RCAR_GP_PIN(3, 0),
2878 };
2879 static const unsigned int msiof2_clk_b_mux[] = {
2880         MSIOF2_SCK_B_MARK,
2881 };
2882 static const unsigned int msiof2_sync_b_pins[] = {
2883         /* SYNC */
2884         RCAR_GP_PIN(3, 1),
2885 };
2886 static const unsigned int msiof2_sync_b_mux[] = {
2887         MSIOF2_SYNC_B_MARK,
2888 };
2889 static const unsigned int msiof2_ss1_b_pins[] = {
2890         /* SS1 */
2891         RCAR_GP_PIN(3, 8),
2892 };
2893 static const unsigned int msiof2_ss1_b_mux[] = {
2894         MSIOF2_SS1_B_MARK,
2895 };
2896 static const unsigned int msiof2_ss2_b_pins[] = {
2897         /* SS2 */
2898         RCAR_GP_PIN(3, 9),
2899 };
2900 static const unsigned int msiof2_ss2_b_mux[] = {
2901         MSIOF2_SS2_B_MARK,
2902 };
2903 static const unsigned int msiof2_rx_b_pins[] = {
2904         /* RXD */
2905         RCAR_GP_PIN(3, 17),
2906 };
2907 static const unsigned int msiof2_rx_b_mux[] = {
2908         MSIOF2_RXD_B_MARK,
2909 };
2910 static const unsigned int msiof2_tx_b_pins[] = {
2911         /* TXD */
2912         RCAR_GP_PIN(3, 16),
2913 };
2914 static const unsigned int msiof2_tx_b_mux[] = {
2915         MSIOF2_TXD_B_MARK,
2916 };
2917
2918 static const unsigned int msiof2_clk_c_pins[] = {
2919         /* SCK */
2920         RCAR_GP_PIN(2, 2),
2921 };
2922 static const unsigned int msiof2_clk_c_mux[] = {
2923         MSIOF2_SCK_C_MARK,
2924 };
2925 static const unsigned int msiof2_sync_c_pins[] = {
2926         /* SYNC */
2927         RCAR_GP_PIN(2, 3),
2928 };
2929 static const unsigned int msiof2_sync_c_mux[] = {
2930         MSIOF2_SYNC_C_MARK,
2931 };
2932 static const unsigned int msiof2_rx_c_pins[] = {
2933         /* RXD */
2934         RCAR_GP_PIN(2, 5),
2935 };
2936 static const unsigned int msiof2_rx_c_mux[] = {
2937         MSIOF2_RXD_C_MARK,
2938 };
2939 static const unsigned int msiof2_tx_c_pins[] = {
2940         /* TXD */
2941         RCAR_GP_PIN(2, 4),
2942 };
2943 static const unsigned int msiof2_tx_c_mux[] = {
2944         MSIOF2_TXD_C_MARK,
2945 };
2946
2947 static const unsigned int msiof2_clk_d_pins[] = {
2948         /* SCK */
2949         RCAR_GP_PIN(2, 14),
2950 };
2951 static const unsigned int msiof2_clk_d_mux[] = {
2952         MSIOF2_SCK_D_MARK,
2953 };
2954 static const unsigned int msiof2_sync_d_pins[] = {
2955         /* SYNC */
2956         RCAR_GP_PIN(2, 15),
2957 };
2958 static const unsigned int msiof2_sync_d_mux[] = {
2959         MSIOF2_SYNC_D_MARK,
2960 };
2961 static const unsigned int msiof2_ss1_d_pins[] = {
2962         /* SS1 */
2963         RCAR_GP_PIN(2, 17),
2964 };
2965 static const unsigned int msiof2_ss1_d_mux[] = {
2966         MSIOF2_SS1_D_MARK,
2967 };
2968 static const unsigned int msiof2_ss2_d_pins[] = {
2969         /* SS2 */
2970         RCAR_GP_PIN(2, 19),
2971 };
2972 static const unsigned int msiof2_ss2_d_mux[] = {
2973         MSIOF2_SS2_D_MARK,
2974 };
2975 static const unsigned int msiof2_rx_d_pins[] = {
2976         /* RXD */
2977         RCAR_GP_PIN(2, 18),
2978 };
2979 static const unsigned int msiof2_rx_d_mux[] = {
2980         MSIOF2_RXD_D_MARK,
2981 };
2982 static const unsigned int msiof2_tx_d_pins[] = {
2983         /* TXD */
2984         RCAR_GP_PIN(2, 16),
2985 };
2986 static const unsigned int msiof2_tx_d_mux[] = {
2987         MSIOF2_TXD_D_MARK,
2988 };
2989
2990 static const unsigned int msiof2_clk_e_pins[] = {
2991         /* SCK */
2992         RCAR_GP_PIN(7, 15),
2993 };
2994 static const unsigned int msiof2_clk_e_mux[] = {
2995         MSIOF2_SCK_E_MARK,
2996 };
2997 static const unsigned int msiof2_sync_e_pins[] = {
2998         /* SYNC */
2999         RCAR_GP_PIN(7, 16),
3000 };
3001 static const unsigned int msiof2_sync_e_mux[] = {
3002         MSIOF2_SYNC_E_MARK,
3003 };
3004 static const unsigned int msiof2_rx_e_pins[] = {
3005         /* RXD */
3006         RCAR_GP_PIN(7, 14),
3007 };
3008 static const unsigned int msiof2_rx_e_mux[] = {
3009         MSIOF2_RXD_E_MARK,
3010 };
3011 static const unsigned int msiof2_tx_e_pins[] = {
3012         /* TXD */
3013         RCAR_GP_PIN(7, 13),
3014 };
3015 static const unsigned int msiof2_tx_e_mux[] = {
3016         MSIOF2_TXD_E_MARK,
3017 };
3018 /* - PWM -------------------------------------------------------------------- */
3019 static const unsigned int pwm0_pins[] = {
3020         RCAR_GP_PIN(6, 14),
3021 };
3022 static const unsigned int pwm0_mux[] = {
3023         PWM0_MARK,
3024 };
3025 static const unsigned int pwm0_b_pins[] = {
3026         RCAR_GP_PIN(5, 30),
3027 };
3028 static const unsigned int pwm0_b_mux[] = {
3029         PWM0_B_MARK,
3030 };
3031 static const unsigned int pwm1_pins[] = {
3032         RCAR_GP_PIN(1, 17),
3033 };
3034 static const unsigned int pwm1_mux[] = {
3035         PWM1_MARK,
3036 };
3037 static const unsigned int pwm1_b_pins[] = {
3038         RCAR_GP_PIN(6, 15),
3039 };
3040 static const unsigned int pwm1_b_mux[] = {
3041         PWM1_B_MARK,
3042 };
3043 static const unsigned int pwm2_pins[] = {
3044         RCAR_GP_PIN(1, 18),
3045 };
3046 static const unsigned int pwm2_mux[] = {
3047         PWM2_MARK,
3048 };
3049 static const unsigned int pwm2_b_pins[] = {
3050         RCAR_GP_PIN(0, 16),
3051 };
3052 static const unsigned int pwm2_b_mux[] = {
3053         PWM2_B_MARK,
3054 };
3055 static const unsigned int pwm3_pins[] = {
3056         RCAR_GP_PIN(1, 24),
3057 };
3058 static const unsigned int pwm3_mux[] = {
3059         PWM3_MARK,
3060 };
3061 static const unsigned int pwm4_pins[] = {
3062         RCAR_GP_PIN(3, 26),
3063 };
3064 static const unsigned int pwm4_mux[] = {
3065         PWM4_MARK,
3066 };
3067 static const unsigned int pwm4_b_pins[] = {
3068         RCAR_GP_PIN(3, 31),
3069 };
3070 static const unsigned int pwm4_b_mux[] = {
3071         PWM4_B_MARK,
3072 };
3073 static const unsigned int pwm5_pins[] = {
3074         RCAR_GP_PIN(7, 21),
3075 };
3076 static const unsigned int pwm5_mux[] = {
3077         PWM5_MARK,
3078 };
3079 static const unsigned int pwm5_b_pins[] = {
3080         RCAR_GP_PIN(7, 20),
3081 };
3082 static const unsigned int pwm5_b_mux[] = {
3083         PWM5_B_MARK,
3084 };
3085 static const unsigned int pwm6_pins[] = {
3086         RCAR_GP_PIN(7, 22),
3087 };
3088 static const unsigned int pwm6_mux[] = {
3089         PWM6_MARK,
3090 };
3091 /* - QSPI ------------------------------------------------------------------- */
3092 static const unsigned int qspi_ctrl_pins[] = {
3093         /* SPCLK, SSL */
3094         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3095 };
3096 static const unsigned int qspi_ctrl_mux[] = {
3097         SPCLK_MARK, SSL_MARK,
3098 };
3099 static const unsigned int qspi_data2_pins[] = {
3100         /* MOSI_IO0, MISO_IO1 */
3101         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3102 };
3103 static const unsigned int qspi_data2_mux[] = {
3104         MOSI_IO0_MARK, MISO_IO1_MARK,
3105 };
3106 static const unsigned int qspi_data4_pins[] = {
3107         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3108         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3109         RCAR_GP_PIN(1, 8),
3110 };
3111 static const unsigned int qspi_data4_mux[] = {
3112         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3113 };
3114
3115 static const unsigned int qspi_ctrl_b_pins[] = {
3116         /* SPCLK, SSL */
3117         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3118 };
3119 static const unsigned int qspi_ctrl_b_mux[] = {
3120         SPCLK_B_MARK, SSL_B_MARK,
3121 };
3122 static const unsigned int qspi_data2_b_pins[] = {
3123         /* MOSI_IO0, MISO_IO1 */
3124         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3125 };
3126 static const unsigned int qspi_data2_b_mux[] = {
3127         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3128 };
3129 static const unsigned int qspi_data4_b_pins[] = {
3130         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3131         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3132         RCAR_GP_PIN(6, 4),
3133 };
3134 static const unsigned int qspi_data4_b_mux[] = {
3135         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3136         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3137 };
3138 /* - SCIF0 ------------------------------------------------------------------ */
3139 static const unsigned int scif0_data_pins[] = {
3140         /* RX, TX */
3141         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3142 };
3143 static const unsigned int scif0_data_mux[] = {
3144         RX0_MARK, TX0_MARK,
3145 };
3146 static const unsigned int scif0_data_b_pins[] = {
3147         /* RX, TX */
3148         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3149 };
3150 static const unsigned int scif0_data_b_mux[] = {
3151         RX0_B_MARK, TX0_B_MARK,
3152 };
3153 static const unsigned int scif0_data_c_pins[] = {
3154         /* RX, TX */
3155         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3156 };
3157 static const unsigned int scif0_data_c_mux[] = {
3158         RX0_C_MARK, TX0_C_MARK,
3159 };
3160 static const unsigned int scif0_data_d_pins[] = {
3161         /* RX, TX */
3162         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3163 };
3164 static const unsigned int scif0_data_d_mux[] = {
3165         RX0_D_MARK, TX0_D_MARK,
3166 };
3167 static const unsigned int scif0_data_e_pins[] = {
3168         /* RX, TX */
3169         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3170 };
3171 static const unsigned int scif0_data_e_mux[] = {
3172         RX0_E_MARK, TX0_E_MARK,
3173 };
3174 /* - SCIF1 ------------------------------------------------------------------ */
3175 static const unsigned int scif1_data_pins[] = {
3176         /* RX, TX */
3177         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3178 };
3179 static const unsigned int scif1_data_mux[] = {
3180         RX1_MARK, TX1_MARK,
3181 };
3182 static const unsigned int scif1_data_b_pins[] = {
3183         /* RX, TX */
3184         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3185 };
3186 static const unsigned int scif1_data_b_mux[] = {
3187         RX1_B_MARK, TX1_B_MARK,
3188 };
3189 static const unsigned int scif1_clk_b_pins[] = {
3190         /* SCK */
3191         RCAR_GP_PIN(3, 10),
3192 };
3193 static const unsigned int scif1_clk_b_mux[] = {
3194         SCIF1_SCK_B_MARK,
3195 };
3196 static const unsigned int scif1_data_c_pins[] = {
3197         /* RX, TX */
3198         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3199 };
3200 static const unsigned int scif1_data_c_mux[] = {
3201         RX1_C_MARK, TX1_C_MARK,
3202 };
3203 static const unsigned int scif1_data_d_pins[] = {
3204         /* RX, TX */
3205         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3206 };
3207 static const unsigned int scif1_data_d_mux[] = {
3208         RX1_D_MARK, TX1_D_MARK,
3209 };
3210 /* - SCIF2 ------------------------------------------------------------------ */
3211 static const unsigned int scif2_data_pins[] = {
3212         /* RX, TX */
3213         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3214 };
3215 static const unsigned int scif2_data_mux[] = {
3216         RX2_MARK, TX2_MARK,
3217 };
3218 static const unsigned int scif2_data_b_pins[] = {
3219         /* RX, TX */
3220         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3221 };
3222 static const unsigned int scif2_data_b_mux[] = {
3223         RX2_B_MARK, TX2_B_MARK,
3224 };
3225 static const unsigned int scif2_clk_b_pins[] = {
3226         /* SCK */
3227         RCAR_GP_PIN(3, 18),
3228 };
3229 static const unsigned int scif2_clk_b_mux[] = {
3230         SCIF2_SCK_B_MARK,
3231 };
3232 static const unsigned int scif2_data_c_pins[] = {
3233         /* RX, TX */
3234         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3235 };
3236 static const unsigned int scif2_data_c_mux[] = {
3237         RX2_C_MARK, TX2_C_MARK,
3238 };
3239 static const unsigned int scif2_data_e_pins[] = {
3240         /* RX, TX */
3241         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3242 };
3243 static const unsigned int scif2_data_e_mux[] = {
3244         RX2_E_MARK, TX2_E_MARK,
3245 };
3246 /* - SCIF3 ------------------------------------------------------------------ */
3247 static const unsigned int scif3_data_pins[] = {
3248         /* RX, TX */
3249         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3250 };
3251 static const unsigned int scif3_data_mux[] = {
3252         RX3_MARK, TX3_MARK,
3253 };
3254 static const unsigned int scif3_clk_pins[] = {
3255         /* SCK */
3256         RCAR_GP_PIN(3, 23),
3257 };
3258 static const unsigned int scif3_clk_mux[] = {
3259         SCIF3_SCK_MARK,
3260 };
3261 static const unsigned int scif3_data_b_pins[] = {
3262         /* RX, TX */
3263         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3264 };
3265 static const unsigned int scif3_data_b_mux[] = {
3266         RX3_B_MARK, TX3_B_MARK,
3267 };
3268 static const unsigned int scif3_clk_b_pins[] = {
3269         /* SCK */
3270         RCAR_GP_PIN(4, 8),
3271 };
3272 static const unsigned int scif3_clk_b_mux[] = {
3273         SCIF3_SCK_B_MARK,
3274 };
3275 static const unsigned int scif3_data_c_pins[] = {
3276         /* RX, TX */
3277         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3278 };
3279 static const unsigned int scif3_data_c_mux[] = {
3280         RX3_C_MARK, TX3_C_MARK,
3281 };
3282 static const unsigned int scif3_data_d_pins[] = {
3283         /* RX, TX */
3284         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3285 };
3286 static const unsigned int scif3_data_d_mux[] = {
3287         RX3_D_MARK, TX3_D_MARK,
3288 };
3289 /* - SCIF4 ------------------------------------------------------------------ */
3290 static const unsigned int scif4_data_pins[] = {
3291         /* RX, TX */
3292         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3293 };
3294 static const unsigned int scif4_data_mux[] = {
3295         RX4_MARK, TX4_MARK,
3296 };
3297 static const unsigned int scif4_data_b_pins[] = {
3298         /* RX, TX */
3299         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3300 };
3301 static const unsigned int scif4_data_b_mux[] = {
3302         RX4_B_MARK, TX4_B_MARK,
3303 };
3304 static const unsigned int scif4_data_c_pins[] = {
3305         /* RX, TX */
3306         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3307 };
3308 static const unsigned int scif4_data_c_mux[] = {
3309         RX4_C_MARK, TX4_C_MARK,
3310 };
3311 /* - SCIF5 ------------------------------------------------------------------ */
3312 static const unsigned int scif5_data_pins[] = {
3313         /* RX, TX */
3314         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3315 };
3316 static const unsigned int scif5_data_mux[] = {
3317         RX5_MARK, TX5_MARK,
3318 };
3319 static const unsigned int scif5_data_b_pins[] = {
3320         /* RX, TX */
3321         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3322 };
3323 static const unsigned int scif5_data_b_mux[] = {
3324         RX5_B_MARK, TX5_B_MARK,
3325 };
3326 /* - SCIFA0 ----------------------------------------------------------------- */
3327 static const unsigned int scifa0_data_pins[] = {
3328         /* RXD, TXD */
3329         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3330 };
3331 static const unsigned int scifa0_data_mux[] = {
3332         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3333 };
3334 static const unsigned int scifa0_data_b_pins[] = {
3335         /* RXD, TXD */
3336         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3337 };
3338 static const unsigned int scifa0_data_b_mux[] = {
3339         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3340 };
3341 /* - SCIFA1 ----------------------------------------------------------------- */
3342 static const unsigned int scifa1_data_pins[] = {
3343         /* RXD, TXD */
3344         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3345 };
3346 static const unsigned int scifa1_data_mux[] = {
3347         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3348 };
3349 static const unsigned int scifa1_clk_pins[] = {
3350         /* SCK */
3351         RCAR_GP_PIN(3, 10),
3352 };
3353 static const unsigned int scifa1_clk_mux[] = {
3354         SCIFA1_SCK_MARK,
3355 };
3356 static const unsigned int scifa1_data_b_pins[] = {
3357         /* RXD, TXD */
3358         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3359 };
3360 static const unsigned int scifa1_data_b_mux[] = {
3361         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3362 };
3363 static const unsigned int scifa1_clk_b_pins[] = {
3364         /* SCK */
3365         RCAR_GP_PIN(1, 0),
3366 };
3367 static const unsigned int scifa1_clk_b_mux[] = {
3368         SCIFA1_SCK_B_MARK,
3369 };
3370 static const unsigned int scifa1_data_c_pins[] = {
3371         /* RXD, TXD */
3372         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3373 };
3374 static const unsigned int scifa1_data_c_mux[] = {
3375         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3376 };
3377 /* - SCIFA2 ----------------------------------------------------------------- */
3378 static const unsigned int scifa2_data_pins[] = {
3379         /* RXD, TXD */
3380         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3381 };
3382 static const unsigned int scifa2_data_mux[] = {
3383         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3384 };
3385 static const unsigned int scifa2_clk_pins[] = {
3386         /* SCK */
3387         RCAR_GP_PIN(3, 18),
3388 };
3389 static const unsigned int scifa2_clk_mux[] = {
3390         SCIFA2_SCK_MARK,
3391 };
3392 static const unsigned int scifa2_data_b_pins[] = {
3393         /* RXD, TXD */
3394         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3395 };
3396 static const unsigned int scifa2_data_b_mux[] = {
3397         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3398 };
3399 /* - SCIFA3 ----------------------------------------------------------------- */
3400 static const unsigned int scifa3_data_pins[] = {
3401         /* RXD, TXD */
3402         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3403 };
3404 static const unsigned int scifa3_data_mux[] = {
3405         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3406 };
3407 static const unsigned int scifa3_clk_pins[] = {
3408         /* SCK */
3409         RCAR_GP_PIN(3, 23),
3410 };
3411 static const unsigned int scifa3_clk_mux[] = {
3412         SCIFA3_SCK_MARK,
3413 };
3414 static const unsigned int scifa3_data_b_pins[] = {
3415         /* RXD, TXD */
3416         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3417 };
3418 static const unsigned int scifa3_data_b_mux[] = {
3419         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3420 };
3421 static const unsigned int scifa3_clk_b_pins[] = {
3422         /* SCK */
3423         RCAR_GP_PIN(4, 8),
3424 };
3425 static const unsigned int scifa3_clk_b_mux[] = {
3426         SCIFA3_SCK_B_MARK,
3427 };
3428 static const unsigned int scifa3_data_c_pins[] = {
3429         /* RXD, TXD */
3430         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3431 };
3432 static const unsigned int scifa3_data_c_mux[] = {
3433         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3434 };
3435 static const unsigned int scifa3_clk_c_pins[] = {
3436         /* SCK */
3437         RCAR_GP_PIN(7, 22),
3438 };
3439 static const unsigned int scifa3_clk_c_mux[] = {
3440         SCIFA3_SCK_C_MARK,
3441 };
3442 /* - SCIFA4 ----------------------------------------------------------------- */
3443 static const unsigned int scifa4_data_pins[] = {
3444         /* RXD, TXD */
3445         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3446 };
3447 static const unsigned int scifa4_data_mux[] = {
3448         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3449 };
3450 static const unsigned int scifa4_data_b_pins[] = {
3451         /* RXD, TXD */
3452         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3453 };
3454 static const unsigned int scifa4_data_b_mux[] = {
3455         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3456 };
3457 static const unsigned int scifa4_data_c_pins[] = {
3458         /* RXD, TXD */
3459         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3460 };
3461 static const unsigned int scifa4_data_c_mux[] = {
3462         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3463 };
3464 /* - SCIFA5 ----------------------------------------------------------------- */
3465 static const unsigned int scifa5_data_pins[] = {
3466         /* RXD, TXD */
3467         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3468 };
3469 static const unsigned int scifa5_data_mux[] = {
3470         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3471 };
3472 static const unsigned int scifa5_data_b_pins[] = {
3473         /* RXD, TXD */
3474         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3475 };
3476 static const unsigned int scifa5_data_b_mux[] = {
3477         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3478 };
3479 static const unsigned int scifa5_data_c_pins[] = {
3480         /* RXD, TXD */
3481         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3482 };
3483 static const unsigned int scifa5_data_c_mux[] = {
3484         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3485 };
3486 /* - SCIFB0 ----------------------------------------------------------------- */
3487 static const unsigned int scifb0_data_pins[] = {
3488         /* RXD, TXD */
3489         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3490 };
3491 static const unsigned int scifb0_data_mux[] = {
3492         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3493 };
3494 static const unsigned int scifb0_clk_pins[] = {
3495         /* SCK */
3496         RCAR_GP_PIN(7, 2),
3497 };
3498 static const unsigned int scifb0_clk_mux[] = {
3499         SCIFB0_SCK_MARK,
3500 };
3501 static const unsigned int scifb0_ctrl_pins[] = {
3502         /* RTS, CTS */
3503         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3504 };
3505 static const unsigned int scifb0_ctrl_mux[] = {
3506         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3507 };
3508 static const unsigned int scifb0_data_b_pins[] = {
3509         /* RXD, TXD */
3510         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3511 };
3512 static const unsigned int scifb0_data_b_mux[] = {
3513         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3514 };
3515 static const unsigned int scifb0_clk_b_pins[] = {
3516         /* SCK */
3517         RCAR_GP_PIN(5, 31),
3518 };
3519 static const unsigned int scifb0_clk_b_mux[] = {
3520         SCIFB0_SCK_B_MARK,
3521 };
3522 static const unsigned int scifb0_ctrl_b_pins[] = {
3523         /* RTS, CTS */
3524         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3525 };
3526 static const unsigned int scifb0_ctrl_b_mux[] = {
3527         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3528 };
3529 static const unsigned int scifb0_data_c_pins[] = {
3530         /* RXD, TXD */
3531         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3532 };
3533 static const unsigned int scifb0_data_c_mux[] = {
3534         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3535 };
3536 static const unsigned int scifb0_clk_c_pins[] = {
3537         /* SCK */
3538         RCAR_GP_PIN(2, 30),
3539 };
3540 static const unsigned int scifb0_clk_c_mux[] = {
3541         SCIFB0_SCK_C_MARK,
3542 };
3543 static const unsigned int scifb0_data_d_pins[] = {
3544         /* RXD, TXD */
3545         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3546 };
3547 static const unsigned int scifb0_data_d_mux[] = {
3548         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3549 };
3550 static const unsigned int scifb0_clk_d_pins[] = {
3551         /* SCK */
3552         RCAR_GP_PIN(4, 17),
3553 };
3554 static const unsigned int scifb0_clk_d_mux[] = {
3555         SCIFB0_SCK_D_MARK,
3556 };
3557 /* - SCIFB1 ----------------------------------------------------------------- */
3558 static const unsigned int scifb1_data_pins[] = {
3559         /* RXD, TXD */
3560         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3561 };
3562 static const unsigned int scifb1_data_mux[] = {
3563         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3564 };
3565 static const unsigned int scifb1_clk_pins[] = {
3566         /* SCK */
3567         RCAR_GP_PIN(7, 7),
3568 };
3569 static const unsigned int scifb1_clk_mux[] = {
3570         SCIFB1_SCK_MARK,
3571 };
3572 static const unsigned int scifb1_ctrl_pins[] = {
3573         /* RTS, CTS */
3574         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3575 };
3576 static const unsigned int scifb1_ctrl_mux[] = {
3577         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3578 };
3579 static const unsigned int scifb1_data_b_pins[] = {
3580         /* RXD, TXD */
3581         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3582 };
3583 static const unsigned int scifb1_data_b_mux[] = {
3584         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3585 };
3586 static const unsigned int scifb1_clk_b_pins[] = {
3587         /* SCK */
3588         RCAR_GP_PIN(1, 3),
3589 };
3590 static const unsigned int scifb1_clk_b_mux[] = {
3591         SCIFB1_SCK_B_MARK,
3592 };
3593 static const unsigned int scifb1_data_c_pins[] = {
3594         /* RXD, TXD */
3595         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3596 };
3597 static const unsigned int scifb1_data_c_mux[] = {
3598         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3599 };
3600 static const unsigned int scifb1_clk_c_pins[] = {
3601         /* SCK */
3602         RCAR_GP_PIN(7, 11),
3603 };
3604 static const unsigned int scifb1_clk_c_mux[] = {
3605         SCIFB1_SCK_C_MARK,
3606 };
3607 static const unsigned int scifb1_data_d_pins[] = {
3608         /* RXD, TXD */
3609         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3610 };
3611 static const unsigned int scifb1_data_d_mux[] = {
3612         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3613 };
3614 /* - SCIFB2 ----------------------------------------------------------------- */
3615 static const unsigned int scifb2_data_pins[] = {
3616         /* RXD, TXD */
3617         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3618 };
3619 static const unsigned int scifb2_data_mux[] = {
3620         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3621 };
3622 static const unsigned int scifb2_clk_pins[] = {
3623         /* SCK */
3624         RCAR_GP_PIN(4, 15),
3625 };
3626 static const unsigned int scifb2_clk_mux[] = {
3627         SCIFB2_SCK_MARK,
3628 };
3629 static const unsigned int scifb2_ctrl_pins[] = {
3630         /* RTS, CTS */
3631         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3632 };
3633 static const unsigned int scifb2_ctrl_mux[] = {
3634         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3635 };
3636 static const unsigned int scifb2_data_b_pins[] = {
3637         /* RXD, TXD */
3638         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3639 };
3640 static const unsigned int scifb2_data_b_mux[] = {
3641         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3642 };
3643 static const unsigned int scifb2_clk_b_pins[] = {
3644         /* SCK */
3645         RCAR_GP_PIN(5, 31),
3646 };
3647 static const unsigned int scifb2_clk_b_mux[] = {
3648         SCIFB2_SCK_B_MARK,
3649 };
3650 static const unsigned int scifb2_ctrl_b_pins[] = {
3651         /* RTS, CTS */
3652         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3653 };
3654 static const unsigned int scifb2_ctrl_b_mux[] = {
3655         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3656 };
3657 static const unsigned int scifb2_data_c_pins[] = {
3658         /* RXD, TXD */
3659         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3660 };
3661 static const unsigned int scifb2_data_c_mux[] = {
3662         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3663 };
3664 static const unsigned int scifb2_clk_c_pins[] = {
3665         /* SCK */
3666         RCAR_GP_PIN(5, 27),
3667 };
3668 static const unsigned int scifb2_clk_c_mux[] = {
3669         SCIFB2_SCK_C_MARK,
3670 };
3671 static const unsigned int scifb2_data_d_pins[] = {
3672         /* RXD, TXD */
3673         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3674 };
3675 static const unsigned int scifb2_data_d_mux[] = {
3676         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3677 };
3678
3679 /* - SCIF Clock ------------------------------------------------------------- */
3680 static const unsigned int scif_clk_pins[] = {
3681         /* SCIF_CLK */
3682         RCAR_GP_PIN(2, 29),
3683 };
3684 static const unsigned int scif_clk_mux[] = {
3685         SCIF_CLK_MARK,
3686 };
3687 static const unsigned int scif_clk_b_pins[] = {
3688         /* SCIF_CLK */
3689         RCAR_GP_PIN(7, 19),
3690 };
3691 static const unsigned int scif_clk_b_mux[] = {
3692         SCIF_CLK_B_MARK,
3693 };
3694
3695 /* - SDHI0 ------------------------------------------------------------------ */
3696 static const unsigned int sdhi0_data1_pins[] = {
3697         /* D0 */
3698         RCAR_GP_PIN(6, 2),
3699 };
3700 static const unsigned int sdhi0_data1_mux[] = {
3701         SD0_DATA0_MARK,
3702 };
3703 static const unsigned int sdhi0_data4_pins[] = {
3704         /* D[0:3] */
3705         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3706         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3707 };
3708 static const unsigned int sdhi0_data4_mux[] = {
3709         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3710 };
3711 static const unsigned int sdhi0_ctrl_pins[] = {
3712         /* CLK, CMD */
3713         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3714 };
3715 static const unsigned int sdhi0_ctrl_mux[] = {
3716         SD0_CLK_MARK, SD0_CMD_MARK,
3717 };
3718 static const unsigned int sdhi0_cd_pins[] = {
3719         /* CD */
3720         RCAR_GP_PIN(6, 6),
3721 };
3722 static const unsigned int sdhi0_cd_mux[] = {
3723         SD0_CD_MARK,
3724 };
3725 static const unsigned int sdhi0_wp_pins[] = {
3726         /* WP */
3727         RCAR_GP_PIN(6, 7),
3728 };
3729 static const unsigned int sdhi0_wp_mux[] = {
3730         SD0_WP_MARK,
3731 };
3732 /* - SDHI1 ------------------------------------------------------------------ */
3733 static const unsigned int sdhi1_data1_pins[] = {
3734         /* D0 */
3735         RCAR_GP_PIN(6, 10),
3736 };
3737 static const unsigned int sdhi1_data1_mux[] = {
3738         SD1_DATA0_MARK,
3739 };
3740 static const unsigned int sdhi1_data4_pins[] = {
3741         /* D[0:3] */
3742         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3743         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3744 };
3745 static const unsigned int sdhi1_data4_mux[] = {
3746         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3747 };
3748 static const unsigned int sdhi1_ctrl_pins[] = {
3749         /* CLK, CMD */
3750         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3751 };
3752 static const unsigned int sdhi1_ctrl_mux[] = {
3753         SD1_CLK_MARK, SD1_CMD_MARK,
3754 };
3755 static const unsigned int sdhi1_cd_pins[] = {
3756         /* CD */
3757         RCAR_GP_PIN(6, 14),
3758 };
3759 static const unsigned int sdhi1_cd_mux[] = {
3760         SD1_CD_MARK,
3761 };
3762 static const unsigned int sdhi1_wp_pins[] = {
3763         /* WP */
3764         RCAR_GP_PIN(6, 15),
3765 };
3766 static const unsigned int sdhi1_wp_mux[] = {
3767         SD1_WP_MARK,
3768 };
3769 /* - SDHI2 ------------------------------------------------------------------ */
3770 static const unsigned int sdhi2_data1_pins[] = {
3771         /* D0 */
3772         RCAR_GP_PIN(6, 18),
3773 };
3774 static const unsigned int sdhi2_data1_mux[] = {
3775         SD2_DATA0_MARK,
3776 };
3777 static const unsigned int sdhi2_data4_pins[] = {
3778         /* D[0:3] */
3779         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3780         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3781 };
3782 static const unsigned int sdhi2_data4_mux[] = {
3783         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3784 };
3785 static const unsigned int sdhi2_ctrl_pins[] = {
3786         /* CLK, CMD */
3787         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3788 };
3789 static const unsigned int sdhi2_ctrl_mux[] = {
3790         SD2_CLK_MARK, SD2_CMD_MARK,
3791 };
3792 static const unsigned int sdhi2_cd_pins[] = {
3793         /* CD */
3794         RCAR_GP_PIN(6, 22),
3795 };
3796 static const unsigned int sdhi2_cd_mux[] = {
3797         SD2_CD_MARK,
3798 };
3799 static const unsigned int sdhi2_wp_pins[] = {
3800         /* WP */
3801         RCAR_GP_PIN(6, 23),
3802 };
3803 static const unsigned int sdhi2_wp_mux[] = {
3804         SD2_WP_MARK,
3805 };
3806
3807 /* - SSI -------------------------------------------------------------------- */
3808 static const unsigned int ssi0_data_pins[] = {
3809         /* SDATA */
3810         RCAR_GP_PIN(2, 2),
3811 };
3812
3813 static const unsigned int ssi0_data_mux[] = {
3814         SSI_SDATA0_MARK,
3815 };
3816
3817 static const unsigned int ssi0_data_b_pins[] = {
3818         /* SDATA */
3819         RCAR_GP_PIN(3, 4),
3820 };
3821
3822 static const unsigned int ssi0_data_b_mux[] = {
3823         SSI_SDATA0_B_MARK,
3824 };
3825
3826 static const unsigned int ssi0129_ctrl_pins[] = {
3827         /* SCK, WS */
3828         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3829 };
3830
3831 static const unsigned int ssi0129_ctrl_mux[] = {
3832         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3833 };
3834
3835 static const unsigned int ssi0129_ctrl_b_pins[] = {
3836         /* SCK, WS */
3837         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3838 };
3839
3840 static const unsigned int ssi0129_ctrl_b_mux[] = {
3841         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3842 };
3843
3844 static const unsigned int ssi1_data_pins[] = {
3845         /* SDATA */
3846         RCAR_GP_PIN(2, 5),
3847 };
3848
3849 static const unsigned int ssi1_data_mux[] = {
3850         SSI_SDATA1_MARK,
3851 };
3852
3853 static const unsigned int ssi1_data_b_pins[] = {
3854         /* SDATA */
3855         RCAR_GP_PIN(3, 7),
3856 };
3857
3858 static const unsigned int ssi1_data_b_mux[] = {
3859         SSI_SDATA1_B_MARK,
3860 };
3861
3862 static const unsigned int ssi1_ctrl_pins[] = {
3863         /* SCK, WS */
3864         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3865 };
3866
3867 static const unsigned int ssi1_ctrl_mux[] = {
3868         SSI_SCK1_MARK, SSI_WS1_MARK,
3869 };
3870
3871 static const unsigned int ssi1_ctrl_b_pins[] = {
3872         /* SCK, WS */
3873         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3874 };
3875
3876 static const unsigned int ssi1_ctrl_b_mux[] = {
3877         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3878 };
3879
3880 static const unsigned int ssi2_data_pins[] = {
3881         /* SDATA */
3882         RCAR_GP_PIN(2, 8),
3883 };
3884
3885 static const unsigned int ssi2_data_mux[] = {
3886         SSI_SDATA2_MARK,
3887 };
3888
3889 static const unsigned int ssi2_ctrl_pins[] = {
3890         /* SCK, WS */
3891         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3892 };
3893
3894 static const unsigned int ssi2_ctrl_mux[] = {
3895         SSI_SCK2_MARK, SSI_WS2_MARK,
3896 };
3897
3898 static const unsigned int ssi3_data_pins[] = {
3899         /* SDATA */
3900         RCAR_GP_PIN(2, 11),
3901 };
3902
3903 static const unsigned int ssi3_data_mux[] = {
3904         SSI_SDATA3_MARK,
3905 };
3906
3907 static const unsigned int ssi34_ctrl_pins[] = {
3908         /* SCK, WS */
3909         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3910 };
3911
3912 static const unsigned int ssi34_ctrl_mux[] = {
3913         SSI_SCK34_MARK, SSI_WS34_MARK,
3914 };
3915
3916 static const unsigned int ssi4_data_pins[] = {
3917         /* SDATA */
3918         RCAR_GP_PIN(2, 14),
3919 };
3920
3921 static const unsigned int ssi4_data_mux[] = {
3922         SSI_SDATA4_MARK,
3923 };
3924
3925 static const unsigned int ssi4_ctrl_pins[] = {
3926         /* SCK, WS */
3927         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3928 };
3929
3930 static const unsigned int ssi4_ctrl_mux[] = {
3931         SSI_SCK4_MARK, SSI_WS4_MARK,
3932 };
3933
3934 static const unsigned int ssi5_data_pins[] = {
3935         /* SDATA */
3936         RCAR_GP_PIN(2, 17),
3937 };
3938
3939 static const unsigned int ssi5_data_mux[] = {
3940         SSI_SDATA5_MARK,
3941 };
3942
3943 static const unsigned int ssi5_ctrl_pins[] = {
3944         /* SCK, WS */
3945         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3946 };
3947
3948 static const unsigned int ssi5_ctrl_mux[] = {
3949         SSI_SCK5_MARK, SSI_WS5_MARK,
3950 };
3951
3952 static const unsigned int ssi6_data_pins[] = {
3953         /* SDATA */
3954         RCAR_GP_PIN(2, 20),
3955 };
3956
3957 static const unsigned int ssi6_data_mux[] = {
3958         SSI_SDATA6_MARK,
3959 };
3960
3961 static const unsigned int ssi6_ctrl_pins[] = {
3962         /* SCK, WS */
3963         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
3964 };
3965
3966 static const unsigned int ssi6_ctrl_mux[] = {
3967         SSI_SCK6_MARK, SSI_WS6_MARK,
3968 };
3969
3970 static const unsigned int ssi7_data_pins[] = {
3971         /* SDATA */
3972         RCAR_GP_PIN(2, 23),
3973 };
3974
3975 static const unsigned int ssi7_data_mux[] = {
3976         SSI_SDATA7_MARK,
3977 };
3978
3979 static const unsigned int ssi7_data_b_pins[] = {
3980         /* SDATA */
3981         RCAR_GP_PIN(3, 12),
3982 };
3983
3984 static const unsigned int ssi7_data_b_mux[] = {
3985         SSI_SDATA7_B_MARK,
3986 };
3987
3988 static const unsigned int ssi78_ctrl_pins[] = {
3989         /* SCK, WS */
3990         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3991 };
3992
3993 static const unsigned int ssi78_ctrl_mux[] = {
3994         SSI_SCK78_MARK, SSI_WS78_MARK,
3995 };
3996
3997 static const unsigned int ssi78_ctrl_b_pins[] = {
3998         /* SCK, WS */
3999         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4000 };
4001
4002 static const unsigned int ssi78_ctrl_b_mux[] = {
4003         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4004 };
4005
4006 static const unsigned int ssi8_data_pins[] = {
4007         /* SDATA */
4008         RCAR_GP_PIN(2, 24),
4009 };
4010
4011 static const unsigned int ssi8_data_mux[] = {
4012         SSI_SDATA8_MARK,
4013 };
4014
4015 static const unsigned int ssi8_data_b_pins[] = {
4016         /* SDATA */
4017         RCAR_GP_PIN(3, 13),
4018 };
4019
4020 static const unsigned int ssi8_data_b_mux[] = {
4021         SSI_SDATA8_B_MARK,
4022 };
4023
4024 static const unsigned int ssi9_data_pins[] = {
4025         /* SDATA */
4026         RCAR_GP_PIN(2, 27),
4027 };
4028
4029 static const unsigned int ssi9_data_mux[] = {
4030         SSI_SDATA9_MARK,
4031 };
4032
4033 static const unsigned int ssi9_data_b_pins[] = {
4034         /* SDATA */
4035         RCAR_GP_PIN(3, 18),
4036 };
4037
4038 static const unsigned int ssi9_data_b_mux[] = {
4039         SSI_SDATA9_B_MARK,
4040 };
4041
4042 static const unsigned int ssi9_ctrl_pins[] = {
4043         /* SCK, WS */
4044         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4045 };
4046
4047 static const unsigned int ssi9_ctrl_mux[] = {
4048         SSI_SCK9_MARK, SSI_WS9_MARK,
4049 };
4050
4051 static const unsigned int ssi9_ctrl_b_pins[] = {
4052         /* SCK, WS */
4053         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4054 };
4055
4056 static const unsigned int ssi9_ctrl_b_mux[] = {
4057         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4058 };
4059
4060 /* - USB0 ------------------------------------------------------------------- */
4061 static const unsigned int usb0_pins[] = {
4062         RCAR_GP_PIN(7, 23), /* PWEN */
4063         RCAR_GP_PIN(7, 24), /* OVC */
4064 };
4065 static const unsigned int usb0_mux[] = {
4066         USB0_PWEN_MARK,
4067         USB0_OVC_MARK,
4068 };
4069 /* - USB1 ------------------------------------------------------------------- */
4070 static const unsigned int usb1_pins[] = {
4071         RCAR_GP_PIN(7, 25), /* PWEN */
4072         RCAR_GP_PIN(6, 30), /* OVC */
4073 };
4074 static const unsigned int usb1_mux[] = {
4075         USB1_PWEN_MARK,
4076         USB1_OVC_MARK,
4077 };
4078 /* - VIN0 ------------------------------------------------------------------- */
4079 static const union vin_data vin0_data_pins = {
4080         .data24 = {
4081                 /* B */
4082                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4083                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4084                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4085                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4086                 /* G */
4087                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4088                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4089                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4090                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4091                 /* R */
4092                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4093                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4094                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4095                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4096         },
4097 };
4098 static const union vin_data vin0_data_mux = {
4099         .data24 = {
4100                 /* B */
4101                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4102                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4103                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4104                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4105                 /* G */
4106                 VI0_G0_MARK, VI0_G1_MARK,
4107                 VI0_G2_MARK, VI0_G3_MARK,
4108                 VI0_G4_MARK, VI0_G5_MARK,
4109                 VI0_G6_MARK, VI0_G7_MARK,
4110                 /* R */
4111                 VI0_R0_MARK, VI0_R1_MARK,
4112                 VI0_R2_MARK, VI0_R3_MARK,
4113                 VI0_R4_MARK, VI0_R5_MARK,
4114                 VI0_R6_MARK, VI0_R7_MARK,
4115         },
4116 };
4117 static const unsigned int vin0_data18_pins[] = {
4118         /* B */
4119         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4120         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4121         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4122         /* G */
4123         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4124         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4125         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4126         /* R */
4127         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4128         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4129         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4130 };
4131 static const unsigned int vin0_data18_mux[] = {
4132         /* B */
4133         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4134         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4135         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4136         /* G */
4137         VI0_G2_MARK, VI0_G3_MARK,
4138         VI0_G4_MARK, VI0_G5_MARK,
4139         VI0_G6_MARK, VI0_G7_MARK,
4140         /* R */
4141         VI0_R2_MARK, VI0_R3_MARK,
4142         VI0_R4_MARK, VI0_R5_MARK,
4143         VI0_R6_MARK, VI0_R7_MARK,
4144 };
4145 static const unsigned int vin0_sync_pins[] = {
4146         RCAR_GP_PIN(4, 3), /* HSYNC */
4147         RCAR_GP_PIN(4, 4), /* VSYNC */
4148 };
4149 static const unsigned int vin0_sync_mux[] = {
4150         VI0_HSYNC_N_MARK,
4151         VI0_VSYNC_N_MARK,
4152 };
4153 static const unsigned int vin0_field_pins[] = {
4154         RCAR_GP_PIN(4, 2),
4155 };
4156 static const unsigned int vin0_field_mux[] = {
4157         VI0_FIELD_MARK,
4158 };
4159 static const unsigned int vin0_clkenb_pins[] = {
4160         RCAR_GP_PIN(4, 1),
4161 };
4162 static const unsigned int vin0_clkenb_mux[] = {
4163         VI0_CLKENB_MARK,
4164 };
4165 static const unsigned int vin0_clk_pins[] = {
4166         RCAR_GP_PIN(4, 0),
4167 };
4168 static const unsigned int vin0_clk_mux[] = {
4169         VI0_CLK_MARK,
4170 };
4171 /* - VIN1 ----------------------------------------------------------------- */
4172 static const unsigned int vin1_data8_pins[] = {
4173         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4174         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4175         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4176         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4177 };
4178 static const unsigned int vin1_data8_mux[] = {
4179         VI1_DATA0_MARK, VI1_DATA1_MARK,
4180         VI1_DATA2_MARK, VI1_DATA3_MARK,
4181         VI1_DATA4_MARK, VI1_DATA5_MARK,
4182         VI1_DATA6_MARK, VI1_DATA7_MARK,
4183 };
4184 static const unsigned int vin1_sync_pins[] = {
4185         RCAR_GP_PIN(5, 0), /* HSYNC */
4186         RCAR_GP_PIN(5, 1), /* VSYNC */
4187 };
4188 static const unsigned int vin1_sync_mux[] = {
4189         VI1_HSYNC_N_MARK,
4190         VI1_VSYNC_N_MARK,
4191 };
4192 static const unsigned int vin1_field_pins[] = {
4193         RCAR_GP_PIN(5, 3),
4194 };
4195 static const unsigned int vin1_field_mux[] = {
4196         VI1_FIELD_MARK,
4197 };
4198 static const unsigned int vin1_clkenb_pins[] = {
4199         RCAR_GP_PIN(5, 2),
4200 };
4201 static const unsigned int vin1_clkenb_mux[] = {
4202         VI1_CLKENB_MARK,
4203 };
4204 static const unsigned int vin1_clk_pins[] = {
4205         RCAR_GP_PIN(5, 4),
4206 };
4207 static const unsigned int vin1_clk_mux[] = {
4208         VI1_CLK_MARK,
4209 };
4210 static const union vin_data vin1_b_data_pins = {
4211         .data24 = {
4212                 /* B */
4213                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4214                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4215                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4216                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4217                 /* G */
4218                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4219                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4220                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4221                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4222                 /* R */
4223                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4224                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4225                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4226                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4227         },
4228 };
4229 static const union vin_data vin1_b_data_mux = {
4230         .data24 = {
4231                 /* B */
4232                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4233                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4234                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4235                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4236                 /* G */
4237                 VI1_G0_B_MARK, VI1_G1_B_MARK,
4238                 VI1_G2_B_MARK, VI1_G3_B_MARK,
4239                 VI1_G4_B_MARK, VI1_G5_B_MARK,
4240                 VI1_G6_B_MARK, VI1_G7_B_MARK,
4241                 /* R */
4242                 VI1_R0_B_MARK, VI1_R1_B_MARK,
4243                 VI1_R2_B_MARK, VI1_R3_B_MARK,
4244                 VI1_R4_B_MARK, VI1_R5_B_MARK,
4245                 VI1_R6_B_MARK, VI1_R7_B_MARK,
4246         },
4247 };
4248 static const unsigned int vin1_b_data18_pins[] = {
4249         /* B */
4250         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4251         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4252         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4253         /* G */
4254         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4255         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4256         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4257         /* R */
4258         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4259         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4260         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4261 };
4262 static const unsigned int vin1_b_data18_mux[] = {
4263         /* B */
4264         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4265         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4266         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4267         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4268         /* G */
4269         VI1_G0_B_MARK, VI1_G1_B_MARK,
4270         VI1_G2_B_MARK, VI1_G3_B_MARK,
4271         VI1_G4_B_MARK, VI1_G5_B_MARK,
4272         VI1_G6_B_MARK, VI1_G7_B_MARK,
4273         /* R */
4274         VI1_R0_B_MARK, VI1_R1_B_MARK,
4275         VI1_R2_B_MARK, VI1_R3_B_MARK,
4276         VI1_R4_B_MARK, VI1_R5_B_MARK,
4277         VI1_R6_B_MARK, VI1_R7_B_MARK,
4278 };
4279 static const unsigned int vin1_b_sync_pins[] = {
4280         RCAR_GP_PIN(3, 17), /* HSYNC */
4281         RCAR_GP_PIN(3, 18), /* VSYNC */
4282 };
4283 static const unsigned int vin1_b_sync_mux[] = {
4284         VI1_HSYNC_N_B_MARK,
4285         VI1_VSYNC_N_B_MARK,
4286 };
4287 static const unsigned int vin1_b_field_pins[] = {
4288         RCAR_GP_PIN(3, 20),
4289 };
4290 static const unsigned int vin1_b_field_mux[] = {
4291         VI1_FIELD_B_MARK,
4292 };
4293 static const unsigned int vin1_b_clkenb_pins[] = {
4294         RCAR_GP_PIN(3, 19),
4295 };
4296 static const unsigned int vin1_b_clkenb_mux[] = {
4297         VI1_CLKENB_B_MARK,
4298 };
4299 static const unsigned int vin1_b_clk_pins[] = {
4300         RCAR_GP_PIN(3, 16),
4301 };
4302 static const unsigned int vin1_b_clk_mux[] = {
4303         VI1_CLK_B_MARK,
4304 };
4305 /* - VIN2 ----------------------------------------------------------------- */
4306 static const unsigned int vin2_data8_pins[] = {
4307         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4308         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4309         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4310         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4311 };
4312 static const unsigned int vin2_data8_mux[] = {
4313         VI2_DATA0_MARK, VI2_DATA1_MARK,
4314         VI2_DATA2_MARK, VI2_DATA3_MARK,
4315         VI2_DATA4_MARK, VI2_DATA5_MARK,
4316         VI2_DATA6_MARK, VI2_DATA7_MARK,
4317 };
4318 static const unsigned int vin2_sync_pins[] = {
4319         RCAR_GP_PIN(4, 15), /* HSYNC */
4320         RCAR_GP_PIN(4, 16), /* VSYNC */
4321 };
4322 static const unsigned int vin2_sync_mux[] = {
4323         VI2_HSYNC_N_MARK,
4324         VI2_VSYNC_N_MARK,
4325 };
4326 static const unsigned int vin2_field_pins[] = {
4327         RCAR_GP_PIN(4, 18),
4328 };
4329 static const unsigned int vin2_field_mux[] = {
4330         VI2_FIELD_MARK,
4331 };
4332 static const unsigned int vin2_clkenb_pins[] = {
4333         RCAR_GP_PIN(4, 17),
4334 };
4335 static const unsigned int vin2_clkenb_mux[] = {
4336         VI2_CLKENB_MARK,
4337 };
4338 static const unsigned int vin2_clk_pins[] = {
4339         RCAR_GP_PIN(4, 19),
4340 };
4341 static const unsigned int vin2_clk_mux[] = {
4342         VI2_CLK_MARK,
4343 };
4344
4345 static const struct sh_pfc_pin_group pinmux_groups[] = {
4346         SH_PFC_PIN_GROUP(audio_clk_a),
4347         SH_PFC_PIN_GROUP(audio_clk_b),
4348         SH_PFC_PIN_GROUP(audio_clk_b_b),
4349         SH_PFC_PIN_GROUP(audio_clk_c),
4350         SH_PFC_PIN_GROUP(audio_clkout),
4351         SH_PFC_PIN_GROUP(avb_link),
4352         SH_PFC_PIN_GROUP(avb_magic),
4353         SH_PFC_PIN_GROUP(avb_phy_int),
4354         SH_PFC_PIN_GROUP(avb_mdio),
4355         SH_PFC_PIN_GROUP(avb_mii),
4356         SH_PFC_PIN_GROUP(avb_gmii),
4357         SH_PFC_PIN_GROUP(can0_data),
4358         SH_PFC_PIN_GROUP(can0_data_b),
4359         SH_PFC_PIN_GROUP(can0_data_c),
4360         SH_PFC_PIN_GROUP(can0_data_d),
4361         SH_PFC_PIN_GROUP(can0_data_e),
4362         SH_PFC_PIN_GROUP(can0_data_f),
4363         SH_PFC_PIN_GROUP(can1_data),
4364         SH_PFC_PIN_GROUP(can1_data_b),
4365         SH_PFC_PIN_GROUP(can1_data_c),
4366         SH_PFC_PIN_GROUP(can1_data_d),
4367         SH_PFC_PIN_GROUP(can_clk),
4368         SH_PFC_PIN_GROUP(can_clk_b),
4369         SH_PFC_PIN_GROUP(can_clk_c),
4370         SH_PFC_PIN_GROUP(can_clk_d),
4371         SH_PFC_PIN_GROUP(du_rgb666),
4372         SH_PFC_PIN_GROUP(du_rgb888),
4373         SH_PFC_PIN_GROUP(du_clk_out_0),
4374         SH_PFC_PIN_GROUP(du_clk_out_1),
4375         SH_PFC_PIN_GROUP(du_sync),
4376         SH_PFC_PIN_GROUP(du_oddf),
4377         SH_PFC_PIN_GROUP(du_cde),
4378         SH_PFC_PIN_GROUP(du_disp),
4379         SH_PFC_PIN_GROUP(du0_clk_in),
4380         SH_PFC_PIN_GROUP(du1_clk_in),
4381         SH_PFC_PIN_GROUP(du1_clk_in_b),
4382         SH_PFC_PIN_GROUP(du1_clk_in_c),
4383         SH_PFC_PIN_GROUP(eth_link),
4384         SH_PFC_PIN_GROUP(eth_magic),
4385         SH_PFC_PIN_GROUP(eth_mdio),
4386         SH_PFC_PIN_GROUP(eth_rmii),
4387         SH_PFC_PIN_GROUP(hscif0_data),
4388         SH_PFC_PIN_GROUP(hscif0_clk),
4389         SH_PFC_PIN_GROUP(hscif0_ctrl),
4390         SH_PFC_PIN_GROUP(hscif0_data_b),
4391         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4392         SH_PFC_PIN_GROUP(hscif0_data_c),
4393         SH_PFC_PIN_GROUP(hscif0_clk_c),
4394         SH_PFC_PIN_GROUP(hscif1_data),
4395         SH_PFC_PIN_GROUP(hscif1_clk),
4396         SH_PFC_PIN_GROUP(hscif1_ctrl),
4397         SH_PFC_PIN_GROUP(hscif1_data_b),
4398         SH_PFC_PIN_GROUP(hscif1_data_c),
4399         SH_PFC_PIN_GROUP(hscif1_clk_c),
4400         SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4401         SH_PFC_PIN_GROUP(hscif1_data_d),
4402         SH_PFC_PIN_GROUP(hscif1_data_e),
4403         SH_PFC_PIN_GROUP(hscif1_clk_e),
4404         SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4405         SH_PFC_PIN_GROUP(hscif2_data),
4406         SH_PFC_PIN_GROUP(hscif2_clk),
4407         SH_PFC_PIN_GROUP(hscif2_ctrl),
4408         SH_PFC_PIN_GROUP(hscif2_data_b),
4409         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4410         SH_PFC_PIN_GROUP(hscif2_data_c),
4411         SH_PFC_PIN_GROUP(hscif2_clk_c),
4412         SH_PFC_PIN_GROUP(hscif2_data_d),
4413         SH_PFC_PIN_GROUP(i2c0),
4414         SH_PFC_PIN_GROUP(i2c0_b),
4415         SH_PFC_PIN_GROUP(i2c0_c),
4416         SH_PFC_PIN_GROUP(i2c1),
4417         SH_PFC_PIN_GROUP(i2c1_b),
4418         SH_PFC_PIN_GROUP(i2c1_c),
4419         SH_PFC_PIN_GROUP(i2c1_d),
4420         SH_PFC_PIN_GROUP(i2c1_e),
4421         SH_PFC_PIN_GROUP(i2c2),
4422         SH_PFC_PIN_GROUP(i2c2_b),
4423         SH_PFC_PIN_GROUP(i2c2_c),
4424         SH_PFC_PIN_GROUP(i2c2_d),
4425         SH_PFC_PIN_GROUP(i2c3),
4426         SH_PFC_PIN_GROUP(i2c3_b),
4427         SH_PFC_PIN_GROUP(i2c3_c),
4428         SH_PFC_PIN_GROUP(i2c3_d),
4429         SH_PFC_PIN_GROUP(i2c4),
4430         SH_PFC_PIN_GROUP(i2c4_b),
4431         SH_PFC_PIN_GROUP(i2c4_c),
4432         SH_PFC_PIN_GROUP(i2c7),
4433         SH_PFC_PIN_GROUP(i2c7_b),
4434         SH_PFC_PIN_GROUP(i2c7_c),
4435         SH_PFC_PIN_GROUP(i2c8),
4436         SH_PFC_PIN_GROUP(i2c8_b),
4437         SH_PFC_PIN_GROUP(i2c8_c),
4438         SH_PFC_PIN_GROUP(intc_irq0),
4439         SH_PFC_PIN_GROUP(intc_irq1),
4440         SH_PFC_PIN_GROUP(intc_irq2),
4441         SH_PFC_PIN_GROUP(intc_irq3),
4442         SH_PFC_PIN_GROUP(mlb_3pin),
4443         SH_PFC_PIN_GROUP(mmc_data1),
4444         SH_PFC_PIN_GROUP(mmc_data4),
4445         SH_PFC_PIN_GROUP(mmc_data8),
4446         SH_PFC_PIN_GROUP(mmc_ctrl),
4447         SH_PFC_PIN_GROUP(msiof0_clk),
4448         SH_PFC_PIN_GROUP(msiof0_sync),
4449         SH_PFC_PIN_GROUP(msiof0_ss1),
4450         SH_PFC_PIN_GROUP(msiof0_ss2),
4451         SH_PFC_PIN_GROUP(msiof0_rx),
4452         SH_PFC_PIN_GROUP(msiof0_tx),
4453         SH_PFC_PIN_GROUP(msiof0_clk_b),
4454         SH_PFC_PIN_GROUP(msiof0_sync_b),
4455         SH_PFC_PIN_GROUP(msiof0_ss1_b),
4456         SH_PFC_PIN_GROUP(msiof0_ss2_b),
4457         SH_PFC_PIN_GROUP(msiof0_rx_b),
4458         SH_PFC_PIN_GROUP(msiof0_tx_b),
4459         SH_PFC_PIN_GROUP(msiof0_clk_c),
4460         SH_PFC_PIN_GROUP(msiof0_sync_c),
4461         SH_PFC_PIN_GROUP(msiof0_ss1_c),
4462         SH_PFC_PIN_GROUP(msiof0_ss2_c),
4463         SH_PFC_PIN_GROUP(msiof0_rx_c),
4464         SH_PFC_PIN_GROUP(msiof0_tx_c),
4465         SH_PFC_PIN_GROUP(msiof1_clk),
4466         SH_PFC_PIN_GROUP(msiof1_sync),
4467         SH_PFC_PIN_GROUP(msiof1_ss1),
4468         SH_PFC_PIN_GROUP(msiof1_ss2),
4469         SH_PFC_PIN_GROUP(msiof1_rx),
4470         SH_PFC_PIN_GROUP(msiof1_tx),
4471         SH_PFC_PIN_GROUP(msiof1_clk_b),
4472         SH_PFC_PIN_GROUP(msiof1_sync_b),
4473         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4474         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4475         SH_PFC_PIN_GROUP(msiof1_rx_b),
4476         SH_PFC_PIN_GROUP(msiof1_tx_b),
4477         SH_PFC_PIN_GROUP(msiof1_clk_c),
4478         SH_PFC_PIN_GROUP(msiof1_sync_c),
4479         SH_PFC_PIN_GROUP(msiof1_rx_c),
4480         SH_PFC_PIN_GROUP(msiof1_tx_c),
4481         SH_PFC_PIN_GROUP(msiof1_clk_d),
4482         SH_PFC_PIN_GROUP(msiof1_sync_d),
4483         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4484         SH_PFC_PIN_GROUP(msiof1_rx_d),
4485         SH_PFC_PIN_GROUP(msiof1_tx_d),
4486         SH_PFC_PIN_GROUP(msiof1_clk_e),
4487         SH_PFC_PIN_GROUP(msiof1_sync_e),
4488         SH_PFC_PIN_GROUP(msiof1_rx_e),
4489         SH_PFC_PIN_GROUP(msiof1_tx_e),
4490         SH_PFC_PIN_GROUP(msiof2_clk),
4491         SH_PFC_PIN_GROUP(msiof2_sync),
4492         SH_PFC_PIN_GROUP(msiof2_ss1),
4493         SH_PFC_PIN_GROUP(msiof2_ss2),
4494         SH_PFC_PIN_GROUP(msiof2_rx),
4495         SH_PFC_PIN_GROUP(msiof2_tx),
4496         SH_PFC_PIN_GROUP(msiof2_clk_b),
4497         SH_PFC_PIN_GROUP(msiof2_sync_b),
4498         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4499         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4500         SH_PFC_PIN_GROUP(msiof2_rx_b),
4501         SH_PFC_PIN_GROUP(msiof2_tx_b),
4502         SH_PFC_PIN_GROUP(msiof2_clk_c),
4503         SH_PFC_PIN_GROUP(msiof2_sync_c),
4504         SH_PFC_PIN_GROUP(msiof2_rx_c),
4505         SH_PFC_PIN_GROUP(msiof2_tx_c),
4506         SH_PFC_PIN_GROUP(msiof2_clk_d),
4507         SH_PFC_PIN_GROUP(msiof2_sync_d),
4508         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4509         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4510         SH_PFC_PIN_GROUP(msiof2_rx_d),
4511         SH_PFC_PIN_GROUP(msiof2_tx_d),
4512         SH_PFC_PIN_GROUP(msiof2_clk_e),
4513         SH_PFC_PIN_GROUP(msiof2_sync_e),
4514         SH_PFC_PIN_GROUP(msiof2_rx_e),
4515         SH_PFC_PIN_GROUP(msiof2_tx_e),
4516         SH_PFC_PIN_GROUP(pwm0),
4517         SH_PFC_PIN_GROUP(pwm0_b),
4518         SH_PFC_PIN_GROUP(pwm1),
4519         SH_PFC_PIN_GROUP(pwm1_b),
4520         SH_PFC_PIN_GROUP(pwm2),
4521         SH_PFC_PIN_GROUP(pwm2_b),
4522         SH_PFC_PIN_GROUP(pwm3),
4523         SH_PFC_PIN_GROUP(pwm4),
4524         SH_PFC_PIN_GROUP(pwm4_b),
4525         SH_PFC_PIN_GROUP(pwm5),
4526         SH_PFC_PIN_GROUP(pwm5_b),
4527         SH_PFC_PIN_GROUP(pwm6),
4528         SH_PFC_PIN_GROUP(qspi_ctrl),
4529         SH_PFC_PIN_GROUP(qspi_data2),
4530         SH_PFC_PIN_GROUP(qspi_data4),
4531         SH_PFC_PIN_GROUP(qspi_ctrl_b),
4532         SH_PFC_PIN_GROUP(qspi_data2_b),
4533         SH_PFC_PIN_GROUP(qspi_data4_b),
4534         SH_PFC_PIN_GROUP(scif0_data),
4535         SH_PFC_PIN_GROUP(scif0_data_b),
4536         SH_PFC_PIN_GROUP(scif0_data_c),
4537         SH_PFC_PIN_GROUP(scif0_data_d),
4538         SH_PFC_PIN_GROUP(scif0_data_e),
4539         SH_PFC_PIN_GROUP(scif1_data),
4540         SH_PFC_PIN_GROUP(scif1_data_b),
4541         SH_PFC_PIN_GROUP(scif1_clk_b),
4542         SH_PFC_PIN_GROUP(scif1_data_c),
4543         SH_PFC_PIN_GROUP(scif1_data_d),
4544         SH_PFC_PIN_GROUP(scif2_data),
4545         SH_PFC_PIN_GROUP(scif2_data_b),
4546         SH_PFC_PIN_GROUP(scif2_clk_b),
4547         SH_PFC_PIN_GROUP(scif2_data_c),
4548         SH_PFC_PIN_GROUP(scif2_data_e),
4549         SH_PFC_PIN_GROUP(scif3_data),
4550         SH_PFC_PIN_GROUP(scif3_clk),
4551         SH_PFC_PIN_GROUP(scif3_data_b),
4552         SH_PFC_PIN_GROUP(scif3_clk_b),
4553         SH_PFC_PIN_GROUP(scif3_data_c),
4554         SH_PFC_PIN_GROUP(scif3_data_d),
4555         SH_PFC_PIN_GROUP(scif4_data),
4556         SH_PFC_PIN_GROUP(scif4_data_b),
4557         SH_PFC_PIN_GROUP(scif4_data_c),
4558         SH_PFC_PIN_GROUP(scif5_data),
4559         SH_PFC_PIN_GROUP(scif5_data_b),
4560         SH_PFC_PIN_GROUP(scifa0_data),
4561         SH_PFC_PIN_GROUP(scifa0_data_b),
4562         SH_PFC_PIN_GROUP(scifa1_data),
4563         SH_PFC_PIN_GROUP(scifa1_clk),
4564         SH_PFC_PIN_GROUP(scifa1_data_b),
4565         SH_PFC_PIN_GROUP(scifa1_clk_b),
4566         SH_PFC_PIN_GROUP(scifa1_data_c),
4567         SH_PFC_PIN_GROUP(scifa2_data),
4568         SH_PFC_PIN_GROUP(scifa2_clk),
4569         SH_PFC_PIN_GROUP(scifa2_data_b),
4570         SH_PFC_PIN_GROUP(scifa3_data),
4571         SH_PFC_PIN_GROUP(scifa3_clk),
4572         SH_PFC_PIN_GROUP(scifa3_data_b),
4573         SH_PFC_PIN_GROUP(scifa3_clk_b),
4574         SH_PFC_PIN_GROUP(scifa3_data_c),
4575         SH_PFC_PIN_GROUP(scifa3_clk_c),
4576         SH_PFC_PIN_GROUP(scifa4_data),
4577         SH_PFC_PIN_GROUP(scifa4_data_b),
4578         SH_PFC_PIN_GROUP(scifa4_data_c),
4579         SH_PFC_PIN_GROUP(scifa5_data),
4580         SH_PFC_PIN_GROUP(scifa5_data_b),
4581         SH_PFC_PIN_GROUP(scifa5_data_c),
4582         SH_PFC_PIN_GROUP(scifb0_data),
4583         SH_PFC_PIN_GROUP(scifb0_clk),
4584         SH_PFC_PIN_GROUP(scifb0_ctrl),
4585         SH_PFC_PIN_GROUP(scifb0_data_b),
4586         SH_PFC_PIN_GROUP(scifb0_clk_b),
4587         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4588         SH_PFC_PIN_GROUP(scifb0_data_c),
4589         SH_PFC_PIN_GROUP(scifb0_clk_c),
4590         SH_PFC_PIN_GROUP(scifb0_data_d),
4591         SH_PFC_PIN_GROUP(scifb0_clk_d),
4592         SH_PFC_PIN_GROUP(scifb1_data),
4593         SH_PFC_PIN_GROUP(scifb1_clk),
4594         SH_PFC_PIN_GROUP(scifb1_ctrl),
4595         SH_PFC_PIN_GROUP(scifb1_data_b),
4596         SH_PFC_PIN_GROUP(scifb1_clk_b),
4597         SH_PFC_PIN_GROUP(scifb1_data_c),
4598         SH_PFC_PIN_GROUP(scifb1_clk_c),
4599         SH_PFC_PIN_GROUP(scifb1_data_d),
4600         SH_PFC_PIN_GROUP(scifb2_data),
4601         SH_PFC_PIN_GROUP(scifb2_clk),
4602         SH_PFC_PIN_GROUP(scifb2_ctrl),
4603         SH_PFC_PIN_GROUP(scifb2_data_b),
4604         SH_PFC_PIN_GROUP(scifb2_clk_b),
4605         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4606         SH_PFC_PIN_GROUP(scifb2_data_c),
4607         SH_PFC_PIN_GROUP(scifb2_clk_c),
4608         SH_PFC_PIN_GROUP(scifb2_data_d),
4609         SH_PFC_PIN_GROUP(scif_clk),
4610         SH_PFC_PIN_GROUP(scif_clk_b),
4611         SH_PFC_PIN_GROUP(sdhi0_data1),
4612         SH_PFC_PIN_GROUP(sdhi0_data4),
4613         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4614         SH_PFC_PIN_GROUP(sdhi0_cd),
4615         SH_PFC_PIN_GROUP(sdhi0_wp),
4616         SH_PFC_PIN_GROUP(sdhi1_data1),
4617         SH_PFC_PIN_GROUP(sdhi1_data4),
4618         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4619         SH_PFC_PIN_GROUP(sdhi1_cd),
4620         SH_PFC_PIN_GROUP(sdhi1_wp),
4621         SH_PFC_PIN_GROUP(sdhi2_data1),
4622         SH_PFC_PIN_GROUP(sdhi2_data4),
4623         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4624         SH_PFC_PIN_GROUP(sdhi2_cd),
4625         SH_PFC_PIN_GROUP(sdhi2_wp),
4626         SH_PFC_PIN_GROUP(ssi0_data),
4627         SH_PFC_PIN_GROUP(ssi0_data_b),
4628         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4629         SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4630         SH_PFC_PIN_GROUP(ssi1_data),
4631         SH_PFC_PIN_GROUP(ssi1_data_b),
4632         SH_PFC_PIN_GROUP(ssi1_ctrl),
4633         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4634         SH_PFC_PIN_GROUP(ssi2_data),
4635         SH_PFC_PIN_GROUP(ssi2_ctrl),
4636         SH_PFC_PIN_GROUP(ssi3_data),
4637         SH_PFC_PIN_GROUP(ssi34_ctrl),
4638         SH_PFC_PIN_GROUP(ssi4_data),
4639         SH_PFC_PIN_GROUP(ssi4_ctrl),
4640         SH_PFC_PIN_GROUP(ssi5_data),
4641         SH_PFC_PIN_GROUP(ssi5_ctrl),
4642         SH_PFC_PIN_GROUP(ssi6_data),
4643         SH_PFC_PIN_GROUP(ssi6_ctrl),
4644         SH_PFC_PIN_GROUP(ssi7_data),
4645         SH_PFC_PIN_GROUP(ssi7_data_b),
4646         SH_PFC_PIN_GROUP(ssi78_ctrl),
4647         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4648         SH_PFC_PIN_GROUP(ssi8_data),
4649         SH_PFC_PIN_GROUP(ssi8_data_b),
4650         SH_PFC_PIN_GROUP(ssi9_data),
4651         SH_PFC_PIN_GROUP(ssi9_data_b),
4652         SH_PFC_PIN_GROUP(ssi9_ctrl),
4653         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4654         SH_PFC_PIN_GROUP(usb0),
4655         SH_PFC_PIN_GROUP(usb1),
4656         VIN_DATA_PIN_GROUP(vin0_data, 24),
4657         VIN_DATA_PIN_GROUP(vin0_data, 20),
4658         SH_PFC_PIN_GROUP(vin0_data18),
4659         VIN_DATA_PIN_GROUP(vin0_data, 16),
4660         VIN_DATA_PIN_GROUP(vin0_data, 12),
4661         VIN_DATA_PIN_GROUP(vin0_data, 10),
4662         VIN_DATA_PIN_GROUP(vin0_data, 8),
4663         SH_PFC_PIN_GROUP(vin0_sync),
4664         SH_PFC_PIN_GROUP(vin0_field),
4665         SH_PFC_PIN_GROUP(vin0_clkenb),
4666         SH_PFC_PIN_GROUP(vin0_clk),
4667         SH_PFC_PIN_GROUP(vin1_data8),
4668         SH_PFC_PIN_GROUP(vin1_sync),
4669         SH_PFC_PIN_GROUP(vin1_field),
4670         SH_PFC_PIN_GROUP(vin1_clkenb),
4671         SH_PFC_PIN_GROUP(vin1_clk),
4672         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4673         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4674         SH_PFC_PIN_GROUP(vin1_b_data18),
4675         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4676         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4677         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4678         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4679         SH_PFC_PIN_GROUP(vin1_b_sync),
4680         SH_PFC_PIN_GROUP(vin1_b_field),
4681         SH_PFC_PIN_GROUP(vin1_b_clkenb),
4682         SH_PFC_PIN_GROUP(vin1_b_clk),
4683         SH_PFC_PIN_GROUP(vin2_data8),
4684         SH_PFC_PIN_GROUP(vin2_sync),
4685         SH_PFC_PIN_GROUP(vin2_field),
4686         SH_PFC_PIN_GROUP(vin2_clkenb),
4687         SH_PFC_PIN_GROUP(vin2_clk),
4688 };
4689
4690 static const char * const audio_clk_groups[] = {
4691         "audio_clk_a",
4692         "audio_clk_b",
4693         "audio_clk_b_b",
4694         "audio_clk_c",
4695         "audio_clkout",
4696 };
4697
4698 static const char * const avb_groups[] = {
4699         "avb_link",
4700         "avb_magic",
4701         "avb_phy_int",
4702         "avb_mdio",
4703         "avb_mii",
4704         "avb_gmii",
4705 };
4706
4707 static const char * const can0_groups[] = {
4708         "can0_data",
4709         "can0_data_b",
4710         "can0_data_c",
4711         "can0_data_d",
4712         "can0_data_e",
4713         "can0_data_f",
4714         "can_clk",
4715         "can_clk_b",
4716         "can_clk_c",
4717         "can_clk_d",
4718 };
4719
4720 static const char * const can1_groups[] = {
4721         "can1_data",
4722         "can1_data_b",
4723         "can1_data_c",
4724         "can1_data_d",
4725         "can_clk",
4726         "can_clk_b",
4727         "can_clk_c",
4728         "can_clk_d",
4729 };
4730
4731 static const char * const du_groups[] = {
4732         "du_rgb666",
4733         "du_rgb888",
4734         "du_clk_out_0",
4735         "du_clk_out_1",
4736         "du_sync",
4737         "du_oddf",
4738         "du_cde",
4739         "du_disp",
4740 };
4741
4742 static const char * const du0_groups[] = {
4743         "du0_clk_in",
4744 };
4745
4746 static const char * const du1_groups[] = {
4747         "du1_clk_in",
4748         "du1_clk_in_b",
4749         "du1_clk_in_c",
4750 };
4751
4752 static const char * const eth_groups[] = {
4753         "eth_link",
4754         "eth_magic",
4755         "eth_mdio",
4756         "eth_rmii",
4757 };
4758
4759 static const char * const hscif0_groups[] = {
4760         "hscif0_data",
4761         "hscif0_clk",
4762         "hscif0_ctrl",
4763         "hscif0_data_b",
4764         "hscif0_ctrl_b",
4765         "hscif0_data_c",
4766         "hscif0_clk_c",
4767 };
4768
4769 static const char * const hscif1_groups[] = {
4770         "hscif1_data",
4771         "hscif1_clk",
4772         "hscif1_ctrl",
4773         "hscif1_data_b",
4774         "hscif1_data_c",
4775         "hscif1_clk_c",
4776         "hscif1_ctrl_c",
4777         "hscif1_data_d",
4778         "hscif1_data_e",
4779         "hscif1_clk_e",
4780         "hscif1_ctrl_e",
4781 };
4782
4783 static const char * const hscif2_groups[] = {
4784         "hscif2_data",
4785         "hscif2_clk",
4786         "hscif2_ctrl",
4787         "hscif2_data_b",
4788         "hscif2_ctrl_b",
4789         "hscif2_data_c",
4790         "hscif2_clk_c",
4791         "hscif2_data_d",
4792 };
4793
4794 static const char * const i2c0_groups[] = {
4795         "i2c0",
4796         "i2c0_b",
4797         "i2c0_c",
4798 };
4799
4800 static const char * const i2c1_groups[] = {
4801         "i2c1",
4802         "i2c1_b",
4803         "i2c1_c",
4804         "i2c1_d",
4805         "i2c1_e",
4806 };
4807
4808 static const char * const i2c2_groups[] = {
4809         "i2c2",
4810         "i2c2_b",
4811         "i2c2_c",
4812         "i2c2_d",
4813 };
4814
4815 static const char * const i2c3_groups[] = {
4816         "i2c3",
4817         "i2c3_b",
4818         "i2c3_c",
4819         "i2c3_d",
4820 };
4821
4822 static const char * const i2c4_groups[] = {
4823         "i2c4",
4824         "i2c4_b",
4825         "i2c4_c",
4826 };
4827
4828 static const char * const i2c7_groups[] = {
4829         "i2c7",
4830         "i2c7_b",
4831         "i2c7_c",
4832 };
4833
4834 static const char * const i2c8_groups[] = {
4835         "i2c8",
4836         "i2c8_b",
4837         "i2c8_c",
4838 };
4839
4840 static const char * const intc_groups[] = {
4841         "intc_irq0",
4842         "intc_irq1",
4843         "intc_irq2",
4844         "intc_irq3",
4845 };
4846
4847 static const char * const mlb_groups[] = {
4848         "mlb_3pin",
4849 };
4850
4851 static const char * const mmc_groups[] = {
4852         "mmc_data1",
4853         "mmc_data4",
4854         "mmc_data8",
4855         "mmc_ctrl",
4856 };
4857
4858 static const char * const msiof0_groups[] = {
4859         "msiof0_clk",
4860         "msiof0_sync",
4861         "msiof0_ss1",
4862         "msiof0_ss2",
4863         "msiof0_rx",
4864         "msiof0_tx",
4865         "msiof0_clk_b",
4866         "msiof0_sync_b",
4867         "msiof0_ss1_b",
4868         "msiof0_ss2_b",
4869         "msiof0_rx_b",
4870         "msiof0_tx_b",
4871         "msiof0_clk_c",
4872         "msiof0_sync_c",
4873         "msiof0_ss1_c",
4874         "msiof0_ss2_c",
4875         "msiof0_rx_c",
4876         "msiof0_tx_c",
4877 };
4878
4879 static const char * const msiof1_groups[] = {
4880         "msiof1_clk",
4881         "msiof1_sync",
4882         "msiof1_ss1",
4883         "msiof1_ss2",
4884         "msiof1_rx",
4885         "msiof1_tx",
4886         "msiof1_clk_b",
4887         "msiof1_sync_b",
4888         "msiof1_ss1_b",
4889         "msiof1_ss2_b",
4890         "msiof1_rx_b",
4891         "msiof1_tx_b",
4892         "msiof1_clk_c",
4893         "msiof1_sync_c",
4894         "msiof1_rx_c",
4895         "msiof1_tx_c",
4896         "msiof1_clk_d",
4897         "msiof1_sync_d",
4898         "msiof1_ss1_d",
4899         "msiof1_rx_d",
4900         "msiof1_tx_d",
4901         "msiof1_clk_e",
4902         "msiof1_sync_e",
4903         "msiof1_rx_e",
4904         "msiof1_tx_e",
4905 };
4906
4907 static const char * const msiof2_groups[] = {
4908         "msiof2_clk",
4909         "msiof2_sync",
4910         "msiof2_ss1",
4911         "msiof2_ss2",
4912         "msiof2_rx",
4913         "msiof2_tx",
4914         "msiof2_clk_b",
4915         "msiof2_sync_b",
4916         "msiof2_ss1_b",
4917         "msiof2_ss2_b",
4918         "msiof2_rx_b",
4919         "msiof2_tx_b",
4920         "msiof2_clk_c",
4921         "msiof2_sync_c",
4922         "msiof2_rx_c",
4923         "msiof2_tx_c",
4924         "msiof2_clk_d",
4925         "msiof2_sync_d",
4926         "msiof2_ss1_d",
4927         "msiof2_ss2_d",
4928         "msiof2_rx_d",
4929         "msiof2_tx_d",
4930         "msiof2_clk_e",
4931         "msiof2_sync_e",
4932         "msiof2_rx_e",
4933         "msiof2_tx_e",
4934 };
4935
4936 static const char * const pwm0_groups[] = {
4937         "pwm0",
4938         "pwm0_b",
4939 };
4940
4941 static const char * const pwm1_groups[] = {
4942         "pwm1",
4943         "pwm1_b",
4944 };
4945
4946 static const char * const pwm2_groups[] = {
4947         "pwm2",
4948         "pwm2_b",
4949 };
4950
4951 static const char * const pwm3_groups[] = {
4952         "pwm3",
4953 };
4954
4955 static const char * const pwm4_groups[] = {
4956         "pwm4",
4957         "pwm4_b",
4958 };
4959
4960 static const char * const pwm5_groups[] = {
4961         "pwm5",
4962         "pwm5_b",
4963 };
4964
4965 static const char * const pwm6_groups[] = {
4966         "pwm6",
4967 };
4968
4969 static const char * const qspi_groups[] = {
4970         "qspi_ctrl",
4971         "qspi_data2",
4972         "qspi_data4",
4973         "qspi_ctrl_b",
4974         "qspi_data2_b",
4975         "qspi_data4_b",
4976 };
4977
4978 static const char * const scif0_groups[] = {
4979         "scif0_data",
4980         "scif0_data_b",
4981         "scif0_data_c",
4982         "scif0_data_d",
4983         "scif0_data_e",
4984 };
4985
4986 static const char * const scif1_groups[] = {
4987         "scif1_data",
4988         "scif1_data_b",
4989         "scif1_clk_b",
4990         "scif1_data_c",
4991         "scif1_data_d",
4992 };
4993
4994 static const char * const scif2_groups[] = {
4995         "scif2_data",
4996         "scif2_data_b",
4997         "scif2_clk_b",
4998         "scif2_data_c",
4999         "scif2_data_e",
5000 };
5001 static const char * const scif3_groups[] = {
5002         "scif3_data",
5003         "scif3_clk",
5004         "scif3_data_b",
5005         "scif3_clk_b",
5006         "scif3_data_c",
5007         "scif3_data_d",
5008 };
5009 static const char * const scif4_groups[] = {
5010         "scif4_data",
5011         "scif4_data_b",
5012         "scif4_data_c",
5013 };
5014 static const char * const scif5_groups[] = {
5015         "scif5_data",
5016         "scif5_data_b",
5017 };
5018 static const char * const scifa0_groups[] = {
5019         "scifa0_data",
5020         "scifa0_data_b",
5021 };
5022 static const char * const scifa1_groups[] = {
5023         "scifa1_data",
5024         "scifa1_clk",
5025         "scifa1_data_b",
5026         "scifa1_clk_b",
5027         "scifa1_data_c",
5028 };
5029 static const char * const scifa2_groups[] = {
5030         "scifa2_data",
5031         "scifa2_clk",
5032         "scifa2_data_b",
5033 };
5034 static const char * const scifa3_groups[] = {
5035         "scifa3_data",
5036         "scifa3_clk",
5037         "scifa3_data_b",
5038         "scifa3_clk_b",
5039         "scifa3_data_c",
5040         "scifa3_clk_c",
5041 };
5042 static const char * const scifa4_groups[] = {
5043         "scifa4_data",
5044         "scifa4_data_b",
5045         "scifa4_data_c",
5046 };
5047 static const char * const scifa5_groups[] = {
5048         "scifa5_data",
5049         "scifa5_data_b",
5050         "scifa5_data_c",
5051 };
5052 static const char * const scifb0_groups[] = {
5053         "scifb0_data",
5054         "scifb0_clk",
5055         "scifb0_ctrl",
5056         "scifb0_data_b",
5057         "scifb0_clk_b",
5058         "scifb0_ctrl_b",
5059         "scifb0_data_c",
5060         "scifb0_clk_c",
5061         "scifb0_data_d",
5062         "scifb0_clk_d",
5063 };
5064 static const char * const scifb1_groups[] = {
5065         "scifb1_data",
5066         "scifb1_clk",
5067         "scifb1_ctrl",
5068         "scifb1_data_b",
5069         "scifb1_clk_b",
5070         "scifb1_data_c",
5071         "scifb1_clk_c",
5072         "scifb1_data_d",
5073 };
5074 static const char * const scifb2_groups[] = {
5075         "scifb2_data",
5076         "scifb2_clk",
5077         "scifb2_ctrl",
5078         "scifb2_data_b",
5079         "scifb2_clk_b",
5080         "scifb2_ctrl_b",
5081         "scifb0_data_c",
5082         "scifb2_clk_c",
5083         "scifb2_data_d",
5084 };
5085
5086 static const char * const scif_clk_groups[] = {
5087         "scif_clk",
5088         "scif_clk_b",
5089 };
5090
5091 static const char * const sdhi0_groups[] = {
5092         "sdhi0_data1",
5093         "sdhi0_data4",
5094         "sdhi0_ctrl",
5095         "sdhi0_cd",
5096         "sdhi0_wp",
5097 };
5098
5099 static const char * const sdhi1_groups[] = {
5100         "sdhi1_data1",
5101         "sdhi1_data4",
5102         "sdhi1_ctrl",
5103         "sdhi1_cd",
5104         "sdhi1_wp",
5105 };
5106
5107 static const char * const sdhi2_groups[] = {
5108         "sdhi2_data1",
5109         "sdhi2_data4",
5110         "sdhi2_ctrl",
5111         "sdhi2_cd",
5112         "sdhi2_wp",
5113 };
5114
5115 static const char * const ssi_groups[] = {
5116         "ssi0_data",
5117         "ssi0_data_b",
5118         "ssi0129_ctrl",
5119         "ssi0129_ctrl_b",
5120         "ssi1_data",
5121         "ssi1_data_b",
5122         "ssi1_ctrl",
5123         "ssi1_ctrl_b",
5124         "ssi2_data",
5125         "ssi2_ctrl",
5126         "ssi3_data",
5127         "ssi34_ctrl",
5128         "ssi4_data",
5129         "ssi4_ctrl",
5130         "ssi5_data",
5131         "ssi5_ctrl",
5132         "ssi6_data",
5133         "ssi6_ctrl",
5134         "ssi7_data",
5135         "ssi7_data_b",
5136         "ssi78_ctrl",
5137         "ssi78_ctrl_b",
5138         "ssi8_data",
5139         "ssi8_data_b",
5140         "ssi9_data",
5141         "ssi9_data_b",
5142         "ssi9_ctrl",
5143         "ssi9_ctrl_b",
5144 };
5145
5146 static const char * const usb0_groups[] = {
5147         "usb0",
5148 };
5149 static const char * const usb1_groups[] = {
5150         "usb1",
5151 };
5152
5153 static const char * const vin0_groups[] = {
5154         "vin0_data24",
5155         "vin0_data20",
5156         "vin0_data18",
5157         "vin0_data16",
5158         "vin0_data12",
5159         "vin0_data10",
5160         "vin0_data8",
5161         "vin0_sync",
5162         "vin0_field",
5163         "vin0_clkenb",
5164         "vin0_clk",
5165 };
5166
5167 static const char * const vin1_groups[] = {
5168         "vin1_data8",
5169         "vin1_sync",
5170         "vin1_field",
5171         "vin1_clkenb",
5172         "vin1_clk",
5173         "vin1_b_data24",
5174         "vin1_b_data20",
5175         "vin1_b_data18",
5176         "vin1_b_data16",
5177         "vin1_b_data12",
5178         "vin1_b_data10",
5179         "vin1_b_data8",
5180         "vin1_b_sync",
5181         "vin1_b_field",
5182         "vin1_b_clkenb",
5183         "vin1_b_clk",
5184 };
5185
5186 static const char * const vin2_groups[] = {
5187         "vin2_data8",
5188         "vin2_sync",
5189         "vin2_field",
5190         "vin2_clkenb",
5191         "vin2_clk",
5192 };
5193
5194 static const struct sh_pfc_function pinmux_functions[] = {
5195         SH_PFC_FUNCTION(audio_clk),
5196         SH_PFC_FUNCTION(avb),
5197         SH_PFC_FUNCTION(can0),
5198         SH_PFC_FUNCTION(can1),
5199         SH_PFC_FUNCTION(du),
5200         SH_PFC_FUNCTION(du0),
5201         SH_PFC_FUNCTION(du1),
5202         SH_PFC_FUNCTION(eth),
5203         SH_PFC_FUNCTION(hscif0),
5204         SH_PFC_FUNCTION(hscif1),
5205         SH_PFC_FUNCTION(hscif2),
5206         SH_PFC_FUNCTION(i2c0),
5207         SH_PFC_FUNCTION(i2c1),
5208         SH_PFC_FUNCTION(i2c2),
5209         SH_PFC_FUNCTION(i2c3),
5210         SH_PFC_FUNCTION(i2c4),
5211         SH_PFC_FUNCTION(i2c7),
5212         SH_PFC_FUNCTION(i2c8),
5213         SH_PFC_FUNCTION(intc),
5214         SH_PFC_FUNCTION(mlb),
5215         SH_PFC_FUNCTION(mmc),
5216         SH_PFC_FUNCTION(msiof0),
5217         SH_PFC_FUNCTION(msiof1),
5218         SH_PFC_FUNCTION(msiof2),
5219         SH_PFC_FUNCTION(pwm0),
5220         SH_PFC_FUNCTION(pwm1),
5221         SH_PFC_FUNCTION(pwm2),
5222         SH_PFC_FUNCTION(pwm3),
5223         SH_PFC_FUNCTION(pwm4),
5224         SH_PFC_FUNCTION(pwm5),
5225         SH_PFC_FUNCTION(pwm6),
5226         SH_PFC_FUNCTION(qspi),
5227         SH_PFC_FUNCTION(scif0),
5228         SH_PFC_FUNCTION(scif1),
5229         SH_PFC_FUNCTION(scif2),
5230         SH_PFC_FUNCTION(scif3),
5231         SH_PFC_FUNCTION(scif4),
5232         SH_PFC_FUNCTION(scif5),
5233         SH_PFC_FUNCTION(scifa0),
5234         SH_PFC_FUNCTION(scifa1),
5235         SH_PFC_FUNCTION(scifa2),
5236         SH_PFC_FUNCTION(scifa3),
5237         SH_PFC_FUNCTION(scifa4),
5238         SH_PFC_FUNCTION(scifa5),
5239         SH_PFC_FUNCTION(scifb0),
5240         SH_PFC_FUNCTION(scifb1),
5241         SH_PFC_FUNCTION(scifb2),
5242         SH_PFC_FUNCTION(scif_clk),
5243         SH_PFC_FUNCTION(sdhi0),
5244         SH_PFC_FUNCTION(sdhi1),
5245         SH_PFC_FUNCTION(sdhi2),
5246         SH_PFC_FUNCTION(ssi),
5247         SH_PFC_FUNCTION(usb0),
5248         SH_PFC_FUNCTION(usb1),
5249         SH_PFC_FUNCTION(vin0),
5250         SH_PFC_FUNCTION(vin1),
5251         SH_PFC_FUNCTION(vin2),
5252 };
5253
5254 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5255         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5256                 GP_0_31_FN, FN_IP1_22_20,
5257                 GP_0_30_FN, FN_IP1_19_17,
5258                 GP_0_29_FN, FN_IP1_16_14,
5259                 GP_0_28_FN, FN_IP1_13_11,
5260                 GP_0_27_FN, FN_IP1_10_8,
5261                 GP_0_26_FN, FN_IP1_7_6,
5262                 GP_0_25_FN, FN_IP1_5_4,
5263                 GP_0_24_FN, FN_IP1_3_2,
5264                 GP_0_23_FN, FN_IP1_1_0,
5265                 GP_0_22_FN, FN_IP0_30_29,
5266                 GP_0_21_FN, FN_IP0_28_27,
5267                 GP_0_20_FN, FN_IP0_26_25,
5268                 GP_0_19_FN, FN_IP0_24_23,
5269                 GP_0_18_FN, FN_IP0_22_21,
5270                 GP_0_17_FN, FN_IP0_20_19,
5271                 GP_0_16_FN, FN_IP0_18_16,
5272                 GP_0_15_FN, FN_IP0_15,
5273                 GP_0_14_FN, FN_IP0_14,
5274                 GP_0_13_FN, FN_IP0_13,
5275                 GP_0_12_FN, FN_IP0_12,
5276                 GP_0_11_FN, FN_IP0_11,
5277                 GP_0_10_FN, FN_IP0_10,
5278                 GP_0_9_FN, FN_IP0_9,
5279                 GP_0_8_FN, FN_IP0_8,
5280                 GP_0_7_FN, FN_IP0_7,
5281                 GP_0_6_FN, FN_IP0_6,
5282                 GP_0_5_FN, FN_IP0_5,
5283                 GP_0_4_FN, FN_IP0_4,
5284                 GP_0_3_FN, FN_IP0_3,
5285                 GP_0_2_FN, FN_IP0_2,
5286                 GP_0_1_FN, FN_IP0_1,
5287                 GP_0_0_FN, FN_IP0_0, }
5288         },
5289         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5290                 0, 0,
5291                 0, 0,
5292                 0, 0,
5293                 0, 0,
5294                 0, 0,
5295                 0, 0,
5296                 GP_1_25_FN, FN_IP3_21_20,
5297                 GP_1_24_FN, FN_IP3_19_18,
5298                 GP_1_23_FN, FN_IP3_17_16,
5299                 GP_1_22_FN, FN_IP3_15_14,
5300                 GP_1_21_FN, FN_IP3_13_12,
5301                 GP_1_20_FN, FN_IP3_11_9,
5302                 GP_1_19_FN, FN_RD_N,
5303                 GP_1_18_FN, FN_IP3_8_6,
5304                 GP_1_17_FN, FN_IP3_5_3,
5305                 GP_1_16_FN, FN_IP3_2_0,
5306                 GP_1_15_FN, FN_IP2_29_27,
5307                 GP_1_14_FN, FN_IP2_26_25,
5308                 GP_1_13_FN, FN_IP2_24_23,
5309                 GP_1_12_FN, FN_EX_CS0_N,
5310                 GP_1_11_FN, FN_IP2_22_21,
5311                 GP_1_10_FN, FN_IP2_20_19,
5312                 GP_1_9_FN, FN_IP2_18_16,
5313                 GP_1_8_FN, FN_IP2_15_13,
5314                 GP_1_7_FN, FN_IP2_12_10,
5315                 GP_1_6_FN, FN_IP2_9_7,
5316                 GP_1_5_FN, FN_IP2_6_5,
5317                 GP_1_4_FN, FN_IP2_4_3,
5318                 GP_1_3_FN, FN_IP2_2_0,
5319                 GP_1_2_FN, FN_IP1_31_29,
5320                 GP_1_1_FN, FN_IP1_28_26,
5321                 GP_1_0_FN, FN_IP1_25_23, }
5322         },
5323         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5324                 GP_2_31_FN, FN_IP6_7_6,
5325                 GP_2_30_FN, FN_IP6_5_3,
5326                 GP_2_29_FN, FN_IP6_2_0,
5327                 GP_2_28_FN, FN_AUDIO_CLKA,
5328                 GP_2_27_FN, FN_IP5_31_29,
5329                 GP_2_26_FN, FN_IP5_28_26,
5330                 GP_2_25_FN, FN_IP5_25_24,
5331                 GP_2_24_FN, FN_IP5_23_22,
5332                 GP_2_23_FN, FN_IP5_21_20,
5333                 GP_2_22_FN, FN_IP5_19_17,
5334                 GP_2_21_FN, FN_IP5_16_15,
5335                 GP_2_20_FN, FN_IP5_14_12,
5336                 GP_2_19_FN, FN_IP5_11_9,
5337                 GP_2_18_FN, FN_IP5_8_6,
5338                 GP_2_17_FN, FN_IP5_5_3,
5339                 GP_2_16_FN, FN_IP5_2_0,
5340                 GP_2_15_FN, FN_IP4_30_28,
5341                 GP_2_14_FN, FN_IP4_27_26,
5342                 GP_2_13_FN, FN_IP4_25_24,
5343                 GP_2_12_FN, FN_IP4_23_22,
5344                 GP_2_11_FN, FN_IP4_21,
5345                 GP_2_10_FN, FN_IP4_20,
5346                 GP_2_9_FN, FN_IP4_19,
5347                 GP_2_8_FN, FN_IP4_18_16,
5348                 GP_2_7_FN, FN_IP4_15_13,
5349                 GP_2_6_FN, FN_IP4_12_10,
5350                 GP_2_5_FN, FN_IP4_9_8,
5351                 GP_2_4_FN, FN_IP4_7_5,
5352                 GP_2_3_FN, FN_IP4_4_2,
5353                 GP_2_2_FN, FN_IP4_1_0,
5354                 GP_2_1_FN, FN_IP3_30_28,
5355                 GP_2_0_FN, FN_IP3_27_25 }
5356         },
5357         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5358                 GP_3_31_FN, FN_IP9_18_17,
5359                 GP_3_30_FN, FN_IP9_16,
5360                 GP_3_29_FN, FN_IP9_15_13,
5361                 GP_3_28_FN, FN_IP9_12,
5362                 GP_3_27_FN, FN_IP9_11,
5363                 GP_3_26_FN, FN_IP9_10_8,
5364                 GP_3_25_FN, FN_IP9_7,
5365                 GP_3_24_FN, FN_IP9_6,
5366                 GP_3_23_FN, FN_IP9_5_3,
5367                 GP_3_22_FN, FN_IP9_2_0,
5368                 GP_3_21_FN, FN_IP8_30_28,
5369                 GP_3_20_FN, FN_IP8_27_26,
5370                 GP_3_19_FN, FN_IP8_25_24,
5371                 GP_3_18_FN, FN_IP8_23_21,
5372                 GP_3_17_FN, FN_IP8_20_18,
5373                 GP_3_16_FN, FN_IP8_17_15,
5374                 GP_3_15_FN, FN_IP8_14_12,
5375                 GP_3_14_FN, FN_IP8_11_9,
5376                 GP_3_13_FN, FN_IP8_8_6,
5377                 GP_3_12_FN, FN_IP8_5_3,
5378                 GP_3_11_FN, FN_IP8_2_0,
5379                 GP_3_10_FN, FN_IP7_29_27,
5380                 GP_3_9_FN, FN_IP7_26_24,
5381                 GP_3_8_FN, FN_IP7_23_21,
5382                 GP_3_7_FN, FN_IP7_20_19,
5383                 GP_3_6_FN, FN_IP7_18_17,
5384                 GP_3_5_FN, FN_IP7_16_15,
5385                 GP_3_4_FN, FN_IP7_14_13,
5386                 GP_3_3_FN, FN_IP7_12_11,
5387                 GP_3_2_FN, FN_IP7_10_9,
5388                 GP_3_1_FN, FN_IP7_8_6,
5389                 GP_3_0_FN, FN_IP7_5_3 }
5390         },
5391         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5392                 GP_4_31_FN, FN_IP15_5_4,
5393                 GP_4_30_FN, FN_IP15_3_2,
5394                 GP_4_29_FN, FN_IP15_1_0,
5395                 GP_4_28_FN, FN_IP11_8_6,
5396                 GP_4_27_FN, FN_IP11_5_3,
5397                 GP_4_26_FN, FN_IP11_2_0,
5398                 GP_4_25_FN, FN_IP10_31_29,
5399                 GP_4_24_FN, FN_IP10_28_27,
5400                 GP_4_23_FN, FN_IP10_26_25,
5401                 GP_4_22_FN, FN_IP10_24_22,
5402                 GP_4_21_FN, FN_IP10_21_19,
5403                 GP_4_20_FN, FN_IP10_18_17,
5404                 GP_4_19_FN, FN_IP10_16_15,
5405                 GP_4_18_FN, FN_IP10_14_12,
5406                 GP_4_17_FN, FN_IP10_11_9,
5407                 GP_4_16_FN, FN_IP10_8_6,
5408                 GP_4_15_FN, FN_IP10_5_3,
5409                 GP_4_14_FN, FN_IP10_2_0,
5410                 GP_4_13_FN, FN_IP9_31_29,
5411                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5412                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5413                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5414                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5415                 GP_4_8_FN, FN_IP9_28_27,
5416                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5417                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5418                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5419                 GP_4_4_FN, FN_IP9_26_25,
5420                 GP_4_3_FN, FN_IP9_24_23,
5421                 GP_4_2_FN, FN_IP9_22_21,
5422                 GP_4_1_FN, FN_IP9_20_19,
5423                 GP_4_0_FN, FN_VI0_CLK }
5424         },
5425         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5426                 GP_5_31_FN, FN_IP3_24_22,
5427                 GP_5_30_FN, FN_IP13_9_7,
5428                 GP_5_29_FN, FN_IP13_6_5,
5429                 GP_5_28_FN, FN_IP13_4_3,
5430                 GP_5_27_FN, FN_IP13_2_0,
5431                 GP_5_26_FN, FN_IP12_29_27,
5432                 GP_5_25_FN, FN_IP12_26_24,
5433                 GP_5_24_FN, FN_IP12_23_22,
5434                 GP_5_23_FN, FN_IP12_21_20,
5435                 GP_5_22_FN, FN_IP12_19_18,
5436                 GP_5_21_FN, FN_IP12_17_16,
5437                 GP_5_20_FN, FN_IP12_15_13,
5438                 GP_5_19_FN, FN_IP12_12_10,
5439                 GP_5_18_FN, FN_IP12_9_7,
5440                 GP_5_17_FN, FN_IP12_6_4,
5441                 GP_5_16_FN, FN_IP12_3_2,
5442                 GP_5_15_FN, FN_IP12_1_0,
5443                 GP_5_14_FN, FN_IP11_31_30,
5444                 GP_5_13_FN, FN_IP11_29_28,
5445                 GP_5_12_FN, FN_IP11_27,
5446                 GP_5_11_FN, FN_IP11_26,
5447                 GP_5_10_FN, FN_IP11_25,
5448                 GP_5_9_FN, FN_IP11_24,
5449                 GP_5_8_FN, FN_IP11_23,
5450                 GP_5_7_FN, FN_IP11_22,
5451                 GP_5_6_FN, FN_IP11_21,
5452                 GP_5_5_FN, FN_IP11_20,
5453                 GP_5_4_FN, FN_IP11_19,
5454                 GP_5_3_FN, FN_IP11_18_17,
5455                 GP_5_2_FN, FN_IP11_16_15,
5456                 GP_5_1_FN, FN_IP11_14_12,
5457                 GP_5_0_FN, FN_IP11_11_9 }
5458         },
5459         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5460                 GP_6_31_FN, FN_DU0_DOTCLKIN,
5461                 GP_6_30_FN, FN_USB1_OVC,
5462                 GP_6_29_FN, FN_IP14_31_29,
5463                 GP_6_28_FN, FN_IP14_28_26,
5464                 GP_6_27_FN, FN_IP14_25_23,
5465                 GP_6_26_FN, FN_IP14_22_20,
5466                 GP_6_25_FN, FN_IP14_19_17,
5467                 GP_6_24_FN, FN_IP14_16_14,
5468                 GP_6_23_FN, FN_IP14_13_11,
5469                 GP_6_22_FN, FN_IP14_10_8,
5470                 GP_6_21_FN, FN_IP14_7,
5471                 GP_6_20_FN, FN_IP14_6,
5472                 GP_6_19_FN, FN_IP14_5,
5473                 GP_6_18_FN, FN_IP14_4,
5474                 GP_6_17_FN, FN_IP14_3,
5475                 GP_6_16_FN, FN_IP14_2,
5476                 GP_6_15_FN, FN_IP14_1_0,
5477                 GP_6_14_FN, FN_IP13_30_28,
5478                 GP_6_13_FN, FN_IP13_27,
5479                 GP_6_12_FN, FN_IP13_26,
5480                 GP_6_11_FN, FN_IP13_25,
5481                 GP_6_10_FN, FN_IP13_24_23,
5482                 GP_6_9_FN, FN_IP13_22,
5483                 GP_6_8_FN, FN_SD1_CLK,
5484                 GP_6_7_FN, FN_IP13_21_19,
5485                 GP_6_6_FN, FN_IP13_18_16,
5486                 GP_6_5_FN, FN_IP13_15,
5487                 GP_6_4_FN, FN_IP13_14,
5488                 GP_6_3_FN, FN_IP13_13,
5489                 GP_6_2_FN, FN_IP13_12,
5490                 GP_6_1_FN, FN_IP13_11,
5491                 GP_6_0_FN, FN_IP13_10 }
5492         },
5493         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5494                 0, 0,
5495                 0, 0,
5496                 0, 0,
5497                 0, 0,
5498                 0, 0,
5499                 0, 0,
5500                 GP_7_25_FN, FN_USB1_PWEN,
5501                 GP_7_24_FN, FN_USB0_OVC,
5502                 GP_7_23_FN, FN_USB0_PWEN,
5503                 GP_7_22_FN, FN_IP15_14_12,
5504                 GP_7_21_FN, FN_IP15_11_9,
5505                 GP_7_20_FN, FN_IP15_8_6,
5506                 GP_7_19_FN, FN_IP7_2_0,
5507                 GP_7_18_FN, FN_IP6_29_27,
5508                 GP_7_17_FN, FN_IP6_26_24,
5509                 GP_7_16_FN, FN_IP6_23_21,
5510                 GP_7_15_FN, FN_IP6_20_19,
5511                 GP_7_14_FN, FN_IP6_18_16,
5512                 GP_7_13_FN, FN_IP6_15_14,
5513                 GP_7_12_FN, FN_IP6_13_12,
5514                 GP_7_11_FN, FN_IP6_11_10,
5515                 GP_7_10_FN, FN_IP6_9_8,
5516                 GP_7_9_FN, FN_IP16_11_10,
5517                 GP_7_8_FN, FN_IP16_9_8,
5518                 GP_7_7_FN, FN_IP16_7_6,
5519                 GP_7_6_FN, FN_IP16_5_3,
5520                 GP_7_5_FN, FN_IP16_2_0,
5521                 GP_7_4_FN, FN_IP15_29_27,
5522                 GP_7_3_FN, FN_IP15_26_24,
5523                 GP_7_2_FN, FN_IP15_23_21,
5524                 GP_7_1_FN, FN_IP15_20_18,
5525                 GP_7_0_FN, FN_IP15_17_15 }
5526         },
5527         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5528                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5529                              1, 1, 1, 1, 1, 1, 1, 1) {
5530                 /* IP0_31 [1] */
5531                 0, 0,
5532                 /* IP0_30_29 [2] */
5533                 FN_A6, FN_MSIOF1_SCK,
5534                 0, 0,
5535                 /* IP0_28_27 [2] */
5536                 FN_A5, FN_MSIOF0_RXD_B,
5537                 0, 0,
5538                 /* IP0_26_25 [2] */
5539                 FN_A4, FN_MSIOF0_TXD_B,
5540                 0, 0,
5541                 /* IP0_24_23 [2] */
5542                 FN_A3, FN_MSIOF0_SS2_B,
5543                 0, 0,
5544                 /* IP0_22_21 [2] */
5545                 FN_A2, FN_MSIOF0_SS1_B,
5546                 0, 0,
5547                 /* IP0_20_19 [2] */
5548                 FN_A1, FN_MSIOF0_SYNC_B,
5549                 0, 0,
5550                 /* IP0_18_16 [3] */
5551                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
5552                 0, 0, 0,
5553                 /* IP0_15 [1] */
5554                 FN_D15, 0,
5555                 /* IP0_14 [1] */
5556                 FN_D14, 0,
5557                 /* IP0_13 [1] */
5558                 FN_D13, 0,
5559                 /* IP0_12 [1] */
5560                 FN_D12, 0,
5561                 /* IP0_11 [1] */
5562                 FN_D11, 0,
5563                 /* IP0_10 [1] */
5564                 FN_D10, 0,
5565                 /* IP0_9 [1] */
5566                 FN_D9, 0,
5567                 /* IP0_8 [1] */
5568                 FN_D8, 0,
5569                 /* IP0_7 [1] */
5570                 FN_D7, 0,
5571                 /* IP0_6 [1] */
5572                 FN_D6, 0,
5573                 /* IP0_5 [1] */
5574                 FN_D5, 0,
5575                 /* IP0_4 [1] */
5576                 FN_D4, 0,
5577                 /* IP0_3 [1] */
5578                 FN_D3, 0,
5579                 /* IP0_2 [1] */
5580                 FN_D2, 0,
5581                 /* IP0_1 [1] */
5582                 FN_D1, 0,
5583                 /* IP0_0 [1] */
5584                 FN_D0, 0, }
5585         },
5586         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5587                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5588                 /* IP1_31_29 [3] */
5589                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5590                 0, 0, 0,
5591                 /* IP1_28_26 [3] */
5592                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
5593                 0, 0, 0, 0,
5594                 /* IP1_25_23 [3] */
5595                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5596                 0, 0, 0,
5597                 /* IP1_22_20 [3] */
5598                 FN_A15, FN_BPFCLK_C,
5599                 0, 0, 0, 0, 0, 0,
5600                 /* IP1_19_17 [3] */
5601                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5602                 0, 0, 0,
5603                 /* IP1_16_14 [3] */
5604                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5605                 0, 0, 0, 0,
5606                 /* IP1_13_11 [3] */
5607                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
5608                 0, 0, 0, 0,
5609                 /* IP1_10_8 [3] */
5610                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
5611                 0, 0, 0, 0,
5612                 /* IP1_7_6 [2] */
5613                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5614                 /* IP1_5_4 [2] */
5615                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
5616                 /* IP1_3_2 [2] */
5617                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
5618                 /* IP1_1_0 [2] */
5619                 FN_A7, FN_MSIOF1_SYNC,
5620                 0, 0, }
5621         },
5622         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5623                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5624                 /* IP2_31_20 [2] */
5625                 0, 0, 0, 0,
5626                 /* IP2_29_27 [3] */
5627                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5628                 FN_ATAG0_N, 0, FN_EX_WAIT1,
5629                 0, 0,
5630                 /* IP2_26_25 [2] */
5631                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5632                 /* IP2_24_23 [2] */
5633                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5634                 /* IP2_22_21 [2] */
5635                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
5636                 /* IP2_20_19 [2] */
5637                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
5638                 /* IP2_18_16 [3] */
5639                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5640                 0, 0,
5641                 /* IP2_15_13 [3] */
5642                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5643                 0, 0, 0,
5644                 /* IP2_12_0 [3] */
5645                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5646                 0, 0, 0,
5647                 /* IP2_9_7 [3] */
5648                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5649                 0, 0, 0,
5650                 /* IP2_6_5 [2] */
5651                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5652                 /* IP2_4_3 [2] */
5653                 FN_A20, FN_SPCLK, 0, 0,
5654                 /* IP2_2_0 [3] */
5655                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5656                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5657         },
5658         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5659                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5660                 /* IP3_31 [1] */
5661                 0, 0,
5662                 /* IP3_30_28 [3] */
5663                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5664                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5665                 0, 0, 0,
5666                 /* IP3_27_25 [3] */
5667                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5668                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5669                 0, 0, 0,
5670                 /* IP3_24_22 [3] */
5671                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5672                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5673                 /* IP3_21_20 [2] */
5674                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5675                 /* IP3_19_18 [2] */
5676                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5677                 /* IP3_17_16 [2] */
5678                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5679                 /* IP3_15_14 [2] */
5680                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5681                 /* IP3_13_12 [2] */
5682                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5683                 /* IP3_11_9 [3] */
5684                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5685                 0, 0, 0,
5686                 /* IP3_8_6 [3] */
5687                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5688                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5689                 /* IP3_5_3 [3] */
5690                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5691                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5692                 /* IP3_2_0 [3] */
5693                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5694                 0, 0, 0, }
5695         },
5696         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5697                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5698                 /* IP4_31 [1] */
5699                 0, 0,
5700                 /* IP4_30_28 [3] */
5701                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5702                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5703                 0, 0,
5704                 /* IP4_27_26 [2] */
5705                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5706                 /* IP4_25_24 [2] */
5707                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5708                 /* IP4_23_22 [2] */
5709                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5710                 /* IP4_21 [1] */
5711                 FN_SSI_SDATA3, 0,
5712                 /* IP4_20 [1] */
5713                 FN_SSI_WS34, 0,
5714                 /* IP4_19 [1] */
5715                 FN_SSI_SCK34, 0,
5716                 /* IP4_18_16 [3] */
5717                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5718                 0, 0, 0, 0,
5719                 /* IP4_15_13 [3] */
5720                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
5721                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5722                 0, 0,
5723                 /* IP4_12_10 [3] */
5724                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5725                 0, 0, 0,
5726                 /* IP4_9_8 [2] */
5727                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
5728                 /* IP4_7_5 [3] */
5729                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
5730                 0, 0, 0,
5731                 /* IP4_4_2 [3] */
5732                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
5733                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5734                 0, 0, 0,
5735                 /* IP4_1_0 [2] */
5736                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
5737         },
5738         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5739                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5740                 /* IP5_31_29 [3] */
5741                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5742                 0, 0, 0, 0, 0,
5743                 /* IP5_28_26 [3] */
5744                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5745                 0, 0, 0, 0,
5746                 /* IP5_25_24 [2] */
5747                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5748                 /* IP5_23_22 [2] */
5749                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5750                 /* IP5_21_20 [2] */
5751                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5752                 /* IP5_19_17 [3] */
5753                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5754                 0, 0, 0, 0,
5755                 /* IP5_16_15 [2] */
5756                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5757                 /* IP5_14_12 [3] */
5758                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5759                 0, 0, 0, 0,
5760                 /* IP5_11_9 [3] */
5761                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5762                 0, 0, 0, 0,
5763                 /* IP5_8_6 [3] */
5764                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5765                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5766                 0, 0,
5767                 /* IP5_5_3 [3] */
5768                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5769                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5770                 0, 0,
5771                 /* IP5_2_0 [3] */
5772                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5773                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5774                 0, 0, }
5775         },
5776         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5777                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5778                 /* IP6_31_30 [2] */
5779                 0, 0, 0, 0,
5780                 /* IP6_29_27 [3] */
5781                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5782                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5783                 0, 0, 0,
5784                 /* IP6_26_24 [3] */
5785                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5786                 FN_GPS_CLK_C, FN_GPS_CLK_D,
5787                 0, 0, 0,
5788                 /* IP6_23_21 [3] */
5789                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5790                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
5791                 0, 0, 0,
5792                 /* IP6_20_19 [2] */
5793                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
5794                 /* IP6_18_16 [3] */
5795                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
5796                 0, 0, 0,
5797                 /* IP6_15_14 [2] */
5798                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5799                 /* IP6_13_12 [2] */
5800                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5801                 /* IP6_11_10 [2] */
5802                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5803                 /* IP6_9_8 [2] */
5804                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5805                 /* IP6_7_6 [2] */
5806                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5807                 /* IP6_5_3 [3] */
5808                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5809                 FN_SCIFA2_RXD, FN_FMIN_E,
5810                 0, 0,
5811                 /* IP6_2_0 [3] */
5812                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5813                 FN_SCIF_CLK, 0, FN_BPFCLK_E,
5814                 0, 0, }
5815         },
5816         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5817                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5818                 /* IP7_31_30 [2] */
5819                 0, 0, 0, 0,
5820                 /* IP7_29_27 [3] */
5821                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5822                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5823                 0, 0,
5824                 /* IP7_26_24 [3] */
5825                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5826                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5827                 0, 0,
5828                 /* IP7_23_21 [3] */
5829                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5830                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5831                 0, 0,
5832                 /* IP7_20_19 [2] */
5833                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5834                 /* IP7_18_17 [2] */
5835                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5836                 /* IP7_16_15 [2] */
5837                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5838                 /* IP7_14_13 [2] */
5839                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5840                 /* IP7_12_11 [2] */
5841                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5842                 /* IP7_10_9 [2] */
5843                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5844                 /* IP7_8_6 [3] */
5845                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5846                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5847                 0, 0,
5848                 /* IP7_5_3 [3] */
5849                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5850                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5851                 0, 0,
5852                 /* IP7_2_0 [3] */
5853                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5854                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5855                 0, 0, }
5856         },
5857         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5858                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5859                 /* IP8_31 [1] */
5860                 0, 0,
5861                 /* IP8_30_28 [3] */
5862                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5863                 0, 0, 0,
5864                 /* IP8_27_26 [2] */
5865                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5866                 /* IP8_25_24 [2] */
5867                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5868                 /* IP8_23_21 [3] */
5869                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5870                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5871                 0, 0,
5872                 /* IP8_20_18 [3] */
5873                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5874                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
5875                 0, 0,
5876                 /* IP8_17_15 [3] */
5877                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
5878                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
5879                 0, 0,
5880                 /* IP8_14_12 [3] */
5881                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
5882                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
5883                 0, 0, 0,
5884                 /* IP8_11_9 [3] */
5885                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
5886                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
5887                 0, 0, 0,
5888                 /* IP8_8_6 [3] */
5889                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
5890                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
5891                 0, 0,
5892                 /* IP8_5_3 [3] */
5893                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
5894                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
5895                 0, 0,
5896                 /* IP8_2_0 [3] */
5897                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
5898                 0, 0, 0, }
5899         },
5900         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5901                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
5902                 /* IP9_31_29 [3] */
5903                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
5904                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
5905                 /* IP9_28_27 [2] */
5906                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
5907                 /* IP9_26_25 [2] */
5908                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
5909                 /* IP9_24_23 [2] */
5910                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
5911                 /* IP9_22_21 [2] */
5912                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
5913                 /* IP9_20_19 [2] */
5914                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
5915                 /* IP9_18_17 [2] */
5916                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
5917                 /* IP9_16 [1] */
5918                 FN_DU1_DISP, FN_QPOLA,
5919                 /* IP9_15_13 [3] */
5920                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
5921                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
5922                 0, 0, 0,
5923                 /* IP9_12 [1] */
5924                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
5925                 /* IP9_11 [1] */
5926                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
5927                 /* IP9_10_8 [3] */
5928                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
5929                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
5930                 0, 0,
5931                 /* IP9_7 [1] */
5932                 FN_DU1_DOTCLKOUT0, FN_QCLK,
5933                 /* IP9_6 [1] */
5934                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
5935                 /* IP9_5_3 [3] */
5936                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
5937                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
5938                 0, 0, 0,
5939                 /* IP9_2_0 [3] */
5940                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
5941                 0, 0, 0, }
5942         },
5943         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5944                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
5945                 /* IP10_31_29 [3] */
5946                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
5947                 0, 0, 0,
5948                 /* IP10_28_27 [2] */
5949                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
5950                 /* IP10_26_25 [2] */
5951                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
5952                 /* IP10_24_22 [3] */
5953                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
5954                 0, 0, 0,
5955                 /* IP10_21_29 [3] */
5956                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
5957                 FN_TS_SDATA0_C, FN_ATACS11_N,
5958                 0, 0, 0,
5959                 /* IP10_18_17 [2] */
5960                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
5961                 /* IP10_16_15 [2] */
5962                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
5963                 /* IP10_14_12 [3] */
5964                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
5965                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
5966                 /* IP10_11_9 [3] */
5967                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
5968                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
5969                 0, 0,
5970                 /* IP10_8_6 [3] */
5971                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
5972                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
5973                 /* IP10_5_3 [3] */
5974                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
5975                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
5976                 /* IP10_2_0 [3] */
5977                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
5978                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
5979         },
5980         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5981                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5982                              3, 3, 3, 3, 3) {
5983                 /* IP11_31_30 [2] */
5984                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
5985                 /* IP11_29_28 [2] */
5986                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
5987                 /* IP11_27 [1] */
5988                 FN_VI1_DATA7, FN_AVB_MDC,
5989                 /* IP11_26 [1] */
5990                 FN_VI1_DATA6, FN_AVB_MAGIC,
5991                 /* IP11_25 [1] */
5992                 FN_VI1_DATA5, FN_AVB_RX_DV,
5993                 /* IP11_24 [1] */
5994                 FN_VI1_DATA4, FN_AVB_MDIO,
5995                 /* IP11_23 [1] */
5996                 FN_VI1_DATA3, FN_AVB_RX_ER,
5997                 /* IP11_22 [1] */
5998                 FN_VI1_DATA2, FN_AVB_RXD7,
5999                 /* IP11_21 [1] */
6000                 FN_VI1_DATA1, FN_AVB_RXD6,
6001                 /* IP11_20 [1] */
6002                 FN_VI1_DATA0, FN_AVB_RXD5,
6003                 /* IP11_19 [1] */
6004                 FN_VI1_CLK, FN_AVB_RXD4,
6005                 /* IP11_18_17 [2] */
6006                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6007                 /* IP11_16_15 [2] */
6008                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6009                 /* IP11_14_12 [3] */
6010                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6011                 FN_RX4_B, FN_SCIFA4_RXD_B,
6012                 0, 0, 0,
6013                 /* IP11_11_9 [3] */
6014                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6015                 FN_TX4_B, FN_SCIFA4_TXD_B,
6016                 0, 0, 0,
6017                 /* IP11_8_6 [3] */
6018                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6019                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6020                 /* IP11_5_3 [3] */
6021                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
6022                 0, 0, 0,
6023                 /* IP11_2_0 [3] */
6024                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
6025                 0, 0, 0, }
6026         },
6027         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6028                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6029                 /* IP12_31_30 [2] */
6030                 0, 0, 0, 0,
6031                 /* IP12_29_27 [3] */
6032                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6033                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6034                 0, 0, 0,
6035                 /* IP12_26_24 [3] */
6036                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6037                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6038                 0, 0, 0,
6039                 /* IP12_23_22 [2] */
6040                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6041                 /* IP12_21_20 [2] */
6042                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6043                 /* IP12_19_18 [2] */
6044                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6045                 /* IP12_17_16 [2] */
6046                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6047                 /* IP12_15_13 [3] */
6048                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6049                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6050                 0, 0, 0,
6051                 /* IP12_12_10 [3] */
6052                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6053                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6054                 0, 0, 0,
6055                 /* IP12_9_7 [3] */
6056                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6057                 FN_SDA2_D, FN_MSIOF1_SCK_E,
6058                 0, 0, 0,
6059                 /* IP12_6_4 [3] */
6060                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6061                 FN_SCL2_D, FN_MSIOF1_RXD_E,
6062                 0, 0, 0,
6063                 /* IP12_3_2 [2] */
6064                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
6065                 /* IP12_1_0 [2] */
6066                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
6067         },
6068         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6069                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6070                              3, 2, 2, 3) {
6071                 /* IP13_31 [1] */
6072                 0, 0,
6073                 /* IP13_30_28 [3] */
6074                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
6075                 0, 0, 0, 0,
6076                 /* IP13_27 [1] */
6077                 FN_SD1_DATA3, FN_IERX_B,
6078                 /* IP13_26 [1] */
6079                 FN_SD1_DATA2, FN_IECLK_B,
6080                 /* IP13_25 [1] */
6081                 FN_SD1_DATA1, FN_IETX_B,
6082                 /* IP13_24_23 [2] */
6083                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6084                 /* IP13_22 [1] */
6085                 FN_SD1_CMD, FN_REMOCON_B,
6086                 /* IP13_21_19 [3] */
6087                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6088                 FN_SCIFA5_RXD_B, FN_RX3_C,
6089                 0, 0,
6090                 /* IP13_18_16 [3] */
6091                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6092                 FN_SCIFA5_TXD_B, FN_TX3_C,
6093                 0, 0,
6094                 /* IP13_15 [1] */
6095                 FN_SD0_DATA3, FN_SSL_B,
6096                 /* IP13_14 [1] */
6097                 FN_SD0_DATA2, FN_IO3_B,
6098                 /* IP13_13 [1] */
6099                 FN_SD0_DATA1, FN_IO2_B,
6100                 /* IP13_12 [1] */
6101                 FN_SD0_DATA0, FN_MISO_IO1_B,
6102                 /* IP13_11 [1] */
6103                 FN_SD0_CMD, FN_MOSI_IO0_B,
6104                 /* IP13_10 [1] */
6105                 FN_SD0_CLK, FN_SPCLK_B,
6106                 /* IP13_9_7 [3] */
6107                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6108                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6109                 0, 0, 0,
6110                 /* IP13_6_5 [2] */
6111                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6112                 /* IP13_4_3 [2] */
6113                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6114                 /* IP13_2_0 [3] */
6115                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6116                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6117                 0, 0, 0, }
6118         },
6119         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6120                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6121                 /* IP14_31_29 [3] */
6122                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6123                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
6124                 /* IP14_28_26 [3] */
6125                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6126                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
6127                 /* IP14_25_23 [3] */
6128                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6129                 0, 0, 0,
6130                 /* IP14_22_20 [3] */
6131                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6132                 0, 0, 0,
6133                 /* IP14_19_17 [3] */
6134                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6135                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6136                 0, 0,
6137                 /* IP14_16_14 [3] */
6138                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6139                 FN_VI1_CLK_C, FN_VI1_G0_B,
6140                 0, 0,
6141                 /* IP14_13_11 [3] */
6142                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6143                 0, 0, 0,
6144                 /* IP14_10_8 [3] */
6145                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6146                 0, 0, 0,
6147                 /* IP14_7 [1] */
6148                 FN_SD2_DATA3, FN_MMC_D3,
6149                 /* IP14_6 [1] */
6150                 FN_SD2_DATA2, FN_MMC_D2,
6151                 /* IP14_5 [1] */
6152                 FN_SD2_DATA1, FN_MMC_D1,
6153                 /* IP14_4 [1] */
6154                 FN_SD2_DATA0, FN_MMC_D0,
6155                 /* IP14_3 [1] */
6156                 FN_SD2_CMD, FN_MMC_CMD,
6157                 /* IP14_2 [1] */
6158                 FN_SD2_CLK, FN_MMC_CLK,
6159                 /* IP14_1_0 [2] */
6160                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
6161         },
6162         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6163                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6164                 /* IP15_31_30 [2] */
6165                 0, 0, 0, 0,
6166                 /* IP15_29_27 [3] */
6167                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6168                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6169                 0, 0,
6170                 /* IP15_26_24 [3] */
6171                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6172                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6173                 0, 0,
6174                 /* IP15_23_21 [3] */
6175                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6176                 FN_TCLK2, FN_VI1_DATA3_C, 0,
6177                 /* IP15_20_18 [3] */
6178                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6179                 0, 0, 0,
6180                 /* IP15_17_15 [3] */
6181                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6182                 FN_TCLK1, FN_VI1_DATA1_C,
6183                 0, 0,
6184                 /* IP15_14_12 [3] */
6185                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6186                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6187                 0, 0,
6188                 /* IP15_11_9 [3] */
6189                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6190                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6191                 0, 0,
6192                 /* IP15_8_6 [3] */
6193                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6194                 FN_PWM5_B, FN_SCIFA3_TXD_C,
6195                 0, 0, 0,
6196                 /* IP15_5_4 [2] */
6197                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6198                 /* IP15_3_2 [2] */
6199                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6200                 /* IP15_1_0 [2] */
6201                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6202         },
6203         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6204                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6205                 /* IP16_31_28 [4] */
6206                 0, 0, 0, 0, 0, 0, 0, 0,
6207                 0, 0, 0, 0, 0, 0, 0, 0,
6208                 /* IP16_27_24 [4] */
6209                 0, 0, 0, 0, 0, 0, 0, 0,
6210                 0, 0, 0, 0, 0, 0, 0, 0,
6211                 /* IP16_23_20 [4] */
6212                 0, 0, 0, 0, 0, 0, 0, 0,
6213                 0, 0, 0, 0, 0, 0, 0, 0,
6214                 /* IP16_19_16 [4] */
6215                 0, 0, 0, 0, 0, 0, 0, 0,
6216                 0, 0, 0, 0, 0, 0, 0, 0,
6217                 /* IP16_15_12 [4] */
6218                 0, 0, 0, 0, 0, 0, 0, 0,
6219                 0, 0, 0, 0, 0, 0, 0, 0,
6220                 /* IP16_11_10 [2] */
6221                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6222                 /* IP16_9_8 [2] */
6223                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6224                 /* IP16_7_6 [2] */
6225                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6226                 /* IP16_5_3 [3] */
6227                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6228                 FN_GLO_SS_C, FN_VI1_DATA7_C,
6229                 0, 0, 0,
6230                 /* IP16_2_0 [3] */
6231                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6232                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6233                 0, 0, 0, }
6234         },
6235         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6236                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6237                              3, 2, 2, 2, 1, 2, 2, 2) {
6238                 /* RESERVED [1] */
6239                 0, 0,
6240                 /* SEL_SCIF1 [2] */
6241                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6242                 /* SEL_SCIFB [2] */
6243                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6244                 /* SEL_SCIFB2 [2] */
6245                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6246                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6247                 /* SEL_SCIFB1 [3] */
6248                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6249                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6250                 0, 0, 0, 0,
6251                 /* SEL_SCIFA1 [2] */
6252                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6253                 /* SEL_SSI9 [1] */
6254                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6255                 /* SEL_SCFA [1] */
6256                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6257                 /* SEL_QSP [1] */
6258                 FN_SEL_QSP_0, FN_SEL_QSP_1,
6259                 /* SEL_SSI7 [1] */
6260                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6261                 /* SEL_HSCIF1 [3] */
6262                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6263                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6264                 0, 0, 0,
6265                 /* RESERVED [2] */
6266                 0, 0, 0, 0,
6267                 /* SEL_VI1 [2] */
6268                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6269                 /* RESERVED [2] */
6270                 0, 0, 0, 0,
6271                 /* SEL_TMU [1] */
6272                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6273                 /* SEL_LBS [2] */
6274                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6275                 /* SEL_TSIF0 [2] */
6276                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6277                 /* SEL_SOF0 [2] */
6278                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6279         },
6280         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6281                              3, 1, 1, 3, 2, 1, 1, 2, 2,
6282                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6283                 /* SEL_SCIF0 [3] */
6284                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6285                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6286                 0, 0, 0,
6287                 /* RESERVED [1] */
6288                 0, 0,
6289                 /* SEL_SCIF [1] */
6290                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6291                 /* SEL_CAN0 [3] */
6292                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6293                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6294                 0, 0,
6295                 /* SEL_CAN1 [2] */
6296                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6297                 /* RESERVED [1] */
6298                 0, 0,
6299                 /* SEL_SCIFA2 [1] */
6300                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6301                 /* SEL_SCIF4 [2] */
6302                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6303                 /* RESERVED [2] */
6304                 0, 0, 0, 0,
6305                 /* SEL_ADG [1] */
6306                 FN_SEL_ADG_0, FN_SEL_ADG_1,
6307                 /* SEL_FM [3] */
6308                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6309                 FN_SEL_FM_3, FN_SEL_FM_4,
6310                 0, 0, 0,
6311                 /* SEL_SCIFA5 [2] */
6312                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6313                 /* RESERVED [1] */
6314                 0, 0,
6315                 /* SEL_GPS [2] */
6316                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6317                 /* SEL_SCIFA4 [2] */
6318                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6319                 /* SEL_SCIFA3 [2] */
6320                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6321                 /* SEL_SIM [1] */
6322                 FN_SEL_SIM_0, FN_SEL_SIM_1,
6323                 /* RESERVED [1] */
6324                 0, 0,
6325                 /* SEL_SSI8 [1] */
6326                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6327         },
6328         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6329                              2, 2, 2, 2, 2, 2, 2, 2,
6330                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
6331                 /* SEL_HSCIF2 [2] */
6332                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6333                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6334                 /* SEL_CANCLK [2] */
6335                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6336                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6337                 /* SEL_IIC8 [2] */
6338                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
6339                 /* SEL_IIC7 [2] */
6340                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
6341                 /* SEL_IIC4 [2] */
6342                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
6343                 /* SEL_IIC3 [2] */
6344                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
6345                 /* SEL_SCIF3 [2] */
6346                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6347                 /* SEL_IEB [2] */
6348                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6349                 /* SEL_MMC [1] */
6350                 FN_SEL_MMC_0, FN_SEL_MMC_1,
6351                 /* SEL_SCIF5 [1] */
6352                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6353                 /* RESERVED [2] */
6354                 0, 0, 0, 0,
6355                 /* SEL_IIC2 [2] */
6356                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
6357                 /* SEL_IIC1 [3] */
6358                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
6359                 FN_SEL_IIC1_4,
6360                 0, 0, 0,
6361                 /* SEL_IIC0 [2] */
6362                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6363                 /* RESERVED [2] */
6364                 0, 0, 0, 0,
6365                 /* RESERVED [2] */
6366                 0, 0, 0, 0,
6367                 /* RESERVED [1] */
6368                 0, 0, }
6369         },
6370         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6371                              3, 2, 2, 1, 1, 1, 1, 3, 2,
6372                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
6373                 /* SEL_SOF1 [3] */
6374                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6375                 FN_SEL_SOF1_4,
6376                 0, 0, 0,
6377                 /* SEL_HSCIF0 [2] */
6378                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6379                 /* SEL_DIS [2] */
6380                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6381                 /* RESERVED [1] */
6382                 0, 0,
6383                 /* SEL_RAD [1] */
6384                 FN_SEL_RAD_0, FN_SEL_RAD_1,
6385                 /* SEL_RCN [1] */
6386                 FN_SEL_RCN_0, FN_SEL_RCN_1,
6387                 /* SEL_RSP [1] */
6388                 FN_SEL_RSP_0, FN_SEL_RSP_1,
6389                 /* SEL_SCIF2 [3] */
6390                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6391                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6392                 0, 0, 0,
6393                 /* RESERVED [2] */
6394                 0, 0, 0, 0,
6395                 /* RESERVED [2] */
6396                 0, 0, 0, 0,
6397                 /* SEL_SOF2 [3] */
6398                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6399                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6400                 0, 0, 0,
6401                 /* RESERVED [1] */
6402                 0, 0,
6403                 /* SEL_SSI1 [1] */
6404                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6405                 /* SEL_SSI0 [1] */
6406                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6407                 /* SEL_SSP [2] */
6408                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6409                 /* RESERVED [2] */
6410                 0, 0, 0, 0,
6411                 /* RESERVED [2] */
6412                 0, 0, 0, 0,
6413                 /* RESERVED [2] */
6414                 0, 0, 0, 0, }
6415         },
6416         { },
6417 };
6418
6419 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6420 {
6421         if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6422                 return -EINVAL;
6423
6424         *pocctrl = 0xe606008c;
6425
6426         return 31 - (pin & 0x1f);
6427 }
6428
6429 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6430         .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6431 };
6432
6433 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6434 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6435         .name = "r8a77910_pfc",
6436         .ops = &r8a7791_pinmux_ops,
6437         .unlock_reg = 0xe6060000, /* PMMR */
6438
6439         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6440
6441         .pins = pinmux_pins,
6442         .nr_pins = ARRAY_SIZE(pinmux_pins),
6443         .groups = pinmux_groups,
6444         .nr_groups = ARRAY_SIZE(pinmux_groups),
6445         .functions = pinmux_functions,
6446         .nr_functions = ARRAY_SIZE(pinmux_functions),
6447
6448         .cfg_regs = pinmux_config_regs,
6449
6450         .pinmux_data = pinmux_data,
6451         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6452 };
6453 #endif
6454
6455 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6456 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6457         .name = "r8a77930_pfc",
6458         .unlock_reg = 0xe6060000, /* PMMR */
6459
6460         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6461
6462         .pins = pinmux_pins,
6463         .nr_pins = ARRAY_SIZE(pinmux_pins),
6464         .groups = pinmux_groups,
6465         .nr_groups = ARRAY_SIZE(pinmux_groups),
6466         .functions = pinmux_functions,
6467         .nr_functions = ARRAY_SIZE(pinmux_functions),
6468
6469         .cfg_regs = pinmux_config_regs,
6470
6471         .pinmux_data = pinmux_data,
6472         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6473 };
6474 #endif