2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
4 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
6 * VME support added by Sam Creasey
8 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
10 * Adapted from mac_scsinew.c:
13 * Generic Macintosh NCR5380 driver
15 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
17 * derived in part from:
20 * Generic Generic NCR5380 driver
22 * Copyright 1995, Russell King
25 #include <linux/types.h>
26 #include <linux/delay.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/platform_device.h>
36 #include <scsi/scsi_host.h>
37 #include "sun3_scsi.h"
39 /* minimum number of bytes to do dma on */
40 #define DMA_MIN_SIZE 129
42 /* Definitions for the core NCR5380 driver. */
44 #define NCR5380_implementation_fields /* none */
46 #define NCR5380_read(reg) in_8(hostdata->io + (reg))
47 #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
49 #define NCR5380_queue_command sun3scsi_queue_command
50 #define NCR5380_bus_reset sun3scsi_bus_reset
51 #define NCR5380_abort sun3scsi_abort
52 #define NCR5380_info sun3scsi_info
54 #define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
55 #define NCR5380_dma_recv_setup sun3scsi_dma_count
56 #define NCR5380_dma_send_setup sun3scsi_dma_count
57 #define NCR5380_dma_residual sun3scsi_dma_residual
59 #define NCR5380_acquire_dma_irq(instance) (1)
60 #define NCR5380_release_dma_irq(instance)
65 extern int sun3_map_test(unsigned long, char *);
67 static int setup_can_queue
= -1;
68 module_param(setup_can_queue
, int, 0);
69 static int setup_cmd_per_lun
= -1;
70 module_param(setup_cmd_per_lun
, int, 0);
71 static int setup_sg_tablesize
= -1;
72 module_param(setup_sg_tablesize
, int, 0);
73 static int setup_hostid
= -1;
74 module_param(setup_hostid
, int, 0);
76 /* ms to wait after hitting dma regs */
77 #define SUN3_DMA_DELAY 10
79 /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
80 #define SUN3_DVMA_BUFSIZE 0xe000
82 static struct scsi_cmnd
*sun3_dma_setup_done
;
83 static volatile struct sun3_dma_regs
*dregs
;
84 static struct sun3_udc_regs
*udc_regs
;
85 static unsigned char *sun3_dma_orig_addr
;
86 static unsigned long sun3_dma_orig_count
;
87 static int sun3_dma_active
;
88 static unsigned long last_residual
;
91 /* dma controller register access functions */
93 static inline unsigned short sun3_udc_read(unsigned char reg
)
97 dregs
->udc_addr
= UDC_CSR
;
98 udelay(SUN3_DMA_DELAY
);
99 ret
= dregs
->udc_data
;
100 udelay(SUN3_DMA_DELAY
);
105 static inline void sun3_udc_write(unsigned short val
, unsigned char reg
)
107 dregs
->udc_addr
= reg
;
108 udelay(SUN3_DMA_DELAY
);
109 dregs
->udc_data
= val
;
110 udelay(SUN3_DMA_DELAY
);
114 // safe bits for the CSR
115 #define CSR_GOOD 0x060f
117 static irqreturn_t
scsi_sun3_intr(int irq
, void *dev
)
119 struct Scsi_Host
*instance
= dev
;
120 unsigned short csr
= dregs
->csr
;
124 dregs
->csr
&= ~CSR_DMA_ENABLE
;
127 if(csr
& ~CSR_GOOD
) {
128 if (csr
& CSR_DMA_BUSERR
)
129 shost_printk(KERN_ERR
, instance
, "bus error in DMA\n");
130 if (csr
& CSR_DMA_CONFLICT
)
131 shost_printk(KERN_ERR
, instance
, "DMA conflict\n");
135 if(csr
& (CSR_SDB_INT
| CSR_DMA_INT
)) {
136 NCR5380_intr(irq
, dev
);
140 return IRQ_RETVAL(handled
);
143 /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
144 static int sun3scsi_dma_setup(struct NCR5380_hostdata
*hostdata
,
145 unsigned char *data
, int count
, int write_flag
)
149 if(sun3_dma_orig_addr
!= NULL
)
150 dvma_unmap(sun3_dma_orig_addr
);
153 addr
= (void *)dvma_map_vme((unsigned long) data
, count
);
155 addr
= (void *)dvma_map((unsigned long) data
, count
);
158 sun3_dma_orig_addr
= addr
;
159 sun3_dma_orig_count
= count
;
161 #ifndef SUN3_SCSI_VME
162 dregs
->fifo_count
= 0;
163 sun3_udc_write(UDC_RESET
, UDC_CSR
);
166 dregs
->csr
&= ~CSR_FIFO
;
167 dregs
->csr
|= CSR_FIFO
;
172 dregs
->csr
|= CSR_SEND
;
174 dregs
->csr
&= ~CSR_SEND
;
177 dregs
->csr
|= CSR_PACK_ENABLE
;
179 dregs
->dma_addr_hi
= ((unsigned long)addr
>> 16);
180 dregs
->dma_addr_lo
= ((unsigned long)addr
& 0xffff);
182 dregs
->dma_count_hi
= 0;
183 dregs
->dma_count_lo
= 0;
184 dregs
->fifo_count_hi
= 0;
185 dregs
->fifo_count
= 0;
187 /* byte count for fifo */
188 dregs
->fifo_count
= count
;
190 sun3_udc_write(UDC_RESET
, UDC_CSR
);
193 dregs
->csr
&= ~CSR_FIFO
;
194 dregs
->csr
|= CSR_FIFO
;
196 if(dregs
->fifo_count
!= count
) {
197 shost_printk(KERN_ERR
, hostdata
->host
,
198 "FIFO mismatch %04x not %04x\n",
199 dregs
->fifo_count
, (unsigned int) count
);
200 NCR5380_dprint(NDEBUG_DMA
, hostdata
->host
);
204 udc_regs
->addr_hi
= (((unsigned long)(addr
) & 0xff0000) >> 8);
205 udc_regs
->addr_lo
= ((unsigned long)(addr
) & 0xffff);
206 udc_regs
->count
= count
/2; /* count in words */
207 udc_regs
->mode_hi
= UDC_MODE_HIWORD
;
211 udc_regs
->mode_lo
= UDC_MODE_LSEND
;
212 udc_regs
->rsel
= UDC_RSEL_SEND
;
214 udc_regs
->mode_lo
= UDC_MODE_LRECV
;
215 udc_regs
->rsel
= UDC_RSEL_RECV
;
218 /* announce location of regs block */
219 sun3_udc_write(((dvma_vtob(udc_regs
) & 0xff0000) >> 8),
222 sun3_udc_write((dvma_vtob(udc_regs
) & 0xffff), UDC_CHN_LO
);
224 /* set dma master on */
225 sun3_udc_write(0xd, UDC_MODE
);
227 /* interrupt enable */
228 sun3_udc_write(UDC_INT_ENABLE
, UDC_CSR
);
235 static int sun3scsi_dma_count(struct NCR5380_hostdata
*hostdata
,
236 unsigned char *data
, int count
)
241 static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata
*hostdata
,
242 unsigned char *data
, int count
)
244 return sun3scsi_dma_setup(hostdata
, data
, count
, 0);
247 static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata
*hostdata
,
248 unsigned char *data
, int count
)
250 return sun3scsi_dma_setup(hostdata
, data
, count
, 1);
253 static int sun3scsi_dma_residual(struct NCR5380_hostdata
*hostdata
)
255 return last_residual
;
258 static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata
*hostdata
,
259 struct scsi_cmnd
*cmd
)
261 int wanted_len
= cmd
->SCp
.this_residual
;
263 if (wanted_len
< DMA_MIN_SIZE
|| cmd
->request
->cmd_type
!= REQ_TYPE_FS
)
269 static inline int sun3scsi_dma_start(unsigned long count
, unsigned char *data
)
276 dregs
->dma_count_hi
= (sun3_dma_orig_count
>> 16);
277 dregs
->dma_count_lo
= (sun3_dma_orig_count
& 0xffff);
279 dregs
->fifo_count_hi
= (sun3_dma_orig_count
>> 16);
280 dregs
->fifo_count
= (sun3_dma_orig_count
& 0xffff);
282 /* if(!(csr & CSR_DMA_ENABLE))
283 * dregs->csr |= CSR_DMA_ENABLE;
286 sun3_udc_write(UDC_CHN_START
, UDC_CSR
);
292 /* clean up after our dma is done */
293 static int sun3scsi_dma_finish(int write_flag
)
295 unsigned short __maybe_unused count
;
302 dregs
->csr
&= ~CSR_DMA_ENABLE
;
304 fifo
= dregs
->fifo_count
;
306 if ((fifo
> 0) && (fifo
< sun3_dma_orig_count
))
310 last_residual
= fifo
;
311 /* empty bytes from the fifo which didn't make it */
312 if ((!write_flag
) && (dregs
->csr
& CSR_LEFT
)) {
313 unsigned char *vaddr
;
315 vaddr
= (unsigned char *)dvma_vmetov(sun3_dma_orig_addr
);
317 vaddr
+= (sun3_dma_orig_count
- fifo
);
320 switch (dregs
->csr
& CSR_LEFT
) {
322 *vaddr
= (dregs
->bpack_lo
& 0xff00) >> 8;
326 *vaddr
= (dregs
->bpack_hi
& 0x00ff);
330 *vaddr
= (dregs
->bpack_hi
& 0xff00) >> 8;
335 // check to empty the fifo on a read
337 int tmo
= 20000; /* .2 sec */
340 if(dregs
->csr
& CSR_FIFO_EMPTY
)
344 printk("sun3scsi: fifo failed to empty!\n");
351 dregs
->udc_addr
= 0x32;
352 udelay(SUN3_DMA_DELAY
);
353 count
= 2 * dregs
->udc_data
;
354 udelay(SUN3_DMA_DELAY
);
356 fifo
= dregs
->fifo_count
;
357 last_residual
= fifo
;
359 /* empty bytes from the fifo which didn't make it */
360 if((!write_flag
) && (count
- fifo
) == 2) {
362 unsigned char *vaddr
;
364 data
= dregs
->fifo_data
;
365 vaddr
= (unsigned char *)dvma_btov(sun3_dma_orig_addr
);
367 vaddr
+= (sun3_dma_orig_count
- fifo
);
369 vaddr
[-2] = (data
& 0xff00) >> 8;
370 vaddr
[-1] = (data
& 0xff);
374 dvma_unmap(sun3_dma_orig_addr
);
375 sun3_dma_orig_addr
= NULL
;
378 dregs
->dma_addr_hi
= 0;
379 dregs
->dma_addr_lo
= 0;
380 dregs
->dma_count_hi
= 0;
381 dregs
->dma_count_lo
= 0;
383 dregs
->fifo_count
= 0;
384 dregs
->fifo_count_hi
= 0;
386 dregs
->csr
&= ~CSR_SEND
;
387 /* dregs->csr |= CSR_DMA_ENABLE; */
389 sun3_udc_write(UDC_RESET
, UDC_CSR
);
390 dregs
->fifo_count
= 0;
391 dregs
->csr
&= ~CSR_SEND
;
394 dregs
->csr
&= ~CSR_FIFO
;
395 dregs
->csr
|= CSR_FIFO
;
398 sun3_dma_setup_done
= NULL
;
407 #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
408 #define DRV_MODULE_NAME "sun3_scsi_vme"
410 #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
411 #define DRV_MODULE_NAME "sun3_scsi"
414 #define PFX DRV_MODULE_NAME ": "
416 static struct scsi_host_template sun3_scsi_template
= {
417 .module
= THIS_MODULE
,
418 .proc_name
= DRV_MODULE_NAME
,
419 .name
= SUN3_SCSI_NAME
,
420 .info
= sun3scsi_info
,
421 .queuecommand
= sun3scsi_queue_command
,
422 .eh_abort_handler
= sun3scsi_abort
,
423 .eh_bus_reset_handler
= sun3scsi_bus_reset
,
426 .sg_tablesize
= SG_NONE
,
428 .use_clustering
= DISABLE_CLUSTERING
,
429 .cmd_size
= NCR5380_CMD_SIZE
,
432 static int __init
sun3_scsi_probe(struct platform_device
*pdev
)
434 struct Scsi_Host
*instance
;
435 struct NCR5380_hostdata
*hostdata
;
437 struct resource
*irq
, *mem
;
438 void __iomem
*ioaddr
;
444 if (setup_can_queue
> 0)
445 sun3_scsi_template
.can_queue
= setup_can_queue
;
446 if (setup_cmd_per_lun
> 0)
447 sun3_scsi_template
.cmd_per_lun
= setup_cmd_per_lun
;
448 if (setup_sg_tablesize
>= 0)
449 sun3_scsi_template
.sg_tablesize
= setup_sg_tablesize
;
450 if (setup_hostid
>= 0)
451 sun3_scsi_template
.this_id
= setup_hostid
& 7;
455 for (i
= 0; i
< 2; i
++) {
458 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, i
);
459 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
463 ioaddr
= sun3_ioremap(mem
->start
, resource_size(mem
),
464 SUN3_PAGE_TYPE_VME16
);
465 dregs
= (struct sun3_dma_regs
*)(ioaddr
+ 8);
467 if (sun3_map_test((unsigned long)dregs
, &x
)) {
468 unsigned short oldcsr
;
472 udelay(SUN3_DMA_DELAY
);
473 if (dregs
->csr
== 0x1400)
485 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
486 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
490 ioaddr
= ioremap(mem
->start
, resource_size(mem
));
491 dregs
= (struct sun3_dma_regs
*)(ioaddr
+ 8);
493 udc_regs
= dvma_malloc(sizeof(struct sun3_udc_regs
));
495 pr_err(PFX
"couldn't allocate DVMA memory!\n");
501 instance
= scsi_host_alloc(&sun3_scsi_template
,
502 sizeof(struct NCR5380_hostdata
));
508 instance
->irq
= irq
->start
;
510 hostdata
= shost_priv(instance
);
511 hostdata
->base
= mem
->start
;
512 hostdata
->io
= ioaddr
;
514 error
= NCR5380_init(instance
, host_flags
);
518 error
= request_irq(instance
->irq
, scsi_sun3_intr
, 0,
519 "NCR5380", instance
);
521 pr_err(PFX
"scsi%d: IRQ %d not free, bailing out\n",
522 instance
->host_no
, instance
->irq
);
527 udelay(SUN3_DMA_DELAY
);
528 dregs
->csr
= CSR_SCSI
| CSR_FIFO
| CSR_INTR
;
529 udelay(SUN3_DMA_DELAY
);
530 dregs
->fifo_count
= 0;
532 dregs
->fifo_count_hi
= 0;
533 dregs
->dma_addr_hi
= 0;
534 dregs
->dma_addr_lo
= 0;
535 dregs
->dma_count_hi
= 0;
536 dregs
->dma_count_lo
= 0;
538 dregs
->ivect
= VME_DATA24
| (instance
->irq
& 0xff);
541 NCR5380_maybe_reset_bus(instance
);
543 error
= scsi_add_host(instance
, NULL
);
547 platform_set_drvdata(pdev
, instance
);
549 scsi_scan_host(instance
);
553 free_irq(instance
->irq
, instance
);
555 NCR5380_exit(instance
);
557 scsi_host_put(instance
);
565 static int __exit
sun3_scsi_remove(struct platform_device
*pdev
)
567 struct Scsi_Host
*instance
= platform_get_drvdata(pdev
);
568 struct NCR5380_hostdata
*hostdata
= shost_priv(instance
);
569 void __iomem
*ioaddr
= hostdata
->io
;
571 scsi_remove_host(instance
);
572 free_irq(instance
->irq
, instance
);
573 NCR5380_exit(instance
);
574 scsi_host_put(instance
);
581 static struct platform_driver sun3_scsi_driver
= {
582 .remove
= __exit_p(sun3_scsi_remove
),
584 .name
= DRV_MODULE_NAME
,
588 module_platform_driver_probe(sun3_scsi_driver
, sun3_scsi_probe
);
590 MODULE_ALIAS("platform:" DRV_MODULE_NAME
);
591 MODULE_LICENSE("GPL");