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[IPV4]: Fix secondary IP addresses after promotion
[linux/fpc-iii.git] / sound / oss / ad1848.c
blob3f30c57676c18c816e2653245833c67214791839
1 /*
2 * sound/ad1848.c
3 *
4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
6 *
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
9 *
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
12 *
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
15 *
16 *
17 *
18 * Copyright (C) by Hannu Savolainen 1993-1997
19 *
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
22 * for more info.
23 *
24 *
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 * Christoph Hellwig : adapted to module_init/module_exit
30 * Aki Laukkanen : added power management support
31 * Arnaldo C. de Melo : added missing restore_flags in ad1848_resume
32 * Miguel Freitas : added ISA PnP support
33 * Alan Cox : Added CS4236->4239 identification
34 * Daniel T. Cobra : Alernate config/mixer for later chips
35 * Alan Cox : Merged chip idents and config code
36 *
37 * TODO
38 * APM save restore assist code on IBM thinkpad
39 *
40 * Status:
41 * Tested. Believed fully functional.
42 */
43
44 #include <linux/config.h>
45 #include <linux/init.h>
46 #include <linux/interrupt.h>
47 #include <linux/module.h>
48 #include <linux/stddef.h>
49 #include <linux/pm.h>
50 #include <linux/pm_legacy.h>
51 #include <linux/isapnp.h>
52 #include <linux/pnp.h>
53 #include <linux/spinlock.h>
54
55 #define DEB(x)
56 #define DEB1(x)
57 #include "sound_config.h"
58
59 #include "ad1848.h"
60 #include "ad1848_mixer.h"
61
62 typedef struct
63 {
64 spinlock_t lock;
65 int base;
66 int irq;
67 int dma1, dma2;
68 int dual_dma; /* 1, when two DMA channels allocated */
69 int subtype;
70 unsigned char MCE_bit;
71 unsigned char saved_regs[64]; /* Includes extended register space */
72 int debug_flag;
73
74 int audio_flags;
75 int record_dev, playback_dev;
76
77 int xfer_count;
78 int audio_mode;
79 int open_mode;
80 int intr_active;
81 char *chip_name, *name;
82 int model;
83 #define MD_1848 1
84 #define MD_4231 2
85 #define MD_4231A 3
86 #define MD_1845 4
87 #define MD_4232 5
88 #define MD_C930 6
89 #define MD_IWAVE 7
90 #define MD_4235 8 /* Crystal Audio CS4235 */
91 #define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
92 #define MD_4236 10 /* 4236 and higher */
93 #define MD_42xB 11 /* CS 42xB */
94 #define MD_4239 12 /* CS4239 */
95
96 /* Mixer parameters */
97 int recmask;
98 int supported_devices, orig_devices;
99 int supported_rec_devices, orig_rec_devices;
100 int *levels;
101 short mixer_reroute[32];
102 int dev_no;
103 volatile unsigned long timer_ticks;
104 int timer_running;
105 int irq_ok;
106 mixer_ents *mix_devices;
107 int mixer_output_port;
108
109 /* Power management */
110 struct pm_dev *pmdev;
111 } ad1848_info;
112
113 typedef struct ad1848_port_info
114 {
115 int open_mode;
116 int speed;
117 unsigned char speed_bits;
118 int channels;
119 int audio_format;
120 unsigned char format_bits;
121 }
122 ad1848_port_info;
123
124 static struct address_info cfg;
125 static int nr_ad1848_devs;
126
127 static int deskpro_xl;
128 static int deskpro_m;
129 static int soundpro;
130
131 static volatile signed char irq2dev[17] = {
132 -1, -1, -1, -1, -1, -1, -1, -1,
133 -1, -1, -1, -1, -1, -1, -1, -1, -1
134 };
135
136 #ifndef EXCLUDE_TIMERS
137 static int timer_installed = -1;
138 #endif
139
140 static int loaded;
141
142 static int ad_format_mask[13 /*devc->model */ ] =
143 {
144 0,
145 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
146 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
147 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
148 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
149 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
150 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
151 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
152 AFMT_U8 | AFMT_S16_LE /* CS4235 */,
153 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/,
154 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
155 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
156 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
157 };
158
159 static ad1848_info adev_info[MAX_AUDIO_DEV];
160
161 #define io_Index_Addr(d) ((d)->base)
162 #define io_Indexed_Data(d) ((d)->base+1)
163 #define io_Status(d) ((d)->base+2)
164 #define io_Polled_IO(d) ((d)->base+3)
165
166 static struct {
167 unsigned char flags;
168 #define CAP_F_TIMER 0x01
169 } capabilities [10 /*devc->model */ ] = {
170 {0}
171 ,{0} /* MD_1848 */
172 ,{CAP_F_TIMER} /* MD_4231 */
173 ,{CAP_F_TIMER} /* MD_4231A */
174 ,{CAP_F_TIMER} /* MD_1845 */
175 ,{CAP_F_TIMER} /* MD_4232 */
176 ,{0} /* MD_C930 */
177 ,{CAP_F_TIMER} /* MD_IWAVE */
178 ,{0} /* MD_4235 */
179 ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
180 };
181
182 #ifdef CONFIG_PNP
183 static int isapnp = 1;
184 static int isapnpjump;
185 static int reverse;
186
187 static int audio_activated;
188 #else
189 static int isapnp;
190 #endif
191
192
193
194 static int ad1848_open(int dev, int mode);
195 static void ad1848_close(int dev);
196 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
197 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
198 static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
199 static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
200 static void ad1848_halt(int dev);
201 static void ad1848_halt_input(int dev);
202 static void ad1848_halt_output(int dev);
203 static void ad1848_trigger(int dev, int bits);
204 static int ad1848_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data);
205
206 #ifndef EXCLUDE_TIMERS
207 static int ad1848_tmr_install(int dev);
208 static void ad1848_tmr_reprogram(int dev);
209 #endif
210
211 static int ad_read(ad1848_info * devc, int reg)
212 {
213 int x;
214 int timeout = 900000;
215
216 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
217 timeout--;
218
219 if(reg < 32)
220 {
221 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
222 x = inb(io_Indexed_Data(devc));
223 }
224 else
225 {
226 int xreg, xra;
227
228 xreg = (reg & 0xff) - 32;
229 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
230 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
231 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
232 x = inb(io_Indexed_Data(devc));
233 }
234
235 return x;
236 }
237
238 static void ad_write(ad1848_info * devc, int reg, int data)
239 {
240 int timeout = 900000;
241
242 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
243 timeout--;
244
245 if(reg < 32)
246 {
247 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
248 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
249 }
250 else
251 {
252 int xreg, xra;
253
254 xreg = (reg & 0xff) - 32;
255 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
256 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
257 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
258 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
259 }
260 }
261
262 static void wait_for_calibration(ad1848_info * devc)
263 {
264 int timeout = 0;
265
266 /*
267 * Wait until the auto calibration process has finished.
268 *
269 * 1) Wait until the chip becomes ready (reads don't return 0x80).
270 * 2) Wait until the ACI bit of I11 gets on and then off.
271 */
272
273 timeout = 100000;
274 while (timeout > 0 && inb(devc->base) == 0x80)
275 timeout--;
276 if (inb(devc->base) & 0x80)
277 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
278
279 timeout = 100;
280 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
281 timeout--;
282 if (!(ad_read(devc, 11) & 0x20))
283 return;
284
285 timeout = 80000;
286 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
287 timeout--;
288 if (ad_read(devc, 11) & 0x20)
289 if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
290 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
291 }
292
293 static void ad_mute(ad1848_info * devc)
294 {
295 int i;
296 unsigned char prev;
297
298 /*
299 * Save old register settings and mute output channels
300 */
301
302 for (i = 6; i < 8; i++)
303 {
304 prev = devc->saved_regs[i] = ad_read(devc, i);
305 }
306
307 }
308
309 static void ad_unmute(ad1848_info * devc)
310 {
311 }
312
313 static void ad_enter_MCE(ad1848_info * devc)
314 {
315 int timeout = 1000;
316 unsigned short prev;
317
318 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
319 timeout--;
320
321 devc->MCE_bit = 0x40;
322 prev = inb(io_Index_Addr(devc));
323 if (prev & 0x40)
324 {
325 return;
326 }
327 outb((devc->MCE_bit), io_Index_Addr(devc));
328 }
329
330 static void ad_leave_MCE(ad1848_info * devc)
331 {
332 unsigned char prev, acal;
333 int timeout = 1000;
334
335 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
336 timeout--;
337
338 acal = ad_read(devc, 9);
339
340 devc->MCE_bit = 0x00;
341 prev = inb(io_Index_Addr(devc));
342 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
343
344 if ((prev & 0x40) == 0) /* Not in MCE mode */
345 {
346 return;
347 }
348 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
349 if (acal & 0x08) /* Auto calibration is enabled */
350 wait_for_calibration(devc);
351 }
352
353 static int ad1848_set_recmask(ad1848_info * devc, int mask)
354 {
355 unsigned char recdev;
356 int i, n;
357 unsigned long flags;
358
359 mask &= devc->supported_rec_devices;
360
361 /* Rename the mixer bits if necessary */
362 for (i = 0; i < 32; i++)
363 {
364 if (devc->mixer_reroute[i] != i)
365 {
366 if (mask & (1 << i))
367 {
368 mask &= ~(1 << i);
369 mask |= (1 << devc->mixer_reroute[i]);
370 }
371 }
372 }
373
374 n = 0;
375 for (i = 0; i < 32; i++) /* Count selected device bits */
376 if (mask & (1 << i))
377 n++;
378
379 spin_lock_irqsave(&devc->lock,flags);
380 if (!soundpro) {
381 if (n == 0)
382 mask = SOUND_MASK_MIC;
383 else if (n != 1) { /* Too many devices selected */
384 mask &= ~devc->recmask; /* Filter out active settings */
385
386 n = 0;
387 for (i = 0; i < 32; i++) /* Count selected device bits */
388 if (mask & (1 << i))
389 n++;
390
391 if (n != 1)
392 mask = SOUND_MASK_MIC;
393 }
394 switch (mask) {
395 case SOUND_MASK_MIC:
396 recdev = 2;
397 break;
398
399 case SOUND_MASK_LINE:
400 case SOUND_MASK_LINE3:
401 recdev = 0;
402 break;
403
404 case SOUND_MASK_CD:
405 case SOUND_MASK_LINE1:
406 recdev = 1;
407 break;
408
409 case SOUND_MASK_IMIX:
410 recdev = 3;
411 break;
412
413 default:
414 mask = SOUND_MASK_MIC;
415 recdev = 2;
416 }
417
418 recdev <<= 6;
419 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
420 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
421 } else { /* soundpro */
422 unsigned char val;
423 int set_rec_bit;
424 int j;
425
426 for (i = 0; i < 32; i++) { /* For each bit */
427 if ((devc->supported_rec_devices & (1 << i)) == 0)
428 continue; /* Device not supported */
429
430 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
431 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
432 continue;
433
434 /*
435 * This is tricky:
436 * set_rec_bit becomes 1 if the corresponding bit in mask is set
437 * then it gets flipped if the polarity is inverse
438 */
439 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
440
441 val = ad_read(devc, devc->mix_devices[i][j].recreg);
442 val &= ~(1 << devc->mix_devices[i][j].recpos);
443 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
444 ad_write(devc, devc->mix_devices[i][j].recreg, val);
445 }
446 }
447 }
448 spin_unlock_irqrestore(&devc->lock,flags);
449
450 /* Rename the mixer bits back if necessary */
451 for (i = 0; i < 32; i++)
452 {
453 if (devc->mixer_reroute[i] != i)
454 {
455 if (mask & (1 << devc->mixer_reroute[i]))
456 {
457 mask &= ~(1 << devc->mixer_reroute[i]);
458 mask |= (1 << i);
459 }
460 }
461 }
462 devc->recmask = mask;
463 return mask;
464 }
465
466 static void change_bits(ad1848_info * devc, unsigned char *regval,
467 unsigned char *muteval, int dev, int chn, int newval)
468 {
469 unsigned char mask;
470 int shift;
471 int mute;
472 int mutemask;
473 int set_mute_bit;
474
475 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
476
477 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
478 newval = 100 - newval;
479
480 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
481 shift = devc->mix_devices[dev][chn].bitpos;
482
483 if (devc->mix_devices[dev][chn].mutepos == 8)
484 { /* if there is no mute bit */
485 mute = 0; /* No mute bit; do nothing special */
486 mutemask = ~0; /* No mute bit; do nothing special */
487 }
488 else
489 {
490 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
491 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
492 }
493
494 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
495 *regval &= ~(mask << shift); /* Clear bits */
496 *regval |= (newval & mask) << shift; /* Set new value */
497
498 *muteval &= mutemask;
499 *muteval |= mute;
500 }
501
502 static int ad1848_mixer_get(ad1848_info * devc, int dev)
503 {
504 if (!((1 << dev) & devc->supported_devices))
505 return -EINVAL;
506
507 dev = devc->mixer_reroute[dev];
508
509 return devc->levels[dev];
510 }
511
512 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
513 {
514 int regoffs, muteregoffs;
515 unsigned char val, muteval;
516 unsigned long flags;
517
518 regoffs = devc->mix_devices[dev][channel].regno;
519 muteregoffs = devc->mix_devices[dev][channel].mutereg;
520 val = ad_read(devc, regoffs);
521
522 if (muteregoffs != regoffs) {
523 muteval = ad_read(devc, muteregoffs);
524 change_bits(devc, &val, &muteval, dev, channel, value);
525 }
526 else
527 change_bits(devc, &val, &val, dev, channel, value);
528
529 spin_lock_irqsave(&devc->lock,flags);
530 ad_write(devc, regoffs, val);
531 devc->saved_regs[regoffs] = val;
532 if (muteregoffs != regoffs) {
533 ad_write(devc, muteregoffs, muteval);
534 devc->saved_regs[muteregoffs] = muteval;
535 }
536 spin_unlock_irqrestore(&devc->lock,flags);
537 }
538
539 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
540 {
541 int left = value & 0x000000ff;
542 int right = (value & 0x0000ff00) >> 8;
543 int retvol;
544
545 if (dev > 31)
546 return -EINVAL;
547
548 if (!(devc->supported_devices & (1 << dev)))
549 return -EINVAL;
550
551 dev = devc->mixer_reroute[dev];
552
553 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
554 return -EINVAL;
555
556 if (left > 100)
557 left = 100;
558 if (right > 100)
559 right = 100;
560
561 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
562 right = left;
563
564 retvol = left | (right << 8);
565
566 /* Scale volumes */
567 left = mix_cvt[left];
568 right = mix_cvt[right];
569
570 devc->levels[dev] = retvol;
571
572 /*
573 * Set the left channel
574 */
575 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
576
577 /*
578 * Set the right channel
579 */
580 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
581 goto out;
582 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
583
584 out:
585 return retvol;
586 }
587
588 static void ad1848_mixer_reset(ad1848_info * devc)
589 {
590 int i;
591 char name[32];
592 unsigned long flags;
593
594 devc->mix_devices = &(ad1848_mix_devices[0]);
595
596 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
597
598 for (i = 0; i < 32; i++)
599 devc->mixer_reroute[i] = i;
600
601 devc->supported_rec_devices = MODE1_REC_DEVICES;
602
603 switch (devc->model)
604 {
605 case MD_4231:
606 case MD_4231A:
607 case MD_1845:
608 case MD_1845_SSCAPE:
609 devc->supported_devices = MODE2_MIXER_DEVICES;
610 break;
611
612 case MD_C930:
613 devc->supported_devices = C930_MIXER_DEVICES;
614 devc->mix_devices = &(c930_mix_devices[0]);
615 break;
616
617 case MD_IWAVE:
618 devc->supported_devices = MODE3_MIXER_DEVICES;
619 devc->mix_devices = &(iwave_mix_devices[0]);
620 break;
621
622 case MD_42xB:
623 case MD_4239:
624 devc->mix_devices = &(cs42xb_mix_devices[0]);
625 devc->supported_devices = MODE3_MIXER_DEVICES;
626 break;
627 case MD_4232:
628 case MD_4235:
629 case MD_4236:
630 devc->supported_devices = MODE3_MIXER_DEVICES;
631 break;
632
633 case MD_1848:
634 if (soundpro) {
635 devc->supported_devices = SPRO_MIXER_DEVICES;
636 devc->supported_rec_devices = SPRO_REC_DEVICES;
637 devc->mix_devices = &(spro_mix_devices[0]);
638 break;
639 }
640
641 default:
642 devc->supported_devices = MODE1_MIXER_DEVICES;
643 }
644
645 devc->orig_devices = devc->supported_devices;
646 devc->orig_rec_devices = devc->supported_rec_devices;
647
648 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
649
650 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
651 {
652 if (devc->supported_devices & (1 << i))
653 ad1848_mixer_set(devc, i, devc->levels[i]);
654 }
655
656 ad1848_set_recmask(devc, SOUND_MASK_MIC);
657
658 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
659
660 spin_lock_irqsave(&devc->lock,flags);
661 if (!soundpro) {
662 if (devc->mixer_output_port & AUDIO_SPEAKER)
663 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
664 else
665 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
666 } else {
667 /*
668 * From the "wouldn't it be nice if the mixer API had (better)
669 * support for custom stuff" category
670 */
671 /* Enable surround mode and SB16 mixer */
672 ad_write(devc, 16, 0x60);
673 }
674 spin_unlock_irqrestore(&devc->lock,flags);
675 }
676
677 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
678 {
679 ad1848_info *devc = mixer_devs[dev]->devc;
680 int val;
681
682 if (cmd == SOUND_MIXER_PRIVATE1)
683 {
684 if (get_user(val, (int __user *)arg))
685 return -EFAULT;
686
687 if (val != 0xffff)
688 {
689 unsigned long flags;
690 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
691 devc->mixer_output_port = val;
692 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
693 devc->mixer_output_port = val;
694 spin_lock_irqsave(&devc->lock,flags);
695 if (val & AUDIO_SPEAKER)
696 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
697 else
698 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
699 spin_unlock_irqrestore(&devc->lock,flags);
700 }
701 val = devc->mixer_output_port;
702 return put_user(val, (int __user *)arg);
703 }
704 if (cmd == SOUND_MIXER_PRIVATE2)
705 {
706 if (get_user(val, (int __user *)arg))
707 return -EFAULT;
708 return(ad1848_control(AD1848_MIXER_REROUTE, val));
709 }
710 if (((cmd >> 8) & 0xff) == 'M')
711 {
712 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
713 {
714 switch (cmd & 0xff)
715 {
716 case SOUND_MIXER_RECSRC:
717 if (get_user(val, (int __user *)arg))
718 return -EFAULT;
719 val = ad1848_set_recmask(devc, val);
720 break;
721
722 default:
723 if (get_user(val, (int __user *)arg))
724 return -EFAULT;
725 val = ad1848_mixer_set(devc, cmd & 0xff, val);
726 break;
727 }
728 return put_user(val, (int __user *)arg);
729 }
730 else
731 {
732 switch (cmd & 0xff)
733 {
734 /*
735 * Return parameters
736 */
737
738 case SOUND_MIXER_RECSRC:
739 val = devc->recmask;
740 break;
741
742 case SOUND_MIXER_DEVMASK:
743 val = devc->supported_devices;
744 break;
745
746 case SOUND_MIXER_STEREODEVS:
747 val = devc->supported_devices;
748 if (devc->model != MD_C930)
749 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
750 break;
751
752 case SOUND_MIXER_RECMASK:
753 val = devc->supported_rec_devices;
754 break;
755
756 case SOUND_MIXER_CAPS:
757 val=SOUND_CAP_EXCL_INPUT;
758 break;
759
760 default:
761 val = ad1848_mixer_get(devc, cmd & 0xff);
762 break;
763 }
764 return put_user(val, (int __user *)arg);
765 }
766 }
767 else
768 return -EINVAL;
769 }
770
771 static int ad1848_set_speed(int dev, int arg)
772 {
773 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
774 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
775
776 /*
777 * The sampling speed is encoded in the least significant nibble of I8. The
778 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
779 * three bits select the divisor (indirectly):
780 *
781 * The available speeds are in the following table. Keep the speeds in
782 * the increasing order.
783 */
784 typedef struct
785 {
786 int speed;
787 unsigned char bits;
788 }
789 speed_struct;
790
791 static speed_struct speed_table[] =
792 {
793 {5510, (0 << 1) | 1},
794 {5510, (0 << 1) | 1},
795 {6620, (7 << 1) | 1},
796 {8000, (0 << 1) | 0},
797 {9600, (7 << 1) | 0},
798 {11025, (1 << 1) | 1},
799 {16000, (1 << 1) | 0},
800 {18900, (2 << 1) | 1},
801 {22050, (3 << 1) | 1},
802 {27420, (2 << 1) | 0},
803 {32000, (3 << 1) | 0},
804 {33075, (6 << 1) | 1},
805 {37800, (4 << 1) | 1},
806 {44100, (5 << 1) | 1},
807 {48000, (6 << 1) | 0}
808 };
809
810 int i, n, selected = -1;
811
812 n = sizeof(speed_table) / sizeof(speed_struct);
813
814 if (arg <= 0)
815 return portc->speed;
816
817 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
818 {
819 if (arg < 4000)
820 arg = 4000;
821 if (arg > 50000)
822 arg = 50000;
823
824 portc->speed = arg;
825 portc->speed_bits = speed_table[3].bits;
826 return portc->speed;
827 }
828 if (arg < speed_table[0].speed)
829 selected = 0;
830 if (arg > speed_table[n - 1].speed)
831 selected = n - 1;
832
833 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
834 {
835 if (speed_table[i].speed == arg)
836 selected = i;
837 else if (speed_table[i].speed > arg)
838 {
839 int diff1, diff2;
840
841 diff1 = arg - speed_table[i - 1].speed;
842 diff2 = speed_table[i].speed - arg;
843
844 if (diff1 < diff2)
845 selected = i - 1;
846 else
847 selected = i;
848 }
849 }
850 if (selected == -1)
851 {
852 printk(KERN_WARNING "ad1848: Can't find speed???\n");
853 selected = 3;
854 }
855 portc->speed = speed_table[selected].speed;
856 portc->speed_bits = speed_table[selected].bits;
857 return portc->speed;
858 }
859
860 static short ad1848_set_channels(int dev, short arg)
861 {
862 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
863
864 if (arg != 1 && arg != 2)
865 return portc->channels;
866
867 portc->channels = arg;
868 return arg;
869 }
870
871 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
872 {
873 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
874 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
875
876 static struct format_tbl
877 {
878 int format;
879 unsigned char bits;
880 }
881 format2bits[] =
882 {
883 {
884 0, 0
885 }
886 ,
887 {
888 AFMT_MU_LAW, 1
889 }
890 ,
891 {
892 AFMT_A_LAW, 3
893 }
894 ,
895 {
896 AFMT_IMA_ADPCM, 5
897 }
898 ,
899 {
900 AFMT_U8, 0
901 }
902 ,
903 {
904 AFMT_S16_LE, 2
905 }
906 ,
907 {
908 AFMT_S16_BE, 6
909 }
910 ,
911 {
912 AFMT_S8, 0
913 }
914 ,
915 {
916 AFMT_U16_LE, 0
917 }
918 ,
919 {
920 AFMT_U16_BE, 0
921 }
922 };
923 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
924
925 if (arg == 0)
926 return portc->audio_format;
927
928 if (!(arg & ad_format_mask[devc->model]))
929 arg = AFMT_U8;
930
931 portc->audio_format = arg;
932
933 for (i = 0; i < n; i++)
934 if (format2bits[i].format == arg)
935 {
936 if ((portc->format_bits = format2bits[i].bits) == 0)
937 return portc->audio_format = AFMT_U8; /* Was not supported */
938
939 return arg;
940 }
941 /* Still hanging here. Something must be terribly wrong */
942 portc->format_bits = 0;
943 return portc->audio_format = AFMT_U8;
944 }
945
946 static struct audio_driver ad1848_audio_driver =
947 {
948 .owner = THIS_MODULE,
949 .open = ad1848_open,
950 .close = ad1848_close,
951 .output_block = ad1848_output_block,
952 .start_input = ad1848_start_input,
953 .prepare_for_input = ad1848_prepare_for_input,
954 .prepare_for_output = ad1848_prepare_for_output,
955 .halt_io = ad1848_halt,
956 .halt_input = ad1848_halt_input,
957 .halt_output = ad1848_halt_output,
958 .trigger = ad1848_trigger,
959 .set_speed = ad1848_set_speed,
960 .set_bits = ad1848_set_bits,
961 .set_channels = ad1848_set_channels
962 };
963
964 static struct mixer_operations ad1848_mixer_operations =
965 {
966 .owner = THIS_MODULE,
967 .id = "SOUNDPORT",
968 .name = "AD1848/CS4248/CS4231",
969 .ioctl = ad1848_mixer_ioctl
970 };
971
972 static int ad1848_open(int dev, int mode)
973 {
974 ad1848_info *devc;
975 ad1848_port_info *portc;
976 unsigned long flags;
977
978 if (dev < 0 || dev >= num_audiodevs)
979 return -ENXIO;
980
981 devc = (ad1848_info *) audio_devs[dev]->devc;
982 portc = (ad1848_port_info *) audio_devs[dev]->portc;
983
984 /* here we don't have to protect against intr */
985 spin_lock(&devc->lock);
986 if (portc->open_mode || (devc->open_mode & mode))
987 {
988 spin_unlock(&devc->lock);
989 return -EBUSY;
990 }
991 devc->dual_dma = 0;
992
993 if (audio_devs[dev]->flags & DMA_DUPLEX)
994 {
995 devc->dual_dma = 1;
996 }
997 devc->intr_active = 0;
998 devc->audio_mode = 0;
999 devc->open_mode |= mode;
1000 portc->open_mode = mode;
1001 spin_unlock(&devc->lock);
1002 ad1848_trigger(dev, 0);
1003
1004 if (mode & OPEN_READ)
1005 devc->record_dev = dev;
1006 if (mode & OPEN_WRITE)
1007 devc->playback_dev = dev;
1008 /*
1009 * Mute output until the playback really starts. This decreases clicking (hope so).
1010 */
1011 spin_lock_irqsave(&devc->lock,flags);
1012 ad_mute(devc);
1013 spin_unlock_irqrestore(&devc->lock,flags);
1014
1015 return 0;
1016 }
1017
1018 static void ad1848_close(int dev)
1019 {
1020 unsigned long flags;
1021 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1022 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1023
1024 DEB(printk("ad1848_close(void)\n"));
1025
1026 devc->intr_active = 0;
1027 ad1848_halt(dev);
1028
1029 spin_lock_irqsave(&devc->lock,flags);
1030
1031 devc->audio_mode = 0;
1032 devc->open_mode &= ~portc->open_mode;
1033 portc->open_mode = 0;
1034
1035 ad_unmute(devc);
1036 spin_unlock_irqrestore(&devc->lock,flags);
1037 }
1038
1039 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1040 {
1041 unsigned long flags, cnt;
1042 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1043 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1044
1045 cnt = count;
1046
1047 if (portc->audio_format == AFMT_IMA_ADPCM)
1048 {
1049 cnt /= 4;
1050 }
1051 else
1052 {
1053 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1054 cnt >>= 1;
1055 }
1056 if (portc->channels > 1)
1057 cnt >>= 1;
1058 cnt--;
1059
1060 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1061 intrflag &&
1062 cnt == devc->xfer_count)
1063 {
1064 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1065 devc->intr_active = 1;
1066 return; /*
1067 * Auto DMA mode on. No need to react
1068 */
1069 }
1070 spin_lock_irqsave(&devc->lock,flags);
1071
1072 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1073 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1074
1075 devc->xfer_count = cnt;
1076 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1077 devc->intr_active = 1;
1078 spin_unlock_irqrestore(&devc->lock,flags);
1079 }
1080
1081 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1082 {
1083 unsigned long flags, cnt;
1084 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1085 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1086
1087 cnt = count;
1088 if (portc->audio_format == AFMT_IMA_ADPCM)
1089 {
1090 cnt /= 4;
1091 }
1092 else
1093 {
1094 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1095 cnt >>= 1;
1096 }
1097 if (portc->channels > 1)
1098 cnt >>= 1;
1099 cnt--;
1100
1101 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1102 intrflag &&
1103 cnt == devc->xfer_count)
1104 {
1105 devc->audio_mode |= PCM_ENABLE_INPUT;
1106 devc->intr_active = 1;
1107 return; /*
1108 * Auto DMA mode on. No need to react
1109 */
1110 }
1111 spin_lock_irqsave(&devc->lock,flags);
1112
1113 if (devc->model == MD_1848)
1114 {
1115 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1116 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1117 }
1118 else
1119 {
1120 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1121 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1122 }
1123
1124 ad_unmute(devc);
1125
1126 devc->xfer_count = cnt;
1127 devc->audio_mode |= PCM_ENABLE_INPUT;
1128 devc->intr_active = 1;
1129 spin_unlock_irqrestore(&devc->lock,flags);
1130 }
1131
1132 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1133 {
1134 int timeout;
1135 unsigned char fs, old_fs, tmp = 0;
1136 unsigned long flags;
1137 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1138 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1139
1140 ad_mute(devc);
1141
1142 spin_lock_irqsave(&devc->lock,flags);
1143 fs = portc->speed_bits | (portc->format_bits << 5);
1144
1145 if (portc->channels > 1)
1146 fs |= 0x10;
1147
1148 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1149
1150 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1151 {
1152 fs &= 0xf0; /* Mask off the rate select bits */
1153
1154 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1155 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1156 }
1157 old_fs = ad_read(devc, 8);
1158
1159 if (devc->model == MD_4232 || devc->model >= MD_4236)
1160 {
1161 tmp = ad_read(devc, 16);
1162 ad_write(devc, 16, tmp | 0x30);
1163 }
1164 if (devc->model == MD_IWAVE)
1165 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1166
1167 ad_write(devc, 8, fs);
1168
1169 /*
1170 * Write to I8 starts resynchronization. Wait until it completes.
1171 */
1172
1173 timeout = 0;
1174 while (timeout < 100 && inb(devc->base) != 0x80)
1175 timeout++;
1176 timeout = 0;
1177 while (timeout < 10000 && inb(devc->base) == 0x80)
1178 timeout++;
1179
1180 if (devc->model >= MD_4232)
1181 ad_write(devc, 16, tmp & ~0x30);
1182
1183 ad_leave_MCE(devc); /*
1184 * Starts the calibration process.
1185 */
1186 spin_unlock_irqrestore(&devc->lock,flags);
1187 devc->xfer_count = 0;
1188
1189 #ifndef EXCLUDE_TIMERS
1190 if (dev == timer_installed && devc->timer_running)
1191 if ((fs & 0x01) != (old_fs & 0x01))
1192 {
1193 ad1848_tmr_reprogram(dev);
1194 }
1195 #endif
1196 ad1848_halt_output(dev);
1197 return 0;
1198 }
1199
1200 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1201 {
1202 int timeout;
1203 unsigned char fs, old_fs, tmp = 0;
1204 unsigned long flags;
1205 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1206 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1207
1208 if (devc->audio_mode)
1209 return 0;
1210
1211 spin_lock_irqsave(&devc->lock,flags);
1212 fs = portc->speed_bits | (portc->format_bits << 5);
1213
1214 if (portc->channels > 1)
1215 fs |= 0x10;
1216
1217 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1218
1219 if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
1220 {
1221 fs &= 0xf0; /* Mask off the rate select bits */
1222
1223 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1224 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1225 }
1226 if (devc->model == MD_4232)
1227 {
1228 tmp = ad_read(devc, 16);
1229 ad_write(devc, 16, tmp | 0x30);
1230 }
1231 if (devc->model == MD_IWAVE)
1232 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1233
1234 /*
1235 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1236 */
1237
1238 if (devc->model != MD_1848)
1239 {
1240 old_fs = ad_read(devc, 28);
1241 ad_write(devc, 28, fs);
1242
1243 /*
1244 * Write to I28 starts resynchronization. Wait until it completes.
1245 */
1246
1247 timeout = 0;
1248 while (timeout < 100 && inb(devc->base) != 0x80)
1249 timeout++;
1250
1251 timeout = 0;
1252 while (timeout < 10000 && inb(devc->base) == 0x80)
1253 timeout++;
1254
1255 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1256 {
1257 /*
1258 * CS4231 compatible devices don't have separate sampling rate selection
1259 * register for recording an playback. The I8 register is shared so we have to
1260 * set the speed encoding bits of it too.
1261 */
1262 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1263
1264 ad_write(devc, 8, tmp);
1265 /*
1266 * Write to I8 starts resynchronization. Wait until it completes.
1267 */
1268 timeout = 0;
1269 while (timeout < 100 && inb(devc->base) != 0x80)
1270 timeout++;
1271
1272 timeout = 0;
1273 while (timeout < 10000 && inb(devc->base) == 0x80)
1274 timeout++;
1275 }
1276 }
1277 else
1278 { /* For AD1848 set I8. */
1279
1280 old_fs = ad_read(devc, 8);
1281 ad_write(devc, 8, fs);
1282 /*
1283 * Write to I8 starts resynchronization. Wait until it completes.
1284 */
1285 timeout = 0;
1286 while (timeout < 100 && inb(devc->base) != 0x80)
1287 timeout++;
1288 timeout = 0;
1289 while (timeout < 10000 && inb(devc->base) == 0x80)
1290 timeout++;
1291 }
1292
1293 if (devc->model == MD_4232)
1294 ad_write(devc, 16, tmp & ~0x30);
1295
1296 ad_leave_MCE(devc); /*
1297 * Starts the calibration process.
1298 */
1299 spin_unlock_irqrestore(&devc->lock,flags);
1300 devc->xfer_count = 0;
1301
1302 #ifndef EXCLUDE_TIMERS
1303 if (dev == timer_installed && devc->timer_running)
1304 {
1305 if ((fs & 0x01) != (old_fs & 0x01))
1306 {
1307 ad1848_tmr_reprogram(dev);
1308 }
1309 }
1310 #endif
1311 ad1848_halt_input(dev);
1312 return 0;
1313 }
1314
1315 static void ad1848_halt(int dev)
1316 {
1317 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1318 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1319
1320 unsigned char bits = ad_read(devc, 9);
1321
1322 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1323 ad1848_halt_output(dev);
1324
1325 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1326 ad1848_halt_input(dev);
1327 devc->audio_mode = 0;
1328 }
1329
1330 static void ad1848_halt_input(int dev)
1331 {
1332 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1333 unsigned long flags;
1334
1335 if (!(ad_read(devc, 9) & 0x02))
1336 return; /* Capture not enabled */
1337
1338 spin_lock_irqsave(&devc->lock,flags);
1339
1340 ad_mute(devc);
1341
1342 {
1343 int tmout;
1344
1345 if(!isa_dma_bridge_buggy)
1346 disable_dma(audio_devs[dev]->dmap_in->dma);
1347
1348 for (tmout = 0; tmout < 100000; tmout++)
1349 if (ad_read(devc, 11) & 0x10)
1350 break;
1351 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1352
1353 if(!isa_dma_bridge_buggy)
1354 enable_dma(audio_devs[dev]->dmap_in->dma);
1355 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1356 }
1357
1358 outb(0, io_Status(devc)); /* Clear interrupt status */
1359 outb(0, io_Status(devc)); /* Clear interrupt status */
1360
1361 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1362
1363 spin_unlock_irqrestore(&devc->lock,flags);
1364 }
1365
1366 static void ad1848_halt_output(int dev)
1367 {
1368 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1369 unsigned long flags;
1370
1371 if (!(ad_read(devc, 9) & 0x01))
1372 return; /* Playback not enabled */
1373
1374 spin_lock_irqsave(&devc->lock,flags);
1375
1376 ad_mute(devc);
1377 {
1378 int tmout;
1379
1380 if(!isa_dma_bridge_buggy)
1381 disable_dma(audio_devs[dev]->dmap_out->dma);
1382
1383 for (tmout = 0; tmout < 100000; tmout++)
1384 if (ad_read(devc, 11) & 0x10)
1385 break;
1386 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1387
1388 if(!isa_dma_bridge_buggy)
1389 enable_dma(audio_devs[dev]->dmap_out->dma);
1390
1391 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1392 }
1393
1394 outb((0), io_Status(devc)); /* Clear interrupt status */
1395 outb((0), io_Status(devc)); /* Clear interrupt status */
1396
1397 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1398
1399 spin_unlock_irqrestore(&devc->lock,flags);
1400 }
1401
1402 static void ad1848_trigger(int dev, int state)
1403 {
1404 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1405 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1406 unsigned long flags;
1407 unsigned char tmp, old;
1408
1409 spin_lock_irqsave(&devc->lock,flags);
1410 state &= devc->audio_mode;
1411
1412 tmp = old = ad_read(devc, 9);
1413
1414 if (portc->open_mode & OPEN_READ)
1415 {
1416 if (state & PCM_ENABLE_INPUT)
1417 tmp |= 0x02;
1418 else
1419 tmp &= ~0x02;
1420 }
1421 if (portc->open_mode & OPEN_WRITE)
1422 {
1423 if (state & PCM_ENABLE_OUTPUT)
1424 tmp |= 0x01;
1425 else
1426 tmp &= ~0x01;
1427 }
1428 /* ad_mute(devc); */
1429 if (tmp != old)
1430 {
1431 ad_write(devc, 9, tmp);
1432 ad_unmute(devc);
1433 }
1434 spin_unlock_irqrestore(&devc->lock,flags);
1435 }
1436
1437 static void ad1848_init_hw(ad1848_info * devc)
1438 {
1439 int i;
1440 int *init_values;
1441
1442 /*
1443 * Initial values for the indirect registers of CS4248/AD1848.
1444 */
1445 static int init_values_a[] =
1446 {
1447 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1448 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1449
1450 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1451 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1453 };
1454
1455 static int init_values_b[] =
1456 {
1457 /*
1458 Values for the newer chips
1459 Some of the register initialization values were changed. In
1460 order to get rid of the click that preceded PCM playback,
1461 calibration was disabled on the 10th byte. On that same byte,
1462 dual DMA was enabled; on the 11th byte, ADC dithering was
1463 enabled, since that is theoretically desirable; on the 13th
1464 byte, Mode 3 was selected, to enable access to extended
1465 registers.
1466 */
1467 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1468 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1469 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1470 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1471 };
1472
1473 /*
1474 * Select initialisation data
1475 */
1476
1477 init_values = init_values_a;
1478 if(devc->model >= MD_4236)
1479 init_values = init_values_b;
1480
1481 for (i = 0; i < 16; i++)
1482 ad_write(devc, i, init_values[i]);
1483
1484
1485 ad_mute(devc); /* Initialize some variables */
1486 ad_unmute(devc); /* Leave it unmuted now */
1487
1488 if (devc->model > MD_1848)
1489 {
1490 if (devc->model == MD_1845_SSCAPE)
1491 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1492 else
1493 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1494
1495 if (devc->model == MD_IWAVE)
1496 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1497
1498 if (devc->model != MD_1845_SSCAPE)
1499 for (i = 16; i < 32; i++)
1500 ad_write(devc, i, init_values[i]);
1501
1502 if (devc->model == MD_IWAVE)
1503 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1504 }
1505 if (devc->model > MD_1848)
1506 {
1507 if (devc->audio_flags & DMA_DUPLEX)
1508 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1509 else
1510 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1511
1512 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1513 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1514
1515 if (devc->model == MD_IWAVE)
1516 { /* Some magic Interwave specific initialization */
1517 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1518 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1519 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1520 }
1521 }
1522 else
1523 {
1524 devc->audio_flags &= ~DMA_DUPLEX;
1525 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1526 if (soundpro)
1527 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1528 }
1529
1530 outb((0), io_Status(devc)); /* Clear pending interrupts */
1531
1532 /*
1533 * Toggle the MCE bit. It completes the initialization phase.
1534 */
1535
1536 ad_enter_MCE(devc); /* In case the bit was off */
1537 ad_leave_MCE(devc);
1538
1539 ad1848_mixer_reset(devc);
1540 }
1541
1542 int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1543 {
1544 unsigned char tmp;
1545 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1546 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1547 int optiC930 = 0; /* OPTi 82C930 flag */
1548 int interwave = 0;
1549 int ad1847_flag = 0;
1550 int cs4248_flag = 0;
1551 int sscape_flag = 0;
1552 int io_base = ports->start;
1553
1554 int i;
1555
1556 DDB(printk("ad1848_detect(%x)\n", io_base));
1557
1558 if (ad_flags)
1559 {
1560 if (*ad_flags == 0x12345678)
1561 {
1562 interwave = 1;
1563 *ad_flags = 0;
1564 }
1565
1566 if (*ad_flags == 0x87654321)
1567 {
1568 sscape_flag = 1;
1569 *ad_flags = 0;
1570 }
1571
1572 if (*ad_flags == 0x12345677)
1573 {
1574 cs4248_flag = 1;
1575 *ad_flags = 0;
1576 }
1577 }
1578 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1579 {
1580 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1581 return 0;
1582 }
1583 spin_lock_init(&devc->lock);
1584 devc->base = io_base;
1585 devc->irq_ok = 0;
1586 devc->timer_running = 0;
1587 devc->MCE_bit = 0x40;
1588 devc->irq = 0;
1589 devc->open_mode = 0;
1590 devc->chip_name = devc->name = "AD1848";
1591 devc->model = MD_1848; /* AD1848 or CS4248 */
1592 devc->levels = NULL;
1593 devc->debug_flag = 0;
1594
1595 /*
1596 * Check that the I/O address is in use.
1597 *
1598 * The bit 0x80 of the base I/O port is known to be 0 after the
1599 * chip has performed its power on initialization. Just assume
1600 * this has happened before the OS is starting.
1601 *
1602 * If the I/O address is unused, it typically returns 0xff.
1603 */
1604
1605 if (inb(devc->base) == 0xff)
1606 {
1607 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1608 }
1609
1610 /*
1611 * Wait for the device to stop initialization
1612 */
1613
1614 DDB(printk("ad1848_detect() - step 0\n"));
1615
1616 for (i = 0; i < 10000000; i++)
1617 {
1618 unsigned char x = inb(devc->base);
1619
1620 if (x == 0xff || !(x & 0x80))
1621 break;
1622 }
1623
1624 DDB(printk("ad1848_detect() - step A\n"));
1625
1626 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1627 ad_leave_MCE(devc);
1628
1629 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1630 {
1631 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1632 return 0;
1633 }
1634
1635 /*
1636 * Test if it's possible to change contents of the indirect registers.
1637 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1638 * so try to avoid using it.
1639 */
1640
1641 DDB(printk("ad1848_detect() - step B\n"));
1642 ad_write(devc, 0, 0xaa);
1643 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1644
1645 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1646 {
1647 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1648 ad1847_flag = 1;
1649 else
1650 {
1651 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1652 return 0;
1653 }
1654 }
1655 DDB(printk("ad1848_detect() - step C\n"));
1656 ad_write(devc, 0, 0x45);
1657 ad_write(devc, 1, 0xaa);
1658
1659 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1660 {
1661 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1662 ad1847_flag = 1;
1663 else
1664 {
1665 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1666 return 0;
1667 }
1668 }
1669
1670 /*
1671 * The indirect register I12 has some read only bits. Let's
1672 * try to change them.
1673 */
1674
1675 DDB(printk("ad1848_detect() - step D\n"));
1676 tmp = ad_read(devc, 12);
1677 ad_write(devc, 12, (~tmp) & 0x0f);
1678
1679 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1680 {
1681 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1682 return 0;
1683 }
1684
1685 /*
1686 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1687 * 0x01=RevB and 0x0A=RevC.
1688 */
1689
1690 /*
1691 * The original AD1848/CS4248 has just 15 indirect registers. This means
1692 * that I0 and I16 should return the same value (etc.).
1693 * However this doesn't work with CS4248. Actually it seems to be impossible
1694 * to detect if the chip is a CS4231 or CS4248.
1695 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1696 * with CS4231.
1697 */
1698
1699 /*
1700 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1701 * with it. Accept this situation as a possible indication of this chip.
1702 */
1703
1704 DDB(printk("ad1848_detect() - step F\n"));
1705 ad_write(devc, 12, 0); /* Mode2=disabled */
1706
1707 for (i = 0; i < 16; i++)
1708 {
1709 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1710 {
1711 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1712 if (!ad1847_flag)
1713 optiC930 = 1;
1714 break;
1715 }
1716 }
1717
1718 /*
1719 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1720 * The bit 0x80 is always 1 in CS4248 and CS4231.
1721 */
1722
1723 DDB(printk("ad1848_detect() - step G\n"));
1724
1725 if (ad_flags && *ad_flags == 400)
1726 *ad_flags = 0;
1727 else
1728 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1729
1730
1731 if (ad_flags)
1732 *ad_flags = 0;
1733
1734 tmp1 = ad_read(devc, 12);
1735 if (tmp1 & 0x80)
1736 {
1737 if (ad_flags)
1738 *ad_flags |= AD_F_CS4248;
1739
1740 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1741 }
1742 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1743 {
1744 /*
1745 * CS4231 detected - is it?
1746 *
1747 * Verify that setting I0 doesn't change I16.
1748 */
1749
1750 DDB(printk("ad1848_detect() - step H\n"));
1751 ad_write(devc, 16, 0); /* Set I16 to known value */
1752
1753 ad_write(devc, 0, 0x45);
1754 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1755 {
1756 ad_write(devc, 0, 0xaa);
1757 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1758 {
1759 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1760 return 0;
1761 }
1762
1763 /*
1764 * Verify that some bits of I25 are read only.
1765 */
1766
1767 DDB(printk("ad1848_detect() - step I\n"));
1768 tmp1 = ad_read(devc, 25); /* Original bits */
1769 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1770 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1771 {
1772 int id;
1773
1774 /*
1775 * It's at least CS4231
1776 */
1777
1778 devc->chip_name = "CS4231";
1779 devc->model = MD_4231;
1780
1781 /*
1782 * It could be an AD1845 or CS4231A as well.
1783 * CS4231 and AD1845 report the same revision info in I25
1784 * while the CS4231A reports different.
1785 */
1786
1787 id = ad_read(devc, 25);
1788 if ((id & 0xe7) == 0x80) /* Device busy??? */
1789 id = ad_read(devc, 25);
1790 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1791 id = ad_read(devc, 25);
1792 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1793
1794 if ((id & 0xe7) == 0x80) {
1795 /*
1796 * It must be a CS4231 or AD1845. The register I23 of
1797 * CS4231 is undefined and it appears to be read only.
1798 * AD1845 uses I23 for setting sample rate. Assume
1799 * the chip is AD1845 if I23 is changeable.
1800 */
1801
1802 unsigned char tmp = ad_read(devc, 23);
1803 ad_write(devc, 23, ~tmp);
1804
1805 if (interwave)
1806 {
1807 devc->model = MD_IWAVE;
1808 devc->chip_name = "IWave";
1809 }
1810 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1811 {
1812 devc->chip_name = "AD1845";
1813 devc->model = MD_1845;
1814 }
1815 else if (cs4248_flag)
1816 {
1817 if (ad_flags)
1818 *ad_flags |= AD_F_CS4248;
1819 devc->chip_name = "CS4248";
1820 devc->model = MD_1848;
1821 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1822 }
1823 ad_write(devc, 23, tmp); /* Restore */
1824 }
1825 else
1826 {
1827 switch (id & 0x1f) {
1828 case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1829 {
1830 int xid;
1831 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1832 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1833 xid = inb(io_Indexed_Data(devc));
1834 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1835 switch (xid & 0x1f)
1836 {
1837 case 0x00:
1838 devc->chip_name = "CS4237B(B)";
1839 devc->model = MD_42xB;
1840 break;
1841 case 0x08:
1842 /* Seems to be a 4238 ?? */
1843 devc->chip_name = "CS4238";
1844 devc->model = MD_42xB;
1845 break;
1846 case 0x09:
1847 devc->chip_name = "CS4238B";
1848 devc->model = MD_42xB;
1849 break;
1850 case 0x0b:
1851 devc->chip_name = "CS4236B";
1852 devc->model = MD_4236;
1853 break;
1854 case 0x10:
1855 devc->chip_name = "CS4237B";
1856 devc->model = MD_42xB;
1857 break;
1858 case 0x1d:
1859 devc->chip_name = "CS4235";
1860 devc->model = MD_4235;
1861 break;
1862 case 0x1e:
1863 devc->chip_name = "CS4239";
1864 devc->model = MD_4239;
1865 break;
1866 default:
1867 printk("Chip ident is %X.\n", xid&0x1F);
1868 devc->chip_name = "CS42xx";
1869 devc->model = MD_4232;
1870 break;
1871 }
1872 }
1873 break;
1874
1875 case 2: /* CS4232/CS4232A */
1876 devc->chip_name = "CS4232";
1877 devc->model = MD_4232;
1878 break;
1879
1880 case 0:
1881 if ((id & 0xe0) == 0xa0)
1882 {
1883 devc->chip_name = "CS4231A";
1884 devc->model = MD_4231A;
1885 }
1886 else
1887 {
1888 devc->chip_name = "CS4321";
1889 devc->model = MD_4231;
1890 }
1891 break;
1892
1893 default: /* maybe */
1894 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1895 if (optiC930)
1896 {
1897 devc->chip_name = "82C930";
1898 devc->model = MD_C930;
1899 }
1900 else
1901 {
1902 devc->chip_name = "CS4231";
1903 devc->model = MD_4231;
1904 }
1905 }
1906 }
1907 }
1908 ad_write(devc, 25, tmp1); /* Restore bits */
1909
1910 DDB(printk("ad1848_detect() - step K\n"));
1911 }
1912 } else if (tmp1 == 0x0a) {
1913 /*
1914 * Is it perhaps a SoundPro CMI8330?
1915 * If so, then we should be able to change indirect registers
1916 * greater than I15 after activating MODE2, even though reading
1917 * back I12 does not show it.
1918 */
1919
1920 /*
1921 * Let's try comparing register values
1922 */
1923 for (i = 0; i < 16; i++) {
1924 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1925 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1926 soundpro = 1;
1927 devc->chip_name = "SoundPro CMI 8330";
1928 break;
1929 }
1930 }
1931 }
1932
1933 DDB(printk("ad1848_detect() - step L\n"));
1934 if (ad_flags)
1935 {
1936 if (devc->model != MD_1848)
1937 *ad_flags |= AD_F_CS4231;
1938 }
1939 DDB(printk("ad1848_detect() - Detected OK\n"));
1940
1941 if (devc->model == MD_1848 && ad1847_flag)
1942 devc->chip_name = "AD1847";
1943
1944
1945 if (sscape_flag == 1)
1946 devc->model = MD_1845_SSCAPE;
1947
1948 return 1;
1949 }
1950
1951 int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1952 int dma_capture, int share_dma, int *osp, struct module *owner)
1953 {
1954 /*
1955 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1956 * so that this driver doesn't need to allocate/deallocate it.
1957 * The actually used IRQ is ABS(irq).
1958 */
1959
1960 int my_dev;
1961 char dev_name[100];
1962 int e;
1963
1964 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1965
1966 ad1848_port_info *portc = NULL;
1967
1968 devc->irq = (irq > 0) ? irq : 0;
1969 devc->open_mode = 0;
1970 devc->timer_ticks = 0;
1971 devc->dma1 = dma_playback;
1972 devc->dma2 = dma_capture;
1973 devc->subtype = cfg.card_subtype;
1974 devc->audio_flags = DMA_AUTOMODE;
1975 devc->playback_dev = devc->record_dev = 0;
1976 if (name != NULL)
1977 devc->name = name;
1978
1979 if (name != NULL && name[0] != 0)
1980 sprintf(dev_name,
1981 "%s (%s)", name, devc->chip_name);
1982 else
1983 sprintf(dev_name,
1984 "Generic audio codec (%s)", devc->chip_name);
1985
1986 rename_region(ports, devc->name);
1987
1988 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1989
1990 if (devc->model == MD_1848 || devc->model == MD_C930)
1991 devc->audio_flags |= DMA_HARDSTOP;
1992
1993 if (devc->model > MD_1848)
1994 {
1995 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1996 devc->audio_flags &= ~DMA_DUPLEX;
1997 else
1998 devc->audio_flags |= DMA_DUPLEX;
1999 }
2000
2001 portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
2002 if(portc==NULL) {
2003 release_region(devc->base, 4);
2004 return -1;
2005 }
2006
2007 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2008 dev_name,
2009 &ad1848_audio_driver,
2010 sizeof(struct audio_driver),
2011 devc->audio_flags,
2012 ad_format_mask[devc->model],
2013 devc,
2014 dma_playback,
2015 dma_capture)) < 0)
2016 {
2017 release_region(devc->base, 4);
2018 kfree(portc);
2019 return -1;
2020 }
2021
2022 audio_devs[my_dev]->portc = portc;
2023 audio_devs[my_dev]->mixer_dev = -1;
2024 if (owner)
2025 audio_devs[my_dev]->d->owner = owner;
2026 memset((char *) portc, 0, sizeof(*portc));
2027
2028 nr_ad1848_devs++;
2029
2030 devc->pmdev = pm_register(PM_ISA_DEV, my_dev, ad1848_pm_callback);
2031 if (devc->pmdev)
2032 devc->pmdev->data = devc;
2033
2034 ad1848_init_hw(devc);
2035
2036 if (irq > 0)
2037 {
2038 devc->dev_no = my_dev;
2039 if (request_irq(devc->irq, adintr, 0, devc->name, (void *)my_dev) < 0)
2040 {
2041 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2042 /* Don't free it either then.. */
2043 devc->irq = 0;
2044 }
2045 if (capabilities[devc->model].flags & CAP_F_TIMER)
2046 {
2047 #ifndef CONFIG_SMP
2048 int x;
2049 unsigned char tmp = ad_read(devc, 16);
2050 #endif
2051
2052 devc->timer_ticks = 0;
2053
2054 ad_write(devc, 21, 0x00); /* Timer MSB */
2055 ad_write(devc, 20, 0x10); /* Timer LSB */
2056 #ifndef CONFIG_SMP
2057 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2058 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2059 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
2060
2061 if (devc->timer_ticks == 0)
2062 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2063 else
2064 {
2065 DDB(printk("Interrupt test OK\n"));
2066 devc->irq_ok = 1;
2067 }
2068 #else
2069 devc->irq_ok = 1;
2070 #endif
2071 }
2072 else
2073 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
2074 } else if (irq < 0)
2075 irq2dev[-irq] = devc->dev_no = my_dev;
2076
2077 #ifndef EXCLUDE_TIMERS
2078 if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2079 devc->irq_ok)
2080 ad1848_tmr_install(my_dev);
2081 #endif
2082
2083 if (!share_dma)
2084 {
2085 if (sound_alloc_dma(dma_playback, devc->name))
2086 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2087
2088 if (dma_capture != dma_playback)
2089 if (sound_alloc_dma(dma_capture, devc->name))
2090 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2091 }
2092
2093 if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2094 dev_name,
2095 &ad1848_mixer_operations,
2096 sizeof(struct mixer_operations),
2097 devc)) >= 0)
2098 {
2099 audio_devs[my_dev]->mixer_dev = e;
2100 if (owner)
2101 mixer_devs[e]->owner = owner;
2102 }
2103 return my_dev;
2104 }
2105
2106 int ad1848_control(int cmd, int arg)
2107 {
2108 ad1848_info *devc;
2109 unsigned long flags;
2110
2111 if (nr_ad1848_devs < 1)
2112 return -ENODEV;
2113
2114 devc = &adev_info[nr_ad1848_devs - 1];
2115
2116 switch (cmd)
2117 {
2118 case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
2119 if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
2120 return -EINVAL;
2121 spin_lock_irqsave(&devc->lock,flags);
2122 ad_enter_MCE(devc);
2123 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2124 ad_leave_MCE(devc);
2125 spin_unlock_irqrestore(&devc->lock,flags);
2126 break;
2127
2128 case AD1848_MIXER_REROUTE:
2129 {
2130 int o = (arg >> 8) & 0xff;
2131 int n = arg & 0xff;
2132
2133 if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2134 return -EINVAL;
2135
2136 if (!(devc->supported_devices & (1 << o)) &&
2137 !(devc->supported_rec_devices & (1 << o)))
2138 return -EINVAL;
2139
2140 if (n == SOUND_MIXER_NONE)
2141 { /* Just hide this control */
2142 ad1848_mixer_set(devc, o, 0); /* Shut up it */
2143 devc->supported_devices &= ~(1 << o);
2144 devc->supported_rec_devices &= ~(1 << o);
2145 break;
2146 }
2147
2148 /* Make the mixer control identified by o to appear as n */
2149 if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2150 return -EINVAL;
2151
2152 devc->mixer_reroute[n] = o; /* Rename the control */
2153 if (devc->supported_devices & (1 << o))
2154 devc->supported_devices |= (1 << n);
2155 if (devc->supported_rec_devices & (1 << o))
2156 devc->supported_rec_devices |= (1 << n);
2157
2158 devc->supported_devices &= ~(1 << o);
2159 devc->supported_rec_devices &= ~(1 << o);
2160 }
2161 break;
2162 }
2163 return 0;
2164 }
2165
2166 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2167 {
2168 int i, mixer, dev = 0;
2169 ad1848_info *devc = NULL;
2170
2171 for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2172 {
2173 if (adev_info[i].base == io_base)
2174 {
2175 devc = &adev_info[i];
2176 dev = devc->dev_no;
2177 }
2178 }
2179
2180 if (devc != NULL)
2181 {
2182 kfree(audio_devs[dev]->portc);
2183 release_region(devc->base, 4);
2184
2185 if (!share_dma)
2186 {
2187 if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2188 free_irq(devc->irq, (void *)devc->dev_no);
2189
2190 sound_free_dma(dma_playback);
2191
2192 if (dma_playback != dma_capture)
2193 sound_free_dma(dma_capture);
2194
2195 }
2196 mixer = audio_devs[devc->dev_no]->mixer_dev;
2197 if(mixer>=0)
2198 sound_unload_mixerdev(mixer);
2199
2200 if (devc->pmdev)
2201 pm_unregister(devc->pmdev);
2202
2203 nr_ad1848_devs--;
2204 for ( ; i < nr_ad1848_devs ; i++)
2205 adev_info[i] = adev_info[i+1];
2206 }
2207 else
2208 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2209 }
2210
2211 irqreturn_t adintr(int irq, void *dev_id, struct pt_regs *dummy)
2212 {
2213 unsigned char status;
2214 ad1848_info *devc;
2215 int dev;
2216 int alt_stat = 0xff;
2217 unsigned char c930_stat = 0;
2218 int cnt = 0;
2219
2220 dev = (int)dev_id;
2221 devc = (ad1848_info *) audio_devs[dev]->devc;
2222
2223 interrupt_again: /* Jump back here if int status doesn't reset */
2224
2225 status = inb(io_Status(devc));
2226
2227 if (status == 0x80)
2228 printk(KERN_DEBUG "adintr: Why?\n");
2229 if (devc->model == MD_1848)
2230 outb((0), io_Status(devc)); /* Clear interrupt status */
2231
2232 if (status & 0x01)
2233 {
2234 if (devc->model == MD_C930)
2235 { /* 82C930 has interrupt status register in MAD16 register MC11 */
2236
2237 spin_lock(&devc->lock);
2238
2239 /* 0xe0e is C930 address port
2240 * 0xe0f is C930 data port
2241 */
2242 outb(11, 0xe0e);
2243 c930_stat = inb(0xe0f);
2244 outb((~c930_stat), 0xe0f);
2245
2246 spin_unlock(&devc->lock);
2247
2248 alt_stat = (c930_stat << 2) & 0x30;
2249 }
2250 else if (devc->model != MD_1848)
2251 {
2252 spin_lock(&devc->lock);
2253 alt_stat = ad_read(devc, 24);
2254 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2255 spin_unlock(&devc->lock);
2256 }
2257
2258 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2259 {
2260 DMAbuf_inputintr(devc->record_dev);
2261 }
2262 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2263 (alt_stat & 0x10))
2264 {
2265 DMAbuf_outputintr(devc->playback_dev, 1);
2266 }
2267 if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
2268 {
2269 devc->timer_ticks++;
2270 #ifndef EXCLUDE_TIMERS
2271 if (timer_installed == dev && devc->timer_running)
2272 sound_timer_interrupt();
2273 #endif
2274 }
2275 }
2276 /*
2277 * Sometimes playback or capture interrupts occur while a timer interrupt
2278 * is being handled. The interrupt will not be retriggered if we don't
2279 * handle it now. Check if an interrupt is still pending and restart
2280 * the handler in this case.
2281 */
2282 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2283 {
2284 goto interrupt_again;
2285 }
2286 return IRQ_HANDLED;
2287 }
2288
2289 /*
2290 * Experimental initialization sequence for the integrated sound system
2291 * of the Compaq Deskpro M.
2292 */
2293
2294 static int init_deskpro_m(struct address_info *hw_config)
2295 {
2296 unsigned char tmp;
2297
2298 if ((tmp = inb(0xc44)) == 0xff)
2299 {
2300 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2301 return 0;
2302 }
2303
2304 outb(0x10, 0xc44);
2305 outb(0x40, 0xc45);
2306 outb(0x00, 0xc46);
2307 outb(0xe8, 0xc47);
2308 outb(0x14, 0xc44);
2309 outb(0x40, 0xc45);
2310 outb(0x00, 0xc46);
2311 outb(0xe8, 0xc47);
2312 outb(0x10, 0xc44);
2313
2314 return 1;
2315 }
2316
2317 /*
2318 * Experimental initialization sequence for the integrated sound system
2319 * of Compaq Deskpro XL.
2320 */
2321
2322 static int init_deskpro(struct address_info *hw_config)
2323 {
2324 unsigned char tmp;
2325
2326 if ((tmp = inb(0xc44)) == 0xff)
2327 {
2328 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2329 return 0;
2330 }
2331 outb((tmp | 0x04), 0xc44); /* Select bank 1 */
2332 if (inb(0xc44) != 0x04)
2333 {
2334 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2335 return 0;
2336 }
2337 /*
2338 * OK. It looks like a Deskpro so let's proceed.
2339 */
2340
2341 /*
2342 * I/O port 0xc44 Audio configuration register.
2343 *
2344 * bits 0xc0: Audio revision bits
2345 * 0x00 = Compaq Business Audio
2346 * 0x40 = MS Sound System Compatible (reset default)
2347 * 0x80 = Reserved
2348 * 0xc0 = Reserved
2349 * bit 0x20: No Wait State Enable
2350 * 0x00 = Disabled (reset default, DMA mode)
2351 * 0x20 = Enabled (programmed I/O mode)
2352 * bit 0x10: MS Sound System Decode Enable
2353 * 0x00 = Decoding disabled (reset default)
2354 * 0x10 = Decoding enabled
2355 * bit 0x08: FM Synthesis Decode Enable
2356 * 0x00 = Decoding Disabled (reset default)
2357 * 0x08 = Decoding enabled
2358 * bit 0x04 Bank select
2359 * 0x00 = Bank 0
2360 * 0x04 = Bank 1
2361 * bits 0x03 MSS Base address
2362 * 0x00 = 0x530 (reset default)
2363 * 0x01 = 0x604
2364 * 0x02 = 0xf40
2365 * 0x03 = 0xe80
2366 */
2367
2368 #ifdef DEBUGXL
2369 /* Debug printing */
2370 printk("Port 0xc44 (before): ");
2371 outb((tmp & ~0x04), 0xc44);
2372 printk("%02x ", inb(0xc44));
2373 outb((tmp | 0x04), 0xc44);
2374 printk("%02x\n", inb(0xc44));
2375 #endif
2376
2377 /* Set bank 1 of the register */
2378 tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
2379
2380 switch (hw_config->io_base)
2381 {
2382 case 0x530:
2383 tmp |= 0x00;
2384 break;
2385 case 0x604:
2386 tmp |= 0x01;
2387 break;
2388 case 0xf40:
2389 tmp |= 0x02;
2390 break;
2391 case 0xe80:
2392 tmp |= 0x03;
2393 break;
2394 default:
2395 DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2396 return 0;
2397 }
2398 outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
2399
2400 #ifdef DEBUGXL
2401 /* Debug printing */
2402 printk("Port 0xc44 (after): ");
2403 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2404 printk("%02x ", inb(0xc44));
2405 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2406 printk("%02x\n", inb(0xc44));
2407 #endif
2408
2409 /*
2410 * I/O port 0xc45 FM Address Decode/MSS ID Register.
2411 *
2412 * bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
2413 * bank=0, bit 0x01: SBIC Power Control Bit
2414 * 0x00 = Powered up
2415 * 0x01 = Powered down
2416 * bank=1, bits 0xfc: MSS ID (default=0x40)
2417 */
2418
2419 #ifdef DEBUGXL
2420 /* Debug printing */
2421 printk("Port 0xc45 (before): ");
2422 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2423 printk("%02x ", inb(0xc45));
2424 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2425 printk("%02x\n", inb(0xc45));
2426 #endif
2427
2428 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2429 outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
2430 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2431 outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
2432
2433 #ifdef DEBUGXL
2434 /* Debug printing */
2435 printk("Port 0xc45 (after): ");
2436 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2437 printk("%02x ", inb(0xc45));
2438 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2439 printk("%02x\n", inb(0xc45));
2440 #endif
2441
2442
2443 /*
2444 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2445 *
2446 * bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
2447 * bank=1, bits 0xff: Audio addressing ASIC id
2448 */
2449
2450 #ifdef DEBUGXL
2451 /* Debug printing */
2452 printk("Port 0xc46 (before): ");
2453 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2454 printk("%02x ", inb(0xc46));
2455 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2456 printk("%02x\n", inb(0xc46));
2457 #endif
2458
2459 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2460 outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
2461 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2462 outb((0x11), 0xc46); /* ASIC ID = 0x11 */
2463
2464 #ifdef DEBUGXL
2465 /* Debug printing */
2466 printk("Port 0xc46 (after): ");
2467 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2468 printk("%02x ", inb(0xc46));
2469 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2470 printk("%02x\n", inb(0xc46));
2471 #endif
2472
2473 /*
2474 * I/O port 0xc47 FM Address Decode Register.
2475 *
2476 * bank=0, bits 0xff: Decode enable selection for various FM address bits
2477 * bank=1, bits 0xff: Reserved
2478 */
2479
2480 #ifdef DEBUGXL
2481 /* Debug printing */
2482 printk("Port 0xc47 (before): ");
2483 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2484 printk("%02x ", inb(0xc47));
2485 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2486 printk("%02x\n", inb(0xc47));
2487 #endif
2488
2489 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2490 outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
2491 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2492 outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
2493
2494 #ifdef DEBUGXL
2495 /* Debug printing */
2496 printk("Port 0xc47 (after): ");
2497 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2498 printk("%02x ", inb(0xc47));
2499 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2500 printk("%02x\n", inb(0xc47));
2501 #endif
2502
2503 /*
2504 * I/O port 0xc6f = Audio Disable Function Register
2505 */
2506
2507 #ifdef DEBUGXL
2508 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2509 #endif
2510
2511 outb((0x80), 0xc6f);
2512
2513 #ifdef DEBUGXL
2514 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2515 #endif
2516
2517 return 1;
2518 }
2519
2520 int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
2521 {
2522 unsigned char tmp;
2523
2524 DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2525
2526 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2527 {
2528 /* check_opl3(0x388, hw_config); */
2529 return ad1848_detect(ports, NULL, hw_config->osp);
2530 }
2531
2532 if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2533 {
2534 if (!init_deskpro(hw_config))
2535 return 0;
2536 }
2537
2538 if (deskpro_m) /* Compaq Deskpro M */
2539 {
2540 if (!init_deskpro_m(hw_config))
2541 return 0;
2542 }
2543
2544 /*
2545 * Check if the IO port returns valid signature. The original MS Sound
2546 * system returns 0x04 while some cards (AudioTrix Pro for example)
2547 * return 0x00 or 0x0f.
2548 */
2549
2550 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
2551 {
2552 int ret;
2553
2554 DDB(printk("I/O address is inactive (%x)\n", tmp));
2555 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2556 return 0;
2557 return 1;
2558 }
2559 DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2560 if ((tmp & 0x3f) != 0x04 &&
2561 (tmp & 0x3f) != 0x0f &&
2562 (tmp & 0x3f) != 0x00)
2563 {
2564 int ret;
2565
2566 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2567 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2568 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2569 return 0;
2570
2571 hw_config->card_subtype = 1;
2572 return 1;
2573 }
2574 if ((hw_config->irq != 5) &&
2575 (hw_config->irq != 7) &&
2576 (hw_config->irq != 9) &&
2577 (hw_config->irq != 10) &&
2578 (hw_config->irq != 11) &&
2579 (hw_config->irq != 12))
2580 {
2581 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2582 return 0;
2583 }
2584 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2585 {
2586 printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2587 return 0;
2588 }
2589 /*
2590 * Check that DMA0 is not in use with a 8 bit board.
2591 */
2592
2593 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2594 {
2595 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2596 return 0;
2597 }
2598 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2599 {
2600 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2601 return 0;
2602 }
2603 return ad1848_detect(ports, NULL, hw_config->osp);
2604 }
2605
2606 void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
2607 {
2608 static signed char interrupt_bits[12] =
2609 {
2610 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2611 };
2612 signed char bits;
2613 char dma2_bit = 0;
2614
2615 static char dma_bits[4] =
2616 {
2617 1, 2, 0, 3
2618 };
2619
2620 int config_port = hw_config->io_base + 0;
2621 int version_port = hw_config->io_base + 3;
2622 int dma = hw_config->dma;
2623 int dma2 = hw_config->dma2;
2624
2625 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2626 {
2627 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2628 hw_config->irq,
2629 hw_config->dma,
2630 hw_config->dma2, 0,
2631 hw_config->osp,
2632 owner);
2633 return;
2634 }
2635 /*
2636 * Set the IRQ and DMA addresses.
2637 */
2638
2639 bits = interrupt_bits[hw_config->irq];
2640 if (bits == -1)
2641 {
2642 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2643 release_region(ports->start, 4);
2644 release_region(ports->start - 4, 4);
2645 return;
2646 }
2647 outb((bits | 0x40), config_port);
2648 if ((inb(version_port) & 0x40) == 0)
2649 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2650
2651 /*
2652 * Handle the capture DMA channel
2653 */
2654
2655 if (dma2 != -1 && dma2 != dma)
2656 {
2657 if (!((dma == 0 && dma2 == 1) ||
2658 (dma == 1 && dma2 == 0) ||
2659 (dma == 3 && dma2 == 0)))
2660 { /* Unsupported combination. Try to swap channels */
2661 int tmp = dma;
2662
2663 dma = dma2;
2664 dma2 = tmp;
2665 }
2666 if ((dma == 0 && dma2 == 1) ||
2667 (dma == 1 && dma2 == 0) ||
2668 (dma == 3 && dma2 == 0))
2669 {
2670 dma2_bit = 0x04; /* Enable capture DMA */
2671 }
2672 else
2673 {
2674 printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2675 dma2 = dma;
2676 }
2677 }
2678 else
2679 {
2680 dma2 = dma;
2681 }
2682
2683 hw_config->dma = dma;
2684 hw_config->dma2 = dma2;
2685
2686 outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
2687
2688 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2689 hw_config->irq,
2690 dma, dma2, 0,
2691 hw_config->osp,
2692 THIS_MODULE);
2693 }
2694
2695 void unload_ms_sound(struct address_info *hw_config)
2696 {
2697 ad1848_unload(hw_config->io_base + 4,
2698 hw_config->irq,
2699 hw_config->dma,
2700 hw_config->dma2, 0);
2701 sound_unload_audiodev(hw_config->slots[0]);
2702 release_region(hw_config->io_base, 4);
2703 }
2704
2705 #ifndef EXCLUDE_TIMERS
2706
2707 /*
2708 * Timer stuff (for /dev/music).
2709 */
2710
2711 static unsigned int current_interval;
2712
2713 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2714 {
2715 unsigned long flags;
2716 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2717 unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
2718 unsigned long divider;
2719
2720 spin_lock_irqsave(&devc->lock,flags);
2721
2722 /*
2723 * Length of the timer interval (in nanoseconds) depends on the
2724 * selected crystal oscillator. Check this from bit 0x01 of I8.
2725 *
2726 * AD1845 has just one oscillator which has cycle time of 10.050 us
2727 * (when a 24.576 MHz xtal oscillator is used).
2728 *
2729 * Convert requested interval to nanoseconds before computing
2730 * the timer divider.
2731 */
2732
2733 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2734 xtal_nsecs = 10050;
2735 else if (ad_read(devc, 8) & 0x01)
2736 xtal_nsecs = 9920;
2737 else
2738 xtal_nsecs = 9969;
2739
2740 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2741
2742 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
2743 divider = 100;
2744
2745 if (divider > 65535) /* Overflow check */
2746 divider = 65535;
2747
2748 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2749 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2750 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2751 devc->timer_running = 1;
2752 spin_unlock_irqrestore(&devc->lock,flags);
2753
2754 return current_interval = (divider * xtal_nsecs + 500) / 1000;
2755 }
2756
2757 static void ad1848_tmr_reprogram(int dev)
2758 {
2759 /*
2760 * Audio driver has changed sampling rate so that a different xtal
2761 * oscillator was selected. We have to reprogram the timer rate.
2762 */
2763
2764 ad1848_tmr_start(dev, current_interval);
2765 sound_timer_syncinterval(current_interval);
2766 }
2767
2768 static void ad1848_tmr_disable(int dev)
2769 {
2770 unsigned long flags;
2771 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2772
2773 spin_lock_irqsave(&devc->lock,flags);
2774 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2775 devc->timer_running = 0;
2776 spin_unlock_irqrestore(&devc->lock,flags);
2777 }
2778
2779 static void ad1848_tmr_restart(int dev)
2780 {
2781 unsigned long flags;
2782 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2783
2784 if (current_interval == 0)
2785 return;
2786
2787 spin_lock_irqsave(&devc->lock,flags);
2788 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2789 devc->timer_running = 1;
2790 spin_unlock_irqrestore(&devc->lock,flags);
2791 }
2792
2793 static struct sound_lowlev_timer ad1848_tmr =
2794 {
2795 0,
2796 2,
2797 ad1848_tmr_start,
2798 ad1848_tmr_disable,
2799 ad1848_tmr_restart
2800 };
2801
2802 static int ad1848_tmr_install(int dev)
2803 {
2804 if (timer_installed != -1)
2805 return 0; /* Don't install another timer */
2806
2807 timer_installed = ad1848_tmr.dev = dev;
2808 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2809
2810 return 1;
2811 }
2812 #endif /* EXCLUDE_TIMERS */
2813
2814 static int ad1848_suspend(ad1848_info *devc)
2815 {
2816 unsigned long flags;
2817
2818 spin_lock_irqsave(&devc->lock,flags);
2819
2820 ad_mute(devc);
2821
2822 spin_unlock_irqrestore(&devc->lock,flags);
2823 return 0;
2824 }
2825
2826 static int ad1848_resume(ad1848_info *devc)
2827 {
2828 int mixer_levels[32], i;
2829
2830 /* Thinkpad is a bit more of PITA than normal. The BIOS tends to
2831 restore it in a different config to the one we use. Need to
2832 fix this somehow */
2833
2834 /* store old mixer levels */
2835 memcpy(mixer_levels, devc->levels, sizeof (mixer_levels));
2836 ad1848_init_hw(devc);
2837
2838 /* restore mixer levels */
2839 for (i = 0; i < 32; i++)
2840 ad1848_mixer_set(devc, devc->dev_no, mixer_levels[i]);
2841
2842 if (!devc->subtype) {
2843 static signed char interrupt_bits[12] = { -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20 };
2844 static char dma_bits[4] = { 1, 2, 0, 3 };
2845 unsigned long flags;
2846 signed char bits;
2847 char dma2_bit = 0;
2848
2849 int config_port = devc->base + 0;
2850
2851 bits = interrupt_bits[devc->irq];
2852 if (bits == -1) {
2853 printk(KERN_ERR "MSS: Bad IRQ %d\n", devc->irq);
2854 return -1;
2855 }
2856
2857 spin_lock_irqsave(&devc->lock,flags);
2858
2859 outb((bits | 0x40), config_port);
2860
2861 if (devc->dma2 != -1 && devc->dma2 != devc->dma1)
2862 if ( (devc->dma1 == 0 && devc->dma2 == 1) ||
2863 (devc->dma1 == 1 && devc->dma2 == 0) ||
2864 (devc->dma1 == 3 && devc->dma2 == 0))
2865 dma2_bit = 0x04;
2866
2867 outb((bits | dma_bits[devc->dma1] | dma2_bit), config_port);
2868 spin_unlock_irqrestore(&devc->lock,flags);
2869 }
2870
2871 return 0;
2872 }
2873
2874 static int ad1848_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
2875 {
2876 ad1848_info *devc = dev->data;
2877 if (devc) {
2878 DEB(printk("ad1848: pm event received: 0x%x\n", rqst));
2879
2880 switch (rqst) {
2881 case PM_SUSPEND:
2882 ad1848_suspend(devc);
2883 break;
2884 case PM_RESUME:
2885 ad1848_resume(devc);
2886 break;
2887 }
2888 }
2889 return 0;
2890 }
2891
2892
2893 EXPORT_SYMBOL(ad1848_detect);
2894 EXPORT_SYMBOL(ad1848_init);
2895 EXPORT_SYMBOL(ad1848_unload);
2896 EXPORT_SYMBOL(ad1848_control);
2897 EXPORT_SYMBOL(adintr);
2898 EXPORT_SYMBOL(probe_ms_sound);
2899 EXPORT_SYMBOL(attach_ms_sound);
2900 EXPORT_SYMBOL(unload_ms_sound);
2901
2902 static int __initdata io = -1;
2903 static int __initdata irq = -1;
2904 static int __initdata dma = -1;
2905 static int __initdata dma2 = -1;
2906 static int __initdata type = 0;
2907
2908 module_param(io, int, 0); /* I/O for a raw AD1848 card */
2909 module_param(irq, int, 0); /* IRQ to use */
2910 module_param(dma, int, 0); /* First DMA channel */
2911 module_param(dma2, int, 0); /* Second DMA channel */
2912 module_param(type, int, 0); /* Card type */
2913 module_param(deskpro_xl, bool, 0); /* Special magic for Deskpro XL boxen */
2914 module_param(deskpro_m, bool, 0); /* Special magic for Deskpro M box */
2915 module_param(soundpro, bool, 0); /* More special magic for SoundPro chips */
2916
2917 #ifdef CONFIG_PNP
2918 module_param(isapnp, int, 0);
2919 module_param(isapnpjump, int, 0);
2920 module_param(reverse, bool, 0);
2921 MODULE_PARM_DESC(isapnp, "When set to 0, Plug & Play support will be disabled");
2922 MODULE_PARM_DESC(isapnpjump, "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2923 MODULE_PARM_DESC(reverse, "When set to 1, will reverse ISAPnP search order");
2924
2925 static struct pnp_dev *ad1848_dev = NULL;
2926
2927 /* Please add new entries at the end of the table */
2928 static struct {
2929 char *name;
2930 unsigned short card_vendor, card_device,
2931 vendor, function;
2932 short mss_io, irq, dma, dma2; /* index into isapnp table */
2933 int type;
2934 } ad1848_isapnp_list[] __initdata = {
2935 {"CMI 8330 SoundPRO",
2936 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2937 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2938 0, 0, 0,-1, 0},
2939 {"CS4232 based card",
2940 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2941 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2942 0, 0, 0, 1, 0},
2943 {"CS4232 based card",
2944 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2945 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2946 0, 0, 0, 1, 0},
2947 {"OPL3-SA2 WSS mode",
2948 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2949 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2950 1, 0, 0, 1, 1},
2951 {"Advanced Gravis InterWave Audio",
2952 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2953 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2954 0, 0, 0, 1, 0},
2955 {NULL}
2956 };
2957
2958 static struct isapnp_device_id id_table[] __devinitdata = {
2959 { ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2960 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2961 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2962 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2963 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2964 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2965 /* The main driver for this card is opl3sa2
2966 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2967 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2968 */
2969 { ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2970 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2971 {0}
2972 };
2973
2974 MODULE_DEVICE_TABLE(isapnp, id_table);
2975
2976 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2977 {
2978 int err;
2979
2980 err = pnp_device_attach(dev);
2981 if (err < 0)
2982 return(NULL);
2983
2984 if((err = pnp_activate_dev(dev)) < 0) {
2985 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2986
2987 pnp_device_detach(dev);
2988
2989 return(NULL);
2990 }
2991 audio_activated = 1;
2992 return(dev);
2993 }
2994
2995 static struct pnp_dev *ad1848_init_generic(struct pnp_card *bus, struct address_info *hw_config, int slot)
2996 {
2997
2998 /* Configure Audio device */
2999 if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
3000 {
3001 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
3002 {
3003 hw_config->io_base = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
3004 hw_config->irq = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
3005 hw_config->dma = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
3006 if(ad1848_isapnp_list[slot].dma2 != -1)
3007 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
3008 else
3009 hw_config->dma2 = -1;
3010 hw_config->card_subtype = ad1848_isapnp_list[slot].type;
3011 } else
3012 return(NULL);
3013 } else
3014 return(NULL);
3015
3016 return(ad1848_dev);
3017 }
3018
3019 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
3020 {
3021 char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
3022
3023 /* Initialize this baby. */
3024
3025 if(ad1848_init_generic(bus, hw_config, slot)) {
3026 /* We got it. */
3027
3028 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
3029 busname,
3030 hw_config->io_base, hw_config->irq, hw_config->dma,
3031 hw_config->dma2);
3032 return 1;
3033 }
3034 return 0;
3035 }
3036
3037 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
3038 {
3039 static int first = 1;
3040 int i;
3041
3042 /* Count entries in sb_isapnp_list */
3043 for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
3044 i--;
3045
3046 /* Check and adjust isapnpjump */
3047 if( isapnpjump < 0 || isapnpjump > i) {
3048 isapnpjump = reverse ? i : 0;
3049 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
3050 }
3051
3052 if(!first || !reverse)
3053 i = isapnpjump;
3054 first = 0;
3055 while(ad1848_isapnp_list[i].card_vendor != 0) {
3056 static struct pnp_card *bus = NULL;
3057
3058 while ((bus = pnp_find_card(
3059 ad1848_isapnp_list[i].card_vendor,
3060 ad1848_isapnp_list[i].card_device,
3061 bus))) {
3062
3063 if(ad1848_isapnp_init(hw_config, bus, i)) {
3064 isapnpjump = i; /* start next search from here */
3065 return 0;
3066 }
3067 }
3068 i += reverse ? -1 : 1;
3069 }
3070
3071 return -ENODEV;
3072 }
3073 #endif
3074
3075
3076 static int __init init_ad1848(void)
3077 {
3078 printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
3079
3080 #ifdef CONFIG_PNP
3081 if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
3082 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
3083 isapnp = 0;
3084 }
3085 #endif
3086
3087 if(io != -1) {
3088 struct resource *ports;
3089 if( isapnp == 0 )
3090 {
3091 if(irq == -1 || dma == -1) {
3092 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3093 return -EINVAL;
3094 }
3095
3096 cfg.irq = irq;
3097 cfg.io_base = io;
3098 cfg.dma = dma;
3099 cfg.dma2 = dma2;
3100 cfg.card_subtype = type;
3101 }
3102
3103 ports = request_region(io + 4, 4, "ad1848");
3104
3105 if (!ports)
3106 return -EBUSY;
3107
3108 if (!request_region(io, 4, "WSS config")) {
3109 release_region(io + 4, 4);
3110 return -EBUSY;
3111 }
3112
3113 if (!probe_ms_sound(&cfg, ports)) {
3114 release_region(io + 4, 4);
3115 release_region(io, 4);
3116 return -ENODEV;
3117 }
3118 attach_ms_sound(&cfg, ports, THIS_MODULE);
3119 loaded = 1;
3120 }
3121 return 0;
3122 }
3123
3124 static void __exit cleanup_ad1848(void)
3125 {
3126 if(loaded)
3127 unload_ms_sound(&cfg);
3128
3129 #ifdef CONFIG_PNP
3130 if(ad1848_dev){
3131 if(audio_activated)
3132 pnp_device_detach(ad1848_dev);
3133 }
3134 #endif
3135 }
3136
3137 module_init(init_ad1848);
3138 module_exit(cleanup_ad1848);
3139
3140 #ifndef MODULE
3141 static int __init setup_ad1848(char *str)
3142 {
3143 /* io, irq, dma, dma2, type */
3144 int ints[6];
3145
3146 str = get_options(str, ARRAY_SIZE(ints), ints);
3147
3148 io = ints[1];
3149 irq = ints[2];
3150 dma = ints[3];
3151 dma2 = ints[4];
3152 type = ints[5];
3153
3154 return 1;
3155 }
3156
3157 __setup("ad1848=", setup_ad1848);
3158 #endif
3159 MODULE_LICENSE("GPL");
Linux with added FPC-III support