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[IPV4]: Fix secondary IP addresses after promotion
[linux/fpc-iii.git] / sound / oss / hal2.c
blobafe97c4ce069a5e28caab718327010185812ee8d
1 /*
2 * Driver for A2 audio system used in SGI machines
3 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
4 *
5 * Based on Ulf Carlsson's code.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 * Supported devices:
21 * /dev/dsp standard dsp device, (mostly) OSS compatible
22 * /dev/mixer standard mixer device, (mostly) OSS compatible
23 *
24 */
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
29 #include <linux/slab.h>
30 #include <linux/poll.h>
31 #include <linux/interrupt.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/sound.h>
34 #include <linux/soundcard.h>
35
36 #include <asm/io.h>
37 #include <asm/sgi/hpc3.h>
38 #include <asm/sgi/ip22.h>
39
40 #include "hal2.h"
41
42 #if 0
43 #define DEBUG(args...) printk(args)
44 #else
45 #define DEBUG(args...)
46 #endif
47
48 #if 0
49 #define DEBUG_MIX(args...) printk(args)
50 #else
51 #define DEBUG_MIX(args...)
52 #endif
53
54 /*
55 * Before touching these look how it works. It is a bit unusual I know,
56 * but it helps to keep things simple. This driver is considered complete
57 * and I won't add any new features although hardware has many cool
58 * capabilities.
59 * (Historical note: HAL2 driver was first written by Ulf Carlsson - ALSA
60 * 0.3 running with 2.2.x kernel. Then ALSA changed completely and it
61 * seemed easier to me to write OSS driver from scratch - this one. Now
62 * when ALSA is official part of 2.6 kernel it's time to write ALSA driver
63 * using (hopefully) final version of ALSA interface)
64 */
65 #define H2_BLOCK_SIZE 1024
66 #define H2_ADC_BUFSIZE 8192
67 #define H2_DAC_BUFSIZE 16834
68
69 struct hal2_pbus {
70 struct hpc3_pbus_dmacregs *pbus;
71 int pbusnr;
72 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */
73 };
74
75 struct hal2_desc {
76 struct hpc_dma_desc desc;
77 u32 cnt; /* don't touch, it is also padding */
78 };
79
80 struct hal2_codec {
81 unsigned char *buffer;
82 struct hal2_desc *desc;
83 int desc_count;
84 int tail, head; /* tail index, head index */
85 struct hal2_pbus pbus;
86 unsigned int format; /* Audio data format */
87 int voices; /* mono/stereo */
88 unsigned int sample_rate;
89 unsigned int master; /* Master frequency */
90 unsigned short mod; /* MOD value */
91 unsigned short inc; /* INC value */
92
93 wait_queue_head_t dma_wait;
94 spinlock_t lock;
95 struct semaphore sem;
96
97 int usecount; /* recording and playback are
98 * independent */
99 };
100
101 #define H2_MIX_OUTPUT_ATT 0
102 #define H2_MIX_INPUT_GAIN 1
103 #define H2_MIXERS 2
104 struct hal2_mixer {
105 int modcnt;
106 unsigned int master;
107 unsigned int volume[H2_MIXERS];
108 };
109
110 struct hal2_card {
111 int dev_dsp; /* audio device */
112 int dev_mixer; /* mixer device */
113 int dev_midi; /* midi device */
114
115 struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
116 struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
117 struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
118 struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
119
120 struct hal2_codec dac;
121 struct hal2_codec adc;
122 struct hal2_mixer mixer;
123 };
124
125 #define H2_INDIRECT_WAIT(regs) while (regs->isr & H2_ISR_TSTATUS);
126
127 #define H2_READ_ADDR(addr) (addr | (1<<7))
128 #define H2_WRITE_ADDR(addr) (addr)
129
130 static char *hal2str = "HAL2";
131
132 /*
133 * I doubt anyone has a machine with two HAL2 cards. It's possible to
134 * have two HPC's, so it is probably possible to have two HAL2 cards.
135 * Try to deal with it, but note that it is not tested.
136 */
137 #define MAXCARDS 2
138 static struct hal2_card* hal2_card[MAXCARDS];
139
140 static const struct {
141 unsigned char idx:4, avail:1;
142 } mixtable[SOUND_MIXER_NRDEVICES] = {
143 [SOUND_MIXER_PCM] = { H2_MIX_OUTPUT_ATT, 1 }, /* voice */
144 [SOUND_MIXER_MIC] = { H2_MIX_INPUT_GAIN, 1 }, /* mic */
145 };
146
147 #define H2_SUPPORTED_FORMATS (AFMT_S16_LE | AFMT_S16_BE)
148
149 static inline void hal2_isr_write(struct hal2_card *hal2, u16 val)
150 {
151 hal2->ctl_regs->isr = val;
152 }
153
154 static inline u16 hal2_isr_look(struct hal2_card *hal2)
155 {
156 return hal2->ctl_regs->isr;
157 }
158
159 static inline u16 hal2_rev_look(struct hal2_card *hal2)
160 {
161 return hal2->ctl_regs->rev;
162 }
163
164 #ifdef HAL2_DUMP_REGS
165 static u16 hal2_i_look16(struct hal2_card *hal2, u16 addr)
166 {
167 struct hal2_ctl_regs *regs = hal2->ctl_regs;
168
169 regs->iar = H2_READ_ADDR(addr);
170 H2_INDIRECT_WAIT(regs);
171 return regs->idr0;
172 }
173 #endif
174
175 static u32 hal2_i_look32(struct hal2_card *hal2, u16 addr)
176 {
177 u32 ret;
178 struct hal2_ctl_regs *regs = hal2->ctl_regs;
179
180 regs->iar = H2_READ_ADDR(addr);
181 H2_INDIRECT_WAIT(regs);
182 ret = regs->idr0 & 0xffff;
183 regs->iar = H2_READ_ADDR(addr | 0x1);
184 H2_INDIRECT_WAIT(regs);
185 ret |= (regs->idr0 & 0xffff) << 16;
186 return ret;
187 }
188
189 static void hal2_i_write16(struct hal2_card *hal2, u16 addr, u16 val)
190 {
191 struct hal2_ctl_regs *regs = hal2->ctl_regs;
192
193 regs->idr0 = val;
194 regs->idr1 = 0;
195 regs->idr2 = 0;
196 regs->idr3 = 0;
197 regs->iar = H2_WRITE_ADDR(addr);
198 H2_INDIRECT_WAIT(regs);
199 }
200
201 static void hal2_i_write32(struct hal2_card *hal2, u16 addr, u32 val)
202 {
203 struct hal2_ctl_regs *regs = hal2->ctl_regs;
204
205 regs->idr0 = val & 0xffff;
206 regs->idr1 = val >> 16;
207 regs->idr2 = 0;
208 regs->idr3 = 0;
209 regs->iar = H2_WRITE_ADDR(addr);
210 H2_INDIRECT_WAIT(regs);
211 }
212
213 static void hal2_i_setbit16(struct hal2_card *hal2, u16 addr, u16 bit)
214 {
215 struct hal2_ctl_regs *regs = hal2->ctl_regs;
216
217 regs->iar = H2_READ_ADDR(addr);
218 H2_INDIRECT_WAIT(regs);
219 regs->idr0 = (regs->idr0 & 0xffff) | bit;
220 regs->idr1 = 0;
221 regs->idr2 = 0;
222 regs->idr3 = 0;
223 regs->iar = H2_WRITE_ADDR(addr);
224 H2_INDIRECT_WAIT(regs);
225 }
226
227 static void hal2_i_setbit32(struct hal2_card *hal2, u16 addr, u32 bit)
228 {
229 u32 tmp;
230 struct hal2_ctl_regs *regs = hal2->ctl_regs;
231
232 regs->iar = H2_READ_ADDR(addr);
233 H2_INDIRECT_WAIT(regs);
234 tmp = (regs->idr0 & 0xffff) | (regs->idr1 << 16) | bit;
235 regs->idr0 = tmp & 0xffff;
236 regs->idr1 = tmp >> 16;
237 regs->idr2 = 0;
238 regs->idr3 = 0;
239 regs->iar = H2_WRITE_ADDR(addr);
240 H2_INDIRECT_WAIT(regs);
241 }
242
243 static void hal2_i_clearbit16(struct hal2_card *hal2, u16 addr, u16 bit)
244 {
245 struct hal2_ctl_regs *regs = hal2->ctl_regs;
246
247 regs->iar = H2_READ_ADDR(addr);
248 H2_INDIRECT_WAIT(regs);
249 regs->idr0 = (regs->idr0 & 0xffff) & ~bit;
250 regs->idr1 = 0;
251 regs->idr2 = 0;
252 regs->idr3 = 0;
253 regs->iar = H2_WRITE_ADDR(addr);
254 H2_INDIRECT_WAIT(regs);
255 }
256
257 #if 0
258 static void hal2_i_clearbit32(struct hal2_card *hal2, u16 addr, u32 bit)
259 {
260 u32 tmp;
261 hal2_ctl_regs_t *regs = hal2->ctl_regs;
262
263 regs->iar = H2_READ_ADDR(addr);
264 H2_INDIRECT_WAIT(regs);
265 tmp = ((regs->idr0 & 0xffff) | (regs->idr1 << 16)) & ~bit;
266 regs->idr0 = tmp & 0xffff;
267 regs->idr1 = tmp >> 16;
268 regs->idr2 = 0;
269 regs->idr3 = 0;
270 regs->iar = H2_WRITE_ADDR(addr);
271 H2_INDIRECT_WAIT(regs);
272 }
273 #endif
274
275 #ifdef HAL2_DUMP_REGS
276 static void hal2_dump_regs(struct hal2_card *hal2)
277 {
278 DEBUG("isr: %08hx ", hal2_isr_look(hal2));
279 DEBUG("rev: %08hx\n", hal2_rev_look(hal2));
280 DEBUG("relay: %04hx\n", hal2_i_look16(hal2, H2I_RELAY_C));
281 DEBUG("port en: %04hx ", hal2_i_look16(hal2, H2I_DMA_PORT_EN));
282 DEBUG("dma end: %04hx ", hal2_i_look16(hal2, H2I_DMA_END));
283 DEBUG("dma drv: %04hx\n", hal2_i_look16(hal2, H2I_DMA_DRV));
284 DEBUG("syn ctl: %04hx ", hal2_i_look16(hal2, H2I_SYNTH_C));
285 DEBUG("aesrx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESRX_C));
286 DEBUG("aestx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESTX_C));
287 DEBUG("dac ctl1: %04hx ", hal2_i_look16(hal2, H2I_ADC_C1));
288 DEBUG("dac ctl2: %08x ", hal2_i_look32(hal2, H2I_ADC_C2));
289 DEBUG("adc ctl1: %04hx ", hal2_i_look16(hal2, H2I_DAC_C1));
290 DEBUG("adc ctl2: %08x ", hal2_i_look32(hal2, H2I_DAC_C2));
291 DEBUG("syn map: %04hx\n", hal2_i_look16(hal2, H2I_SYNTH_MAP_C));
292 DEBUG("bres1 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES1_C1));
293 DEBUG("bres1 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES1_C2));
294 DEBUG("bres2 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES2_C1));
295 DEBUG("bres2 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES2_C2));
296 DEBUG("bres3 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES3_C1));
297 DEBUG("bres3 ctl2: %04x\n", hal2_i_look32(hal2, H2I_BRES3_C2));
298 }
299 #endif
300
301 static struct hal2_card* hal2_dsp_find_card(int minor)
302 {
303 int i;
304
305 for (i = 0; i < MAXCARDS; i++)
306 if (hal2_card[i] != NULL && hal2_card[i]->dev_dsp == minor)
307 return hal2_card[i];
308 return NULL;
309 }
310
311 static struct hal2_card* hal2_mixer_find_card(int minor)
312 {
313 int i;
314
315 for (i = 0; i < MAXCARDS; i++)
316 if (hal2_card[i] != NULL && hal2_card[i]->dev_mixer == minor)
317 return hal2_card[i];
318 return NULL;
319 }
320
321 static void hal2_inc_head(struct hal2_codec *codec)
322 {
323 codec->head++;
324 if (codec->head == codec->desc_count)
325 codec->head = 0;
326 }
327
328 static void hal2_inc_tail(struct hal2_codec *codec)
329 {
330 codec->tail++;
331 if (codec->tail == codec->desc_count)
332 codec->tail = 0;
333 }
334
335 static void hal2_dac_interrupt(struct hal2_codec *dac)
336 {
337 int running;
338
339 spin_lock(&dac->lock);
340 /* if tail buffer contains zero samples DMA stream was already
341 * stopped */
342 running = dac->desc[dac->tail].cnt;
343 dac->desc[dac->tail].cnt = 0;
344 dac->desc[dac->tail].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOX;
345 /* we just proccessed empty buffer, don't update tail pointer */
346 if (running)
347 hal2_inc_tail(dac);
348 spin_unlock(&dac->lock);
349
350 wake_up(&dac->dma_wait);
351 }
352
353 static void hal2_adc_interrupt(struct hal2_codec *adc)
354 {
355 int running;
356
357 spin_lock(&adc->lock);
358 /* if head buffer contains nonzero samples DMA stream was already
359 * stopped */
360 running = !adc->desc[adc->head].cnt;
361 adc->desc[adc->head].cnt = H2_BLOCK_SIZE;
362 adc->desc[adc->head].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOR;
363 /* we just proccessed empty buffer, don't update head pointer */
364 if (running)
365 hal2_inc_head(adc);
366 spin_unlock(&adc->lock);
367
368 wake_up(&adc->dma_wait);
369 }
370
371 static irqreturn_t hal2_interrupt(int irq, void *dev_id, struct pt_regs *regs)
372 {
373 struct hal2_card *hal2 = (struct hal2_card*)dev_id;
374 irqreturn_t ret = IRQ_NONE;
375
376 /* decide what caused this interrupt */
377 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
378 hal2_dac_interrupt(&hal2->dac);
379 ret = IRQ_HANDLED;
380 }
381 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
382 hal2_adc_interrupt(&hal2->adc);
383 ret = IRQ_HANDLED;
384 }
385 return ret;
386 }
387
388 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
389 {
390 unsigned short mod;
391
392 DEBUG("rate: %d\n", rate);
393
394 if (rate < 4000) rate = 4000;
395 else if (rate > 48000) rate = 48000;
396
397 if (44100 % rate < 48000 % rate) {
398 mod = 4 * 44100 / rate;
399 codec->master = 44100;
400 } else {
401 mod = 4 * 48000 / rate;
402 codec->master = 48000;
403 }
404
405 codec->inc = 4;
406 codec->mod = mod;
407 rate = 4 * codec->master / mod;
408
409 DEBUG("real_rate: %d\n", rate);
410
411 return rate;
412 }
413
414 static void hal2_set_dac_rate(struct hal2_card *hal2)
415 {
416 unsigned int master = hal2->dac.master;
417 int inc = hal2->dac.inc;
418 int mod = hal2->dac.mod;
419
420 DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
421
422 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
423 hal2_i_write32(hal2, H2I_BRES1_C2, ((0xffff & (inc - mod - 1)) << 16) | inc);
424 }
425
426 static void hal2_set_adc_rate(struct hal2_card *hal2)
427 {
428 unsigned int master = hal2->adc.master;
429 int inc = hal2->adc.inc;
430 int mod = hal2->adc.mod;
431
432 DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
433
434 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
435 hal2_i_write32(hal2, H2I_BRES2_C2, ((0xffff & (inc - mod - 1)) << 16) | inc);
436 }
437
438 static void hal2_setup_dac(struct hal2_card *hal2)
439 {
440 unsigned int fifobeg, fifoend, highwater, sample_size;
441 struct hal2_pbus *pbus = &hal2->dac.pbus;
442
443 DEBUG("hal2_setup_dac\n");
444
445 /* Now we set up some PBUS information. The PBUS needs information about
446 * what portion of the fifo it will use. If it's receiving or
447 * transmitting, and finally whether the stream is little endian or big
448 * endian. The information is written later, on the start call.
449 */
450 sample_size = 2 * hal2->dac.voices;
451 /* Fifo should be set to hold exactly four samples. Highwater mark
452 * should be set to two samples. */
453 highwater = (sample_size * 2) >> 1; /* halfwords */
454 fifobeg = 0; /* playback is first */
455 fifoend = (sample_size * 4) >> 3; /* doublewords */
456 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
457 (highwater << 8) | (fifobeg << 16) | (fifoend << 24) |
458 (hal2->dac.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0);
459 /* We disable everything before we do anything at all */
460 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
461 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
462 /* Setup the HAL2 for playback */
463 hal2_set_dac_rate(hal2);
464 /* Set endianess */
465 if (hal2->dac.format & AFMT_S16_LE)
466 hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
467 else
468 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
469 /* Set DMA bus */
470 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
471 /* We are using 1st Bresenham clock generator for playback */
472 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
473 | (1 << H2I_C1_CLKID_SHIFT)
474 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
475 }
476
477 static void hal2_setup_adc(struct hal2_card *hal2)
478 {
479 unsigned int fifobeg, fifoend, highwater, sample_size;
480 struct hal2_pbus *pbus = &hal2->adc.pbus;
481
482 DEBUG("hal2_setup_adc\n");
483
484 sample_size = 2 * hal2->adc.voices;
485 highwater = (sample_size * 2) >> 1; /* halfwords */
486 fifobeg = (4 * 4) >> 3; /* record is second */
487 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
488 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
489 (highwater << 8) | (fifobeg << 16) | (fifoend << 24) |
490 (hal2->adc.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0);
491 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
492 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
493 /* Setup the HAL2 for record */
494 hal2_set_adc_rate(hal2);
495 /* Set endianess */
496 if (hal2->adc.format & AFMT_S16_LE)
497 hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
498 else
499 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
500 /* Set DMA bus */
501 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
502 /* We are using 2nd Bresenham clock generator for record */
503 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
504 | (2 << H2I_C1_CLKID_SHIFT)
505 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
506 }
507
508 static dma_addr_t hal2_desc_addr(struct hal2_codec *codec, int i)
509 {
510 if (--i < 0)
511 i = codec->desc_count - 1;
512 return codec->desc[i].desc.pnext;
513 }
514
515 static void hal2_start_dac(struct hal2_card *hal2)
516 {
517 struct hal2_codec *dac = &hal2->dac;
518 struct hal2_pbus *pbus = &dac->pbus;
519
520 pbus->pbus->pbdma_dptr = hal2_desc_addr(dac, dac->tail);
521 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
522 /* enable DAC */
523 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
524 }
525
526 static void hal2_start_adc(struct hal2_card *hal2)
527 {
528 struct hal2_codec *adc = &hal2->adc;
529 struct hal2_pbus *pbus = &adc->pbus;
530
531 pbus->pbus->pbdma_dptr = hal2_desc_addr(adc, adc->head);
532 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
533 /* enable ADC */
534 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
535 }
536
537 static inline void hal2_stop_dac(struct hal2_card *hal2)
538 {
539 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
540 /* The HAL2 itself may remain enabled safely */
541 }
542
543 static inline void hal2_stop_adc(struct hal2_card *hal2)
544 {
545 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
546 }
547
548 static int hal2_alloc_dmabuf(struct hal2_codec *codec, int size,
549 int count, int cntinfo, int dir)
550 {
551 struct hal2_desc *desc, *dma_addr;
552 int i;
553
554 DEBUG("allocating %dk DMA buffer.\n", size / 1024);
555
556 codec->buffer = (unsigned char *)__get_free_pages(GFP_KERNEL | GFP_DMA,
557 get_order(size));
558 if (!codec->buffer)
559 return -ENOMEM;
560 desc = dma_alloc_coherent(NULL, count * sizeof(struct hal2_desc),
561 (dma_addr_t *)&dma_addr, GFP_KERNEL);
562 if (!desc) {
563 free_pages((unsigned long)codec->buffer, get_order(size));
564 return -ENOMEM;
565 }
566 codec->desc = desc;
567 for (i = 0; i < count; i++) {
568 desc->desc.pbuf = dma_map_single(NULL,
569 (void *)(codec->buffer + i * H2_BLOCK_SIZE),
570 H2_BLOCK_SIZE, dir);
571 desc->desc.cntinfo = cntinfo;
572 desc->desc.pnext = (i == count - 1) ?
573 (u32)dma_addr : (u32)(dma_addr + i + 1);
574 desc->cnt = 0;
575 desc++;
576 }
577 codec->desc_count = count;
578 codec->head = codec->tail = 0;
579 return 0;
580 }
581
582 static int hal2_alloc_dac_dmabuf(struct hal2_codec *codec)
583 {
584 return hal2_alloc_dmabuf(codec, H2_DAC_BUFSIZE,
585 H2_DAC_BUFSIZE / H2_BLOCK_SIZE,
586 HPCDMA_XIE | HPCDMA_EOX,
587 DMA_TO_DEVICE);
588 }
589
590 static int hal2_alloc_adc_dmabuf(struct hal2_codec *codec)
591 {
592 return hal2_alloc_dmabuf(codec, H2_ADC_BUFSIZE,
593 H2_ADC_BUFSIZE / H2_BLOCK_SIZE,
594 HPCDMA_XIE | H2_BLOCK_SIZE,
595 DMA_TO_DEVICE);
596 }
597
598 static void hal2_free_dmabuf(struct hal2_codec *codec, int size, int dir)
599 {
600 dma_addr_t dma_addr;
601 int i;
602
603 dma_addr = codec->desc[codec->desc_count - 1].desc.pnext;
604 for (i = 0; i < codec->desc_count; i++)
605 dma_unmap_single(NULL, codec->desc[i].desc.pbuf,
606 H2_BLOCK_SIZE, dir);
607 dma_free_coherent(NULL, codec->desc_count * sizeof(struct hal2_desc),
608 (void *)codec->desc, dma_addr);
609 free_pages((unsigned long)codec->buffer, get_order(size));
610 }
611
612 static void hal2_free_dac_dmabuf(struct hal2_codec *codec)
613 {
614 return hal2_free_dmabuf(codec, H2_DAC_BUFSIZE, DMA_TO_DEVICE);
615 }
616
617 static void hal2_free_adc_dmabuf(struct hal2_codec *codec)
618 {
619 return hal2_free_dmabuf(codec, H2_ADC_BUFSIZE, DMA_FROM_DEVICE);
620 }
621
622 /*
623 * Add 'count' bytes to 'buffer' from DMA ring buffers. Return number of
624 * bytes added or -EFAULT if copy_from_user failed.
625 */
626 static int hal2_get_buffer(struct hal2_card *hal2, char *buffer, int count)
627 {
628 unsigned long flags;
629 int size, ret = 0;
630 unsigned char *buf;
631 struct hal2_desc *tail;
632 struct hal2_codec *adc = &hal2->adc;
633
634 DEBUG("getting %d bytes ", count);
635
636 spin_lock_irqsave(&adc->lock, flags);
637 tail = &adc->desc[adc->tail];
638 /* enable DMA stream if there are no data */
639 if (!tail->cnt && !(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
640 hal2_start_adc(hal2);
641 while (tail->cnt > 0 && count > 0) {
642 size = min((int)tail->cnt, count);
643 buf = &adc->buffer[(adc->tail + 1) * H2_BLOCK_SIZE - tail->cnt];
644 spin_unlock_irqrestore(&adc->lock, flags);
645 dma_sync_single(NULL, tail->desc.pbuf, size, DMA_FROM_DEVICE);
646 if (copy_to_user(buffer, buf, size)) {
647 ret = -EFAULT;
648 goto out;
649 }
650 spin_lock_irqsave(&adc->lock, flags);
651 tail->cnt -= size;
652 /* buffer is empty, update tail pointer */
653 if (tail->cnt == 0) {
654 tail->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
655 hal2_inc_tail(adc);
656 tail = &adc->desc[adc->tail];
657 /* enable DMA stream again if needed */
658 if (!(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
659 hal2_start_adc(hal2);
660 }
661 buffer += size;
662 ret += size;
663 count -= size;
664
665 DEBUG("(%d) ", size);
666 }
667 spin_unlock_irqrestore(&adc->lock, flags);
668 out:
669 DEBUG("\n");
670
671 return ret;
672 }
673
674 /*
675 * Add 'count' bytes from 'buffer' to DMA ring buffers. Return number of
676 * bytes added or -EFAULT if copy_from_user failed.
677 */
678 static int hal2_add_buffer(struct hal2_card *hal2, char *buffer, int count)
679 {
680 unsigned long flags;
681 unsigned char *buf;
682 int size, ret = 0;
683 struct hal2_desc *head;
684 struct hal2_codec *dac = &hal2->dac;
685
686 DEBUG("adding %d bytes ", count);
687
688 spin_lock_irqsave(&dac->lock, flags);
689 head = &dac->desc[dac->head];
690 while (head->cnt == 0 && count > 0) {
691 size = min((int)H2_BLOCK_SIZE, count);
692 buf = &dac->buffer[dac->head * H2_BLOCK_SIZE];
693 spin_unlock_irqrestore(&dac->lock, flags);
694 if (copy_from_user(buf, buffer, size)) {
695 ret = -EFAULT;
696 goto out;
697 }
698 dma_sync_single(NULL, head->desc.pbuf, size, DMA_TO_DEVICE);
699 spin_lock_irqsave(&dac->lock, flags);
700 head->desc.cntinfo = size | HPCDMA_XIE;
701 head->cnt = size;
702 buffer += size;
703 ret += size;
704 count -= size;
705 hal2_inc_head(dac);
706 head = &dac->desc[dac->head];
707
708 DEBUG("(%d) ", size);
709 }
710 if (!(dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) && ret > 0)
711 hal2_start_dac(hal2);
712 spin_unlock_irqrestore(&dac->lock, flags);
713 out:
714 DEBUG("\n");
715
716 return ret;
717 }
718
719 #define hal2_reset_dac_pointer(hal2) hal2_reset_pointer(hal2, 1)
720 #define hal2_reset_adc_pointer(hal2) hal2_reset_pointer(hal2, 0)
721 static void hal2_reset_pointer(struct hal2_card *hal2, int is_dac)
722 {
723 int i;
724 struct hal2_codec *codec = (is_dac) ? &hal2->dac : &hal2->adc;
725
726 DEBUG("hal2_reset_pointer\n");
727
728 for (i = 0; i < codec->desc_count; i++) {
729 codec->desc[i].cnt = 0;
730 codec->desc[i].desc.cntinfo = HPCDMA_XIE | (is_dac) ?
731 HPCDMA_EOX : H2_BLOCK_SIZE;
732 }
733 codec->head = codec->tail = 0;
734 }
735
736 static int hal2_sync_dac(struct hal2_card *hal2)
737 {
738 DECLARE_WAITQUEUE(wait, current);
739 struct hal2_codec *dac = &hal2->dac;
740 int ret = 0;
741 unsigned long flags;
742 signed long timeout = 1000 * H2_BLOCK_SIZE * 2 * dac->voices *
743 HZ / dac->sample_rate / 900;
744
745 while (dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) {
746 add_wait_queue(&dac->dma_wait, &wait);
747 set_current_state(TASK_INTERRUPTIBLE);
748 schedule_timeout(timeout);
749 spin_lock_irqsave(&dac->lock, flags);
750 if (dac->desc[dac->tail].cnt)
751 ret = -ETIME;
752 spin_unlock_irqrestore(&dac->lock, flags);
753 if (signal_pending(current))
754 ret = -ERESTARTSYS;
755 if (ret) {
756 hal2_stop_dac(hal2);
757 hal2_reset_dac_pointer(hal2);
758 }
759 remove_wait_queue(&dac->dma_wait, &wait);
760 }
761
762 return ret;
763 }
764
765 static int hal2_write_mixer(struct hal2_card *hal2, int index, int vol)
766 {
767 unsigned int l, r, tmp;
768
769 DEBUG_MIX("mixer %d write\n", index);
770
771 if (index >= SOUND_MIXER_NRDEVICES || !mixtable[index].avail)
772 return -EINVAL;
773
774 r = (vol >> 8) & 0xff;
775 if (r > 100)
776 r = 100;
777 l = vol & 0xff;
778 if (l > 100)
779 l = 100;
780
781 hal2->mixer.volume[mixtable[index].idx] = l | (r << 8);
782
783 switch (mixtable[index].idx) {
784 case H2_MIX_OUTPUT_ATT:
785
786 DEBUG_MIX("output attenuator %d,%d\n", l, r);
787
788 if (r | l) {
789 tmp = hal2_i_look32(hal2, H2I_DAC_C2);
790 tmp &= ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
791
792 /* Attenuator has five bits */
793 l = 31 * (100 - l) / 99;
794 r = 31 * (100 - r) / 99;
795
796 DEBUG_MIX("left: %d, right %d\n", l, r);
797
798 tmp |= (l << H2I_C2_L_ATT_SHIFT) & H2I_C2_L_ATT_M;
799 tmp |= (r << H2I_C2_R_ATT_SHIFT) & H2I_C2_R_ATT_M;
800 hal2_i_write32(hal2, H2I_DAC_C2, tmp);
801 } else
802 hal2_i_setbit32(hal2, H2I_DAC_C2, H2I_C2_MUTE);
803 break;
804 case H2_MIX_INPUT_GAIN:
805
806 DEBUG_MIX("input gain %d,%d\n", l, r);
807
808 tmp = hal2_i_look32(hal2, H2I_ADC_C2);
809 tmp &= ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
810
811 /* Gain control has four bits */
812 l = 16 * l / 100;
813 r = 16 * r / 100;
814
815 DEBUG_MIX("left: %d, right %d\n", l, r);
816
817 tmp |= (l << H2I_C2_L_GAIN_SHIFT) & H2I_C2_L_GAIN_M;
818 tmp |= (r << H2I_C2_R_GAIN_SHIFT) & H2I_C2_R_GAIN_M;
819 hal2_i_write32(hal2, H2I_ADC_C2, tmp);
820
821 break;
822 }
823
824 return 0;
825 }
826
827 static void hal2_init_mixer(struct hal2_card *hal2)
828 {
829 int i;
830
831 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
832 if (mixtable[i].avail)
833 hal2->mixer.volume[mixtable[i].idx] = 100 | (100 << 8);
834
835 /* disable attenuator */
836 hal2_i_write32(hal2, H2I_DAC_C2, 0);
837 /* set max input gain */
838 hal2_i_write32(hal2, H2I_ADC_C2, H2I_C2_MUTE |
839 (H2I_C2_L_GAIN_M << H2I_C2_L_GAIN_SHIFT) |
840 (H2I_C2_R_GAIN_M << H2I_C2_R_GAIN_SHIFT));
841 /* set max volume */
842 hal2->mixer.master = 0xff;
843 hal2->vol_regs->left = 0xff;
844 hal2->vol_regs->right = 0xff;
845 }
846
847 /*
848 * XXX: later i'll implement mixer for main volume which will be disabled
849 * by default. enabling it users will be allowed to have master volume level
850 * control on panel in their favourite X desktop
851 */
852 static void hal2_volume_control(int direction)
853 {
854 unsigned int master = hal2_card[0]->mixer.master;
855 struct hal2_vol_regs *vol = hal2_card[0]->vol_regs;
856
857 /* volume up */
858 if (direction > 0 && master < 0xff)
859 master++;
860 /* volume down */
861 else if (direction < 0 && master > 0)
862 master--;
863 /* TODO: mute/unmute */
864 vol->left = master;
865 vol->right = master;
866 hal2_card[0]->mixer.master = master;
867 }
868
869 static int hal2_mixer_ioctl(struct hal2_card *hal2, unsigned int cmd,
870 unsigned long arg)
871 {
872 int val;
873
874 if (cmd == SOUND_MIXER_INFO) {
875 mixer_info info;
876
877 memset(&info, 0, sizeof(info));
878 strlcpy(info.id, hal2str, sizeof(info.id));
879 strlcpy(info.name, hal2str, sizeof(info.name));
880 info.modify_counter = hal2->mixer.modcnt;
881 if (copy_to_user((void *)arg, &info, sizeof(info)))
882 return -EFAULT;
883 return 0;
884 }
885 if (cmd == SOUND_OLD_MIXER_INFO) {
886 _old_mixer_info info;
887
888 memset(&info, 0, sizeof(info));
889 strlcpy(info.id, hal2str, sizeof(info.id));
890 strlcpy(info.name, hal2str, sizeof(info.name));
891 if (copy_to_user((void *)arg, &info, sizeof(info)))
892 return -EFAULT;
893 return 0;
894 }
895 if (cmd == OSS_GETVERSION)
896 return put_user(SOUND_VERSION, (int *)arg);
897
898 if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
899 return -EINVAL;
900
901 if (_IOC_DIR(cmd) == _IOC_READ) {
902 switch (_IOC_NR(cmd)) {
903 /* Give the current record source */
904 case SOUND_MIXER_RECSRC:
905 val = 0; /* FIXME */
906 break;
907 /* Give the supported mixers, all of them support stereo */
908 case SOUND_MIXER_DEVMASK:
909 case SOUND_MIXER_STEREODEVS: {
910 int i;
911
912 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
913 if (mixtable[i].avail)
914 val |= 1 << i;
915 break;
916 }
917 /* Arg contains a bit for each supported recording source */
918 case SOUND_MIXER_RECMASK:
919 val = 0;
920 break;
921 case SOUND_MIXER_CAPS:
922 val = 0;
923 break;
924 /* Read a specific mixer */
925 default: {
926 int i = _IOC_NR(cmd);
927
928 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail)
929 return -EINVAL;
930 val = hal2->mixer.volume[mixtable[i].idx];
931 break;
932 }
933 }
934 return put_user(val, (int *)arg);
935 }
936
937 if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
938 return -EINVAL;
939
940 hal2->mixer.modcnt++;
941
942 if (get_user(val, (int *)arg))
943 return -EFAULT;
944
945 switch (_IOC_NR(cmd)) {
946 /* Arg contains a bit for each recording source */
947 case SOUND_MIXER_RECSRC:
948 return 0; /* FIXME */
949 default:
950 return hal2_write_mixer(hal2, _IOC_NR(cmd), val);
951 }
952
953 return 0;
954 }
955
956 static int hal2_open_mixdev(struct inode *inode, struct file *file)
957 {
958 struct hal2_card *hal2 = hal2_mixer_find_card(iminor(inode));
959
960 if (hal2) {
961 file->private_data = hal2;
962 return nonseekable_open(inode, file);
963 }
964 return -ENODEV;
965 }
966
967 static int hal2_release_mixdev(struct inode *inode, struct file *file)
968 {
969 return 0;
970 }
971
972 static int hal2_ioctl_mixdev(struct inode *inode, struct file *file,
973 unsigned int cmd, unsigned long arg)
974 {
975 return hal2_mixer_ioctl((struct hal2_card *)file->private_data, cmd, arg);
976 }
977
978 static int hal2_ioctl(struct inode *inode, struct file *file,
979 unsigned int cmd, unsigned long arg)
980 {
981 int val;
982 struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
983
984 switch (cmd) {
985 case OSS_GETVERSION:
986 return put_user(SOUND_VERSION, (int *)arg);
987
988 case SNDCTL_DSP_SYNC:
989 if (file->f_mode & FMODE_WRITE)
990 return hal2_sync_dac(hal2);
991 return 0;
992
993 case SNDCTL_DSP_SETDUPLEX:
994 return 0;
995
996 case SNDCTL_DSP_GETCAPS:
997 return put_user(DSP_CAP_DUPLEX | DSP_CAP_MULTI, (int *)arg);
998
999 case SNDCTL_DSP_RESET:
1000 if (file->f_mode & FMODE_READ) {
1001 hal2_stop_adc(hal2);
1002 hal2_reset_adc_pointer(hal2);
1003 }
1004 if (file->f_mode & FMODE_WRITE) {
1005 hal2_stop_dac(hal2);
1006 hal2_reset_dac_pointer(hal2);
1007 }
1008 return 0;
1009
1010 case SNDCTL_DSP_SPEED:
1011 if (get_user(val, (int *)arg))
1012 return -EFAULT;
1013 if (file->f_mode & FMODE_READ) {
1014 hal2_stop_adc(hal2);
1015 val = hal2_compute_rate(&hal2->adc, val);
1016 hal2->adc.sample_rate = val;
1017 hal2_set_adc_rate(hal2);
1018 }
1019 if (file->f_mode & FMODE_WRITE) {
1020 hal2_stop_dac(hal2);
1021 val = hal2_compute_rate(&hal2->dac, val);
1022 hal2->dac.sample_rate = val;
1023 hal2_set_dac_rate(hal2);
1024 }
1025 return put_user(val, (int *)arg);
1026
1027 case SNDCTL_DSP_STEREO:
1028 if (get_user(val, (int *)arg))
1029 return -EFAULT;
1030 if (file->f_mode & FMODE_READ) {
1031 hal2_stop_adc(hal2);
1032 hal2->adc.voices = (val) ? 2 : 1;
1033 hal2_setup_adc(hal2);
1034 }
1035 if (file->f_mode & FMODE_WRITE) {
1036 hal2_stop_dac(hal2);
1037 hal2->dac.voices = (val) ? 2 : 1;
1038 hal2_setup_dac(hal2);
1039 }
1040 return 0;
1041
1042 case SNDCTL_DSP_CHANNELS:
1043 if (get_user(val, (int *)arg))
1044 return -EFAULT;
1045 if (val != 0) {
1046 if (file->f_mode & FMODE_READ) {
1047 hal2_stop_adc(hal2);
1048 hal2->adc.voices = (val == 1) ? 1 : 2;
1049 hal2_setup_adc(hal2);
1050 }
1051 if (file->f_mode & FMODE_WRITE) {
1052 hal2_stop_dac(hal2);
1053 hal2->dac.voices = (val == 1) ? 1 : 2;
1054 hal2_setup_dac(hal2);
1055 }
1056 }
1057 val = -EINVAL;
1058 if (file->f_mode & FMODE_READ)
1059 val = hal2->adc.voices;
1060 if (file->f_mode & FMODE_WRITE)
1061 val = hal2->dac.voices;
1062 return put_user(val, (int *)arg);
1063
1064 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1065 return put_user(H2_SUPPORTED_FORMATS, (int *)arg);
1066
1067 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1068 if (get_user(val, (int *)arg))
1069 return -EFAULT;
1070 if (val != AFMT_QUERY) {
1071 if (!(val & H2_SUPPORTED_FORMATS))
1072 return -EINVAL;
1073 if (file->f_mode & FMODE_READ) {
1074 hal2_stop_adc(hal2);
1075 hal2->adc.format = val;
1076 hal2_setup_adc(hal2);
1077 }
1078 if (file->f_mode & FMODE_WRITE) {
1079 hal2_stop_dac(hal2);
1080 hal2->dac.format = val;
1081 hal2_setup_dac(hal2);
1082 }
1083 } else {
1084 val = -EINVAL;
1085 if (file->f_mode & FMODE_READ)
1086 val = hal2->adc.format;
1087 if (file->f_mode & FMODE_WRITE)
1088 val = hal2->dac.format;
1089 }
1090 return put_user(val, (int *)arg);
1091
1092 case SNDCTL_DSP_POST:
1093 return 0;
1094
1095 case SNDCTL_DSP_GETOSPACE: {
1096 audio_buf_info info;
1097 int i;
1098 unsigned long flags;
1099 struct hal2_codec *dac = &hal2->dac;
1100
1101 if (!(file->f_mode & FMODE_WRITE))
1102 return -EINVAL;
1103 info.fragments = 0;
1104 spin_lock_irqsave(&dac->lock, flags);
1105 for (i = 0; i < dac->desc_count; i++)
1106 if (dac->desc[i].cnt == 0)
1107 info.fragments++;
1108 spin_unlock_irqrestore(&dac->lock, flags);
1109 info.fragstotal = dac->desc_count;
1110 info.fragsize = H2_BLOCK_SIZE;
1111 info.bytes = info.fragsize * info.fragments;
1112
1113 return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
1114 }
1115
1116 case SNDCTL_DSP_GETISPACE: {
1117 audio_buf_info info;
1118 int i;
1119 unsigned long flags;
1120 struct hal2_codec *adc = &hal2->adc;
1121
1122 if (!(file->f_mode & FMODE_READ))
1123 return -EINVAL;
1124 info.fragments = 0;
1125 info.bytes = 0;
1126 spin_lock_irqsave(&adc->lock, flags);
1127 for (i = 0; i < adc->desc_count; i++)
1128 if (adc->desc[i].cnt > 0) {
1129 info.fragments++;
1130 info.bytes += adc->desc[i].cnt;
1131 }
1132 spin_unlock_irqrestore(&adc->lock, flags);
1133 info.fragstotal = adc->desc_count;
1134 info.fragsize = H2_BLOCK_SIZE;
1135
1136 return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
1137 }
1138
1139 case SNDCTL_DSP_NONBLOCK:
1140 file->f_flags |= O_NONBLOCK;
1141 return 0;
1142
1143 case SNDCTL_DSP_GETBLKSIZE:
1144 return put_user(H2_BLOCK_SIZE, (int *)arg);
1145
1146 case SNDCTL_DSP_SETFRAGMENT:
1147 return 0;
1148
1149 case SOUND_PCM_READ_RATE:
1150 val = -EINVAL;
1151 if (file->f_mode & FMODE_READ)
1152 val = hal2->adc.sample_rate;
1153 if (file->f_mode & FMODE_WRITE)
1154 val = hal2->dac.sample_rate;
1155 return put_user(val, (int *)arg);
1156
1157 case SOUND_PCM_READ_CHANNELS:
1158 val = -EINVAL;
1159 if (file->f_mode & FMODE_READ)
1160 val = hal2->adc.voices;
1161 if (file->f_mode & FMODE_WRITE)
1162 val = hal2->dac.voices;
1163 return put_user(val, (int *)arg);
1164
1165 case SOUND_PCM_READ_BITS:
1166 return put_user(16, (int *)arg);
1167 }
1168
1169 return hal2_mixer_ioctl(hal2, cmd, arg);
1170 }
1171
1172 static ssize_t hal2_read(struct file *file, char *buffer,
1173 size_t count, loff_t *ppos)
1174 {
1175 ssize_t err;
1176 struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1177 struct hal2_codec *adc = &hal2->adc;
1178
1179 if (!count)
1180 return 0;
1181 if (down_interruptible(&adc->sem))
1182 return -EINTR;
1183 if (file->f_flags & O_NONBLOCK) {
1184 err = hal2_get_buffer(hal2, buffer, count);
1185 err = err == 0 ? -EAGAIN : err;
1186 } else {
1187 do {
1188 /* ~10% longer */
1189 signed long timeout = 1000 * H2_BLOCK_SIZE *
1190 2 * adc->voices * HZ / adc->sample_rate / 900;
1191 unsigned long flags;
1192 DECLARE_WAITQUEUE(wait, current);
1193 ssize_t cnt = 0;
1194
1195 err = hal2_get_buffer(hal2, buffer, count);
1196 if (err > 0) {
1197 count -= err;
1198 cnt += err;
1199 buffer += err;
1200 err = cnt;
1201 }
1202 if (count > 0 && err >= 0) {
1203 add_wait_queue(&adc->dma_wait, &wait);
1204 set_current_state(TASK_INTERRUPTIBLE);
1205 schedule_timeout(timeout);
1206 spin_lock_irqsave(&adc->lock, flags);
1207 if (!adc->desc[adc->tail].cnt)
1208 err = -EAGAIN;
1209 spin_unlock_irqrestore(&adc->lock, flags);
1210 if (signal_pending(current))
1211 err = -ERESTARTSYS;
1212 remove_wait_queue(&adc->dma_wait, &wait);
1213 if (err < 0) {
1214 hal2_stop_adc(hal2);
1215 hal2_reset_adc_pointer(hal2);
1216 }
1217 }
1218 } while (count > 0 && err >= 0);
1219 }
1220 up(&adc->sem);
1221
1222 return err;
1223 }
1224
1225 static ssize_t hal2_write(struct file *file, const char *buffer,
1226 size_t count, loff_t *ppos)
1227 {
1228 ssize_t err;
1229 char *buf = (char*) buffer;
1230 struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1231 struct hal2_codec *dac = &hal2->dac;
1232
1233 if (!count)
1234 return 0;
1235 if (down_interruptible(&dac->sem))
1236 return -EINTR;
1237 if (file->f_flags & O_NONBLOCK) {
1238 err = hal2_add_buffer(hal2, buf, count);
1239 err = err == 0 ? -EAGAIN : err;
1240 } else {
1241 do {
1242 /* ~10% longer */
1243 signed long timeout = 1000 * H2_BLOCK_SIZE *
1244 2 * dac->voices * HZ / dac->sample_rate / 900;
1245 unsigned long flags;
1246 DECLARE_WAITQUEUE(wait, current);
1247 ssize_t cnt = 0;
1248
1249 err = hal2_add_buffer(hal2, buf, count);
1250 if (err > 0) {
1251 count -= err;
1252 cnt += err;
1253 buf += err;
1254 err = cnt;
1255 }
1256 if (count > 0 && err >= 0) {
1257 add_wait_queue(&dac->dma_wait, &wait);
1258 set_current_state(TASK_INTERRUPTIBLE);
1259 schedule_timeout(timeout);
1260 spin_lock_irqsave(&dac->lock, flags);
1261 if (dac->desc[dac->head].cnt)
1262 err = -EAGAIN;
1263 spin_unlock_irqrestore(&dac->lock, flags);
1264 if (signal_pending(current))
1265 err = -ERESTARTSYS;
1266 remove_wait_queue(&dac->dma_wait, &wait);
1267 if (err < 0) {
1268 hal2_stop_dac(hal2);
1269 hal2_reset_dac_pointer(hal2);
1270 }
1271 }
1272 } while (count > 0 && err >= 0);
1273 }
1274 up(&dac->sem);
1275
1276 return err;
1277 }
1278
1279 static unsigned int hal2_poll(struct file *file, struct poll_table_struct *wait)
1280 {
1281 unsigned long flags;
1282 unsigned int mask = 0;
1283 struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1284
1285 if (file->f_mode & FMODE_READ) {
1286 struct hal2_codec *adc = &hal2->adc;
1287
1288 poll_wait(file, &adc->dma_wait, wait);
1289 spin_lock_irqsave(&adc->lock, flags);
1290 if (adc->desc[adc->tail].cnt > 0)
1291 mask |= POLLIN;
1292 spin_unlock_irqrestore(&adc->lock, flags);
1293 }
1294
1295 if (file->f_mode & FMODE_WRITE) {
1296 struct hal2_codec *dac = &hal2->dac;
1297
1298 poll_wait(file, &dac->dma_wait, wait);
1299 spin_lock_irqsave(&dac->lock, flags);
1300 if (dac->desc[dac->head].cnt == 0)
1301 mask |= POLLOUT;
1302 spin_unlock_irqrestore(&dac->lock, flags);
1303 }
1304
1305 return mask;
1306 }
1307
1308 static int hal2_open(struct inode *inode, struct file *file)
1309 {
1310 int err;
1311 struct hal2_card *hal2 = hal2_dsp_find_card(iminor(inode));
1312
1313 if (!hal2)
1314 return -ENODEV;
1315 file->private_data = hal2;
1316 if (file->f_mode & FMODE_READ) {
1317 struct hal2_codec *adc = &hal2->adc;
1318
1319 if (adc->usecount)
1320 return -EBUSY;
1321 /* OSS spec wanted us to use 8 bit, 8 kHz mono by default,
1322 * but HAL2 can't do 8bit audio */
1323 adc->format = AFMT_S16_BE;
1324 adc->voices = 1;
1325 adc->sample_rate = hal2_compute_rate(adc, 8000);
1326 hal2_set_adc_rate(hal2);
1327 err = hal2_alloc_adc_dmabuf(adc);
1328 if (err)
1329 return err;
1330 hal2_setup_adc(hal2);
1331 adc->usecount++;
1332 }
1333 if (file->f_mode & FMODE_WRITE) {
1334 struct hal2_codec *dac = &hal2->dac;
1335
1336 if (dac->usecount)
1337 return -EBUSY;
1338 dac->format = AFMT_S16_BE;
1339 dac->voices = 1;
1340 dac->sample_rate = hal2_compute_rate(dac, 8000);
1341 hal2_set_dac_rate(hal2);
1342 err = hal2_alloc_dac_dmabuf(dac);
1343 if (err)
1344 return err;
1345 hal2_setup_dac(hal2);
1346 dac->usecount++;
1347 }
1348
1349 return nonseekable_open(inode, file);
1350 }
1351
1352 static int hal2_release(struct inode *inode, struct file *file)
1353 {
1354 struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
1355
1356 if (file->f_mode & FMODE_READ) {
1357 struct hal2_codec *adc = &hal2->adc;
1358
1359 down(&adc->sem);
1360 hal2_stop_adc(hal2);
1361 hal2_free_adc_dmabuf(adc);
1362 adc->usecount--;
1363 up(&adc->sem);
1364 }
1365 if (file->f_mode & FMODE_WRITE) {
1366 struct hal2_codec *dac = &hal2->dac;
1367
1368 down(&dac->sem);
1369 hal2_sync_dac(hal2);
1370 hal2_free_dac_dmabuf(dac);
1371 dac->usecount--;
1372 up(&dac->sem);
1373 }
1374
1375 return 0;
1376 }
1377
1378 static struct file_operations hal2_audio_fops = {
1379 .owner = THIS_MODULE,
1380 .llseek = no_llseek,
1381 .read = hal2_read,
1382 .write = hal2_write,
1383 .poll = hal2_poll,
1384 .ioctl = hal2_ioctl,
1385 .open = hal2_open,
1386 .release = hal2_release,
1387 };
1388
1389 static struct file_operations hal2_mixer_fops = {
1390 .owner = THIS_MODULE,
1391 .llseek = no_llseek,
1392 .ioctl = hal2_ioctl_mixdev,
1393 .open = hal2_open_mixdev,
1394 .release = hal2_release_mixdev,
1395 };
1396
1397 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
1398 int index)
1399 {
1400 codec->pbus.pbusnr = index;
1401 codec->pbus.pbus = &hpc3->pbdma[index];
1402 init_waitqueue_head(&codec->dma_wait);
1403 init_MUTEX(&codec->sem);
1404 spin_lock_init(&codec->lock);
1405 }
1406
1407 static int hal2_detect(struct hal2_card *hal2)
1408 {
1409 unsigned short board, major, minor;
1410 unsigned short rev;
1411
1412 /* reset HAL2 */
1413 hal2_isr_write(hal2, 0);
1414 /* release reset */
1415 hal2_isr_write(hal2, H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N);
1416
1417 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
1418 if ((rev = hal2_rev_look(hal2)) & H2_REV_AUDIO_PRESENT)
1419 return -ENODEV;
1420
1421 board = (rev & H2_REV_BOARD_M) >> 12;
1422 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
1423 minor = (rev & H2_REV_MINOR_CHIP_M);
1424
1425 printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
1426 board, major, minor);
1427
1428 return 0;
1429 }
1430
1431 static int hal2_init_card(struct hal2_card **phal2, struct hpc3_regs *hpc3)
1432 {
1433 int ret = 0;
1434 struct hal2_card *hal2;
1435
1436 hal2 = (struct hal2_card *) kmalloc(sizeof(struct hal2_card), GFP_KERNEL);
1437 if (!hal2)
1438 return -ENOMEM;
1439 memset(hal2, 0, sizeof(struct hal2_card));
1440
1441 hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
1442 hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
1443 hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
1444 hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
1445
1446 if (hal2_detect(hal2) < 0) {
1447 ret = -ENODEV;
1448 goto free_card;
1449 }
1450
1451 hal2_init_codec(&hal2->dac, hpc3, 0);
1452 hal2_init_codec(&hal2->adc, hpc3, 1);
1453
1454 /*
1455 * All DMA channel interfaces in HAL2 are designed to operate with
1456 * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
1457 * in D5. HAL2 is a 16-bit device which can accept both big and little
1458 * endian format. It assumes that even address bytes are on high
1459 * portion of PBUS (15:8) and assumes that HPC3 is programmed to
1460 * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
1461 */
1462 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
1463 (2 << HPC3_DMACFG_D4R_SHIFT) | \
1464 (2 << HPC3_DMACFG_D5R_SHIFT) | \
1465 (0 << HPC3_DMACFG_D3W_SHIFT) | \
1466 (2 << HPC3_DMACFG_D4W_SHIFT) | \
1467 (2 << HPC3_DMACFG_D5W_SHIFT) | \
1468 HPC3_DMACFG_DS16 | \
1469 HPC3_DMACFG_EVENHI | \
1470 HPC3_DMACFG_RTIME | \
1471 (8 << HPC3_DMACFG_BURST_SHIFT) | \
1472 HPC3_DMACFG_DRQLIVE)
1473 /*
1474 * Ignore what's mentioned in the specification and write value which
1475 * works in The Real World (TM)
1476 */
1477 hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
1478 hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
1479
1480 if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, SA_SHIRQ,
1481 hal2str, hal2)) {
1482 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
1483 ret = -EAGAIN;
1484 goto free_card;
1485 }
1486
1487 hal2->dev_dsp = register_sound_dsp(&hal2_audio_fops, -1);
1488 if (hal2->dev_dsp < 0) {
1489 ret = hal2->dev_dsp;
1490 goto free_irq;
1491 }
1492
1493 hal2->dev_mixer = register_sound_mixer(&hal2_mixer_fops, -1);
1494 if (hal2->dev_mixer < 0) {
1495 ret = hal2->dev_mixer;
1496 goto unregister_dsp;
1497 }
1498
1499 hal2_init_mixer(hal2);
1500
1501 *phal2 = hal2;
1502 return 0;
1503 unregister_dsp:
1504 unregister_sound_dsp(hal2->dev_dsp);
1505 free_irq:
1506 free_irq(SGI_HPCDMA_IRQ, hal2);
1507 free_card:
1508 kfree(hal2);
1509
1510 return ret;
1511 }
1512
1513 extern void (*indy_volume_button)(int);
1514
1515 /*
1516 * Assuming only one HAL2 card. Mail me if you ever meet machine with
1517 * more than one.
1518 */
1519 static int __init init_hal2(void)
1520 {
1521 int i, error;
1522
1523 for (i = 0; i < MAXCARDS; i++)
1524 hal2_card[i] = NULL;
1525
1526 error = hal2_init_card(&hal2_card[0], hpc3c0);
1527
1528 /* let Indy's volume buttons work */
1529 if (!error && !ip22_is_fullhouse())
1530 indy_volume_button = hal2_volume_control;
1531
1532 return error;
1533
1534 }
1535
1536 static void __exit exit_hal2(void)
1537 {
1538 int i;
1539
1540 /* unregister volume butons callback function */
1541 indy_volume_button = NULL;
1542
1543 for (i = 0; i < MAXCARDS; i++)
1544 if (hal2_card[i]) {
1545 free_irq(SGI_HPCDMA_IRQ, hal2_card[i]);
1546 unregister_sound_dsp(hal2_card[i]->dev_dsp);
1547 unregister_sound_mixer(hal2_card[i]->dev_mixer);
1548 kfree(hal2_card[i]);
1549 }
1550 }
1551
1552 module_init(init_hal2);
1553 module_exit(exit_hal2);
1554
1555 MODULE_DESCRIPTION("OSS compatible driver for SGI HAL2 audio");
1556 MODULE_AUTHOR("Ladislav Michl");
1557 MODULE_LICENSE("GPL");
Linux with added FPC-III support