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Linux 4.15.6
[linux/fpc-iii.git] / sound / soc / codecs / rt5659.c
blob07e7757417bc4e8ae159fae364f396f478f91a81
1 /*
2 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2015 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/acpi.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/jack.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/rt5659.h>
33
34 #include "rl6231.h"
35 #include "rt5659.h"
36
37 static const struct reg_default rt5659_reg[] = {
38 { 0x0000, 0x0000 },
39 { 0x0001, 0x4848 },
40 { 0x0002, 0x8080 },
41 { 0x0003, 0xc8c8 },
42 { 0x0004, 0xc80a },
43 { 0x0005, 0x0000 },
44 { 0x0006, 0x0000 },
45 { 0x0007, 0x0103 },
46 { 0x0008, 0x0080 },
47 { 0x0009, 0x0000 },
48 { 0x000a, 0x0000 },
49 { 0x000c, 0x0000 },
50 { 0x000d, 0x0000 },
51 { 0x000f, 0x0808 },
52 { 0x0010, 0x3080 },
53 { 0x0011, 0x4a00 },
54 { 0x0012, 0x4e00 },
55 { 0x0015, 0x42c1 },
56 { 0x0016, 0x0000 },
57 { 0x0018, 0x000b },
58 { 0x0019, 0xafaf },
59 { 0x001a, 0xafaf },
60 { 0x001b, 0x0011 },
61 { 0x001c, 0x2f2f },
62 { 0x001d, 0x2f2f },
63 { 0x001e, 0x2f2f },
64 { 0x001f, 0x0000 },
65 { 0x0020, 0x0000 },
66 { 0x0021, 0x0000 },
67 { 0x0022, 0x5757 },
68 { 0x0023, 0x0039 },
69 { 0x0026, 0xc060 },
70 { 0x0027, 0xd8d8 },
71 { 0x0029, 0x8080 },
72 { 0x002a, 0xaaaa },
73 { 0x002b, 0xaaaa },
74 { 0x002c, 0x00af },
75 { 0x002d, 0x0000 },
76 { 0x002f, 0x1002 },
77 { 0x0031, 0x5000 },
78 { 0x0032, 0x0000 },
79 { 0x0033, 0x0000 },
80 { 0x0034, 0x0000 },
81 { 0x0035, 0x0000 },
82 { 0x0036, 0x0000 },
83 { 0x003a, 0x0000 },
84 { 0x003b, 0x0000 },
85 { 0x003c, 0x007f },
86 { 0x003d, 0x0000 },
87 { 0x003e, 0x007f },
88 { 0x0040, 0x0808 },
89 { 0x0046, 0x001f },
90 { 0x0047, 0x001f },
91 { 0x0048, 0x0003 },
92 { 0x0049, 0xe061 },
93 { 0x004a, 0x0000 },
94 { 0x004b, 0x031f },
95 { 0x004d, 0x0000 },
96 { 0x004e, 0x001f },
97 { 0x004f, 0x0000 },
98 { 0x0050, 0x001f },
99 { 0x0052, 0xf000 },
100 { 0x0053, 0x0111 },
101 { 0x0054, 0x0064 },
102 { 0x0055, 0x0080 },
103 { 0x0056, 0xef0e },
104 { 0x0057, 0xf0f0 },
105 { 0x0058, 0xef0e },
106 { 0x0059, 0xf0f0 },
107 { 0x005a, 0xef0e },
108 { 0x005b, 0xf0f0 },
109 { 0x005c, 0xf000 },
110 { 0x005d, 0x0000 },
111 { 0x005e, 0x1f2c },
112 { 0x005f, 0x1f2c },
113 { 0x0060, 0x2717 },
114 { 0x0061, 0x0000 },
115 { 0x0062, 0x0000 },
116 { 0x0063, 0x003e },
117 { 0x0064, 0x0000 },
118 { 0x0065, 0x0000 },
119 { 0x0066, 0x0000 },
120 { 0x0067, 0x0000 },
121 { 0x006a, 0x0000 },
122 { 0x006b, 0x0000 },
123 { 0x006c, 0x0000 },
124 { 0x006e, 0x0000 },
125 { 0x006f, 0x0000 },
126 { 0x0070, 0x8000 },
127 { 0x0071, 0x8000 },
128 { 0x0072, 0x8000 },
129 { 0x0073, 0x1110 },
130 { 0x0074, 0xfe00 },
131 { 0x0075, 0x2409 },
132 { 0x0076, 0x000a },
133 { 0x0077, 0x00f0 },
134 { 0x0078, 0x0000 },
135 { 0x0079, 0x0000 },
136 { 0x007a, 0x0123 },
137 { 0x007b, 0x8003 },
138 { 0x0080, 0x0000 },
139 { 0x0081, 0x0000 },
140 { 0x0082, 0x0000 },
141 { 0x0083, 0x0000 },
142 { 0x0084, 0x0000 },
143 { 0x0085, 0x0000 },
144 { 0x0086, 0x0008 },
145 { 0x0087, 0x0000 },
146 { 0x0088, 0x0000 },
147 { 0x0089, 0x0000 },
148 { 0x008a, 0x0000 },
149 { 0x008b, 0x0000 },
150 { 0x008c, 0x0003 },
151 { 0x008e, 0x0000 },
152 { 0x008f, 0x1000 },
153 { 0x0090, 0x0646 },
154 { 0x0091, 0x0c16 },
155 { 0x0092, 0x0073 },
156 { 0x0093, 0x0000 },
157 { 0x0094, 0x0080 },
158 { 0x0097, 0x0000 },
159 { 0x0098, 0x0000 },
160 { 0x0099, 0x0000 },
161 { 0x009a, 0x0000 },
162 { 0x009b, 0x0000 },
163 { 0x009c, 0x007f },
164 { 0x009d, 0x0000 },
165 { 0x009e, 0x007f },
166 { 0x009f, 0x0000 },
167 { 0x00a0, 0x0060 },
168 { 0x00a1, 0x90a1 },
169 { 0x00ae, 0x2000 },
170 { 0x00af, 0x0000 },
171 { 0x00b0, 0x2000 },
172 { 0x00b1, 0x0000 },
173 { 0x00b2, 0x0000 },
174 { 0x00b6, 0x0000 },
175 { 0x00b7, 0x0000 },
176 { 0x00b8, 0x0000 },
177 { 0x00b9, 0x0000 },
178 { 0x00ba, 0x0000 },
179 { 0x00bb, 0x0000 },
180 { 0x00be, 0x0000 },
181 { 0x00bf, 0x0000 },
182 { 0x00c0, 0x0000 },
183 { 0x00c1, 0x0000 },
184 { 0x00c2, 0x0000 },
185 { 0x00c3, 0x0000 },
186 { 0x00c4, 0x0003 },
187 { 0x00c5, 0x0000 },
188 { 0x00cb, 0xa02f },
189 { 0x00cc, 0x0000 },
190 { 0x00cd, 0x0e02 },
191 { 0x00d6, 0x0000 },
192 { 0x00d7, 0x2244 },
193 { 0x00d9, 0x0809 },
194 { 0x00da, 0x0000 },
195 { 0x00db, 0x0008 },
196 { 0x00dc, 0x00c0 },
197 { 0x00dd, 0x6724 },
198 { 0x00de, 0x3131 },
199 { 0x00df, 0x0008 },
200 { 0x00e0, 0x4000 },
201 { 0x00e1, 0x3131 },
202 { 0x00e4, 0x400c },
203 { 0x00e5, 0x8031 },
204 { 0x00ea, 0xb320 },
205 { 0x00eb, 0x0000 },
206 { 0x00ec, 0xb300 },
207 { 0x00ed, 0x0000 },
208 { 0x00f0, 0x0000 },
209 { 0x00f1, 0x0202 },
210 { 0x00f2, 0x0ddd },
211 { 0x00f3, 0x0ddd },
212 { 0x00f4, 0x0ddd },
213 { 0x00f6, 0x0000 },
214 { 0x00f7, 0x0000 },
215 { 0x00f8, 0x0000 },
216 { 0x00f9, 0x0000 },
217 { 0x00fa, 0x8000 },
218 { 0x00fb, 0x0000 },
219 { 0x00fc, 0x0000 },
220 { 0x00fd, 0x0001 },
221 { 0x00fe, 0x10ec },
222 { 0x00ff, 0x6311 },
223 { 0x0100, 0xaaaa },
224 { 0x010a, 0xaaaa },
225 { 0x010b, 0x00a0 },
226 { 0x010c, 0xaeae },
227 { 0x010d, 0xaaaa },
228 { 0x010e, 0xaaa8 },
229 { 0x010f, 0xa0aa },
230 { 0x0110, 0xe02a },
231 { 0x0111, 0xa702 },
232 { 0x0112, 0xaaaa },
233 { 0x0113, 0x2800 },
234 { 0x0116, 0x0000 },
235 { 0x0117, 0x0f00 },
236 { 0x011a, 0x0020 },
237 { 0x011b, 0x0011 },
238 { 0x011c, 0x0150 },
239 { 0x011d, 0x0000 },
240 { 0x011e, 0x0000 },
241 { 0x011f, 0x0000 },
242 { 0x0120, 0x0000 },
243 { 0x0121, 0x009b },
244 { 0x0122, 0x5014 },
245 { 0x0123, 0x0421 },
246 { 0x0124, 0x7cea },
247 { 0x0125, 0x0420 },
248 { 0x0126, 0x5550 },
249 { 0x0132, 0x0000 },
250 { 0x0133, 0x0000 },
251 { 0x0137, 0x5055 },
252 { 0x0138, 0x3700 },
253 { 0x0139, 0x79a1 },
254 { 0x013a, 0x2020 },
255 { 0x013b, 0x2020 },
256 { 0x013c, 0x2005 },
257 { 0x013e, 0x1f00 },
258 { 0x013f, 0x0000 },
259 { 0x0145, 0x0002 },
260 { 0x0146, 0x0000 },
261 { 0x0147, 0x0000 },
262 { 0x0148, 0x0000 },
263 { 0x0150, 0x1813 },
264 { 0x0151, 0x0690 },
265 { 0x0152, 0x1c17 },
266 { 0x0153, 0x6883 },
267 { 0x0154, 0xd3ce },
268 { 0x0155, 0x352d },
269 { 0x0156, 0x00eb },
270 { 0x0157, 0x3717 },
271 { 0x0158, 0x4c6a },
272 { 0x0159, 0xe41b },
273 { 0x015a, 0x2a13 },
274 { 0x015b, 0xb600 },
275 { 0x015c, 0xc730 },
276 { 0x015d, 0x35d4 },
277 { 0x015e, 0x00bf },
278 { 0x0160, 0x0ec0 },
279 { 0x0161, 0x0020 },
280 { 0x0162, 0x0080 },
281 { 0x0163, 0x0800 },
282 { 0x0164, 0x0000 },
283 { 0x0165, 0x0000 },
284 { 0x0166, 0x0000 },
285 { 0x0167, 0x001f },
286 { 0x0170, 0x4e80 },
287 { 0x0171, 0x0020 },
288 { 0x0172, 0x0080 },
289 { 0x0173, 0x0800 },
290 { 0x0174, 0x000c },
291 { 0x0175, 0x0000 },
292 { 0x0190, 0x3300 },
293 { 0x0191, 0x2200 },
294 { 0x0192, 0x0000 },
295 { 0x01b0, 0x4b38 },
296 { 0x01b1, 0x0000 },
297 { 0x01b2, 0x0000 },
298 { 0x01b3, 0x0000 },
299 { 0x01c0, 0x0045 },
300 { 0x01c1, 0x0540 },
301 { 0x01c2, 0x0000 },
302 { 0x01c3, 0x0030 },
303 { 0x01c7, 0x0000 },
304 { 0x01c8, 0x5757 },
305 { 0x01c9, 0x5757 },
306 { 0x01ca, 0x5757 },
307 { 0x01cb, 0x5757 },
308 { 0x01cc, 0x5757 },
309 { 0x01cd, 0x5757 },
310 { 0x01ce, 0x006f },
311 { 0x01da, 0x0000 },
312 { 0x01db, 0x0000 },
313 { 0x01de, 0x7d00 },
314 { 0x01df, 0x10c0 },
315 { 0x01e0, 0x06a1 },
316 { 0x01e1, 0x0000 },
317 { 0x01e2, 0x0000 },
318 { 0x01e3, 0x0000 },
319 { 0x01e4, 0x0001 },
320 { 0x01e6, 0x0000 },
321 { 0x01e7, 0x0000 },
322 { 0x01e8, 0x0000 },
323 { 0x01ea, 0x0000 },
324 { 0x01eb, 0x0000 },
325 { 0x01ec, 0x0000 },
326 { 0x01ed, 0x0000 },
327 { 0x01ee, 0x0000 },
328 { 0x01ef, 0x0000 },
329 { 0x01f0, 0x0000 },
330 { 0x01f1, 0x0000 },
331 { 0x01f2, 0x0000 },
332 { 0x01f6, 0x1e04 },
333 { 0x01f7, 0x01a1 },
334 { 0x01f8, 0x0000 },
335 { 0x01f9, 0x0000 },
336 { 0x01fa, 0x0002 },
337 { 0x01fb, 0x0000 },
338 { 0x01fc, 0x0000 },
339 { 0x01fd, 0x0000 },
340 { 0x01fe, 0x0000 },
341 { 0x0200, 0x066c },
342 { 0x0201, 0x7fff },
343 { 0x0202, 0x7fff },
344 { 0x0203, 0x0000 },
345 { 0x0204, 0x0000 },
346 { 0x0205, 0x0000 },
347 { 0x0206, 0x0000 },
348 { 0x0207, 0x0000 },
349 { 0x0208, 0x0000 },
350 { 0x0256, 0x0000 },
351 { 0x0257, 0x0000 },
352 { 0x0258, 0x0000 },
353 { 0x0259, 0x0000 },
354 { 0x025a, 0x0000 },
355 { 0x025b, 0x3333 },
356 { 0x025c, 0x3333 },
357 { 0x025d, 0x3333 },
358 { 0x025e, 0x0000 },
359 { 0x025f, 0x0000 },
360 { 0x0260, 0x0000 },
361 { 0x0261, 0x0022 },
362 { 0x0262, 0x0300 },
363 { 0x0265, 0x1e80 },
364 { 0x0266, 0x0131 },
365 { 0x0267, 0x0003 },
366 { 0x0268, 0x0000 },
367 { 0x0269, 0x0000 },
368 { 0x026a, 0x0000 },
369 { 0x026b, 0x0000 },
370 { 0x026c, 0x0000 },
371 { 0x026d, 0x0000 },
372 { 0x026e, 0x0000 },
373 { 0x026f, 0x0000 },
374 { 0x0270, 0x0000 },
375 { 0x0271, 0x0000 },
376 { 0x0272, 0x0000 },
377 { 0x0273, 0x0000 },
378 { 0x0280, 0x0000 },
379 { 0x0281, 0x0000 },
380 { 0x0282, 0x0418 },
381 { 0x0283, 0x7fff },
382 { 0x0284, 0x7000 },
383 { 0x0290, 0x01d0 },
384 { 0x0291, 0x0100 },
385 { 0x02fa, 0x0000 },
386 { 0x02fb, 0x0000 },
387 { 0x02fc, 0x0000 },
388 { 0x0300, 0x001f },
389 { 0x0301, 0x032c },
390 { 0x0302, 0x5f21 },
391 { 0x0303, 0x4000 },
392 { 0x0304, 0x4000 },
393 { 0x0305, 0x0600 },
394 { 0x0306, 0x8000 },
395 { 0x0307, 0x0700 },
396 { 0x0308, 0x001f },
397 { 0x0309, 0x032c },
398 { 0x030a, 0x5f21 },
399 { 0x030b, 0x4000 },
400 { 0x030c, 0x4000 },
401 { 0x030d, 0x0600 },
402 { 0x030e, 0x8000 },
403 { 0x030f, 0x0700 },
404 { 0x0310, 0x4560 },
405 { 0x0311, 0xa4a8 },
406 { 0x0312, 0x7418 },
407 { 0x0313, 0x0000 },
408 { 0x0314, 0x0006 },
409 { 0x0315, 0x00ff },
410 { 0x0316, 0xc400 },
411 { 0x0317, 0x4560 },
412 { 0x0318, 0xa4a8 },
413 { 0x0319, 0x7418 },
414 { 0x031a, 0x0000 },
415 { 0x031b, 0x0006 },
416 { 0x031c, 0x00ff },
417 { 0x031d, 0xc400 },
418 { 0x0320, 0x0f20 },
419 { 0x0321, 0x8700 },
420 { 0x0322, 0x7dc2 },
421 { 0x0323, 0xa178 },
422 { 0x0324, 0x5383 },
423 { 0x0325, 0x7dc2 },
424 { 0x0326, 0xa178 },
425 { 0x0327, 0x5383 },
426 { 0x0328, 0x003e },
427 { 0x0329, 0x02c1 },
428 { 0x032a, 0xd37d },
429 { 0x0330, 0x00a6 },
430 { 0x0331, 0x04c3 },
431 { 0x0332, 0x27c8 },
432 { 0x0333, 0xbf50 },
433 { 0x0334, 0x0045 },
434 { 0x0335, 0x2007 },
435 { 0x0336, 0x7418 },
436 { 0x0337, 0x0501 },
437 { 0x0338, 0x0000 },
438 { 0x0339, 0x0010 },
439 { 0x033a, 0x1010 },
440 { 0x0340, 0x0800 },
441 { 0x0341, 0x0800 },
442 { 0x0342, 0x0800 },
443 { 0x0343, 0x0800 },
444 { 0x0344, 0x0000 },
445 { 0x0345, 0x0000 },
446 { 0x0346, 0x0000 },
447 { 0x0347, 0x0000 },
448 { 0x0348, 0x0000 },
449 { 0x0349, 0x0000 },
450 { 0x034a, 0x0000 },
451 { 0x034b, 0x0000 },
452 { 0x034c, 0x0000 },
453 { 0x034d, 0x0000 },
454 { 0x034e, 0x0000 },
455 { 0x034f, 0x0000 },
456 { 0x0350, 0x0000 },
457 { 0x0351, 0x0000 },
458 { 0x0352, 0x0000 },
459 { 0x0353, 0x0000 },
460 { 0x0354, 0x0000 },
461 { 0x0355, 0x0000 },
462 { 0x0356, 0x0000 },
463 { 0x0357, 0x0000 },
464 { 0x0358, 0x0000 },
465 { 0x0359, 0x0000 },
466 { 0x035a, 0x0000 },
467 { 0x035b, 0x0000 },
468 { 0x035c, 0x0000 },
469 { 0x035d, 0x0000 },
470 { 0x035e, 0x2000 },
471 { 0x035f, 0x0000 },
472 { 0x0360, 0x2000 },
473 { 0x0361, 0x2000 },
474 { 0x0362, 0x0000 },
475 { 0x0363, 0x2000 },
476 { 0x0364, 0x0200 },
477 { 0x0365, 0x0000 },
478 { 0x0366, 0x0000 },
479 { 0x0367, 0x0000 },
480 { 0x0368, 0x0000 },
481 { 0x0369, 0x0000 },
482 { 0x036a, 0x0000 },
483 { 0x036b, 0x0000 },
484 { 0x036c, 0x0000 },
485 { 0x036d, 0x0000 },
486 { 0x036e, 0x0200 },
487 { 0x036f, 0x0000 },
488 { 0x0370, 0x0000 },
489 { 0x0371, 0x0000 },
490 { 0x0372, 0x0000 },
491 { 0x0373, 0x0000 },
492 { 0x0374, 0x0000 },
493 { 0x0375, 0x0000 },
494 { 0x0376, 0x0000 },
495 { 0x0377, 0x0000 },
496 { 0x03d0, 0x0000 },
497 { 0x03d1, 0x0000 },
498 { 0x03d2, 0x0000 },
499 { 0x03d3, 0x0000 },
500 { 0x03d4, 0x2000 },
501 { 0x03d5, 0x2000 },
502 { 0x03d6, 0x0000 },
503 { 0x03d7, 0x0000 },
504 { 0x03d8, 0x2000 },
505 { 0x03d9, 0x2000 },
506 { 0x03da, 0x2000 },
507 { 0x03db, 0x2000 },
508 { 0x03dc, 0x0000 },
509 { 0x03dd, 0x0000 },
510 { 0x03de, 0x0000 },
511 { 0x03df, 0x2000 },
512 { 0x03e0, 0x0000 },
513 { 0x03e1, 0x0000 },
514 { 0x03e2, 0x0000 },
515 { 0x03e3, 0x0000 },
516 { 0x03e4, 0x0000 },
517 { 0x03e5, 0x0000 },
518 { 0x03e6, 0x0000 },
519 { 0x03e7, 0x0000 },
520 { 0x03e8, 0x0000 },
521 { 0x03e9, 0x0000 },
522 { 0x03ea, 0x0000 },
523 { 0x03eb, 0x0000 },
524 { 0x03ec, 0x0000 },
525 { 0x03ed, 0x0000 },
526 { 0x03ee, 0x0000 },
527 { 0x03ef, 0x0000 },
528 { 0x03f0, 0x0800 },
529 { 0x03f1, 0x0800 },
530 { 0x03f2, 0x0800 },
531 { 0x03f3, 0x0800 },
532 };
533
534 static bool rt5659_volatile_register(struct device *dev, unsigned int reg)
535 {
536 switch (reg) {
537 case RT5659_RESET:
538 case RT5659_EJD_CTRL_2:
539 case RT5659_SILENCE_CTRL:
540 case RT5659_DAC2_DIG_VOL:
541 case RT5659_HP_IMP_GAIN_2:
542 case RT5659_PDM_OUT_CTRL:
543 case RT5659_PDM_DATA_CTRL_1:
544 case RT5659_PDM_DATA_CTRL_4:
545 case RT5659_HAPTIC_GEN_CTRL_1:
546 case RT5659_HAPTIC_GEN_CTRL_3:
547 case RT5659_HAPTIC_LPF_CTRL_3:
548 case RT5659_CLK_DET:
549 case RT5659_MICBIAS_1:
550 case RT5659_ASRC_11:
551 case RT5659_ADC_EQ_CTRL_1:
552 case RT5659_DAC_EQ_CTRL_1:
553 case RT5659_INT_ST_1:
554 case RT5659_INT_ST_2:
555 case RT5659_GPIO_STA:
556 case RT5659_SINE_GEN_CTRL_1:
557 case RT5659_IL_CMD_1:
558 case RT5659_4BTN_IL_CMD_1:
559 case RT5659_PSV_IL_CMD_1:
560 case RT5659_AJD1_CTRL:
561 case RT5659_AJD2_AJD3_CTRL:
562 case RT5659_JD_CTRL_3:
563 case RT5659_VENDOR_ID:
564 case RT5659_VENDOR_ID_1:
565 case RT5659_DEVICE_ID:
566 case RT5659_MEMORY_TEST:
567 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
568 case RT5659_VOL_TEST:
569 case RT5659_STO_NG2_CTRL_1:
570 case RT5659_STO_NG2_CTRL_5:
571 case RT5659_STO_NG2_CTRL_6:
572 case RT5659_STO_NG2_CTRL_7:
573 case RT5659_MONO_NG2_CTRL_1:
574 case RT5659_MONO_NG2_CTRL_5:
575 case RT5659_MONO_NG2_CTRL_6:
576 case RT5659_HP_IMP_SENS_CTRL_1:
577 case RT5659_HP_IMP_SENS_CTRL_3:
578 case RT5659_HP_IMP_SENS_CTRL_4:
579 case RT5659_HP_CALIB_CTRL_1:
580 case RT5659_HP_CALIB_CTRL_9:
581 case RT5659_HP_CALIB_STA_1:
582 case RT5659_HP_CALIB_STA_2:
583 case RT5659_HP_CALIB_STA_3:
584 case RT5659_HP_CALIB_STA_4:
585 case RT5659_HP_CALIB_STA_5:
586 case RT5659_HP_CALIB_STA_6:
587 case RT5659_HP_CALIB_STA_7:
588 case RT5659_HP_CALIB_STA_8:
589 case RT5659_HP_CALIB_STA_9:
590 case RT5659_MONO_AMP_CALIB_CTRL_1:
591 case RT5659_MONO_AMP_CALIB_CTRL_3:
592 case RT5659_MONO_AMP_CALIB_STA_1:
593 case RT5659_MONO_AMP_CALIB_STA_2:
594 case RT5659_MONO_AMP_CALIB_STA_3:
595 case RT5659_MONO_AMP_CALIB_STA_4:
596 case RT5659_SPK_PWR_LMT_STA_1:
597 case RT5659_SPK_PWR_LMT_STA_2:
598 case RT5659_SPK_PWR_LMT_STA_3:
599 case RT5659_SPK_PWR_LMT_STA_4:
600 case RT5659_SPK_PWR_LMT_STA_5:
601 case RT5659_SPK_PWR_LMT_STA_6:
602 case RT5659_SPK_DC_CAILB_CTRL_1:
603 case RT5659_SPK_DC_CAILB_STA_1:
604 case RT5659_SPK_DC_CAILB_STA_2:
605 case RT5659_SPK_DC_CAILB_STA_3:
606 case RT5659_SPK_DC_CAILB_STA_4:
607 case RT5659_SPK_DC_CAILB_STA_5:
608 case RT5659_SPK_DC_CAILB_STA_6:
609 case RT5659_SPK_DC_CAILB_STA_7:
610 case RT5659_SPK_DC_CAILB_STA_8:
611 case RT5659_SPK_DC_CAILB_STA_9:
612 case RT5659_SPK_DC_CAILB_STA_10:
613 case RT5659_SPK_VDD_STA_1:
614 case RT5659_SPK_VDD_STA_2:
615 case RT5659_SPK_DC_DET_CTRL_1:
616 case RT5659_PURE_DC_DET_CTRL_1:
617 case RT5659_PURE_DC_DET_CTRL_2:
618 case RT5659_DRC1_PRIV_1:
619 case RT5659_DRC1_PRIV_4:
620 case RT5659_DRC1_PRIV_5:
621 case RT5659_DRC1_PRIV_6:
622 case RT5659_DRC1_PRIV_7:
623 case RT5659_DRC2_PRIV_1:
624 case RT5659_DRC2_PRIV_4:
625 case RT5659_DRC2_PRIV_5:
626 case RT5659_DRC2_PRIV_6:
627 case RT5659_DRC2_PRIV_7:
628 case RT5659_ALC_PGA_STA_1:
629 case RT5659_ALC_PGA_STA_2:
630 case RT5659_ALC_PGA_STA_3:
631 return true;
632 default:
633 return false;
634 }
635 }
636
637 static bool rt5659_readable_register(struct device *dev, unsigned int reg)
638 {
639 switch (reg) {
640 case RT5659_RESET:
641 case RT5659_SPO_VOL:
642 case RT5659_HP_VOL:
643 case RT5659_LOUT:
644 case RT5659_MONO_OUT:
645 case RT5659_HPL_GAIN:
646 case RT5659_HPR_GAIN:
647 case RT5659_MONO_GAIN:
648 case RT5659_SPDIF_CTRL_1:
649 case RT5659_SPDIF_CTRL_2:
650 case RT5659_CAL_BST_CTRL:
651 case RT5659_IN1_IN2:
652 case RT5659_IN3_IN4:
653 case RT5659_INL1_INR1_VOL:
654 case RT5659_EJD_CTRL_1:
655 case RT5659_EJD_CTRL_2:
656 case RT5659_EJD_CTRL_3:
657 case RT5659_SILENCE_CTRL:
658 case RT5659_PSV_CTRL:
659 case RT5659_SIDETONE_CTRL:
660 case RT5659_DAC1_DIG_VOL:
661 case RT5659_DAC2_DIG_VOL:
662 case RT5659_DAC_CTRL:
663 case RT5659_STO1_ADC_DIG_VOL:
664 case RT5659_MONO_ADC_DIG_VOL:
665 case RT5659_STO2_ADC_DIG_VOL:
666 case RT5659_STO1_BOOST:
667 case RT5659_MONO_BOOST:
668 case RT5659_STO2_BOOST:
669 case RT5659_HP_IMP_GAIN_1:
670 case RT5659_HP_IMP_GAIN_2:
671 case RT5659_STO1_ADC_MIXER:
672 case RT5659_MONO_ADC_MIXER:
673 case RT5659_AD_DA_MIXER:
674 case RT5659_STO_DAC_MIXER:
675 case RT5659_MONO_DAC_MIXER:
676 case RT5659_DIG_MIXER:
677 case RT5659_A_DAC_MUX:
678 case RT5659_DIG_INF23_DATA:
679 case RT5659_PDM_OUT_CTRL:
680 case RT5659_PDM_DATA_CTRL_1:
681 case RT5659_PDM_DATA_CTRL_2:
682 case RT5659_PDM_DATA_CTRL_3:
683 case RT5659_PDM_DATA_CTRL_4:
684 case RT5659_SPDIF_CTRL:
685 case RT5659_REC1_GAIN:
686 case RT5659_REC1_L1_MIXER:
687 case RT5659_REC1_L2_MIXER:
688 case RT5659_REC1_R1_MIXER:
689 case RT5659_REC1_R2_MIXER:
690 case RT5659_CAL_REC:
691 case RT5659_REC2_L1_MIXER:
692 case RT5659_REC2_L2_MIXER:
693 case RT5659_REC2_R1_MIXER:
694 case RT5659_REC2_R2_MIXER:
695 case RT5659_SPK_L_MIXER:
696 case RT5659_SPK_R_MIXER:
697 case RT5659_SPO_AMP_GAIN:
698 case RT5659_ALC_BACK_GAIN:
699 case RT5659_MONOMIX_GAIN:
700 case RT5659_MONOMIX_IN_GAIN:
701 case RT5659_OUT_L_GAIN:
702 case RT5659_OUT_L_MIXER:
703 case RT5659_OUT_R_GAIN:
704 case RT5659_OUT_R_MIXER:
705 case RT5659_LOUT_MIXER:
706 case RT5659_HAPTIC_GEN_CTRL_1:
707 case RT5659_HAPTIC_GEN_CTRL_2:
708 case RT5659_HAPTIC_GEN_CTRL_3:
709 case RT5659_HAPTIC_GEN_CTRL_4:
710 case RT5659_HAPTIC_GEN_CTRL_5:
711 case RT5659_HAPTIC_GEN_CTRL_6:
712 case RT5659_HAPTIC_GEN_CTRL_7:
713 case RT5659_HAPTIC_GEN_CTRL_8:
714 case RT5659_HAPTIC_GEN_CTRL_9:
715 case RT5659_HAPTIC_GEN_CTRL_10:
716 case RT5659_HAPTIC_GEN_CTRL_11:
717 case RT5659_HAPTIC_LPF_CTRL_1:
718 case RT5659_HAPTIC_LPF_CTRL_2:
719 case RT5659_HAPTIC_LPF_CTRL_3:
720 case RT5659_PWR_DIG_1:
721 case RT5659_PWR_DIG_2:
722 case RT5659_PWR_ANLG_1:
723 case RT5659_PWR_ANLG_2:
724 case RT5659_PWR_ANLG_3:
725 case RT5659_PWR_MIXER:
726 case RT5659_PWR_VOL:
727 case RT5659_PRIV_INDEX:
728 case RT5659_CLK_DET:
729 case RT5659_PRIV_DATA:
730 case RT5659_PRE_DIV_1:
731 case RT5659_PRE_DIV_2:
732 case RT5659_I2S1_SDP:
733 case RT5659_I2S2_SDP:
734 case RT5659_I2S3_SDP:
735 case RT5659_ADDA_CLK_1:
736 case RT5659_ADDA_CLK_2:
737 case RT5659_DMIC_CTRL_1:
738 case RT5659_DMIC_CTRL_2:
739 case RT5659_TDM_CTRL_1:
740 case RT5659_TDM_CTRL_2:
741 case RT5659_TDM_CTRL_3:
742 case RT5659_TDM_CTRL_4:
743 case RT5659_TDM_CTRL_5:
744 case RT5659_GLB_CLK:
745 case RT5659_PLL_CTRL_1:
746 case RT5659_PLL_CTRL_2:
747 case RT5659_ASRC_1:
748 case RT5659_ASRC_2:
749 case RT5659_ASRC_3:
750 case RT5659_ASRC_4:
751 case RT5659_ASRC_5:
752 case RT5659_ASRC_6:
753 case RT5659_ASRC_7:
754 case RT5659_ASRC_8:
755 case RT5659_ASRC_9:
756 case RT5659_ASRC_10:
757 case RT5659_DEPOP_1:
758 case RT5659_DEPOP_2:
759 case RT5659_DEPOP_3:
760 case RT5659_HP_CHARGE_PUMP_1:
761 case RT5659_HP_CHARGE_PUMP_2:
762 case RT5659_MICBIAS_1:
763 case RT5659_MICBIAS_2:
764 case RT5659_ASRC_11:
765 case RT5659_ASRC_12:
766 case RT5659_ASRC_13:
767 case RT5659_REC_M1_M2_GAIN_CTRL:
768 case RT5659_RC_CLK_CTRL:
769 case RT5659_CLASSD_CTRL_1:
770 case RT5659_CLASSD_CTRL_2:
771 case RT5659_ADC_EQ_CTRL_1:
772 case RT5659_ADC_EQ_CTRL_2:
773 case RT5659_DAC_EQ_CTRL_1:
774 case RT5659_DAC_EQ_CTRL_2:
775 case RT5659_DAC_EQ_CTRL_3:
776 case RT5659_IRQ_CTRL_1:
777 case RT5659_IRQ_CTRL_2:
778 case RT5659_IRQ_CTRL_3:
779 case RT5659_IRQ_CTRL_4:
780 case RT5659_IRQ_CTRL_5:
781 case RT5659_IRQ_CTRL_6:
782 case RT5659_INT_ST_1:
783 case RT5659_INT_ST_2:
784 case RT5659_GPIO_CTRL_1:
785 case RT5659_GPIO_CTRL_2:
786 case RT5659_GPIO_CTRL_3:
787 case RT5659_GPIO_CTRL_4:
788 case RT5659_GPIO_CTRL_5:
789 case RT5659_GPIO_STA:
790 case RT5659_SINE_GEN_CTRL_1:
791 case RT5659_SINE_GEN_CTRL_2:
792 case RT5659_SINE_GEN_CTRL_3:
793 case RT5659_HP_AMP_DET_CTRL_1:
794 case RT5659_HP_AMP_DET_CTRL_2:
795 case RT5659_SV_ZCD_1:
796 case RT5659_SV_ZCD_2:
797 case RT5659_IL_CMD_1:
798 case RT5659_IL_CMD_2:
799 case RT5659_IL_CMD_3:
800 case RT5659_IL_CMD_4:
801 case RT5659_4BTN_IL_CMD_1:
802 case RT5659_4BTN_IL_CMD_2:
803 case RT5659_4BTN_IL_CMD_3:
804 case RT5659_PSV_IL_CMD_1:
805 case RT5659_PSV_IL_CMD_2:
806 case RT5659_ADC_STO1_HP_CTRL_1:
807 case RT5659_ADC_STO1_HP_CTRL_2:
808 case RT5659_ADC_MONO_HP_CTRL_1:
809 case RT5659_ADC_MONO_HP_CTRL_2:
810 case RT5659_AJD1_CTRL:
811 case RT5659_AJD2_AJD3_CTRL:
812 case RT5659_JD1_THD:
813 case RT5659_JD2_THD:
814 case RT5659_JD3_THD:
815 case RT5659_JD_CTRL_1:
816 case RT5659_JD_CTRL_2:
817 case RT5659_JD_CTRL_3:
818 case RT5659_JD_CTRL_4:
819 case RT5659_DIG_MISC:
820 case RT5659_DUMMY_2:
821 case RT5659_DUMMY_3:
822 case RT5659_VENDOR_ID:
823 case RT5659_VENDOR_ID_1:
824 case RT5659_DEVICE_ID:
825 case RT5659_DAC_ADC_DIG_VOL:
826 case RT5659_BIAS_CUR_CTRL_1:
827 case RT5659_BIAS_CUR_CTRL_2:
828 case RT5659_BIAS_CUR_CTRL_3:
829 case RT5659_BIAS_CUR_CTRL_4:
830 case RT5659_BIAS_CUR_CTRL_5:
831 case RT5659_BIAS_CUR_CTRL_6:
832 case RT5659_BIAS_CUR_CTRL_7:
833 case RT5659_BIAS_CUR_CTRL_8:
834 case RT5659_BIAS_CUR_CTRL_9:
835 case RT5659_BIAS_CUR_CTRL_10:
836 case RT5659_MEMORY_TEST:
837 case RT5659_VREF_REC_OP_FB_CAP_CTRL:
838 case RT5659_CLASSD_0:
839 case RT5659_CLASSD_1:
840 case RT5659_CLASSD_2:
841 case RT5659_CLASSD_3:
842 case RT5659_CLASSD_4:
843 case RT5659_CLASSD_5:
844 case RT5659_CLASSD_6:
845 case RT5659_CLASSD_7:
846 case RT5659_CLASSD_8:
847 case RT5659_CLASSD_9:
848 case RT5659_CLASSD_10:
849 case RT5659_CHARGE_PUMP_1:
850 case RT5659_CHARGE_PUMP_2:
851 case RT5659_DIG_IN_CTRL_1:
852 case RT5659_DIG_IN_CTRL_2:
853 case RT5659_PAD_DRIVING_CTRL:
854 case RT5659_SOFT_RAMP_DEPOP:
855 case RT5659_PLL:
856 case RT5659_CHOP_DAC:
857 case RT5659_CHOP_ADC:
858 case RT5659_CALIB_ADC_CTRL:
859 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
860 case RT5659_VOL_TEST:
861 case RT5659_TEST_MODE_CTRL_1:
862 case RT5659_TEST_MODE_CTRL_2:
863 case RT5659_TEST_MODE_CTRL_3:
864 case RT5659_TEST_MODE_CTRL_4:
865 case RT5659_BASSBACK_CTRL:
866 case RT5659_MP3_PLUS_CTRL_1:
867 case RT5659_MP3_PLUS_CTRL_2:
868 case RT5659_MP3_HPF_A1:
869 case RT5659_MP3_HPF_A2:
870 case RT5659_MP3_HPF_H0:
871 case RT5659_MP3_LPF_H0:
872 case RT5659_3D_SPK_CTRL:
873 case RT5659_3D_SPK_COEF_1:
874 case RT5659_3D_SPK_COEF_2:
875 case RT5659_3D_SPK_COEF_3:
876 case RT5659_3D_SPK_COEF_4:
877 case RT5659_3D_SPK_COEF_5:
878 case RT5659_3D_SPK_COEF_6:
879 case RT5659_3D_SPK_COEF_7:
880 case RT5659_STO_NG2_CTRL_1:
881 case RT5659_STO_NG2_CTRL_2:
882 case RT5659_STO_NG2_CTRL_3:
883 case RT5659_STO_NG2_CTRL_4:
884 case RT5659_STO_NG2_CTRL_5:
885 case RT5659_STO_NG2_CTRL_6:
886 case RT5659_STO_NG2_CTRL_7:
887 case RT5659_STO_NG2_CTRL_8:
888 case RT5659_MONO_NG2_CTRL_1:
889 case RT5659_MONO_NG2_CTRL_2:
890 case RT5659_MONO_NG2_CTRL_3:
891 case RT5659_MONO_NG2_CTRL_4:
892 case RT5659_MONO_NG2_CTRL_5:
893 case RT5659_MONO_NG2_CTRL_6:
894 case RT5659_MID_HP_AMP_DET:
895 case RT5659_LOW_HP_AMP_DET:
896 case RT5659_LDO_CTRL:
897 case RT5659_HP_DECROSS_CTRL_1:
898 case RT5659_HP_DECROSS_CTRL_2:
899 case RT5659_HP_DECROSS_CTRL_3:
900 case RT5659_HP_DECROSS_CTRL_4:
901 case RT5659_HP_IMP_SENS_CTRL_1:
902 case RT5659_HP_IMP_SENS_CTRL_2:
903 case RT5659_HP_IMP_SENS_CTRL_3:
904 case RT5659_HP_IMP_SENS_CTRL_4:
905 case RT5659_HP_IMP_SENS_MAP_1:
906 case RT5659_HP_IMP_SENS_MAP_2:
907 case RT5659_HP_IMP_SENS_MAP_3:
908 case RT5659_HP_IMP_SENS_MAP_4:
909 case RT5659_HP_IMP_SENS_MAP_5:
910 case RT5659_HP_IMP_SENS_MAP_6:
911 case RT5659_HP_IMP_SENS_MAP_7:
912 case RT5659_HP_IMP_SENS_MAP_8:
913 case RT5659_HP_LOGIC_CTRL_1:
914 case RT5659_HP_LOGIC_CTRL_2:
915 case RT5659_HP_CALIB_CTRL_1:
916 case RT5659_HP_CALIB_CTRL_2:
917 case RT5659_HP_CALIB_CTRL_3:
918 case RT5659_HP_CALIB_CTRL_4:
919 case RT5659_HP_CALIB_CTRL_5:
920 case RT5659_HP_CALIB_CTRL_6:
921 case RT5659_HP_CALIB_CTRL_7:
922 case RT5659_HP_CALIB_CTRL_9:
923 case RT5659_HP_CALIB_CTRL_10:
924 case RT5659_HP_CALIB_CTRL_11:
925 case RT5659_HP_CALIB_STA_1:
926 case RT5659_HP_CALIB_STA_2:
927 case RT5659_HP_CALIB_STA_3:
928 case RT5659_HP_CALIB_STA_4:
929 case RT5659_HP_CALIB_STA_5:
930 case RT5659_HP_CALIB_STA_6:
931 case RT5659_HP_CALIB_STA_7:
932 case RT5659_HP_CALIB_STA_8:
933 case RT5659_HP_CALIB_STA_9:
934 case RT5659_MONO_AMP_CALIB_CTRL_1:
935 case RT5659_MONO_AMP_CALIB_CTRL_2:
936 case RT5659_MONO_AMP_CALIB_CTRL_3:
937 case RT5659_MONO_AMP_CALIB_CTRL_4:
938 case RT5659_MONO_AMP_CALIB_CTRL_5:
939 case RT5659_MONO_AMP_CALIB_STA_1:
940 case RT5659_MONO_AMP_CALIB_STA_2:
941 case RT5659_MONO_AMP_CALIB_STA_3:
942 case RT5659_MONO_AMP_CALIB_STA_4:
943 case RT5659_SPK_PWR_LMT_CTRL_1:
944 case RT5659_SPK_PWR_LMT_CTRL_2:
945 case RT5659_SPK_PWR_LMT_CTRL_3:
946 case RT5659_SPK_PWR_LMT_STA_1:
947 case RT5659_SPK_PWR_LMT_STA_2:
948 case RT5659_SPK_PWR_LMT_STA_3:
949 case RT5659_SPK_PWR_LMT_STA_4:
950 case RT5659_SPK_PWR_LMT_STA_5:
951 case RT5659_SPK_PWR_LMT_STA_6:
952 case RT5659_FLEX_SPK_BST_CTRL_1:
953 case RT5659_FLEX_SPK_BST_CTRL_2:
954 case RT5659_FLEX_SPK_BST_CTRL_3:
955 case RT5659_FLEX_SPK_BST_CTRL_4:
956 case RT5659_SPK_EX_LMT_CTRL_1:
957 case RT5659_SPK_EX_LMT_CTRL_2:
958 case RT5659_SPK_EX_LMT_CTRL_3:
959 case RT5659_SPK_EX_LMT_CTRL_4:
960 case RT5659_SPK_EX_LMT_CTRL_5:
961 case RT5659_SPK_EX_LMT_CTRL_6:
962 case RT5659_SPK_EX_LMT_CTRL_7:
963 case RT5659_ADJ_HPF_CTRL_1:
964 case RT5659_ADJ_HPF_CTRL_2:
965 case RT5659_SPK_DC_CAILB_CTRL_1:
966 case RT5659_SPK_DC_CAILB_CTRL_2:
967 case RT5659_SPK_DC_CAILB_CTRL_3:
968 case RT5659_SPK_DC_CAILB_CTRL_4:
969 case RT5659_SPK_DC_CAILB_CTRL_5:
970 case RT5659_SPK_DC_CAILB_STA_1:
971 case RT5659_SPK_DC_CAILB_STA_2:
972 case RT5659_SPK_DC_CAILB_STA_3:
973 case RT5659_SPK_DC_CAILB_STA_4:
974 case RT5659_SPK_DC_CAILB_STA_5:
975 case RT5659_SPK_DC_CAILB_STA_6:
976 case RT5659_SPK_DC_CAILB_STA_7:
977 case RT5659_SPK_DC_CAILB_STA_8:
978 case RT5659_SPK_DC_CAILB_STA_9:
979 case RT5659_SPK_DC_CAILB_STA_10:
980 case RT5659_SPK_VDD_STA_1:
981 case RT5659_SPK_VDD_STA_2:
982 case RT5659_SPK_DC_DET_CTRL_1:
983 case RT5659_SPK_DC_DET_CTRL_2:
984 case RT5659_SPK_DC_DET_CTRL_3:
985 case RT5659_PURE_DC_DET_CTRL_1:
986 case RT5659_PURE_DC_DET_CTRL_2:
987 case RT5659_DUMMY_4:
988 case RT5659_DUMMY_5:
989 case RT5659_DUMMY_6:
990 case RT5659_DRC1_CTRL_1:
991 case RT5659_DRC1_CTRL_2:
992 case RT5659_DRC1_CTRL_3:
993 case RT5659_DRC1_CTRL_4:
994 case RT5659_DRC1_CTRL_5:
995 case RT5659_DRC1_CTRL_6:
996 case RT5659_DRC1_HARD_LMT_CTRL_1:
997 case RT5659_DRC1_HARD_LMT_CTRL_2:
998 case RT5659_DRC2_CTRL_1:
999 case RT5659_DRC2_CTRL_2:
1000 case RT5659_DRC2_CTRL_3:
1001 case RT5659_DRC2_CTRL_4:
1002 case RT5659_DRC2_CTRL_5:
1003 case RT5659_DRC2_CTRL_6:
1004 case RT5659_DRC2_HARD_LMT_CTRL_1:
1005 case RT5659_DRC2_HARD_LMT_CTRL_2:
1006 case RT5659_DRC1_PRIV_1:
1007 case RT5659_DRC1_PRIV_2:
1008 case RT5659_DRC1_PRIV_3:
1009 case RT5659_DRC1_PRIV_4:
1010 case RT5659_DRC1_PRIV_5:
1011 case RT5659_DRC1_PRIV_6:
1012 case RT5659_DRC1_PRIV_7:
1013 case RT5659_DRC2_PRIV_1:
1014 case RT5659_DRC2_PRIV_2:
1015 case RT5659_DRC2_PRIV_3:
1016 case RT5659_DRC2_PRIV_4:
1017 case RT5659_DRC2_PRIV_5:
1018 case RT5659_DRC2_PRIV_6:
1019 case RT5659_DRC2_PRIV_7:
1020 case RT5659_MULTI_DRC_CTRL:
1021 case RT5659_CROSS_OVER_1:
1022 case RT5659_CROSS_OVER_2:
1023 case RT5659_CROSS_OVER_3:
1024 case RT5659_CROSS_OVER_4:
1025 case RT5659_CROSS_OVER_5:
1026 case RT5659_CROSS_OVER_6:
1027 case RT5659_CROSS_OVER_7:
1028 case RT5659_CROSS_OVER_8:
1029 case RT5659_CROSS_OVER_9:
1030 case RT5659_CROSS_OVER_10:
1031 case RT5659_ALC_PGA_CTRL_1:
1032 case RT5659_ALC_PGA_CTRL_2:
1033 case RT5659_ALC_PGA_CTRL_3:
1034 case RT5659_ALC_PGA_CTRL_4:
1035 case RT5659_ALC_PGA_CTRL_5:
1036 case RT5659_ALC_PGA_CTRL_6:
1037 case RT5659_ALC_PGA_CTRL_7:
1038 case RT5659_ALC_PGA_CTRL_8:
1039 case RT5659_ALC_PGA_STA_1:
1040 case RT5659_ALC_PGA_STA_2:
1041 case RT5659_ALC_PGA_STA_3:
1042 case RT5659_DAC_L_EQ_PRE_VOL:
1043 case RT5659_DAC_R_EQ_PRE_VOL:
1044 case RT5659_DAC_L_EQ_POST_VOL:
1045 case RT5659_DAC_R_EQ_POST_VOL:
1046 case RT5659_DAC_L_EQ_LPF1_A1:
1047 case RT5659_DAC_L_EQ_LPF1_H0:
1048 case RT5659_DAC_R_EQ_LPF1_A1:
1049 case RT5659_DAC_R_EQ_LPF1_H0:
1050 case RT5659_DAC_L_EQ_BPF2_A1:
1051 case RT5659_DAC_L_EQ_BPF2_A2:
1052 case RT5659_DAC_L_EQ_BPF2_H0:
1053 case RT5659_DAC_R_EQ_BPF2_A1:
1054 case RT5659_DAC_R_EQ_BPF2_A2:
1055 case RT5659_DAC_R_EQ_BPF2_H0:
1056 case RT5659_DAC_L_EQ_BPF3_A1:
1057 case RT5659_DAC_L_EQ_BPF3_A2:
1058 case RT5659_DAC_L_EQ_BPF3_H0:
1059 case RT5659_DAC_R_EQ_BPF3_A1:
1060 case RT5659_DAC_R_EQ_BPF3_A2:
1061 case RT5659_DAC_R_EQ_BPF3_H0:
1062 case RT5659_DAC_L_EQ_BPF4_A1:
1063 case RT5659_DAC_L_EQ_BPF4_A2:
1064 case RT5659_DAC_L_EQ_BPF4_H0:
1065 case RT5659_DAC_R_EQ_BPF4_A1:
1066 case RT5659_DAC_R_EQ_BPF4_A2:
1067 case RT5659_DAC_R_EQ_BPF4_H0:
1068 case RT5659_DAC_L_EQ_HPF1_A1:
1069 case RT5659_DAC_L_EQ_HPF1_H0:
1070 case RT5659_DAC_R_EQ_HPF1_A1:
1071 case RT5659_DAC_R_EQ_HPF1_H0:
1072 case RT5659_DAC_L_EQ_HPF2_A1:
1073 case RT5659_DAC_L_EQ_HPF2_A2:
1074 case RT5659_DAC_L_EQ_HPF2_H0:
1075 case RT5659_DAC_R_EQ_HPF2_A1:
1076 case RT5659_DAC_R_EQ_HPF2_A2:
1077 case RT5659_DAC_R_EQ_HPF2_H0:
1078 case RT5659_DAC_L_BI_EQ_BPF1_H0_1:
1079 case RT5659_DAC_L_BI_EQ_BPF1_H0_2:
1080 case RT5659_DAC_L_BI_EQ_BPF1_B1_1:
1081 case RT5659_DAC_L_BI_EQ_BPF1_B1_2:
1082 case RT5659_DAC_L_BI_EQ_BPF1_B2_1:
1083 case RT5659_DAC_L_BI_EQ_BPF1_B2_2:
1084 case RT5659_DAC_L_BI_EQ_BPF1_A1_1:
1085 case RT5659_DAC_L_BI_EQ_BPF1_A1_2:
1086 case RT5659_DAC_L_BI_EQ_BPF1_A2_1:
1087 case RT5659_DAC_L_BI_EQ_BPF1_A2_2:
1088 case RT5659_DAC_R_BI_EQ_BPF1_H0_1:
1089 case RT5659_DAC_R_BI_EQ_BPF1_H0_2:
1090 case RT5659_DAC_R_BI_EQ_BPF1_B1_1:
1091 case RT5659_DAC_R_BI_EQ_BPF1_B1_2:
1092 case RT5659_DAC_R_BI_EQ_BPF1_B2_1:
1093 case RT5659_DAC_R_BI_EQ_BPF1_B2_2:
1094 case RT5659_DAC_R_BI_EQ_BPF1_A1_1:
1095 case RT5659_DAC_R_BI_EQ_BPF1_A1_2:
1096 case RT5659_DAC_R_BI_EQ_BPF1_A2_1:
1097 case RT5659_DAC_R_BI_EQ_BPF1_A2_2:
1098 case RT5659_ADC_L_EQ_LPF1_A1:
1099 case RT5659_ADC_R_EQ_LPF1_A1:
1100 case RT5659_ADC_L_EQ_LPF1_H0:
1101 case RT5659_ADC_R_EQ_LPF1_H0:
1102 case RT5659_ADC_L_EQ_BPF1_A1:
1103 case RT5659_ADC_R_EQ_BPF1_A1:
1104 case RT5659_ADC_L_EQ_BPF1_A2:
1105 case RT5659_ADC_R_EQ_BPF1_A2:
1106 case RT5659_ADC_L_EQ_BPF1_H0:
1107 case RT5659_ADC_R_EQ_BPF1_H0:
1108 case RT5659_ADC_L_EQ_BPF2_A1:
1109 case RT5659_ADC_R_EQ_BPF2_A1:
1110 case RT5659_ADC_L_EQ_BPF2_A2:
1111 case RT5659_ADC_R_EQ_BPF2_A2:
1112 case RT5659_ADC_L_EQ_BPF2_H0:
1113 case RT5659_ADC_R_EQ_BPF2_H0:
1114 case RT5659_ADC_L_EQ_BPF3_A1:
1115 case RT5659_ADC_R_EQ_BPF3_A1:
1116 case RT5659_ADC_L_EQ_BPF3_A2:
1117 case RT5659_ADC_R_EQ_BPF3_A2:
1118 case RT5659_ADC_L_EQ_BPF3_H0:
1119 case RT5659_ADC_R_EQ_BPF3_H0:
1120 case RT5659_ADC_L_EQ_BPF4_A1:
1121 case RT5659_ADC_R_EQ_BPF4_A1:
1122 case RT5659_ADC_L_EQ_BPF4_A2:
1123 case RT5659_ADC_R_EQ_BPF4_A2:
1124 case RT5659_ADC_L_EQ_BPF4_H0:
1125 case RT5659_ADC_R_EQ_BPF4_H0:
1126 case RT5659_ADC_L_EQ_HPF1_A1:
1127 case RT5659_ADC_R_EQ_HPF1_A1:
1128 case RT5659_ADC_L_EQ_HPF1_H0:
1129 case RT5659_ADC_R_EQ_HPF1_H0:
1130 case RT5659_ADC_L_EQ_PRE_VOL:
1131 case RT5659_ADC_R_EQ_PRE_VOL:
1132 case RT5659_ADC_L_EQ_POST_VOL:
1133 case RT5659_ADC_R_EQ_POST_VOL:
1134 return true;
1135 default:
1136 return false;
1137 }
1138 }
1139
1140 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1141 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1142 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1143 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1144 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1145 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1146 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1147
1148 /* Interface data select */
1149 static const char * const rt5659_data_select[] = {
1150 "L/R", "R/L", "L/L", "R/R"
1151 };
1152
1153 static SOC_ENUM_SINGLE_DECL(rt5659_if1_01_adc_enum,
1154 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT01_SFT, rt5659_data_select);
1155
1156 static SOC_ENUM_SINGLE_DECL(rt5659_if1_23_adc_enum,
1157 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT23_SFT, rt5659_data_select);
1158
1159 static SOC_ENUM_SINGLE_DECL(rt5659_if1_45_adc_enum,
1160 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT45_SFT, rt5659_data_select);
1161
1162 static SOC_ENUM_SINGLE_DECL(rt5659_if1_67_adc_enum,
1163 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT67_SFT, rt5659_data_select);
1164
1165 static SOC_ENUM_SINGLE_DECL(rt5659_if2_dac_enum,
1166 RT5659_DIG_INF23_DATA, RT5659_IF2_DAC_SEL_SFT, rt5659_data_select);
1167
1168 static SOC_ENUM_SINGLE_DECL(rt5659_if2_adc_enum,
1169 RT5659_DIG_INF23_DATA, RT5659_IF2_ADC_SEL_SFT, rt5659_data_select);
1170
1171 static SOC_ENUM_SINGLE_DECL(rt5659_if3_dac_enum,
1172 RT5659_DIG_INF23_DATA, RT5659_IF3_DAC_SEL_SFT, rt5659_data_select);
1173
1174 static SOC_ENUM_SINGLE_DECL(rt5659_if3_adc_enum,
1175 RT5659_DIG_INF23_DATA, RT5659_IF3_ADC_SEL_SFT, rt5659_data_select);
1176
1177 static const struct snd_kcontrol_new rt5659_if1_01_adc_swap_mux =
1178 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
1179
1180 static const struct snd_kcontrol_new rt5659_if1_23_adc_swap_mux =
1181 SOC_DAPM_ENUM("IF1 23 ADC1 Swap Source", rt5659_if1_23_adc_enum);
1182
1183 static const struct snd_kcontrol_new rt5659_if1_45_adc_swap_mux =
1184 SOC_DAPM_ENUM("IF1 45 ADC1 Swap Source", rt5659_if1_45_adc_enum);
1185
1186 static const struct snd_kcontrol_new rt5659_if1_67_adc_swap_mux =
1187 SOC_DAPM_ENUM("IF1 67 ADC1 Swap Source", rt5659_if1_67_adc_enum);
1188
1189 static const struct snd_kcontrol_new rt5659_if2_dac_swap_mux =
1190 SOC_DAPM_ENUM("IF2 DAC Swap Source", rt5659_if2_dac_enum);
1191
1192 static const struct snd_kcontrol_new rt5659_if2_adc_swap_mux =
1193 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
1194
1195 static const struct snd_kcontrol_new rt5659_if3_dac_swap_mux =
1196 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5659_if3_dac_enum);
1197
1198 static const struct snd_kcontrol_new rt5659_if3_adc_swap_mux =
1199 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
1200
1201 static const char * const rt5659_asrc_clk_src[] = {
1202 "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track",
1203 "clk_i2s3_track", "clk_sys2", "clk_sys3"
1204 };
1205
1206 static unsigned int rt5659_asrc_clk_map_values[] = {
1207 0, 1, 2, 3, 5, 6,
1208 };
1209
1210 static SOC_VALUE_ENUM_SINGLE_DECL(
1211 rt5659_da_sto_asrc_enum, RT5659_ASRC_2, RT5659_DA_STO_T_SFT, 0x7,
1212 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1213
1214 static SOC_VALUE_ENUM_SINGLE_DECL(
1215 rt5659_da_monol_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_L_T_SFT, 0x7,
1216 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1217
1218 static SOC_VALUE_ENUM_SINGLE_DECL(
1219 rt5659_da_monor_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_R_T_SFT, 0x7,
1220 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1221
1222 static SOC_VALUE_ENUM_SINGLE_DECL(
1223 rt5659_ad_sto1_asrc_enum, RT5659_ASRC_2, RT5659_AD_STO1_T_SFT, 0x7,
1224 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1225
1226 static SOC_VALUE_ENUM_SINGLE_DECL(
1227 rt5659_ad_sto2_asrc_enum, RT5659_ASRC_3, RT5659_AD_STO2_T_SFT, 0x7,
1228 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1229
1230 static SOC_VALUE_ENUM_SINGLE_DECL(
1231 rt5659_ad_monol_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_L_T_SFT, 0x7,
1232 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1233
1234 static SOC_VALUE_ENUM_SINGLE_DECL(
1235 rt5659_ad_monor_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_R_T_SFT, 0x7,
1236 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1237
1238 static int rt5659_hp_vol_put(struct snd_kcontrol *kcontrol,
1239 struct snd_ctl_elem_value *ucontrol)
1240 {
1241 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1242 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1243
1244 if (snd_soc_read(codec, RT5659_STO_NG2_CTRL_1) & RT5659_NG2_EN) {
1245 snd_soc_update_bits(codec, RT5659_STO_NG2_CTRL_1,
1246 RT5659_NG2_EN_MASK, RT5659_NG2_DIS);
1247 snd_soc_update_bits(codec, RT5659_STO_NG2_CTRL_1,
1248 RT5659_NG2_EN_MASK, RT5659_NG2_EN);
1249 }
1250
1251 return ret;
1252 }
1253
1254 static void rt5659_enable_push_button_irq(struct snd_soc_codec *codec,
1255 bool enable)
1256 {
1257 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1258
1259 if (enable) {
1260 snd_soc_write(codec, RT5659_4BTN_IL_CMD_1, 0x000b);
1261
1262 /* MICBIAS1 and Mic Det Power for button detect*/
1263 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1264 snd_soc_dapm_force_enable_pin(dapm,
1265 "Mic Det Power");
1266 snd_soc_dapm_sync(dapm);
1267
1268 snd_soc_update_bits(codec, RT5659_PWR_ANLG_2,
1269 RT5659_PWR_MB1, RT5659_PWR_MB1);
1270 snd_soc_update_bits(codec, RT5659_PWR_VOL,
1271 RT5659_PWR_MIC_DET, RT5659_PWR_MIC_DET);
1272
1273 snd_soc_update_bits(codec, RT5659_IRQ_CTRL_2,
1274 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
1275 snd_soc_update_bits(codec, RT5659_4BTN_IL_CMD_2,
1276 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
1277 } else {
1278 snd_soc_update_bits(codec, RT5659_4BTN_IL_CMD_2,
1279 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_DIS);
1280 snd_soc_update_bits(codec, RT5659_IRQ_CTRL_2,
1281 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_DIS);
1282 /* MICBIAS1 and Mic Det Power for button detect*/
1283 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1284 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1285 snd_soc_dapm_sync(dapm);
1286 }
1287 }
1288
1289 /**
1290 * rt5659_headset_detect - Detect headset.
1291 * @codec: SoC audio codec device.
1292 * @jack_insert: Jack insert or not.
1293 *
1294 * Detect whether is headset or not when jack inserted.
1295 *
1296 * Returns detect status.
1297 */
1298
1299 static int rt5659_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1300 {
1301 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1302 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1303 int reg_63;
1304
1305 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
1306
1307 if (jack_insert) {
1308 snd_soc_dapm_force_enable_pin(dapm,
1309 "Mic Det Power");
1310 snd_soc_dapm_sync(dapm);
1311 reg_63 = snd_soc_read(codec, RT5659_PWR_ANLG_1);
1312
1313 snd_soc_update_bits(codec, RT5659_PWR_ANLG_1,
1314 RT5659_PWR_VREF2 | RT5659_PWR_MB,
1315 RT5659_PWR_VREF2 | RT5659_PWR_MB);
1316 msleep(20);
1317 snd_soc_update_bits(codec, RT5659_PWR_ANLG_1,
1318 RT5659_PWR_FV2, RT5659_PWR_FV2);
1319
1320 snd_soc_write(codec, RT5659_EJD_CTRL_2, 0x4160);
1321 snd_soc_update_bits(codec, RT5659_EJD_CTRL_1,
1322 0x20, 0x0);
1323 msleep(20);
1324 snd_soc_update_bits(codec, RT5659_EJD_CTRL_1,
1325 0x20, 0x20);
1326
1327 while (i < 5) {
1328 msleep(sleep_time[i]);
1329 val = snd_soc_read(codec, RT5659_EJD_CTRL_2) & 0x0003;
1330 i++;
1331 if (val == 0x1 || val == 0x2 || val == 0x3)
1332 break;
1333 }
1334
1335 switch (val) {
1336 case 1:
1337 rt5659->jack_type = SND_JACK_HEADSET;
1338 rt5659_enable_push_button_irq(codec, true);
1339 break;
1340 default:
1341 snd_soc_write(codec, RT5659_PWR_ANLG_1, reg_63);
1342 rt5659->jack_type = SND_JACK_HEADPHONE;
1343 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1344 snd_soc_dapm_sync(dapm);
1345 break;
1346 }
1347 } else {
1348 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1349 snd_soc_dapm_sync(dapm);
1350 if (rt5659->jack_type == SND_JACK_HEADSET)
1351 rt5659_enable_push_button_irq(codec, false);
1352 rt5659->jack_type = 0;
1353 }
1354
1355 dev_dbg(codec->dev, "jack_type = %d\n", rt5659->jack_type);
1356 return rt5659->jack_type;
1357 }
1358
1359 static int rt5659_button_detect(struct snd_soc_codec *codec)
1360 {
1361 int btn_type, val;
1362
1363 val = snd_soc_read(codec, RT5659_4BTN_IL_CMD_1);
1364 btn_type = val & 0xfff0;
1365 snd_soc_write(codec, RT5659_4BTN_IL_CMD_1, val);
1366
1367 return btn_type;
1368 }
1369
1370 static irqreturn_t rt5659_irq(int irq, void *data)
1371 {
1372 struct rt5659_priv *rt5659 = data;
1373
1374 queue_delayed_work(system_power_efficient_wq,
1375 &rt5659->jack_detect_work, msecs_to_jiffies(250));
1376
1377 return IRQ_HANDLED;
1378 }
1379
1380 int rt5659_set_jack_detect(struct snd_soc_codec *codec,
1381 struct snd_soc_jack *hs_jack)
1382 {
1383 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
1384
1385 rt5659->hs_jack = hs_jack;
1386
1387 rt5659_irq(0, rt5659);
1388
1389 return 0;
1390 }
1391 EXPORT_SYMBOL_GPL(rt5659_set_jack_detect);
1392
1393 static void rt5659_jack_detect_work(struct work_struct *work)
1394 {
1395 struct rt5659_priv *rt5659 =
1396 container_of(work, struct rt5659_priv, jack_detect_work.work);
1397 int val, btn_type, report = 0;
1398
1399 if (!rt5659->codec)
1400 return;
1401
1402 val = snd_soc_read(rt5659->codec, RT5659_INT_ST_1) & 0x0080;
1403 if (!val) {
1404 /* jack in */
1405 if (rt5659->jack_type == 0) {
1406 /* jack was out, report jack type */
1407 report = rt5659_headset_detect(rt5659->codec, 1);
1408 } else {
1409 /* jack is already in, report button event */
1410 report = SND_JACK_HEADSET;
1411 btn_type = rt5659_button_detect(rt5659->codec);
1412 /**
1413 * rt5659 can report three kinds of button behavior,
1414 * one click, double click and hold. However,
1415 * currently we will report button pressed/released
1416 * event. So all the three button behaviors are
1417 * treated as button pressed.
1418 */
1419 switch (btn_type) {
1420 case 0x8000:
1421 case 0x4000:
1422 case 0x2000:
1423 report |= SND_JACK_BTN_0;
1424 break;
1425 case 0x1000:
1426 case 0x0800:
1427 case 0x0400:
1428 report |= SND_JACK_BTN_1;
1429 break;
1430 case 0x0200:
1431 case 0x0100:
1432 case 0x0080:
1433 report |= SND_JACK_BTN_2;
1434 break;
1435 case 0x0040:
1436 case 0x0020:
1437 case 0x0010:
1438 report |= SND_JACK_BTN_3;
1439 break;
1440 case 0x0000: /* unpressed */
1441 break;
1442 default:
1443 btn_type = 0;
1444 dev_err(rt5659->codec->dev,
1445 "Unexpected button code 0x%04x\n",
1446 btn_type);
1447 break;
1448 }
1449
1450 /* button release or spurious interrput*/
1451 if (btn_type == 0)
1452 report = rt5659->jack_type;
1453 }
1454 } else {
1455 /* jack out */
1456 report = rt5659_headset_detect(rt5659->codec, 0);
1457 }
1458
1459 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET |
1460 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1461 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1462 }
1463
1464 static const struct snd_kcontrol_new rt5659_snd_controls[] = {
1465 /* Speaker Output Volume */
1466 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5659_SPO_VOL,
1467 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1468
1469 /* Headphone Output Volume */
1470 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5659_HPL_GAIN,
1471 RT5659_HPR_GAIN, RT5659_G_HP_SFT, 31, 1, snd_soc_get_volsw,
1472 rt5659_hp_vol_put, hp_vol_tlv),
1473
1474 /* Mono Output Volume */
1475 SOC_SINGLE_TLV("Mono Playback Volume", RT5659_MONO_OUT,
1476 RT5659_L_VOL_SFT, 39, 1, out_vol_tlv),
1477
1478 /* Output Volume */
1479 SOC_DOUBLE_TLV("OUT Playback Volume", RT5659_LOUT,
1480 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1481
1482 /* DAC Digital Volume */
1483 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5659_DAC1_DIG_VOL,
1484 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1485 SOC_DOUBLE("DAC1 Playback Switch", RT5659_AD_DA_MIXER,
1486 RT5659_M_DAC1_L_SFT, RT5659_M_DAC1_R_SFT, 1, 1),
1487
1488 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5659_DAC2_DIG_VOL,
1489 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1490 SOC_DOUBLE("DAC2 Playback Switch", RT5659_DAC_CTRL,
1491 RT5659_M_DAC2_L_VOL_SFT, RT5659_M_DAC2_R_VOL_SFT, 1, 1),
1492
1493 /* IN1/IN2/IN3/IN4 Volume */
1494 SOC_SINGLE_TLV("IN1 Boost Volume", RT5659_IN1_IN2,
1495 RT5659_BST1_SFT, 69, 0, in_bst_tlv),
1496 SOC_SINGLE_TLV("IN2 Boost Volume", RT5659_IN1_IN2,
1497 RT5659_BST2_SFT, 69, 0, in_bst_tlv),
1498 SOC_SINGLE_TLV("IN3 Boost Volume", RT5659_IN3_IN4,
1499 RT5659_BST3_SFT, 69, 0, in_bst_tlv),
1500 SOC_SINGLE_TLV("IN4 Boost Volume", RT5659_IN3_IN4,
1501 RT5659_BST4_SFT, 69, 0, in_bst_tlv),
1502
1503 /* INL/INR Volume Control */
1504 SOC_DOUBLE_TLV("IN Capture Volume", RT5659_INL1_INR1_VOL,
1505 RT5659_INL_VOL_SFT, RT5659_INR_VOL_SFT, 31, 1, in_vol_tlv),
1506
1507 /* ADC Digital Volume Control */
1508 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
1509 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1510 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
1511 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1512 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
1513 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1514 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
1515 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1516 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
1517 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1518 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
1519 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1520
1521 /* ADC Boost Volume Control */
1522 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
1523 RT5659_STO1_ADC_L_BST_SFT, RT5659_STO1_ADC_R_BST_SFT,
1524 3, 0, adc_bst_tlv),
1525
1526 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
1527 RT5659_MONO_ADC_L_BST_SFT, RT5659_MONO_ADC_R_BST_SFT,
1528 3, 0, adc_bst_tlv),
1529
1530 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
1531 RT5659_STO2_ADC_L_BST_SFT, RT5659_STO2_ADC_R_BST_SFT,
1532 3, 0, adc_bst_tlv),
1533
1534 SOC_SINGLE("DAC IF1 DAC1 L Data Switch", RT5659_TDM_CTRL_4, 12, 7, 0),
1535 SOC_SINGLE("DAC IF1 DAC1 R Data Switch", RT5659_TDM_CTRL_4, 8, 7, 0),
1536 SOC_SINGLE("DAC IF1 DAC2 L Data Switch", RT5659_TDM_CTRL_4, 4, 7, 0),
1537 SOC_SINGLE("DAC IF1 DAC2 R Data Switch", RT5659_TDM_CTRL_4, 0, 7, 0),
1538 };
1539
1540 /**
1541 * set_dmic_clk - Set parameter of dmic.
1542 *
1543 * @w: DAPM widget.
1544 * @kcontrol: The kcontrol of this widget.
1545 * @event: Event id.
1546 *
1547 * Choose dmic clock between 1MHz and 3MHz.
1548 * It is better for clock to approximate 3MHz.
1549 */
1550 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1551 struct snd_kcontrol *kcontrol, int event)
1552 {
1553 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1554 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
1555 int pd, idx = -EINVAL;
1556
1557 pd = rl6231_get_pre_div(rt5659->regmap,
1558 RT5659_ADDA_CLK_1, RT5659_I2S_PD1_SFT);
1559 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd);
1560
1561 if (idx < 0)
1562 dev_err(codec->dev, "Failed to set DMIC clock\n");
1563 else {
1564 snd_soc_update_bits(codec, RT5659_DMIC_CTRL_1,
1565 RT5659_DMIC_CLK_MASK, idx << RT5659_DMIC_CLK_SFT);
1566 }
1567 return idx;
1568 }
1569
1570 static int set_adc_clk(struct snd_soc_dapm_widget *w,
1571 struct snd_kcontrol *kcontrol, int event)
1572 {
1573 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1574
1575 switch (event) {
1576 case SND_SOC_DAPM_POST_PMU:
1577 snd_soc_update_bits(codec, RT5659_CHOP_ADC,
1578 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK,
1579 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK);
1580 break;
1581
1582 case SND_SOC_DAPM_PRE_PMD:
1583 snd_soc_update_bits(codec, RT5659_CHOP_ADC,
1584 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK, 0);
1585 break;
1586
1587 default:
1588 return 0;
1589 }
1590
1591 return 0;
1592
1593 }
1594
1595 static int rt5659_charge_pump_event(struct snd_soc_dapm_widget *w,
1596 struct snd_kcontrol *kcontrol, int event)
1597 {
1598 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1599
1600 switch (event) {
1601 case SND_SOC_DAPM_PRE_PMU:
1602 /* Depop */
1603 snd_soc_write(codec, RT5659_DEPOP_1, 0x0009);
1604 break;
1605 case SND_SOC_DAPM_POST_PMD:
1606 snd_soc_write(codec, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
1607 break;
1608 default:
1609 return 0;
1610 }
1611
1612 return 0;
1613 }
1614
1615 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1616 struct snd_soc_dapm_widget *sink)
1617 {
1618 unsigned int val;
1619 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1620
1621 val = snd_soc_read(codec, RT5659_GLB_CLK);
1622 val &= RT5659_SCLK_SRC_MASK;
1623 if (val == RT5659_SCLK_SRC_PLL1)
1624 return 1;
1625 else
1626 return 0;
1627 }
1628
1629 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1630 struct snd_soc_dapm_widget *sink)
1631 {
1632 unsigned int reg, shift, val;
1633 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1634
1635 switch (w->shift) {
1636 case RT5659_ADC_MONO_R_ASRC_SFT:
1637 reg = RT5659_ASRC_3;
1638 shift = RT5659_AD_MONO_R_T_SFT;
1639 break;
1640 case RT5659_ADC_MONO_L_ASRC_SFT:
1641 reg = RT5659_ASRC_3;
1642 shift = RT5659_AD_MONO_L_T_SFT;
1643 break;
1644 case RT5659_ADC_STO1_ASRC_SFT:
1645 reg = RT5659_ASRC_2;
1646 shift = RT5659_AD_STO1_T_SFT;
1647 break;
1648 case RT5659_DAC_MONO_R_ASRC_SFT:
1649 reg = RT5659_ASRC_2;
1650 shift = RT5659_DA_MONO_R_T_SFT;
1651 break;
1652 case RT5659_DAC_MONO_L_ASRC_SFT:
1653 reg = RT5659_ASRC_2;
1654 shift = RT5659_DA_MONO_L_T_SFT;
1655 break;
1656 case RT5659_DAC_STO_ASRC_SFT:
1657 reg = RT5659_ASRC_2;
1658 shift = RT5659_DA_STO_T_SFT;
1659 break;
1660 default:
1661 return 0;
1662 }
1663
1664 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1665 switch (val) {
1666 case 1:
1667 case 2:
1668 case 3:
1669 /* I2S_Pre_Div1 should be 1 in asrc mode */
1670 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
1671 RT5659_I2S_PD1_MASK, RT5659_I2S_PD1_2);
1672 return 1;
1673 default:
1674 return 0;
1675 }
1676
1677 }
1678
1679 /* Digital Mixer */
1680 static const struct snd_kcontrol_new rt5659_sto1_adc_l_mix[] = {
1681 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1682 RT5659_M_STO1_ADC_L1_SFT, 1, 1),
1683 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1684 RT5659_M_STO1_ADC_L2_SFT, 1, 1),
1685 };
1686
1687 static const struct snd_kcontrol_new rt5659_sto1_adc_r_mix[] = {
1688 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1689 RT5659_M_STO1_ADC_R1_SFT, 1, 1),
1690 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1691 RT5659_M_STO1_ADC_R2_SFT, 1, 1),
1692 };
1693
1694 static const struct snd_kcontrol_new rt5659_mono_adc_l_mix[] = {
1695 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1696 RT5659_M_MONO_ADC_L1_SFT, 1, 1),
1697 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1698 RT5659_M_MONO_ADC_L2_SFT, 1, 1),
1699 };
1700
1701 static const struct snd_kcontrol_new rt5659_mono_adc_r_mix[] = {
1702 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1703 RT5659_M_MONO_ADC_R1_SFT, 1, 1),
1704 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1705 RT5659_M_MONO_ADC_R2_SFT, 1, 1),
1706 };
1707
1708 static const struct snd_kcontrol_new rt5659_dac_l_mix[] = {
1709 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1710 RT5659_M_ADCMIX_L_SFT, 1, 1),
1711 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1712 RT5659_M_DAC1_L_SFT, 1, 1),
1713 };
1714
1715 static const struct snd_kcontrol_new rt5659_dac_r_mix[] = {
1716 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1717 RT5659_M_ADCMIX_R_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1719 RT5659_M_DAC1_R_SFT, 1, 1),
1720 };
1721
1722 static const struct snd_kcontrol_new rt5659_sto_dac_l_mix[] = {
1723 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1724 RT5659_M_DAC_L1_STO_L_SFT, 1, 1),
1725 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1726 RT5659_M_DAC_R1_STO_L_SFT, 1, 1),
1727 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1728 RT5659_M_DAC_L2_STO_L_SFT, 1, 1),
1729 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1730 RT5659_M_DAC_R2_STO_L_SFT, 1, 1),
1731 };
1732
1733 static const struct snd_kcontrol_new rt5659_sto_dac_r_mix[] = {
1734 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1735 RT5659_M_DAC_L1_STO_R_SFT, 1, 1),
1736 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1737 RT5659_M_DAC_R1_STO_R_SFT, 1, 1),
1738 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1739 RT5659_M_DAC_L2_STO_R_SFT, 1, 1),
1740 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1741 RT5659_M_DAC_R2_STO_R_SFT, 1, 1),
1742 };
1743
1744 static const struct snd_kcontrol_new rt5659_mono_dac_l_mix[] = {
1745 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1746 RT5659_M_DAC_L1_MONO_L_SFT, 1, 1),
1747 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1748 RT5659_M_DAC_R1_MONO_L_SFT, 1, 1),
1749 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1750 RT5659_M_DAC_L2_MONO_L_SFT, 1, 1),
1751 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1752 RT5659_M_DAC_R2_MONO_L_SFT, 1, 1),
1753 };
1754
1755 static const struct snd_kcontrol_new rt5659_mono_dac_r_mix[] = {
1756 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1757 RT5659_M_DAC_L1_MONO_R_SFT, 1, 1),
1758 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1759 RT5659_M_DAC_R1_MONO_R_SFT, 1, 1),
1760 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1761 RT5659_M_DAC_L2_MONO_R_SFT, 1, 1),
1762 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1763 RT5659_M_DAC_R2_MONO_R_SFT, 1, 1),
1764 };
1765
1766 /* Analog Input Mixer */
1767 static const struct snd_kcontrol_new rt5659_rec1_l_mix[] = {
1768 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC1_L2_MIXER,
1769 RT5659_M_SPKVOLL_RM1_L_SFT, 1, 1),
1770 SOC_DAPM_SINGLE("INL Switch", RT5659_REC1_L2_MIXER,
1771 RT5659_M_INL_RM1_L_SFT, 1, 1),
1772 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_L2_MIXER,
1773 RT5659_M_BST4_RM1_L_SFT, 1, 1),
1774 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_L2_MIXER,
1775 RT5659_M_BST3_RM1_L_SFT, 1, 1),
1776 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_L2_MIXER,
1777 RT5659_M_BST2_RM1_L_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_L2_MIXER,
1779 RT5659_M_BST1_RM1_L_SFT, 1, 1),
1780 };
1781
1782 static const struct snd_kcontrol_new rt5659_rec1_r_mix[] = {
1783 SOC_DAPM_SINGLE("HPOVOLR Switch", RT5659_REC1_L2_MIXER,
1784 RT5659_M_HPOVOLR_RM1_R_SFT, 1, 1),
1785 SOC_DAPM_SINGLE("INR Switch", RT5659_REC1_R2_MIXER,
1786 RT5659_M_INR_RM1_R_SFT, 1, 1),
1787 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_R2_MIXER,
1788 RT5659_M_BST4_RM1_R_SFT, 1, 1),
1789 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_R2_MIXER,
1790 RT5659_M_BST3_RM1_R_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_R2_MIXER,
1792 RT5659_M_BST2_RM1_R_SFT, 1, 1),
1793 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_R2_MIXER,
1794 RT5659_M_BST1_RM1_R_SFT, 1, 1),
1795 };
1796
1797 static const struct snd_kcontrol_new rt5659_rec2_l_mix[] = {
1798 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC2_L2_MIXER,
1799 RT5659_M_SPKVOL_RM2_L_SFT, 1, 1),
1800 SOC_DAPM_SINGLE("OUTVOLL Switch", RT5659_REC2_L2_MIXER,
1801 RT5659_M_OUTVOLL_RM2_L_SFT, 1, 1),
1802 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_L2_MIXER,
1803 RT5659_M_BST4_RM2_L_SFT, 1, 1),
1804 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_L2_MIXER,
1805 RT5659_M_BST3_RM2_L_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_L2_MIXER,
1807 RT5659_M_BST2_RM2_L_SFT, 1, 1),
1808 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_L2_MIXER,
1809 RT5659_M_BST1_RM2_L_SFT, 1, 1),
1810 };
1811
1812 static const struct snd_kcontrol_new rt5659_rec2_r_mix[] = {
1813 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_REC2_R2_MIXER,
1814 RT5659_M_MONOVOL_RM2_R_SFT, 1, 1),
1815 SOC_DAPM_SINGLE("OUTVOLR Switch", RT5659_REC2_R2_MIXER,
1816 RT5659_M_OUTVOLR_RM2_R_SFT, 1, 1),
1817 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_R2_MIXER,
1818 RT5659_M_BST4_RM2_R_SFT, 1, 1),
1819 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_R2_MIXER,
1820 RT5659_M_BST3_RM2_R_SFT, 1, 1),
1821 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_R2_MIXER,
1822 RT5659_M_BST2_RM2_R_SFT, 1, 1),
1823 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_R2_MIXER,
1824 RT5659_M_BST1_RM2_R_SFT, 1, 1),
1825 };
1826
1827 static const struct snd_kcontrol_new rt5659_spk_l_mix[] = {
1828 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPK_L_MIXER,
1829 RT5659_M_DAC_L2_SM_L_SFT, 1, 1),
1830 SOC_DAPM_SINGLE("BST1 Switch", RT5659_SPK_L_MIXER,
1831 RT5659_M_BST1_SM_L_SFT, 1, 1),
1832 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_L_MIXER,
1833 RT5659_M_IN_L_SM_L_SFT, 1, 1),
1834 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_L_MIXER,
1835 RT5659_M_IN_R_SM_L_SFT, 1, 1),
1836 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_L_MIXER,
1837 RT5659_M_BST3_SM_L_SFT, 1, 1),
1838 };
1839
1840 static const struct snd_kcontrol_new rt5659_spk_r_mix[] = {
1841 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPK_R_MIXER,
1842 RT5659_M_DAC_R2_SM_R_SFT, 1, 1),
1843 SOC_DAPM_SINGLE("BST4 Switch", RT5659_SPK_R_MIXER,
1844 RT5659_M_BST4_SM_R_SFT, 1, 1),
1845 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_R_MIXER,
1846 RT5659_M_IN_L_SM_R_SFT, 1, 1),
1847 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_R_MIXER,
1848 RT5659_M_IN_R_SM_R_SFT, 1, 1),
1849 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_R_MIXER,
1850 RT5659_M_BST3_SM_R_SFT, 1, 1),
1851 };
1852
1853 static const struct snd_kcontrol_new rt5659_monovol_mix[] = {
1854 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1855 RT5659_M_DAC_L2_MM_SFT, 1, 1),
1856 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONOMIX_IN_GAIN,
1857 RT5659_M_DAC_R2_MM_SFT, 1, 1),
1858 SOC_DAPM_SINGLE("BST1 Switch", RT5659_MONOMIX_IN_GAIN,
1859 RT5659_M_BST1_MM_SFT, 1, 1),
1860 SOC_DAPM_SINGLE("BST2 Switch", RT5659_MONOMIX_IN_GAIN,
1861 RT5659_M_BST2_MM_SFT, 1, 1),
1862 SOC_DAPM_SINGLE("BST3 Switch", RT5659_MONOMIX_IN_GAIN,
1863 RT5659_M_BST3_MM_SFT, 1, 1),
1864 };
1865
1866 static const struct snd_kcontrol_new rt5659_out_l_mix[] = {
1867 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_OUT_L_MIXER,
1868 RT5659_M_DAC_L2_OM_L_SFT, 1, 1),
1869 SOC_DAPM_SINGLE("INL Switch", RT5659_OUT_L_MIXER,
1870 RT5659_M_IN_L_OM_L_SFT, 1, 1),
1871 SOC_DAPM_SINGLE("BST1 Switch", RT5659_OUT_L_MIXER,
1872 RT5659_M_BST1_OM_L_SFT, 1, 1),
1873 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_L_MIXER,
1874 RT5659_M_BST2_OM_L_SFT, 1, 1),
1875 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_L_MIXER,
1876 RT5659_M_BST3_OM_L_SFT, 1, 1),
1877 };
1878
1879 static const struct snd_kcontrol_new rt5659_out_r_mix[] = {
1880 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_OUT_R_MIXER,
1881 RT5659_M_DAC_R2_OM_R_SFT, 1, 1),
1882 SOC_DAPM_SINGLE("INR Switch", RT5659_OUT_R_MIXER,
1883 RT5659_M_IN_R_OM_R_SFT, 1, 1),
1884 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_R_MIXER,
1885 RT5659_M_BST2_OM_R_SFT, 1, 1),
1886 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_R_MIXER,
1887 RT5659_M_BST3_OM_R_SFT, 1, 1),
1888 SOC_DAPM_SINGLE("BST4 Switch", RT5659_OUT_R_MIXER,
1889 RT5659_M_BST4_OM_R_SFT, 1, 1),
1890 };
1891
1892 static const struct snd_kcontrol_new rt5659_spo_l_mix[] = {
1893 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPO_AMP_GAIN,
1894 RT5659_M_DAC_L2_SPKOMIX_SFT, 1, 0),
1895 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5659_SPO_AMP_GAIN,
1896 RT5659_M_SPKVOLL_SPKOMIX_SFT, 1, 0),
1897 };
1898
1899 static const struct snd_kcontrol_new rt5659_spo_r_mix[] = {
1900 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPO_AMP_GAIN,
1901 RT5659_M_DAC_R2_SPKOMIX_SFT, 1, 0),
1902 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5659_SPO_AMP_GAIN,
1903 RT5659_M_SPKVOLR_SPKOMIX_SFT, 1, 0),
1904 };
1905
1906 static const struct snd_kcontrol_new rt5659_mono_mix[] = {
1907 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1908 RT5659_M_DAC_L2_MA_SFT, 1, 1),
1909 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_MONOMIX_IN_GAIN,
1910 RT5659_M_MONOVOL_MA_SFT, 1, 1),
1911 };
1912
1913 static const struct snd_kcontrol_new rt5659_lout_l_mix[] = {
1914 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_LOUT_MIXER,
1915 RT5659_M_DAC_L2_LM_SFT, 1, 1),
1916 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5659_LOUT_MIXER,
1917 RT5659_M_OV_L_LM_SFT, 1, 1),
1918 };
1919
1920 static const struct snd_kcontrol_new rt5659_lout_r_mix[] = {
1921 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_LOUT_MIXER,
1922 RT5659_M_DAC_R2_LM_SFT, 1, 1),
1923 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5659_LOUT_MIXER,
1924 RT5659_M_OV_R_LM_SFT, 1, 1),
1925 };
1926
1927 /*DAC L2, DAC R2*/
1928 /*MX-1B [6:4], MX-1B [2:0]*/
1929 static const char * const rt5659_dac2_src[] = {
1930 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
1931 };
1932
1933 static SOC_ENUM_SINGLE_DECL(
1934 rt5659_dac_l2_enum, RT5659_DAC_CTRL,
1935 RT5659_DAC_L2_SEL_SFT, rt5659_dac2_src);
1936
1937 static const struct snd_kcontrol_new rt5659_dac_l2_mux =
1938 SOC_DAPM_ENUM("DAC L2 Source", rt5659_dac_l2_enum);
1939
1940 static SOC_ENUM_SINGLE_DECL(
1941 rt5659_dac_r2_enum, RT5659_DAC_CTRL,
1942 RT5659_DAC_R2_SEL_SFT, rt5659_dac2_src);
1943
1944 static const struct snd_kcontrol_new rt5659_dac_r2_mux =
1945 SOC_DAPM_ENUM("DAC R2 Source", rt5659_dac_r2_enum);
1946
1947
1948 /* STO1 ADC1 Source */
1949 /* MX-26 [13] */
1950 static const char * const rt5659_sto1_adc1_src[] = {
1951 "DAC MIX", "ADC"
1952 };
1953
1954 static SOC_ENUM_SINGLE_DECL(
1955 rt5659_sto1_adc1_enum, RT5659_STO1_ADC_MIXER,
1956 RT5659_STO1_ADC1_SRC_SFT, rt5659_sto1_adc1_src);
1957
1958 static const struct snd_kcontrol_new rt5659_sto1_adc1_mux =
1959 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5659_sto1_adc1_enum);
1960
1961 /* STO1 ADC Source */
1962 /* MX-26 [12] */
1963 static const char * const rt5659_sto1_adc_src[] = {
1964 "ADC1", "ADC2"
1965 };
1966
1967 static SOC_ENUM_SINGLE_DECL(
1968 rt5659_sto1_adc_enum, RT5659_STO1_ADC_MIXER,
1969 RT5659_STO1_ADC_SRC_SFT, rt5659_sto1_adc_src);
1970
1971 static const struct snd_kcontrol_new rt5659_sto1_adc_mux =
1972 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
1973
1974 /* STO1 ADC2 Source */
1975 /* MX-26 [11] */
1976 static const char * const rt5659_sto1_adc2_src[] = {
1977 "DAC MIX", "DMIC"
1978 };
1979
1980 static SOC_ENUM_SINGLE_DECL(
1981 rt5659_sto1_adc2_enum, RT5659_STO1_ADC_MIXER,
1982 RT5659_STO1_ADC2_SRC_SFT, rt5659_sto1_adc2_src);
1983
1984 static const struct snd_kcontrol_new rt5659_sto1_adc2_mux =
1985 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5659_sto1_adc2_enum);
1986
1987 /* STO1 DMIC Source */
1988 /* MX-26 [8] */
1989 static const char * const rt5659_sto1_dmic_src[] = {
1990 "DMIC1", "DMIC2"
1991 };
1992
1993 static SOC_ENUM_SINGLE_DECL(
1994 rt5659_sto1_dmic_enum, RT5659_STO1_ADC_MIXER,
1995 RT5659_STO1_DMIC_SRC_SFT, rt5659_sto1_dmic_src);
1996
1997 static const struct snd_kcontrol_new rt5659_sto1_dmic_mux =
1998 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5659_sto1_dmic_enum);
1999
2000
2001 /* MONO ADC L2 Source */
2002 /* MX-27 [12] */
2003 static const char * const rt5659_mono_adc_l2_src[] = {
2004 "Mono DAC MIXL", "DMIC"
2005 };
2006
2007 static SOC_ENUM_SINGLE_DECL(
2008 rt5659_mono_adc_l2_enum, RT5659_MONO_ADC_MIXER,
2009 RT5659_MONO_ADC_L2_SRC_SFT, rt5659_mono_adc_l2_src);
2010
2011 static const struct snd_kcontrol_new rt5659_mono_adc_l2_mux =
2012 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
2013
2014
2015 /* MONO ADC L1 Source */
2016 /* MX-27 [11] */
2017 static const char * const rt5659_mono_adc_l1_src[] = {
2018 "Mono DAC MIXL", "ADC"
2019 };
2020
2021 static SOC_ENUM_SINGLE_DECL(
2022 rt5659_mono_adc_l1_enum, RT5659_MONO_ADC_MIXER,
2023 RT5659_MONO_ADC_L1_SRC_SFT, rt5659_mono_adc_l1_src);
2024
2025 static const struct snd_kcontrol_new rt5659_mono_adc_l1_mux =
2026 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
2027
2028 /* MONO ADC L Source, MONO ADC R Source*/
2029 /* MX-27 [10:9], MX-27 [2:1] */
2030 static const char * const rt5659_mono_adc_src[] = {
2031 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2032 };
2033
2034 static SOC_ENUM_SINGLE_DECL(
2035 rt5659_mono_adc_l_enum, RT5659_MONO_ADC_MIXER,
2036 RT5659_MONO_ADC_L_SRC_SFT, rt5659_mono_adc_src);
2037
2038 static const struct snd_kcontrol_new rt5659_mono_adc_l_mux =
2039 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
2040
2041 static SOC_ENUM_SINGLE_DECL(
2042 rt5659_mono_adcr_enum, RT5659_MONO_ADC_MIXER,
2043 RT5659_MONO_ADC_R_SRC_SFT, rt5659_mono_adc_src);
2044
2045 static const struct snd_kcontrol_new rt5659_mono_adc_r_mux =
2046 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
2047
2048 /* MONO DMIC L Source */
2049 /* MX-27 [8] */
2050 static const char * const rt5659_mono_dmic_l_src[] = {
2051 "DMIC1 L", "DMIC2 L"
2052 };
2053
2054 static SOC_ENUM_SINGLE_DECL(
2055 rt5659_mono_dmic_l_enum, RT5659_MONO_ADC_MIXER,
2056 RT5659_MONO_DMIC_L_SRC_SFT, rt5659_mono_dmic_l_src);
2057
2058 static const struct snd_kcontrol_new rt5659_mono_dmic_l_mux =
2059 SOC_DAPM_ENUM("Mono DMIC L Source", rt5659_mono_dmic_l_enum);
2060
2061 /* MONO ADC R2 Source */
2062 /* MX-27 [4] */
2063 static const char * const rt5659_mono_adc_r2_src[] = {
2064 "Mono DAC MIXR", "DMIC"
2065 };
2066
2067 static SOC_ENUM_SINGLE_DECL(
2068 rt5659_mono_adc_r2_enum, RT5659_MONO_ADC_MIXER,
2069 RT5659_MONO_ADC_R2_SRC_SFT, rt5659_mono_adc_r2_src);
2070
2071 static const struct snd_kcontrol_new rt5659_mono_adc_r2_mux =
2072 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
2073
2074 /* MONO ADC R1 Source */
2075 /* MX-27 [3] */
2076 static const char * const rt5659_mono_adc_r1_src[] = {
2077 "Mono DAC MIXR", "ADC"
2078 };
2079
2080 static SOC_ENUM_SINGLE_DECL(
2081 rt5659_mono_adc_r1_enum, RT5659_MONO_ADC_MIXER,
2082 RT5659_MONO_ADC_R1_SRC_SFT, rt5659_mono_adc_r1_src);
2083
2084 static const struct snd_kcontrol_new rt5659_mono_adc_r1_mux =
2085 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
2086
2087 /* MONO DMIC R Source */
2088 /* MX-27 [0] */
2089 static const char * const rt5659_mono_dmic_r_src[] = {
2090 "DMIC1 R", "DMIC2 R"
2091 };
2092
2093 static SOC_ENUM_SINGLE_DECL(
2094 rt5659_mono_dmic_r_enum, RT5659_MONO_ADC_MIXER,
2095 RT5659_MONO_DMIC_R_SRC_SFT, rt5659_mono_dmic_r_src);
2096
2097 static const struct snd_kcontrol_new rt5659_mono_dmic_r_mux =
2098 SOC_DAPM_ENUM("Mono DMIC R Source", rt5659_mono_dmic_r_enum);
2099
2100
2101 /* DAC R1 Source, DAC L1 Source*/
2102 /* MX-29 [11:10], MX-29 [9:8]*/
2103 static const char * const rt5659_dac1_src[] = {
2104 "IF1 DAC1", "IF2 DAC", "IF3 DAC"
2105 };
2106
2107 static SOC_ENUM_SINGLE_DECL(
2108 rt5659_dac_r1_enum, RT5659_AD_DA_MIXER,
2109 RT5659_DAC1_R_SEL_SFT, rt5659_dac1_src);
2110
2111 static const struct snd_kcontrol_new rt5659_dac_r1_mux =
2112 SOC_DAPM_ENUM("DAC R1 Source", rt5659_dac_r1_enum);
2113
2114 static SOC_ENUM_SINGLE_DECL(
2115 rt5659_dac_l1_enum, RT5659_AD_DA_MIXER,
2116 RT5659_DAC1_L_SEL_SFT, rt5659_dac1_src);
2117
2118 static const struct snd_kcontrol_new rt5659_dac_l1_mux =
2119 SOC_DAPM_ENUM("DAC L1 Source", rt5659_dac_l1_enum);
2120
2121 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2122 /* MX-2C [6], MX-2C [4]*/
2123 static const char * const rt5659_dig_dac_mix_src[] = {
2124 "Stereo DAC Mixer", "Mono DAC Mixer"
2125 };
2126
2127 static SOC_ENUM_SINGLE_DECL(
2128 rt5659_dig_dac_mixl_enum, RT5659_DIG_MIXER,
2129 RT5659_DAC_MIX_L_SFT, rt5659_dig_dac_mix_src);
2130
2131 static const struct snd_kcontrol_new rt5659_dig_dac_mixl_mux =
2132 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5659_dig_dac_mixl_enum);
2133
2134 static SOC_ENUM_SINGLE_DECL(
2135 rt5659_dig_dac_mixr_enum, RT5659_DIG_MIXER,
2136 RT5659_DAC_MIX_R_SFT, rt5659_dig_dac_mix_src);
2137
2138 static const struct snd_kcontrol_new rt5659_dig_dac_mixr_mux =
2139 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5659_dig_dac_mixr_enum);
2140
2141 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2142 /* MX-2D [3], MX-2D [2]*/
2143 static const char * const rt5659_alg_dac1_src[] = {
2144 "DAC", "Stereo DAC Mixer"
2145 };
2146
2147 static SOC_ENUM_SINGLE_DECL(
2148 rt5659_alg_dac_l1_enum, RT5659_A_DAC_MUX,
2149 RT5659_A_DACL1_SFT, rt5659_alg_dac1_src);
2150
2151 static const struct snd_kcontrol_new rt5659_alg_dac_l1_mux =
2152 SOC_DAPM_ENUM("Analog DACL1 Source", rt5659_alg_dac_l1_enum);
2153
2154 static SOC_ENUM_SINGLE_DECL(
2155 rt5659_alg_dac_r1_enum, RT5659_A_DAC_MUX,
2156 RT5659_A_DACR1_SFT, rt5659_alg_dac1_src);
2157
2158 static const struct snd_kcontrol_new rt5659_alg_dac_r1_mux =
2159 SOC_DAPM_ENUM("Analog DACR1 Source", rt5659_alg_dac_r1_enum);
2160
2161 /* Analog DAC LR Source, Analog DAC R2 Source*/
2162 /* MX-2D [1], MX-2D [0]*/
2163 static const char * const rt5659_alg_dac2_src[] = {
2164 "Stereo DAC Mixer", "Mono DAC Mixer"
2165 };
2166
2167 static SOC_ENUM_SINGLE_DECL(
2168 rt5659_alg_dac_l2_enum, RT5659_A_DAC_MUX,
2169 RT5659_A_DACL2_SFT, rt5659_alg_dac2_src);
2170
2171 static const struct snd_kcontrol_new rt5659_alg_dac_l2_mux =
2172 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5659_alg_dac_l2_enum);
2173
2174 static SOC_ENUM_SINGLE_DECL(
2175 rt5659_alg_dac_r2_enum, RT5659_A_DAC_MUX,
2176 RT5659_A_DACR2_SFT, rt5659_alg_dac2_src);
2177
2178 static const struct snd_kcontrol_new rt5659_alg_dac_r2_mux =
2179 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5659_alg_dac_r2_enum);
2180
2181 /* Interface2 ADC Data Input*/
2182 /* MX-2F [13:12] */
2183 static const char * const rt5659_if2_adc_in_src[] = {
2184 "IF_ADC1", "IF_ADC2", "DAC_REF", "IF_ADC3"
2185 };
2186
2187 static SOC_ENUM_SINGLE_DECL(
2188 rt5659_if2_adc_in_enum, RT5659_DIG_INF23_DATA,
2189 RT5659_IF2_ADC_IN_SFT, rt5659_if2_adc_in_src);
2190
2191 static const struct snd_kcontrol_new rt5659_if2_adc_in_mux =
2192 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
2193
2194 /* Interface3 ADC Data Input*/
2195 /* MX-2F [1:0] */
2196 static const char * const rt5659_if3_adc_in_src[] = {
2197 "IF_ADC1", "IF_ADC2", "DAC_REF", "Stereo2_ADC_L/R"
2198 };
2199
2200 static SOC_ENUM_SINGLE_DECL(
2201 rt5659_if3_adc_in_enum, RT5659_DIG_INF23_DATA,
2202 RT5659_IF3_ADC_IN_SFT, rt5659_if3_adc_in_src);
2203
2204 static const struct snd_kcontrol_new rt5659_if3_adc_in_mux =
2205 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
2206
2207 /* PDM 1 L/R*/
2208 /* MX-31 [15] [13] */
2209 static const char * const rt5659_pdm_src[] = {
2210 "Mono DAC", "Stereo DAC"
2211 };
2212
2213 static SOC_ENUM_SINGLE_DECL(
2214 rt5659_pdm_l_enum, RT5659_PDM_OUT_CTRL,
2215 RT5659_PDM1_L_SFT, rt5659_pdm_src);
2216
2217 static const struct snd_kcontrol_new rt5659_pdm_l_mux =
2218 SOC_DAPM_ENUM("PDM L Source", rt5659_pdm_l_enum);
2219
2220 static SOC_ENUM_SINGLE_DECL(
2221 rt5659_pdm_r_enum, RT5659_PDM_OUT_CTRL,
2222 RT5659_PDM1_R_SFT, rt5659_pdm_src);
2223
2224 static const struct snd_kcontrol_new rt5659_pdm_r_mux =
2225 SOC_DAPM_ENUM("PDM R Source", rt5659_pdm_r_enum);
2226
2227 /* SPDIF Output source*/
2228 /* MX-36 [1:0] */
2229 static const char * const rt5659_spdif_src[] = {
2230 "IF1_DAC1", "IF1_DAC2", "IF2_DAC", "IF3_DAC"
2231 };
2232
2233 static SOC_ENUM_SINGLE_DECL(
2234 rt5659_spdif_enum, RT5659_SPDIF_CTRL,
2235 RT5659_SPDIF_SEL_SFT, rt5659_spdif_src);
2236
2237 static const struct snd_kcontrol_new rt5659_spdif_mux =
2238 SOC_DAPM_ENUM("SPDIF Source", rt5659_spdif_enum);
2239
2240 /* I2S1 TDM ADCDAT Source */
2241 /* MX-78[4:0] */
2242 static const char * const rt5659_rx_adc_data_src[] = {
2243 "AD1:AD2:DAC:NUL", "AD1:AD2:NUL:DAC", "AD1:DAC:AD2:NUL",
2244 "AD1:DAC:NUL:AD2", "AD1:NUL:DAC:AD2", "AD1:NUL:AD2:DAC",
2245 "AD2:AD1:DAC:NUL", "AD2:AD1:NUL:DAC", "AD2:DAC:AD1:NUL",
2246 "AD2:DAC:NUL:AD1", "AD2:NUL:DAC:AD1", "AD1:NUL:AD1:DAC",
2247 "DAC:AD1:AD2:NUL", "DAC:AD1:NUL:AD2", "DAC:AD2:AD1:NUL",
2248 "DAC:AD2:NUL:AD1", "DAC:NUL:DAC:AD2", "DAC:NUL:AD2:DAC",
2249 "NUL:AD1:AD2:DAC", "NUL:AD1:DAC:AD2", "NUL:AD2:AD1:DAC",
2250 "NUL:AD2:DAC:AD1", "NUL:DAC:DAC:AD2", "NUL:DAC:AD2:DAC"
2251 };
2252
2253 static SOC_ENUM_SINGLE_DECL(
2254 rt5659_rx_adc_data_enum, RT5659_TDM_CTRL_2,
2255 RT5659_ADCDAT_SRC_SFT, rt5659_rx_adc_data_src);
2256
2257 static const struct snd_kcontrol_new rt5659_rx_adc_dac_mux =
2258 SOC_DAPM_ENUM("TDM ADCDAT Source", rt5659_rx_adc_data_enum);
2259
2260 /* Out Volume Switch */
2261 static const struct snd_kcontrol_new spkvol_l_switch =
2262 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_L_SFT, 1, 1);
2263
2264 static const struct snd_kcontrol_new spkvol_r_switch =
2265 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_R_SFT, 1, 1);
2266
2267 static const struct snd_kcontrol_new monovol_switch =
2268 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_VOL_L_SFT, 1, 1);
2269
2270 static const struct snd_kcontrol_new outvol_l_switch =
2271 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_L_SFT, 1, 1);
2272
2273 static const struct snd_kcontrol_new outvol_r_switch =
2274 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_R_SFT, 1, 1);
2275
2276 /* Out Switch */
2277 static const struct snd_kcontrol_new spo_switch =
2278 SOC_DAPM_SINGLE("Switch", RT5659_CLASSD_2, RT5659_M_RF_DIG_SFT, 1, 1);
2279
2280 static const struct snd_kcontrol_new mono_switch =
2281 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_L_MUTE_SFT, 1, 1);
2282
2283 static const struct snd_kcontrol_new hpo_l_switch =
2284 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_L_MUTE_SFT, 1, 1);
2285
2286 static const struct snd_kcontrol_new hpo_r_switch =
2287 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_R_MUTE_SFT, 1, 1);
2288
2289 static const struct snd_kcontrol_new lout_l_switch =
2290 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_L_MUTE_SFT, 1, 1);
2291
2292 static const struct snd_kcontrol_new lout_r_switch =
2293 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_R_MUTE_SFT, 1, 1);
2294
2295 static const struct snd_kcontrol_new pdm_l_switch =
2296 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_L_SFT, 1,
2297 1);
2298
2299 static const struct snd_kcontrol_new pdm_r_switch =
2300 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_R_SFT, 1,
2301 1);
2302
2303 static int rt5659_spk_event(struct snd_soc_dapm_widget *w,
2304 struct snd_kcontrol *kcontrol, int event)
2305 {
2306 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2307
2308 switch (event) {
2309 case SND_SOC_DAPM_PRE_PMU:
2310 snd_soc_update_bits(codec, RT5659_CLASSD_CTRL_1,
2311 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_EN);
2312 snd_soc_update_bits(codec, RT5659_CLASSD_2,
2313 RT5659_M_RI_DIG, RT5659_M_RI_DIG);
2314 snd_soc_write(codec, RT5659_CLASSD_1, 0x0803);
2315 snd_soc_write(codec, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
2316 break;
2317
2318 case SND_SOC_DAPM_POST_PMD:
2319 snd_soc_write(codec, RT5659_CLASSD_1, 0x0011);
2320 snd_soc_update_bits(codec, RT5659_CLASSD_2,
2321 RT5659_M_RI_DIG, 0x0);
2322 snd_soc_write(codec, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
2323 snd_soc_update_bits(codec, RT5659_CLASSD_CTRL_1,
2324 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_DIS);
2325 break;
2326
2327 default:
2328 return 0;
2329 }
2330
2331 return 0;
2332
2333 }
2334
2335 static int rt5659_mono_event(struct snd_soc_dapm_widget *w,
2336 struct snd_kcontrol *kcontrol, int event)
2337 {
2338 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2339
2340 switch (event) {
2341 case SND_SOC_DAPM_PRE_PMU:
2342 snd_soc_write(codec, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
2343 break;
2344
2345 case SND_SOC_DAPM_POST_PMD:
2346 snd_soc_write(codec, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
2347 break;
2348
2349 default:
2350 return 0;
2351 }
2352
2353 return 0;
2354
2355 }
2356
2357 static int rt5659_hp_event(struct snd_soc_dapm_widget *w,
2358 struct snd_kcontrol *kcontrol, int event)
2359 {
2360 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2361
2362 switch (event) {
2363 case SND_SOC_DAPM_POST_PMU:
2364 snd_soc_write(codec, RT5659_HP_CHARGE_PUMP_1, 0x0e1e);
2365 snd_soc_update_bits(codec, RT5659_DEPOP_1, 0x0010, 0x0010);
2366 break;
2367
2368 case SND_SOC_DAPM_PRE_PMD:
2369 snd_soc_write(codec, RT5659_DEPOP_1, 0x0000);
2370 break;
2371
2372 default:
2373 return 0;
2374 }
2375
2376 return 0;
2377 }
2378
2379 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2380 struct snd_kcontrol *kcontrol, int event)
2381 {
2382 switch (event) {
2383 case SND_SOC_DAPM_POST_PMU:
2384 /*Add delay to avoid pop noise*/
2385 msleep(450);
2386 break;
2387
2388 default:
2389 return 0;
2390 }
2391
2392 return 0;
2393 }
2394
2395 static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = {
2396 SND_SOC_DAPM_SUPPLY("LDO2", RT5659_PWR_ANLG_3, RT5659_PWR_LDO2_BIT, 0,
2397 NULL, 0),
2398 SND_SOC_DAPM_SUPPLY("PLL", RT5659_PWR_ANLG_3, RT5659_PWR_PLL_BIT, 0,
2399 NULL, 0),
2400 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5659_PWR_VOL,
2401 RT5659_PWR_MIC_DET_BIT, 0, NULL, 0),
2402 SND_SOC_DAPM_SUPPLY("Mono Vref", RT5659_PWR_ANLG_1,
2403 RT5659_PWR_VREF3_BIT, 0, NULL, 0),
2404
2405 /* ASRC */
2406 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5659_ASRC_1,
2407 RT5659_I2S1_ASRC_SFT, 0, NULL, 0),
2408 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5659_ASRC_1,
2409 RT5659_I2S2_ASRC_SFT, 0, NULL, 0),
2410 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5659_ASRC_1,
2411 RT5659_I2S3_ASRC_SFT, 0, NULL, 0),
2412 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5659_ASRC_1,
2413 RT5659_DAC_STO_ASRC_SFT, 0, NULL, 0),
2414 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5659_ASRC_1,
2415 RT5659_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2416 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5659_ASRC_1,
2417 RT5659_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2418 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
2419 RT5659_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2420 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
2421 RT5659_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2422 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
2423 RT5659_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2424
2425 /* Input Side */
2426 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5659_PWR_ANLG_2, RT5659_PWR_MB1_BIT,
2427 0, NULL, 0),
2428 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5659_PWR_ANLG_2, RT5659_PWR_MB2_BIT,
2429 0, NULL, 0),
2430 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5659_PWR_ANLG_2, RT5659_PWR_MB3_BIT,
2431 0, NULL, 0),
2432
2433 /* Input Lines */
2434 SND_SOC_DAPM_INPUT("DMIC L1"),
2435 SND_SOC_DAPM_INPUT("DMIC R1"),
2436 SND_SOC_DAPM_INPUT("DMIC L2"),
2437 SND_SOC_DAPM_INPUT("DMIC R2"),
2438
2439 SND_SOC_DAPM_INPUT("IN1P"),
2440 SND_SOC_DAPM_INPUT("IN1N"),
2441 SND_SOC_DAPM_INPUT("IN2P"),
2442 SND_SOC_DAPM_INPUT("IN2N"),
2443 SND_SOC_DAPM_INPUT("IN3P"),
2444 SND_SOC_DAPM_INPUT("IN3N"),
2445 SND_SOC_DAPM_INPUT("IN4P"),
2446 SND_SOC_DAPM_INPUT("IN4N"),
2447
2448 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2449 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2450
2451 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2452 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2453 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5659_DMIC_CTRL_1,
2454 RT5659_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2455 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5659_DMIC_CTRL_1,
2456 RT5659_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2457
2458 /* Boost */
2459 SND_SOC_DAPM_PGA("BST1", RT5659_PWR_ANLG_2,
2460 RT5659_PWR_BST1_P_BIT, 0, NULL, 0),
2461 SND_SOC_DAPM_PGA("BST2", RT5659_PWR_ANLG_2,
2462 RT5659_PWR_BST2_P_BIT, 0, NULL, 0),
2463 SND_SOC_DAPM_PGA("BST3", RT5659_PWR_ANLG_2,
2464 RT5659_PWR_BST3_P_BIT, 0, NULL, 0),
2465 SND_SOC_DAPM_PGA("BST4", RT5659_PWR_ANLG_2,
2466 RT5659_PWR_BST4_P_BIT, 0, NULL, 0),
2467 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5659_PWR_ANLG_2,
2468 RT5659_PWR_BST1_BIT, 0, NULL, 0),
2469 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5659_PWR_ANLG_2,
2470 RT5659_PWR_BST2_BIT, 0, NULL, 0),
2471 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5659_PWR_ANLG_2,
2472 RT5659_PWR_BST3_BIT, 0, NULL, 0),
2473 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5659_PWR_ANLG_2,
2474 RT5659_PWR_BST4_BIT, 0, NULL, 0),
2475
2476
2477 /* Input Volume */
2478 SND_SOC_DAPM_PGA("INL VOL", RT5659_PWR_VOL, RT5659_PWR_IN_L_BIT,
2479 0, NULL, 0),
2480 SND_SOC_DAPM_PGA("INR VOL", RT5659_PWR_VOL, RT5659_PWR_IN_R_BIT,
2481 0, NULL, 0),
2482
2483 /* REC Mixer */
2484 SND_SOC_DAPM_MIXER("RECMIX1L", RT5659_PWR_MIXER, RT5659_PWR_RM1_L_BIT,
2485 0, rt5659_rec1_l_mix, ARRAY_SIZE(rt5659_rec1_l_mix)),
2486 SND_SOC_DAPM_MIXER("RECMIX1R", RT5659_PWR_MIXER, RT5659_PWR_RM1_R_BIT,
2487 0, rt5659_rec1_r_mix, ARRAY_SIZE(rt5659_rec1_r_mix)),
2488 SND_SOC_DAPM_MIXER("RECMIX2L", RT5659_PWR_MIXER, RT5659_PWR_RM2_L_BIT,
2489 0, rt5659_rec2_l_mix, ARRAY_SIZE(rt5659_rec2_l_mix)),
2490 SND_SOC_DAPM_MIXER("RECMIX2R", RT5659_PWR_MIXER, RT5659_PWR_RM2_R_BIT,
2491 0, rt5659_rec2_r_mix, ARRAY_SIZE(rt5659_rec2_r_mix)),
2492
2493 /* ADCs */
2494 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2495 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2496 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2497 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2498
2499 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5659_PWR_DIG_1,
2500 RT5659_PWR_ADC_L1_BIT, 0, NULL, 0),
2501 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1,
2502 RT5659_PWR_ADC_R1_BIT, 0, NULL, 0),
2503 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_2,
2504 RT5659_PWR_ADC_L2_BIT, 0, NULL, 0),
2505 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_2,
2506 RT5659_PWR_ADC_R2_BIT, 0, NULL, 0),
2507 SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,
2508 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2509 SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,
2510 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2511
2512 /* ADC Mux */
2513 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2514 &rt5659_sto1_dmic_mux),
2515 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2516 &rt5659_sto1_dmic_mux),
2517 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2518 &rt5659_sto1_adc1_mux),
2519 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2520 &rt5659_sto1_adc1_mux),
2521 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2522 &rt5659_sto1_adc2_mux),
2523 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2524 &rt5659_sto1_adc2_mux),
2525 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2526 &rt5659_sto1_adc_mux),
2527 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2528 &rt5659_sto1_adc_mux),
2529 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2530 &rt5659_mono_adc_l2_mux),
2531 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2532 &rt5659_mono_adc_r2_mux),
2533 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2534 &rt5659_mono_adc_l1_mux),
2535 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2536 &rt5659_mono_adc_r1_mux),
2537 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2538 &rt5659_mono_dmic_l_mux),
2539 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2540 &rt5659_mono_dmic_r_mux),
2541 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2542 &rt5659_mono_adc_l_mux),
2543 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2544 &rt5659_mono_adc_r_mux),
2545 /* ADC Mixer */
2546 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
2547 RT5659_PWR_ADC_S1F_BIT, 0, NULL, 0),
2548 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
2549 RT5659_PWR_ADC_S2F_BIT, 0, NULL, 0),
2550 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
2551 0, 0, rt5659_sto1_adc_l_mix,
2552 ARRAY_SIZE(rt5659_sto1_adc_l_mix)),
2553 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
2554 0, 0, rt5659_sto1_adc_r_mix,
2555 ARRAY_SIZE(rt5659_sto1_adc_r_mix)),
2556 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
2557 RT5659_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2558 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
2559 RT5659_L_MUTE_SFT, 1, rt5659_mono_adc_l_mix,
2560 ARRAY_SIZE(rt5659_mono_adc_l_mix)),
2561 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
2562 RT5659_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2563 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
2564 RT5659_R_MUTE_SFT, 1, rt5659_mono_adc_r_mix,
2565 ARRAY_SIZE(rt5659_mono_adc_r_mix)),
2566
2567 /* ADC PGA */
2568 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2572 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2573 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2574 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2575 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
2576
2577 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
2578 RT5659_L_MUTE_SFT, 1, NULL, 0),
2579 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
2580 RT5659_R_MUTE_SFT, 1, NULL, 0),
2581
2582 /* Digital Interface */
2583 SND_SOC_DAPM_SUPPLY("I2S1", RT5659_PWR_DIG_1, RT5659_PWR_I2S1_BIT,
2584 0, NULL, 0),
2585 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2587 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2588 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2589 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2591 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2592 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2594 SND_SOC_DAPM_SUPPLY("I2S2", RT5659_PWR_DIG_1, RT5659_PWR_I2S2_BIT, 0,
2595 NULL, 0),
2596 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2597 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2599 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2602 SND_SOC_DAPM_SUPPLY("I2S3", RT5659_PWR_DIG_1, RT5659_PWR_I2S3_BIT, 0,
2603 NULL, 0),
2604 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2605 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2606 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2609 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2610
2611 /* Digital Interface Select */
2612 SND_SOC_DAPM_PGA("TDM AD1:AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("TDM AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2614 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
2615 &rt5659_rx_adc_dac_mux),
2616 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
2617 &rt5659_if2_adc_in_mux),
2618 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2619 &rt5659_if3_adc_in_mux),
2620 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2621 &rt5659_if1_01_adc_swap_mux),
2622 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2623 &rt5659_if1_23_adc_swap_mux),
2624 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2625 &rt5659_if1_45_adc_swap_mux),
2626 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2627 &rt5659_if1_67_adc_swap_mux),
2628 SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2629 &rt5659_if2_dac_swap_mux),
2630 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2631 &rt5659_if2_adc_swap_mux),
2632 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2633 &rt5659_if3_dac_swap_mux),
2634 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2635 &rt5659_if3_adc_swap_mux),
2636
2637 /* Audio Interface */
2638 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2639 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2640 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2641 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2642 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2643 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2644
2645 /* Output Side */
2646 /* DAC mixer before sound effect */
2647 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2648 rt5659_dac_l_mix, ARRAY_SIZE(rt5659_dac_l_mix)),
2649 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2650 rt5659_dac_r_mix, ARRAY_SIZE(rt5659_dac_r_mix)),
2651
2652 /* DAC channel Mux */
2653 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux),
2654 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux),
2655 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux),
2656 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux),
2657
2658 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
2659 &rt5659_alg_dac_l1_mux),
2660 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
2661 &rt5659_alg_dac_r1_mux),
2662 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
2663 &rt5659_alg_dac_l2_mux),
2664 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
2665 &rt5659_alg_dac_r2_mux),
2666
2667 /* DAC Mixer */
2668 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5659_PWR_DIG_2,
2669 RT5659_PWR_DAC_S1F_BIT, 0, NULL, 0),
2670 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5659_PWR_DIG_2,
2671 RT5659_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2672 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5659_PWR_DIG_2,
2673 RT5659_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2674 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2675 rt5659_sto_dac_l_mix, ARRAY_SIZE(rt5659_sto_dac_l_mix)),
2676 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2677 rt5659_sto_dac_r_mix, ARRAY_SIZE(rt5659_sto_dac_r_mix)),
2678 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2679 rt5659_mono_dac_l_mix, ARRAY_SIZE(rt5659_mono_dac_l_mix)),
2680 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2681 rt5659_mono_dac_r_mix, ARRAY_SIZE(rt5659_mono_dac_r_mix)),
2682 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
2683 &rt5659_dig_dac_mixl_mux),
2684 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
2685 &rt5659_dig_dac_mixr_mux),
2686
2687 /* DACs */
2688 SND_SOC_DAPM_SUPPLY_S("DAC L1 Power", 1, RT5659_PWR_DIG_1,
2689 RT5659_PWR_DAC_L1_BIT, 0, NULL, 0),
2690 SND_SOC_DAPM_SUPPLY_S("DAC R1 Power", 1, RT5659_PWR_DIG_1,
2691 RT5659_PWR_DAC_R1_BIT, 0, NULL, 0),
2692 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2693 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2694
2695 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5659_PWR_DIG_1,
2696 RT5659_PWR_DAC_L2_BIT, 0, NULL, 0),
2697 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5659_PWR_DIG_1,
2698 RT5659_PWR_DAC_R2_BIT, 0, NULL, 0),
2699 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2700 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2701 SND_SOC_DAPM_PGA("DAC_REF", SND_SOC_NOPM, 0, 0, NULL, 0),
2702
2703 /* OUT Mixer */
2704 SND_SOC_DAPM_MIXER("SPK MIXL", RT5659_PWR_MIXER, RT5659_PWR_SM_L_BIT,
2705 0, rt5659_spk_l_mix, ARRAY_SIZE(rt5659_spk_l_mix)),
2706 SND_SOC_DAPM_MIXER("SPK MIXR", RT5659_PWR_MIXER, RT5659_PWR_SM_R_BIT,
2707 0, rt5659_spk_r_mix, ARRAY_SIZE(rt5659_spk_r_mix)),
2708 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5659_PWR_MIXER, RT5659_PWR_MM_BIT,
2709 0, rt5659_monovol_mix, ARRAY_SIZE(rt5659_monovol_mix)),
2710 SND_SOC_DAPM_MIXER("OUT MIXL", RT5659_PWR_MIXER, RT5659_PWR_OM_L_BIT,
2711 0, rt5659_out_l_mix, ARRAY_SIZE(rt5659_out_l_mix)),
2712 SND_SOC_DAPM_MIXER("OUT MIXR", RT5659_PWR_MIXER, RT5659_PWR_OM_R_BIT,
2713 0, rt5659_out_r_mix, ARRAY_SIZE(rt5659_out_r_mix)),
2714
2715 /* Output Volume */
2716 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5659_PWR_VOL, RT5659_PWR_SV_L_BIT, 0,
2717 &spkvol_l_switch),
2718 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5659_PWR_VOL, RT5659_PWR_SV_R_BIT, 0,
2719 &spkvol_r_switch),
2720 SND_SOC_DAPM_SWITCH("MONOVOL", RT5659_PWR_VOL, RT5659_PWR_MV_BIT, 0,
2721 &monovol_switch),
2722 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5659_PWR_VOL, RT5659_PWR_OV_L_BIT, 0,
2723 &outvol_l_switch),
2724 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5659_PWR_VOL, RT5659_PWR_OV_R_BIT, 0,
2725 &outvol_r_switch),
2726
2727 /* SPO/MONO/HPO/LOUT */
2728 SND_SOC_DAPM_MIXER("SPO L MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_l_mix,
2729 ARRAY_SIZE(rt5659_spo_l_mix)),
2730 SND_SOC_DAPM_MIXER("SPO R MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_r_mix,
2731 ARRAY_SIZE(rt5659_spo_r_mix)),
2732 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5659_mono_mix,
2733 ARRAY_SIZE(rt5659_mono_mix)),
2734 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_l_mix,
2735 ARRAY_SIZE(rt5659_lout_l_mix)),
2736 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_r_mix,
2737 ARRAY_SIZE(rt5659_lout_r_mix)),
2738
2739 SND_SOC_DAPM_PGA_S("SPK Amp", 1, RT5659_PWR_DIG_1, RT5659_PWR_CLS_D_BIT,
2740 0, rt5659_spk_event, SND_SOC_DAPM_POST_PMD |
2741 SND_SOC_DAPM_PRE_PMU),
2742 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_MA_BIT,
2743 0, rt5659_mono_event, SND_SOC_DAPM_POST_PMD |
2744 SND_SOC_DAPM_PRE_PMU),
2745 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5659_hp_event,
2746 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2747 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_LM_BIT,
2748 0, NULL, 0),
2749
2750 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
2751 rt5659_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2752 SND_SOC_DAPM_POST_PMD),
2753
2754 SND_SOC_DAPM_SWITCH("SPO Playback", SND_SOC_NOPM, 0, 0, &spo_switch),
2755 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
2756 &mono_switch),
2757 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
2758 &hpo_l_switch),
2759 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
2760 &hpo_r_switch),
2761 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
2762 &lout_l_switch),
2763 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
2764 &lout_r_switch),
2765 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
2766 &pdm_l_switch),
2767 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
2768 &pdm_r_switch),
2769
2770 /* PDM */
2771 SND_SOC_DAPM_SUPPLY("PDM Power", RT5659_PWR_DIG_2,
2772 RT5659_PWR_PDM1_BIT, 0, NULL, 0),
2773 SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL,
2774 RT5659_M_PDM1_L_SFT, 1, &rt5659_pdm_l_mux),
2775 SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL,
2776 RT5659_M_PDM1_R_SFT, 1, &rt5659_pdm_r_mux),
2777
2778 /* SPDIF */
2779 SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux),
2780
2781 SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0),
2782 SND_SOC_DAPM_SUPPLY("CLKDET", RT5659_CLK_DET, 0, 0, NULL, 0),
2783
2784 /* Output Lines */
2785 SND_SOC_DAPM_OUTPUT("HPOL"),
2786 SND_SOC_DAPM_OUTPUT("HPOR"),
2787 SND_SOC_DAPM_OUTPUT("SPOL"),
2788 SND_SOC_DAPM_OUTPUT("SPOR"),
2789 SND_SOC_DAPM_OUTPUT("LOUTL"),
2790 SND_SOC_DAPM_OUTPUT("LOUTR"),
2791 SND_SOC_DAPM_OUTPUT("MONOOUT"),
2792 SND_SOC_DAPM_OUTPUT("PDML"),
2793 SND_SOC_DAPM_OUTPUT("PDMR"),
2794 SND_SOC_DAPM_OUTPUT("SPDIF"),
2795 };
2796
2797 static const struct snd_soc_dapm_route rt5659_dapm_routes[] = {
2798 /*PLL*/
2799 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2800 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
2801 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2802 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2803 { "DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2804 { "DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2805 { "DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2806
2807 /*ASRC*/
2808 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2809 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
2810 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
2811 { "DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc },
2812 { "DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc },
2813 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
2814
2815 { "SYS CLK DET", NULL, "CLKDET" },
2816
2817 { "I2S1", NULL, "I2S1 ASRC" },
2818 { "I2S2", NULL, "I2S2 ASRC" },
2819 { "I2S3", NULL, "I2S3 ASRC" },
2820
2821 { "IN1P", NULL, "LDO2" },
2822 { "IN2P", NULL, "LDO2" },
2823 { "IN3P", NULL, "LDO2" },
2824 { "IN4P", NULL, "LDO2" },
2825
2826 { "DMIC1", NULL, "DMIC L1" },
2827 { "DMIC1", NULL, "DMIC R1" },
2828 { "DMIC2", NULL, "DMIC L2" },
2829 { "DMIC2", NULL, "DMIC R2" },
2830
2831 { "BST1", NULL, "IN1P" },
2832 { "BST1", NULL, "IN1N" },
2833 { "BST1", NULL, "BST1 Power" },
2834 { "BST2", NULL, "IN2P" },
2835 { "BST2", NULL, "IN2N" },
2836 { "BST2", NULL, "BST2 Power" },
2837 { "BST3", NULL, "IN3P" },
2838 { "BST3", NULL, "IN3N" },
2839 { "BST3", NULL, "BST3 Power" },
2840 { "BST4", NULL, "IN4P" },
2841 { "BST4", NULL, "IN4N" },
2842 { "BST4", NULL, "BST4 Power" },
2843
2844 { "INL VOL", NULL, "IN2P" },
2845 { "INR VOL", NULL, "IN2N" },
2846
2847 { "RECMIX1L", "SPKVOLL Switch", "SPKVOL L" },
2848 { "RECMIX1L", "INL Switch", "INL VOL" },
2849 { "RECMIX1L", "BST4 Switch", "BST4" },
2850 { "RECMIX1L", "BST3 Switch", "BST3" },
2851 { "RECMIX1L", "BST2 Switch", "BST2" },
2852 { "RECMIX1L", "BST1 Switch", "BST1" },
2853
2854 { "RECMIX1R", "HPOVOLR Switch", "HPO R Playback" },
2855 { "RECMIX1R", "INR Switch", "INR VOL" },
2856 { "RECMIX1R", "BST4 Switch", "BST4" },
2857 { "RECMIX1R", "BST3 Switch", "BST3" },
2858 { "RECMIX1R", "BST2 Switch", "BST2" },
2859 { "RECMIX1R", "BST1 Switch", "BST1" },
2860
2861 { "RECMIX2L", "SPKVOLL Switch", "SPKVOL L" },
2862 { "RECMIX2L", "OUTVOLL Switch", "OUTVOL L" },
2863 { "RECMIX2L", "BST4 Switch", "BST4" },
2864 { "RECMIX2L", "BST3 Switch", "BST3" },
2865 { "RECMIX2L", "BST2 Switch", "BST2" },
2866 { "RECMIX2L", "BST1 Switch", "BST1" },
2867
2868 { "RECMIX2R", "MONOVOL Switch", "MONOVOL" },
2869 { "RECMIX2R", "OUTVOLR Switch", "OUTVOL R" },
2870 { "RECMIX2R", "BST4 Switch", "BST4" },
2871 { "RECMIX2R", "BST3 Switch", "BST3" },
2872 { "RECMIX2R", "BST2 Switch", "BST2" },
2873 { "RECMIX2R", "BST1 Switch", "BST1" },
2874
2875 { "ADC1 L", NULL, "RECMIX1L" },
2876 { "ADC1 L", NULL, "ADC1 L Power" },
2877 { "ADC1 L", NULL, "ADC1 clock" },
2878 { "ADC1 R", NULL, "RECMIX1R" },
2879 { "ADC1 R", NULL, "ADC1 R Power" },
2880 { "ADC1 R", NULL, "ADC1 clock" },
2881
2882 { "ADC2 L", NULL, "RECMIX2L" },
2883 { "ADC2 L", NULL, "ADC2 L Power" },
2884 { "ADC2 L", NULL, "ADC2 clock" },
2885 { "ADC2 R", NULL, "RECMIX2R" },
2886 { "ADC2 R", NULL, "ADC2 R Power" },
2887 { "ADC2 R", NULL, "ADC2 clock" },
2888
2889 { "DMIC L1", NULL, "DMIC CLK" },
2890 { "DMIC L1", NULL, "DMIC1 Power" },
2891 { "DMIC R1", NULL, "DMIC CLK" },
2892 { "DMIC R1", NULL, "DMIC1 Power" },
2893 { "DMIC L2", NULL, "DMIC CLK" },
2894 { "DMIC L2", NULL, "DMIC2 Power" },
2895 { "DMIC R2", NULL, "DMIC CLK" },
2896 { "DMIC R2", NULL, "DMIC2 Power" },
2897
2898 { "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" },
2899 { "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" },
2900
2901 { "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" },
2902 { "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" },
2903
2904 { "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" },
2905 { "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" },
2906
2907 { "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" },
2908 { "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" },
2909
2910 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
2911 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
2912 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
2913 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
2914
2915 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
2916 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2917 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
2918 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2919
2920 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
2921 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2922 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
2923 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2924
2925 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
2926 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
2927 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
2928 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
2929
2930 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
2931 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
2932 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
2933 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
2934
2935 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2936 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2937 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2938 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
2939
2940 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2941 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
2942 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2943 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2944
2945 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2946 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2947 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
2948
2949 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2950 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2951 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
2952
2953 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2954 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2955 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
2956
2957 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2958 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2959 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
2960
2961 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
2962 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
2963
2964 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
2965 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
2966 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2967 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2968
2969 { "TDM AD1:AD2:DAC", NULL, "IF_ADC1" },
2970 { "TDM AD1:AD2:DAC", NULL, "IF_ADC2" },
2971 { "TDM AD1:AD2:DAC", NULL, "DAC_REF" },
2972 { "TDM AD2:DAC", NULL, "IF_ADC2" },
2973 { "TDM AD2:DAC", NULL, "DAC_REF" },
2974 { "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" },
2975 { "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" },
2976 { "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" },
2977 { "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" },
2978 { "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" },
2979 { "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" },
2980 { "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" },
2981 { "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" },
2982 { "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" },
2983 { "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" },
2984 { "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" },
2985 { "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" },
2986 { "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" },
2987 { "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" },
2988 { "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" },
2989 { "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" },
2990 { "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" },
2991 { "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" },
2992 { "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" },
2993 { "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" },
2994 { "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" },
2995 { "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" },
2996 { "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" },
2997 { "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" },
2998 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
2999 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
3000 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
3001 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
3002 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
3003 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
3004 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
3005 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
3006 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
3007 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
3008 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
3009 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
3010 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
3011 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
3012 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
3013 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
3014 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
3015 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
3016 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
3017 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
3018 { "IF1 ADC", NULL, "I2S1" },
3019
3020 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
3021 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
3022 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
3023 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
3024 { "IF2 ADC", NULL, "IF2 ADC Mux"},
3025 { "IF2 ADC", NULL, "I2S2" },
3026
3027 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
3028 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
3029 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
3030 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
3031 { "IF3 ADC", NULL, "IF3 ADC Mux"},
3032 { "IF3 ADC", NULL, "I2S3" },
3033
3034 { "AIF1TX", NULL, "IF1 ADC" },
3035 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
3036 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
3037 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
3038 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
3039 { "AIF2TX", NULL, "IF2 ADC Swap Mux" },
3040 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
3041 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
3042 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
3043 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
3044 { "AIF3TX", NULL, "IF3 ADC Swap Mux" },
3045
3046 { "IF1 DAC1", NULL, "AIF1RX" },
3047 { "IF1 DAC2", NULL, "AIF1RX" },
3048 { "IF2 DAC Swap Mux", "L/R", "AIF2RX" },
3049 { "IF2 DAC Swap Mux", "R/L", "AIF2RX" },
3050 { "IF2 DAC Swap Mux", "L/L", "AIF2RX" },
3051 { "IF2 DAC Swap Mux", "R/R", "AIF2RX" },
3052 { "IF2 DAC", NULL, "IF2 DAC Swap Mux" },
3053 { "IF3 DAC Swap Mux", "L/R", "AIF3RX" },
3054 { "IF3 DAC Swap Mux", "R/L", "AIF3RX" },
3055 { "IF3 DAC Swap Mux", "L/L", "AIF3RX" },
3056 { "IF3 DAC Swap Mux", "R/R", "AIF3RX" },
3057 { "IF3 DAC", NULL, "IF3 DAC Swap Mux" },
3058
3059 { "IF1 DAC1", NULL, "I2S1" },
3060 { "IF1 DAC2", NULL, "I2S1" },
3061 { "IF2 DAC", NULL, "I2S2" },
3062 { "IF3 DAC", NULL, "I2S3" },
3063
3064 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
3065 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
3066 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
3067 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
3068 { "IF2 DAC L", NULL, "IF2 DAC" },
3069 { "IF2 DAC R", NULL, "IF2 DAC" },
3070 { "IF3 DAC L", NULL, "IF3 DAC" },
3071 { "IF3 DAC R", NULL, "IF3 DAC" },
3072
3073 { "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" },
3074 { "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" },
3075 { "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" },
3076 { "DAC L1 Mux", NULL, "DAC Stereo1 Filter" },
3077
3078 { "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" },
3079 { "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" },
3080 { "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" },
3081 { "DAC R1 Mux", NULL, "DAC Stereo1 Filter" },
3082
3083 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
3084 { "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" },
3085 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
3086 { "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" },
3087
3088 { "DAC_REF", NULL, "DAC1 MIXL" },
3089 { "DAC_REF", NULL, "DAC1 MIXR" },
3090
3091 { "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" },
3092 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
3093 { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
3094 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
3095 { "DAC L2 Mux", NULL, "DAC Mono Left Filter" },
3096
3097 { "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" },
3098 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
3099 { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
3100 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
3101 { "DAC R2 Mux", NULL, "DAC Mono Right Filter" },
3102
3103 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3104 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3105 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3106 { "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3107
3108 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3109 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3110 { "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3111 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3112
3113 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3114 { "Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3115 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3116 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3117 { "Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3118 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3119 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3120 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3121
3122 { "DAC MIXL", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3123 { "DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL" },
3124 { "DAC MIXR", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3125 { "DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR" },
3126
3127 { "DAC L1 Source", NULL, "DAC L1 Power" },
3128 { "DAC L1 Source", "DAC", "DAC1 MIXL" },
3129 { "DAC L1 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3130 { "DAC R1 Source", NULL, "DAC R1 Power" },
3131 { "DAC R1 Source", "DAC", "DAC1 MIXR" },
3132 { "DAC R1 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3133 { "DAC L2 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3134 { "DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL" },
3135 { "DAC L2 Source", NULL, "DAC L2 Power" },
3136 { "DAC R2 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3137 { "DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR" },
3138 { "DAC R2 Source", NULL, "DAC R2 Power" },
3139
3140 { "DAC L1", NULL, "DAC L1 Source" },
3141 { "DAC R1", NULL, "DAC R1 Source" },
3142 { "DAC L2", NULL, "DAC L2 Source" },
3143 { "DAC R2", NULL, "DAC R2 Source" },
3144
3145 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
3146 { "SPK MIXL", "BST1 Switch", "BST1" },
3147 { "SPK MIXL", "INL Switch", "INL VOL" },
3148 { "SPK MIXL", "INR Switch", "INR VOL" },
3149 { "SPK MIXL", "BST3 Switch", "BST3" },
3150 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
3151 { "SPK MIXR", "BST4 Switch", "BST4" },
3152 { "SPK MIXR", "INL Switch", "INL VOL" },
3153 { "SPK MIXR", "INR Switch", "INR VOL" },
3154 { "SPK MIXR", "BST3 Switch", "BST3" },
3155
3156 { "MONOVOL MIX", "DAC L2 Switch", "DAC L2" },
3157 { "MONOVOL MIX", "DAC R2 Switch", "DAC R2" },
3158 { "MONOVOL MIX", "BST1 Switch", "BST1" },
3159 { "MONOVOL MIX", "BST2 Switch", "BST2" },
3160 { "MONOVOL MIX", "BST3 Switch", "BST3" },
3161
3162 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
3163 { "OUT MIXL", "INL Switch", "INL VOL" },
3164 { "OUT MIXL", "BST1 Switch", "BST1" },
3165 { "OUT MIXL", "BST2 Switch", "BST2" },
3166 { "OUT MIXL", "BST3 Switch", "BST3" },
3167 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
3168 { "OUT MIXR", "INR Switch", "INR VOL" },
3169 { "OUT MIXR", "BST2 Switch", "BST2" },
3170 { "OUT MIXR", "BST3 Switch", "BST3" },
3171 { "OUT MIXR", "BST4 Switch", "BST4" },
3172
3173 { "SPKVOL L", "Switch", "SPK MIXL" },
3174 { "SPKVOL R", "Switch", "SPK MIXR" },
3175 { "SPO L MIX", "DAC L2 Switch", "DAC L2" },
3176 { "SPO L MIX", "SPKVOL L Switch", "SPKVOL L" },
3177 { "SPO R MIX", "DAC R2 Switch", "DAC R2" },
3178 { "SPO R MIX", "SPKVOL R Switch", "SPKVOL R" },
3179 { "SPK Amp", NULL, "SPO L MIX" },
3180 { "SPK Amp", NULL, "SPO R MIX" },
3181 { "SPK Amp", NULL, "SYS CLK DET" },
3182 { "SPO Playback", "Switch", "SPK Amp" },
3183 { "SPOL", NULL, "SPO Playback" },
3184 { "SPOR", NULL, "SPO Playback" },
3185
3186 { "MONOVOL", "Switch", "MONOVOL MIX" },
3187 { "Mono MIX", "DAC L2 Switch", "DAC L2" },
3188 { "Mono MIX", "MONOVOL Switch", "MONOVOL" },
3189 { "Mono Amp", NULL, "Mono MIX" },
3190 { "Mono Amp", NULL, "Mono Vref" },
3191 { "Mono Amp", NULL, "SYS CLK DET" },
3192 { "Mono Playback", "Switch", "Mono Amp" },
3193 { "MONOOUT", NULL, "Mono Playback" },
3194
3195 { "HP Amp", NULL, "DAC L1" },
3196 { "HP Amp", NULL, "DAC R1" },
3197 { "HP Amp", NULL, "Charge Pump" },
3198 { "HP Amp", NULL, "SYS CLK DET" },
3199 { "HPO L Playback", "Switch", "HP Amp"},
3200 { "HPO R Playback", "Switch", "HP Amp"},
3201 { "HPOL", NULL, "HPO L Playback" },
3202 { "HPOR", NULL, "HPO R Playback" },
3203
3204 { "OUTVOL L", "Switch", "OUT MIXL" },
3205 { "OUTVOL R", "Switch", "OUT MIXR" },
3206 { "LOUT L MIX", "DAC L2 Switch", "DAC L2" },
3207 { "LOUT L MIX", "OUTVOL L Switch", "OUTVOL L" },
3208 { "LOUT R MIX", "DAC R2 Switch", "DAC R2" },
3209 { "LOUT R MIX", "OUTVOL R Switch", "OUTVOL R" },
3210 { "LOUT Amp", NULL, "LOUT L MIX" },
3211 { "LOUT Amp", NULL, "LOUT R MIX" },
3212 { "LOUT Amp", NULL, "Charge Pump" },
3213 { "LOUT Amp", NULL, "SYS CLK DET" },
3214 { "LOUT L Playback", "Switch", "LOUT Amp" },
3215 { "LOUT R Playback", "Switch", "LOUT Amp" },
3216 { "LOUTL", NULL, "LOUT L Playback" },
3217 { "LOUTR", NULL, "LOUT R Playback" },
3218
3219 { "PDM L Mux", "Mono DAC", "Mono DAC MIXL" },
3220 { "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" },
3221 { "PDM L Mux", NULL, "PDM Power" },
3222 { "PDM R Mux", "Mono DAC", "Mono DAC MIXR" },
3223 { "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" },
3224 { "PDM R Mux", NULL, "PDM Power" },
3225 { "PDM L Playback", "Switch", "PDM L Mux" },
3226 { "PDM R Playback", "Switch", "PDM R Mux" },
3227 { "PDML", NULL, "PDM L Playback" },
3228 { "PDMR", NULL, "PDM R Playback" },
3229
3230 { "SPDIF Mux", "IF3_DAC", "IF3 DAC" },
3231 { "SPDIF Mux", "IF2_DAC", "IF2 DAC" },
3232 { "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" },
3233 { "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" },
3234 { "SPDIF", NULL, "SPDIF Mux" },
3235 };
3236
3237 static int rt5659_hw_params(struct snd_pcm_substream *substream,
3238 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3239 {
3240 struct snd_soc_codec *codec = dai->codec;
3241 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3242 unsigned int val_len = 0, val_clk, mask_clk;
3243 int pre_div, frame_size;
3244
3245 rt5659->lrck[dai->id] = params_rate(params);
3246 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]);
3247 if (pre_div < 0) {
3248 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
3249 rt5659->lrck[dai->id], dai->id);
3250 return -EINVAL;
3251 }
3252 frame_size = snd_soc_params_to_frame_size(params);
3253 if (frame_size < 0) {
3254 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3255 return -EINVAL;
3256 }
3257
3258 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
3259 rt5659->lrck[dai->id], pre_div, dai->id);
3260
3261 switch (params_width(params)) {
3262 case 16:
3263 break;
3264 case 20:
3265 val_len |= RT5659_I2S_DL_20;
3266 break;
3267 case 24:
3268 val_len |= RT5659_I2S_DL_24;
3269 break;
3270 case 8:
3271 val_len |= RT5659_I2S_DL_8;
3272 break;
3273 default:
3274 return -EINVAL;
3275 }
3276
3277 switch (dai->id) {
3278 case RT5659_AIF1:
3279 mask_clk = RT5659_I2S_PD1_MASK;
3280 val_clk = pre_div << RT5659_I2S_PD1_SFT;
3281 snd_soc_update_bits(codec, RT5659_I2S1_SDP,
3282 RT5659_I2S_DL_MASK, val_len);
3283 break;
3284 case RT5659_AIF2:
3285 mask_clk = RT5659_I2S_PD2_MASK;
3286 val_clk = pre_div << RT5659_I2S_PD2_SFT;
3287 snd_soc_update_bits(codec, RT5659_I2S2_SDP,
3288 RT5659_I2S_DL_MASK, val_len);
3289 break;
3290 case RT5659_AIF3:
3291 mask_clk = RT5659_I2S_PD3_MASK;
3292 val_clk = pre_div << RT5659_I2S_PD3_SFT;
3293 snd_soc_update_bits(codec, RT5659_I2S3_SDP,
3294 RT5659_I2S_DL_MASK, val_len);
3295 break;
3296 default:
3297 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
3298 return -EINVAL;
3299 }
3300
3301 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1, mask_clk, val_clk);
3302
3303 switch (rt5659->lrck[dai->id]) {
3304 case 192000:
3305 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3306 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_32);
3307 break;
3308 case 96000:
3309 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3310 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_64);
3311 break;
3312 default:
3313 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3314 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_128);
3315 break;
3316 }
3317
3318 return 0;
3319 }
3320
3321 static int rt5659_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3322 {
3323 struct snd_soc_codec *codec = dai->codec;
3324 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3325 unsigned int reg_val = 0;
3326
3327 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3328 case SND_SOC_DAIFMT_CBM_CFM:
3329 rt5659->master[dai->id] = 1;
3330 break;
3331 case SND_SOC_DAIFMT_CBS_CFS:
3332 reg_val |= RT5659_I2S_MS_S;
3333 rt5659->master[dai->id] = 0;
3334 break;
3335 default:
3336 return -EINVAL;
3337 }
3338
3339 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3340 case SND_SOC_DAIFMT_NB_NF:
3341 break;
3342 case SND_SOC_DAIFMT_IB_NF:
3343 reg_val |= RT5659_I2S_BP_INV;
3344 break;
3345 default:
3346 return -EINVAL;
3347 }
3348
3349 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3350 case SND_SOC_DAIFMT_I2S:
3351 break;
3352 case SND_SOC_DAIFMT_LEFT_J:
3353 reg_val |= RT5659_I2S_DF_LEFT;
3354 break;
3355 case SND_SOC_DAIFMT_DSP_A:
3356 reg_val |= RT5659_I2S_DF_PCM_A;
3357 break;
3358 case SND_SOC_DAIFMT_DSP_B:
3359 reg_val |= RT5659_I2S_DF_PCM_B;
3360 break;
3361 default:
3362 return -EINVAL;
3363 }
3364
3365 switch (dai->id) {
3366 case RT5659_AIF1:
3367 snd_soc_update_bits(codec, RT5659_I2S1_SDP,
3368 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3369 RT5659_I2S_DF_MASK, reg_val);
3370 break;
3371 case RT5659_AIF2:
3372 snd_soc_update_bits(codec, RT5659_I2S2_SDP,
3373 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3374 RT5659_I2S_DF_MASK, reg_val);
3375 break;
3376 case RT5659_AIF3:
3377 snd_soc_update_bits(codec, RT5659_I2S3_SDP,
3378 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3379 RT5659_I2S_DF_MASK, reg_val);
3380 break;
3381 default:
3382 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
3383 return -EINVAL;
3384 }
3385 return 0;
3386 }
3387
3388 static int rt5659_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
3389 int source, unsigned int freq, int dir)
3390 {
3391 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3392 unsigned int reg_val = 0;
3393
3394 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src)
3395 return 0;
3396
3397 switch (clk_id) {
3398 case RT5659_SCLK_S_MCLK:
3399 reg_val |= RT5659_SCLK_SRC_MCLK;
3400 break;
3401 case RT5659_SCLK_S_PLL1:
3402 reg_val |= RT5659_SCLK_SRC_PLL1;
3403 break;
3404 case RT5659_SCLK_S_RCCLK:
3405 reg_val |= RT5659_SCLK_SRC_RCCLK;
3406 break;
3407 default:
3408 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3409 return -EINVAL;
3410 }
3411 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3412 RT5659_SCLK_SRC_MASK, reg_val);
3413 rt5659->sysclk = freq;
3414 rt5659->sysclk_src = clk_id;
3415
3416 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
3417 freq, clk_id);
3418
3419 return 0;
3420 }
3421
3422 static int rt5659_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
3423 int source, unsigned int freq_in,
3424 unsigned int freq_out)
3425 {
3426 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3427 struct rl6231_pll_code pll_code;
3428 int ret;
3429
3430 if (source == rt5659->pll_src && freq_in == rt5659->pll_in &&
3431 freq_out == rt5659->pll_out)
3432 return 0;
3433
3434 if (!freq_in || !freq_out) {
3435 dev_dbg(codec->dev, "PLL disabled\n");
3436
3437 rt5659->pll_in = 0;
3438 rt5659->pll_out = 0;
3439 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3440 RT5659_SCLK_SRC_MASK, RT5659_SCLK_SRC_MCLK);
3441 return 0;
3442 }
3443
3444 switch (source) {
3445 case RT5659_PLL1_S_MCLK:
3446 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3447 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_MCLK);
3448 break;
3449 case RT5659_PLL1_S_BCLK1:
3450 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3451 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK1);
3452 break;
3453 case RT5659_PLL1_S_BCLK2:
3454 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3455 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK2);
3456 break;
3457 case RT5659_PLL1_S_BCLK3:
3458 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3459 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK3);
3460 break;
3461 default:
3462 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3463 return -EINVAL;
3464 }
3465
3466 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
3467 if (ret < 0) {
3468 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3469 return ret;
3470 }
3471
3472 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
3473 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3474 pll_code.n_code, pll_code.k_code);
3475
3476 snd_soc_write(codec, RT5659_PLL_CTRL_1,
3477 pll_code.n_code << RT5659_PLL_N_SFT | pll_code.k_code);
3478 snd_soc_write(codec, RT5659_PLL_CTRL_2,
3479 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5659_PLL_M_SFT |
3480 pll_code.m_bp << RT5659_PLL_M_BP_SFT);
3481
3482 rt5659->pll_in = freq_in;
3483 rt5659->pll_out = freq_out;
3484 rt5659->pll_src = source;
3485
3486 return 0;
3487 }
3488
3489 static int rt5659_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3490 unsigned int rx_mask, int slots, int slot_width)
3491 {
3492 struct snd_soc_codec *codec = dai->codec;
3493 unsigned int val = 0;
3494
3495 if (rx_mask || tx_mask)
3496 val |= (1 << 15);
3497
3498 switch (slots) {
3499 case 4:
3500 val |= (1 << 10);
3501 val |= (1 << 8);
3502 break;
3503 case 6:
3504 val |= (2 << 10);
3505 val |= (2 << 8);
3506 break;
3507 case 8:
3508 val |= (3 << 10);
3509 val |= (3 << 8);
3510 break;
3511 case 2:
3512 break;
3513 default:
3514 return -EINVAL;
3515 }
3516
3517 switch (slot_width) {
3518 case 20:
3519 val |= (1 << 6);
3520 val |= (1 << 4);
3521 break;
3522 case 24:
3523 val |= (2 << 6);
3524 val |= (2 << 4);
3525 break;
3526 case 32:
3527 val |= (3 << 6);
3528 val |= (3 << 4);
3529 break;
3530 case 16:
3531 break;
3532 default:
3533 return -EINVAL;
3534 }
3535
3536 snd_soc_update_bits(codec, RT5659_TDM_CTRL_1, 0x8ff0, val);
3537
3538 return 0;
3539 }
3540
3541 static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3542 {
3543 struct snd_soc_codec *codec = dai->codec;
3544 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3545
3546 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
3547
3548 rt5659->bclk[dai->id] = ratio;
3549
3550 if (ratio == 64) {
3551 switch (dai->id) {
3552 case RT5659_AIF2:
3553 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3554 RT5659_I2S_BCLK_MS2_MASK,
3555 RT5659_I2S_BCLK_MS2_64);
3556 break;
3557 case RT5659_AIF3:
3558 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3559 RT5659_I2S_BCLK_MS3_MASK,
3560 RT5659_I2S_BCLK_MS3_64);
3561 break;
3562 }
3563 }
3564
3565 return 0;
3566 }
3567
3568 static int rt5659_set_bias_level(struct snd_soc_codec *codec,
3569 enum snd_soc_bias_level level)
3570 {
3571 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3572 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3573 int ret;
3574
3575 switch (level) {
3576 case SND_SOC_BIAS_PREPARE:
3577 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3578 RT5659_DIG_GATE_CTRL, RT5659_DIG_GATE_CTRL);
3579 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3580 RT5659_PWR_LDO, RT5659_PWR_LDO);
3581 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3582 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2,
3583 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2);
3584 msleep(20);
3585 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3586 RT5659_PWR_FV1 | RT5659_PWR_FV2,
3587 RT5659_PWR_FV1 | RT5659_PWR_FV2);
3588 break;
3589
3590 case SND_SOC_BIAS_STANDBY:
3591 if (dapm->bias_level == SND_SOC_BIAS_OFF) {
3592 ret = clk_prepare_enable(rt5659->mclk);
3593 if (ret) {
3594 dev_err(codec->dev,
3595 "failed to enable MCLK: %d\n", ret);
3596 return ret;
3597 }
3598 }
3599 break;
3600
3601 case SND_SOC_BIAS_OFF:
3602 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3603 RT5659_PWR_LDO, 0);
3604 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3605 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2
3606 | RT5659_PWR_FV1 | RT5659_PWR_FV2,
3607 RT5659_PWR_MB | RT5659_PWR_VREF2);
3608 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3609 RT5659_DIG_GATE_CTRL, 0);
3610 clk_disable_unprepare(rt5659->mclk);
3611 break;
3612
3613 default:
3614 break;
3615 }
3616
3617 return 0;
3618 }
3619
3620 static int rt5659_probe(struct snd_soc_codec *codec)
3621 {
3622 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3623
3624 rt5659->codec = codec;
3625
3626 return 0;
3627 }
3628
3629 static int rt5659_remove(struct snd_soc_codec *codec)
3630 {
3631 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3632
3633 regmap_write(rt5659->regmap, RT5659_RESET, 0);
3634
3635 return 0;
3636 }
3637
3638 #ifdef CONFIG_PM
3639 static int rt5659_suspend(struct snd_soc_codec *codec)
3640 {
3641 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3642
3643 regcache_cache_only(rt5659->regmap, true);
3644 regcache_mark_dirty(rt5659->regmap);
3645 return 0;
3646 }
3647
3648 static int rt5659_resume(struct snd_soc_codec *codec)
3649 {
3650 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3651
3652 regcache_cache_only(rt5659->regmap, false);
3653 regcache_sync(rt5659->regmap);
3654
3655 return 0;
3656 }
3657 #else
3658 #define rt5659_suspend NULL
3659 #define rt5659_resume NULL
3660 #endif
3661
3662 #define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3663 #define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3664 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3665
3666 static const struct snd_soc_dai_ops rt5659_aif_dai_ops = {
3667 .hw_params = rt5659_hw_params,
3668 .set_fmt = rt5659_set_dai_fmt,
3669 .set_tdm_slot = rt5659_set_tdm_slot,
3670 .set_bclk_ratio = rt5659_set_bclk_ratio,
3671 };
3672
3673 static struct snd_soc_dai_driver rt5659_dai[] = {
3674 {
3675 .name = "rt5659-aif1",
3676 .id = RT5659_AIF1,
3677 .playback = {
3678 .stream_name = "AIF1 Playback",
3679 .channels_min = 1,
3680 .channels_max = 2,
3681 .rates = RT5659_STEREO_RATES,
3682 .formats = RT5659_FORMATS,
3683 },
3684 .capture = {
3685 .stream_name = "AIF1 Capture",
3686 .channels_min = 1,
3687 .channels_max = 2,
3688 .rates = RT5659_STEREO_RATES,
3689 .formats = RT5659_FORMATS,
3690 },
3691 .ops = &rt5659_aif_dai_ops,
3692 },
3693 {
3694 .name = "rt5659-aif2",
3695 .id = RT5659_AIF2,
3696 .playback = {
3697 .stream_name = "AIF2 Playback",
3698 .channels_min = 1,
3699 .channels_max = 2,
3700 .rates = RT5659_STEREO_RATES,
3701 .formats = RT5659_FORMATS,
3702 },
3703 .capture = {
3704 .stream_name = "AIF2 Capture",
3705 .channels_min = 1,
3706 .channels_max = 2,
3707 .rates = RT5659_STEREO_RATES,
3708 .formats = RT5659_FORMATS,
3709 },
3710 .ops = &rt5659_aif_dai_ops,
3711 },
3712 {
3713 .name = "rt5659-aif3",
3714 .id = RT5659_AIF3,
3715 .playback = {
3716 .stream_name = "AIF3 Playback",
3717 .channels_min = 1,
3718 .channels_max = 2,
3719 .rates = RT5659_STEREO_RATES,
3720 .formats = RT5659_FORMATS,
3721 },
3722 .capture = {
3723 .stream_name = "AIF3 Capture",
3724 .channels_min = 1,
3725 .channels_max = 2,
3726 .rates = RT5659_STEREO_RATES,
3727 .formats = RT5659_FORMATS,
3728 },
3729 .ops = &rt5659_aif_dai_ops,
3730 },
3731 };
3732
3733 static const struct snd_soc_codec_driver soc_codec_dev_rt5659 = {
3734 .probe = rt5659_probe,
3735 .remove = rt5659_remove,
3736 .suspend = rt5659_suspend,
3737 .resume = rt5659_resume,
3738 .set_bias_level = rt5659_set_bias_level,
3739 .idle_bias_off = true,
3740 .component_driver = {
3741 .controls = rt5659_snd_controls,
3742 .num_controls = ARRAY_SIZE(rt5659_snd_controls),
3743 .dapm_widgets = rt5659_dapm_widgets,
3744 .num_dapm_widgets = ARRAY_SIZE(rt5659_dapm_widgets),
3745 .dapm_routes = rt5659_dapm_routes,
3746 .num_dapm_routes = ARRAY_SIZE(rt5659_dapm_routes),
3747 },
3748 .set_sysclk = rt5659_set_codec_sysclk,
3749 .set_pll = rt5659_set_codec_pll,
3750 };
3751
3752
3753 static const struct regmap_config rt5659_regmap = {
3754 .reg_bits = 16,
3755 .val_bits = 16,
3756 .max_register = 0x0400,
3757 .volatile_reg = rt5659_volatile_register,
3758 .readable_reg = rt5659_readable_register,
3759 .cache_type = REGCACHE_RBTREE,
3760 .reg_defaults = rt5659_reg,
3761 .num_reg_defaults = ARRAY_SIZE(rt5659_reg),
3762 };
3763
3764 static const struct i2c_device_id rt5659_i2c_id[] = {
3765 { "rt5658", 0 },
3766 { "rt5659", 0 },
3767 { }
3768 };
3769 MODULE_DEVICE_TABLE(i2c, rt5659_i2c_id);
3770
3771 static int rt5659_parse_dt(struct rt5659_priv *rt5659, struct device *dev)
3772 {
3773 rt5659->pdata.in1_diff = device_property_read_bool(dev,
3774 "realtek,in1-differential");
3775 rt5659->pdata.in3_diff = device_property_read_bool(dev,
3776 "realtek,in3-differential");
3777 rt5659->pdata.in4_diff = device_property_read_bool(dev,
3778 "realtek,in4-differential");
3779
3780
3781 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3782 &rt5659->pdata.dmic1_data_pin);
3783 device_property_read_u32(dev, "realtek,dmic2-data-pin",
3784 &rt5659->pdata.dmic2_data_pin);
3785 device_property_read_u32(dev, "realtek,jd-src",
3786 &rt5659->pdata.jd_src);
3787
3788 return 0;
3789 }
3790
3791 static void rt5659_calibrate(struct rt5659_priv *rt5659)
3792 {
3793 int value, count;
3794
3795 /* Calibrate HPO Start */
3796 /* Fine tune HP Performance */
3797 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502);
3798 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030);
3799
3800 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00);
3801 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc);
3802 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280);
3803 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001);
3804 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000);
3805
3806 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e);
3807 msleep(60);
3808 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e);
3809 msleep(50);
3810 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004);
3811 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400);
3812 msleep(50);
3813 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080);
3814 usleep_range(10000, 10005);
3815 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009);
3816 msleep(50);
3817 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80);
3818 msleep(50);
3819 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16);
3820 msleep(50);
3821
3822 /* Enalbe K ADC Power And Clock */
3823 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505);
3824 msleep(50);
3825 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184);
3826 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05);
3827 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1);
3828
3829 /* K Headphone */
3830 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3831 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100);
3832 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014);
3833 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100);
3834 msleep(60);
3835
3836 /* Manual K ADC Offset */
3837 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3838 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900);
3839 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016);
3840 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3841 0x8000, 0x8000);
3842
3843 count = 0;
3844 while (true) {
3845 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3846 if (value & 0x8000)
3847 usleep_range(10000, 10005);
3848 else
3849 break;
3850
3851 if (count > 30) {
3852 dev_err(rt5659->codec->dev,
3853 "HP Calibration 1 Failure\n");
3854 return;
3855 }
3856
3857 count++;
3858 }
3859
3860 /* Manual K Internal Path Offset */
3861 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3862 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000);
3863 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500);
3864 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f);
3865 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3866 0x8000, 0x8000);
3867
3868 count = 0;
3869 while (true) {
3870 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3871 if (value & 0x8000)
3872 usleep_range(10000, 10005);
3873 else
3874 break;
3875
3876 if (count > 85) {
3877 dev_err(rt5659->codec->dev,
3878 "HP Calibration 2 Failure\n");
3879 return;
3880 }
3881
3882 count++;
3883 }
3884
3885 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000);
3886 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
3887 /* Calibrate HPO End */
3888
3889 /* Calibrate SPO Start */
3890 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
3891 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260);
3892 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000);
3893 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000);
3894 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c);
3895 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000);
3896 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808);
3897 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e);
3898 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e);
3899 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803);
3900 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554);
3901 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103);
3902
3903 /* Enalbe K ADC Power And Clock */
3904 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909);
3905 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001,
3906 0x0001);
3907
3908 /* Start Calibration */
3909 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
3910 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021);
3911 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80);
3912 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1,
3913 0x8000, 0x8000);
3914
3915 count = 0;
3916 while (true) {
3917 regmap_read(rt5659->regmap,
3918 RT5659_SPK_DC_CAILB_CTRL_1, &value);
3919 if (value & 0x8000)
3920 usleep_range(10000, 10005);
3921 else
3922 break;
3923
3924 if (count > 10) {
3925 dev_err(rt5659->codec->dev,
3926 "SPK Calibration Failure\n");
3927 return;
3928 }
3929
3930 count++;
3931 }
3932 /* Calibrate SPO End */
3933
3934 /* Calibrate MONO Start */
3935 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000);
3936 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f);
3937 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a);
3938 /* MONO NG2 GAIN 5dB */
3939 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003);
3940 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009);
3941
3942 /* Start Calibration */
3943 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f);
3944 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
3945 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
3946 0x8000, 0x8000);
3947
3948 count = 0;
3949 while (true) {
3950 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
3951 &value);
3952 if (value & 0x8000)
3953 usleep_range(10000, 10005);
3954 else
3955 break;
3956
3957 if (count > 35) {
3958 dev_err(rt5659->codec->dev,
3959 "Mono Calibration Failure\n");
3960 return;
3961 }
3962
3963 count++;
3964 }
3965
3966 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
3967 /* Calibrate MONO End */
3968
3969 /* Power Off */
3970 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808);
3971 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000);
3972 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005);
3973 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
3974 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000);
3975 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011);
3976 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150);
3977 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e);
3978 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a);
3979 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
3980 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000);
3981 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000);
3982 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000);
3983 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000);
3984 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e);
3985 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060);
3986 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
3987 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000);
3988 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080);
3989 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080);
3990 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
3991 }
3992
3993 static int rt5659_i2c_probe(struct i2c_client *i2c,
3994 const struct i2c_device_id *id)
3995 {
3996 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev);
3997 struct rt5659_priv *rt5659;
3998 int ret;
3999 unsigned int val;
4000
4001 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv),
4002 GFP_KERNEL);
4003
4004 if (rt5659 == NULL)
4005 return -ENOMEM;
4006
4007 i2c_set_clientdata(i2c, rt5659);
4008
4009 if (pdata)
4010 rt5659->pdata = *pdata;
4011 else
4012 rt5659_parse_dt(rt5659, &i2c->dev);
4013
4014 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en",
4015 GPIOD_OUT_HIGH);
4016 if (IS_ERR(rt5659->gpiod_ldo1_en))
4017 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n");
4018
4019 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset",
4020 GPIOD_OUT_HIGH);
4021
4022 /* Sleep for 300 ms miniumum */
4023 msleep(300);
4024
4025 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap);
4026 if (IS_ERR(rt5659->regmap)) {
4027 ret = PTR_ERR(rt5659->regmap);
4028 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4029 ret);
4030 return ret;
4031 }
4032
4033 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val);
4034 if (val != DEVICE_ID) {
4035 dev_err(&i2c->dev,
4036 "Device with ID register %x is not rt5659\n", val);
4037 return -ENODEV;
4038 }
4039
4040 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4041
4042 /* Check if MCLK provided */
4043 rt5659->mclk = devm_clk_get(&i2c->dev, "mclk");
4044 if (IS_ERR(rt5659->mclk)) {
4045 if (PTR_ERR(rt5659->mclk) != -ENOENT)
4046 return PTR_ERR(rt5659->mclk);
4047 /* Otherwise mark the mclk pointer to NULL */
4048 rt5659->mclk = NULL;
4049 }
4050
4051 rt5659_calibrate(rt5659);
4052
4053 /* line in diff mode*/
4054 if (rt5659->pdata.in1_diff)
4055 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2,
4056 RT5659_IN1_DF_MASK, RT5659_IN1_DF_MASK);
4057 if (rt5659->pdata.in3_diff)
4058 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4059 RT5659_IN3_DF_MASK, RT5659_IN3_DF_MASK);
4060 if (rt5659->pdata.in4_diff)
4061 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4062 RT5659_IN4_DF_MASK, RT5659_IN4_DF_MASK);
4063
4064 /* DMIC pin*/
4065 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL ||
4066 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) {
4067 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4068 RT5659_GP2_PIN_MASK, RT5659_GP2_PIN_DMIC1_SCL);
4069
4070 switch (rt5659->pdata.dmic1_data_pin) {
4071 case RT5659_DMIC1_DATA_IN2N:
4072 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4073 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_IN2N);
4074 break;
4075
4076 case RT5659_DMIC1_DATA_GPIO5:
4077 regmap_update_bits(rt5659->regmap,
4078 RT5659_GPIO_CTRL_3,
4079 RT5659_I2S2_PIN_MASK,
4080 RT5659_I2S2_PIN_GPIO);
4081 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4082 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO5);
4083 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4084 RT5659_GP5_PIN_MASK, RT5659_GP5_PIN_DMIC1_SDA);
4085 break;
4086
4087 case RT5659_DMIC1_DATA_GPIO9:
4088 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4089 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO9);
4090 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4091 RT5659_GP9_PIN_MASK, RT5659_GP9_PIN_DMIC1_SDA);
4092 break;
4093
4094 case RT5659_DMIC1_DATA_GPIO11:
4095 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4096 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO11);
4097 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4098 RT5659_GP11_PIN_MASK,
4099 RT5659_GP11_PIN_DMIC1_SDA);
4100 break;
4101
4102 default:
4103 dev_dbg(&i2c->dev, "no DMIC1\n");
4104 break;
4105 }
4106
4107 switch (rt5659->pdata.dmic2_data_pin) {
4108 case RT5659_DMIC2_DATA_IN2P:
4109 regmap_update_bits(rt5659->regmap,
4110 RT5659_DMIC_CTRL_1,
4111 RT5659_DMIC_2_DP_MASK,
4112 RT5659_DMIC_2_DP_IN2P);
4113 break;
4114
4115 case RT5659_DMIC2_DATA_GPIO6:
4116 regmap_update_bits(rt5659->regmap,
4117 RT5659_DMIC_CTRL_1,
4118 RT5659_DMIC_2_DP_MASK,
4119 RT5659_DMIC_2_DP_GPIO6);
4120 regmap_update_bits(rt5659->regmap,
4121 RT5659_GPIO_CTRL_1,
4122 RT5659_GP6_PIN_MASK,
4123 RT5659_GP6_PIN_DMIC2_SDA);
4124 break;
4125
4126 case RT5659_DMIC2_DATA_GPIO10:
4127 regmap_update_bits(rt5659->regmap,
4128 RT5659_DMIC_CTRL_1,
4129 RT5659_DMIC_2_DP_MASK,
4130 RT5659_DMIC_2_DP_GPIO10);
4131 regmap_update_bits(rt5659->regmap,
4132 RT5659_GPIO_CTRL_1,
4133 RT5659_GP10_PIN_MASK,
4134 RT5659_GP10_PIN_DMIC2_SDA);
4135 break;
4136
4137 case RT5659_DMIC2_DATA_GPIO12:
4138 regmap_update_bits(rt5659->regmap,
4139 RT5659_DMIC_CTRL_1,
4140 RT5659_DMIC_2_DP_MASK,
4141 RT5659_DMIC_2_DP_GPIO12);
4142 regmap_update_bits(rt5659->regmap,
4143 RT5659_GPIO_CTRL_1,
4144 RT5659_GP12_PIN_MASK,
4145 RT5659_GP12_PIN_DMIC2_SDA);
4146 break;
4147
4148 default:
4149 dev_dbg(&i2c->dev, "no DMIC2\n");
4150 break;
4151
4152 }
4153 } else {
4154 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4155 RT5659_GP2_PIN_MASK | RT5659_GP5_PIN_MASK |
4156 RT5659_GP9_PIN_MASK | RT5659_GP11_PIN_MASK |
4157 RT5659_GP6_PIN_MASK | RT5659_GP10_PIN_MASK |
4158 RT5659_GP12_PIN_MASK,
4159 RT5659_GP2_PIN_GPIO2 | RT5659_GP5_PIN_GPIO5 |
4160 RT5659_GP9_PIN_GPIO9 | RT5659_GP11_PIN_GPIO11 |
4161 RT5659_GP6_PIN_GPIO6 | RT5659_GP10_PIN_GPIO10 |
4162 RT5659_GP12_PIN_GPIO12);
4163 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4164 RT5659_DMIC_1_DP_MASK | RT5659_DMIC_2_DP_MASK,
4165 RT5659_DMIC_1_DP_IN2N | RT5659_DMIC_2_DP_IN2P);
4166 }
4167
4168 switch (rt5659->pdata.jd_src) {
4169 case RT5659_JD3:
4170 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880);
4171 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000);
4172 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800);
4173 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4174 RT5659_PWR_MB, RT5659_PWR_MB);
4175 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001);
4176 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040);
4177 break;
4178 case RT5659_JD_NULL:
4179 break;
4180 default:
4181 dev_warn(&i2c->dev, "Currently, support JD3 only\n");
4182 break;
4183 }
4184
4185 INIT_DELAYED_WORK(&rt5659->jack_detect_work, rt5659_jack_detect_work);
4186
4187 if (i2c->irq) {
4188 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4189 rt5659_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4190 | IRQF_ONESHOT, "rt5659", rt5659);
4191 if (ret)
4192 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4193
4194 /* Enable IRQ output for GPIO1 pin any way */
4195 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4196 RT5659_GP1_PIN_MASK, RT5659_GP1_PIN_IRQ);
4197 }
4198
4199 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5659,
4200 rt5659_dai, ARRAY_SIZE(rt5659_dai));
4201 }
4202
4203 static int rt5659_i2c_remove(struct i2c_client *i2c)
4204 {
4205 snd_soc_unregister_codec(&i2c->dev);
4206
4207 return 0;
4208 }
4209
4210 static void rt5659_i2c_shutdown(struct i2c_client *client)
4211 {
4212 struct rt5659_priv *rt5659 = i2c_get_clientdata(client);
4213
4214 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4215 }
4216
4217 #ifdef CONFIG_OF
4218 static const struct of_device_id rt5659_of_match[] = {
4219 { .compatible = "realtek,rt5658", },
4220 { .compatible = "realtek,rt5659", },
4221 { },
4222 };
4223 MODULE_DEVICE_TABLE(of, rt5659_of_match);
4224 #endif
4225
4226 #ifdef CONFIG_ACPI
4227 static const struct acpi_device_id rt5659_acpi_match[] = {
4228 { "10EC5658", 0, },
4229 { "10EC5659", 0, },
4230 { },
4231 };
4232 MODULE_DEVICE_TABLE(acpi, rt5659_acpi_match);
4233 #endif
4234
4235 static struct i2c_driver rt5659_i2c_driver = {
4236 .driver = {
4237 .name = "rt5659",
4238 .of_match_table = of_match_ptr(rt5659_of_match),
4239 .acpi_match_table = ACPI_PTR(rt5659_acpi_match),
4240 },
4241 .probe = rt5659_i2c_probe,
4242 .remove = rt5659_i2c_remove,
4243 .shutdown = rt5659_i2c_shutdown,
4244 .id_table = rt5659_i2c_id,
4245 };
4246 module_i2c_driver(rt5659_i2c_driver);
4247
4248 MODULE_DESCRIPTION("ASoC RT5659 driver");
4249 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4250 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support