sound/soc/intel/skylake/skl-tplg-interface.h

   1 /*
   2  * skl-tplg-interface.h - Intel DSP FW private data interface
   3  *
   4  * Copyright (C) 2015 Intel Corp
   5  * Author: Jeeja KP <jeeja.kp@intel.com>
   6  *          Nilofer, Samreen <samreen.nilofer@intel.com>
   7  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  */
  18
  19 #ifndef __HDA_TPLG_INTERFACE_H__
  20 #define __HDA_TPLG_INTERFACE_H__
  21
  22 /*
  23  * Default types range from 0~12. type can range from 0 to 0xff
  24  * SST types start at higher to avoid any overlapping in future
  25  */
  26 #define SKL_CONTROL_TYPE_BYTE_TLV       0x100
  27 #define SKL_CONTROL_TYPE_MIC_SELECT     0x102
  28
  29 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
  30 #define MAX_IN_QUEUE 8
  31 #define MAX_OUT_QUEUE 8
  32
  33 #define SKL_UUID_STR_SZ 40
  34 /* Event types goes here */
  35 /* Reserve event type 0 for no event handlers */
  36 enum skl_event_types {
  37         SKL_EVENT_NONE = 0,
  38         SKL_MIXER_EVENT,
  39         SKL_MUX_EVENT,
  40         SKL_VMIXER_EVENT,
  41         SKL_PGA_EVENT
  42 };
  43
  44 /**
  45  * enum skl_ch_cfg - channel configuration
  46  *
  47  * @SKL_CH_CFG_MONO:    One channel only
  48  * @SKL_CH_CFG_STEREO:  L & R
  49  * @SKL_CH_CFG_2_1:     L, R & LFE
  50  * @SKL_CH_CFG_3_0:     L, C & R
  51  * @SKL_CH_CFG_3_1:     L, C, R & LFE
  52  * @SKL_CH_CFG_QUATRO:  L, R, Ls & Rs
  53  * @SKL_CH_CFG_4_0:     L, C, R & Cs
  54  * @SKL_CH_CFG_5_0:     L, C, R, Ls & Rs
  55  * @SKL_CH_CFG_5_1:     L, C, R, Ls, Rs & LFE
  56  * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
  57  * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
  58  * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
  59  * @SKL_CH_CFG_INVALID: Invalid
  60  */
  61 enum skl_ch_cfg {
  62         SKL_CH_CFG_MONO = 0,
  63         SKL_CH_CFG_STEREO = 1,
  64         SKL_CH_CFG_2_1 = 2,
  65         SKL_CH_CFG_3_0 = 3,
  66         SKL_CH_CFG_3_1 = 4,
  67         SKL_CH_CFG_QUATRO = 5,
  68         SKL_CH_CFG_4_0 = 6,
  69         SKL_CH_CFG_5_0 = 7,
  70         SKL_CH_CFG_5_1 = 8,
  71         SKL_CH_CFG_DUAL_MONO = 9,
  72         SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
  73         SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
  74         SKL_CH_CFG_4_CHANNEL = 12,
  75         SKL_CH_CFG_INVALID
  76 };
  77
  78 enum skl_module_type {
  79         SKL_MODULE_TYPE_MIXER = 0,
  80         SKL_MODULE_TYPE_COPIER,
  81         SKL_MODULE_TYPE_UPDWMIX,
  82         SKL_MODULE_TYPE_SRCINT,
  83         SKL_MODULE_TYPE_ALGO,
  84         SKL_MODULE_TYPE_BASE_OUTFMT,
  85         SKL_MODULE_TYPE_KPB,
  86         SKL_MODULE_TYPE_MIC_SELECT,
  87 };
  88
  89 enum skl_core_affinity {
  90         SKL_AFFINITY_CORE_0 = 0,
  91         SKL_AFFINITY_CORE_1,
  92         SKL_AFFINITY_CORE_MAX
  93 };
  94
  95 enum skl_pipe_conn_type {
  96         SKL_PIPE_CONN_TYPE_NONE = 0,
  97         SKL_PIPE_CONN_TYPE_FE,
  98         SKL_PIPE_CONN_TYPE_BE
  99 };
 100
 101 enum skl_hw_conn_type {
 102         SKL_CONN_NONE = 0,
 103         SKL_CONN_SOURCE = 1,
 104         SKL_CONN_SINK = 2
 105 };
 106
 107 enum skl_dev_type {
 108         SKL_DEVICE_BT = 0x0,
 109         SKL_DEVICE_DMIC = 0x1,
 110         SKL_DEVICE_I2S = 0x2,
 111         SKL_DEVICE_SLIMBUS = 0x3,
 112         SKL_DEVICE_HDALINK = 0x4,
 113         SKL_DEVICE_HDAHOST = 0x5,
 114         SKL_DEVICE_NONE
 115 };
 116
 117 /**
 118  * enum skl_interleaving - interleaving style
 119  *
 120  * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
 121  * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
 122  */
 123 enum skl_interleaving {
 124         SKL_INTERLEAVING_PER_CHANNEL = 0,
 125         SKL_INTERLEAVING_PER_SAMPLE = 1,
 126 };
 127
 128 enum skl_sample_type {
 129         SKL_SAMPLE_TYPE_INT_MSB = 0,
 130         SKL_SAMPLE_TYPE_INT_LSB = 1,
 131         SKL_SAMPLE_TYPE_INT_SIGNED = 2,
 132         SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
 133         SKL_SAMPLE_TYPE_FLOAT = 4
 134 };
 135
 136 enum module_pin_type {
 137         /* All pins of the module takes same PCM inputs or outputs
 138         * e.g. mixout
 139         */
 140         SKL_PIN_TYPE_HOMOGENEOUS,
 141         /* All pins of the module takes different PCM inputs or outputs
 142         * e.g mux
 143         */
 144         SKL_PIN_TYPE_HETEROGENEOUS,
 145 };
 146
 147 enum skl_module_param_type {
 148         SKL_PARAM_DEFAULT = 0,
 149         SKL_PARAM_INIT,
 150         SKL_PARAM_SET,
 151         SKL_PARAM_BIND
 152 };
 153
 154 struct skl_dfw_algo_data {
 155         u32 set_params:2;
 156         u32 rsvd:30;
 157         u32 param_id;
 158         u32 max;
 159         char params[0];
 160 } __packed;
 161
 162 enum skl_tkn_dir {
 163         SKL_DIR_IN,
 164         SKL_DIR_OUT
 165 };
 166
 167 enum skl_tuple_type {
 168         SKL_TYPE_TUPLE,
 169         SKL_TYPE_DATA
 170 };
 171
 172 #endif