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ixgbevf: Fix checksum error when using stacked vlan
[linux/fpc-iii.git] / sound / soc / davinci / davinci-mcasp.c
blob30b94d4f9c5de369531713517adc2a9f1d3a46f7
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29
30 #include <sound/asoundef.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/initval.h>
35 #include <sound/soc.h>
36 #include <sound/dmaengine_pcm.h>
37 #include <sound/omap-pcm.h>
38
39 #include "davinci-pcm.h"
40 #include "edma-pcm.h"
41 #include "davinci-mcasp.h"
42
43 #define MCASP_MAX_AFIFO_DEPTH 64
44
45 static u32 context_regs[] = {
46 DAVINCI_MCASP_TXFMCTL_REG,
47 DAVINCI_MCASP_RXFMCTL_REG,
48 DAVINCI_MCASP_TXFMT_REG,
49 DAVINCI_MCASP_RXFMT_REG,
50 DAVINCI_MCASP_ACLKXCTL_REG,
51 DAVINCI_MCASP_ACLKRCTL_REG,
52 DAVINCI_MCASP_AHCLKXCTL_REG,
53 DAVINCI_MCASP_AHCLKRCTL_REG,
54 DAVINCI_MCASP_PDIR_REG,
55 DAVINCI_MCASP_RXMASK_REG,
56 DAVINCI_MCASP_TXMASK_REG,
57 DAVINCI_MCASP_RXTDM_REG,
58 DAVINCI_MCASP_TXTDM_REG,
59 };
60
61 struct davinci_mcasp_context {
62 u32 config_regs[ARRAY_SIZE(context_regs)];
63 u32 afifo_regs[2]; /* for read/write fifo control registers */
64 u32 *xrsr_regs; /* for serializer configuration */
65 };
66
67 struct davinci_mcasp {
68 struct davinci_pcm_dma_params dma_params[2];
69 struct snd_dmaengine_dai_dma_data dma_data[2];
70 void __iomem *base;
71 u32 fifo_base;
72 struct device *dev;
73 struct snd_pcm_substream *substreams[2];
74
75 /* McASP specific data */
76 int tdm_slots;
77 u8 op_mode;
78 u8 num_serializer;
79 u8 *serial_dir;
80 u8 version;
81 u8 bclk_div;
82 u16 bclk_lrclk_ratio;
83 int streams;
84 u32 irq_request[2];
85
86 int sysclk_freq;
87 bool bclk_master;
88
89 /* McASP FIFO related */
90 u8 txnumevt;
91 u8 rxnumevt;
92
93 bool dat_port;
94
95 /* Used for comstraint setting on the second stream */
96 u32 channels;
97
98 #ifdef CONFIG_PM_SLEEP
99 struct davinci_mcasp_context context;
100 #endif
101 };
102
103 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
104 u32 val)
105 {
106 void __iomem *reg = mcasp->base + offset;
107 __raw_writel(__raw_readl(reg) | val, reg);
108 }
109
110 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
111 u32 val)
112 {
113 void __iomem *reg = mcasp->base + offset;
114 __raw_writel((__raw_readl(reg) & ~(val)), reg);
115 }
116
117 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
118 u32 val, u32 mask)
119 {
120 void __iomem *reg = mcasp->base + offset;
121 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
122 }
123
124 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
125 u32 val)
126 {
127 __raw_writel(val, mcasp->base + offset);
128 }
129
130 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
131 {
132 return (u32)__raw_readl(mcasp->base + offset);
133 }
134
135 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
136 {
137 int i = 0;
138
139 mcasp_set_bits(mcasp, ctl_reg, val);
140
141 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
142 /* loop count is to avoid the lock-up */
143 for (i = 0; i < 1000; i++) {
144 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
145 break;
146 }
147
148 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
149 printk(KERN_ERR "GBLCTL write error\n");
150 }
151
152 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
153 {
154 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
155 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
156
157 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
158 }
159
160 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
161 {
162 if (mcasp->rxnumevt) { /* enable FIFO */
163 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
164
165 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
166 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
167 }
168
169 /* Start clocks */
170 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
172 /*
173 * When ASYNC == 0 the transmit and receive sections operate
174 * synchronously from the transmit clock and frame sync. We need to make
175 * sure that the TX signlas are enabled when starting reception.
176 */
177 if (mcasp_is_synchronous(mcasp)) {
178 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
180 }
181
182 /* Activate serializer(s) */
183 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
184 /* Release RX state machine */
185 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
186 /* Release Frame Sync generator */
187 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
188 if (mcasp_is_synchronous(mcasp))
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
190
191 /* enable receive IRQs */
192 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
193 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
194 }
195
196 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
197 {
198 u32 cnt;
199
200 if (mcasp->txnumevt) { /* enable FIFO */
201 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
202
203 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
204 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
205 }
206
207 /* Start clocks */
208 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
209 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
210 /* Activate serializer(s) */
211 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
212
213 /* wait for XDATA to be cleared */
214 cnt = 0;
215 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
216 ~XRDATA) && (cnt < 100000))
217 cnt++;
218
219 /* Release TX state machine */
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
221 /* Release Frame Sync generator */
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
223
224 /* enable transmit IRQs */
225 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
226 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
227 }
228
229 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
230 {
231 mcasp->streams++;
232
233 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
234 mcasp_start_tx(mcasp);
235 else
236 mcasp_start_rx(mcasp);
237 }
238
239 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
240 {
241 /* disable IRQ sources */
242 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
243 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
244
245 /*
246 * In synchronous mode stop the TX clocks if no other stream is
247 * running
248 */
249 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
250 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
251
252 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
253 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
254
255 if (mcasp->rxnumevt) { /* disable FIFO */
256 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
257
258 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
259 }
260 }
261
262 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
263 {
264 u32 val = 0;
265
266 /* disable IRQ sources */
267 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
268 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
269
270 /*
271 * In synchronous mode keep TX clocks running if the capture stream is
272 * still running.
273 */
274 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
275 val = TXHCLKRST | TXCLKRST | TXFSRST;
276
277 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
278 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
279
280 if (mcasp->txnumevt) { /* disable FIFO */
281 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
282
283 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
284 }
285 }
286
287 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
288 {
289 mcasp->streams--;
290
291 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
292 mcasp_stop_tx(mcasp);
293 else
294 mcasp_stop_rx(mcasp);
295 }
296
297 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
298 {
299 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
300 struct snd_pcm_substream *substream;
301 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
302 u32 handled_mask = 0;
303 u32 stat;
304
305 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
306 if (stat & XUNDRN & irq_mask) {
307 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
308 handled_mask |= XUNDRN;
309
310 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
311 if (substream) {
312 snd_pcm_stream_lock_irq(substream);
313 if (snd_pcm_running(substream))
314 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
315 snd_pcm_stream_unlock_irq(substream);
316 }
317 }
318
319 if (!handled_mask)
320 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
321 stat);
322
323 if (stat & XRERR)
324 handled_mask |= XRERR;
325
326 /* Ack the handled event only */
327 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
328
329 return IRQ_RETVAL(handled_mask);
330 }
331
332 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
333 {
334 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
335 struct snd_pcm_substream *substream;
336 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
337 u32 handled_mask = 0;
338 u32 stat;
339
340 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
341 if (stat & ROVRN & irq_mask) {
342 dev_warn(mcasp->dev, "Receive buffer overflow\n");
343 handled_mask |= ROVRN;
344
345 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
346 if (substream) {
347 snd_pcm_stream_lock_irq(substream);
348 if (snd_pcm_running(substream))
349 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
350 snd_pcm_stream_unlock_irq(substream);
351 }
352 }
353
354 if (!handled_mask)
355 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
356 stat);
357
358 if (stat & XRERR)
359 handled_mask |= XRERR;
360
361 /* Ack the handled event only */
362 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
363
364 return IRQ_RETVAL(handled_mask);
365 }
366
367 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
368 unsigned int fmt)
369 {
370 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
371 int ret = 0;
372 u32 data_delay;
373 bool fs_pol_rising;
374 bool inv_fs = false;
375
376 pm_runtime_get_sync(mcasp->dev);
377 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
378 case SND_SOC_DAIFMT_DSP_A:
379 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
380 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
381 /* 1st data bit occur one ACLK cycle after the frame sync */
382 data_delay = 1;
383 break;
384 case SND_SOC_DAIFMT_DSP_B:
385 case SND_SOC_DAIFMT_AC97:
386 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
387 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
388 /* No delay after FS */
389 data_delay = 0;
390 break;
391 case SND_SOC_DAIFMT_I2S:
392 /* configure a full-word SYNC pulse (LRCLK) */
393 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
394 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
395 /* 1st data bit occur one ACLK cycle after the frame sync */
396 data_delay = 1;
397 /* FS need to be inverted */
398 inv_fs = true;
399 break;
400 case SND_SOC_DAIFMT_LEFT_J:
401 /* configure a full-word SYNC pulse (LRCLK) */
402 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
403 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
404 /* No delay after FS */
405 data_delay = 0;
406 break;
407 default:
408 ret = -EINVAL;
409 goto out;
410 }
411
412 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
413 FSXDLY(3));
414 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
415 FSRDLY(3));
416
417 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
418 case SND_SOC_DAIFMT_CBS_CFS:
419 /* codec is clock and frame slave */
420 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
421 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
422
423 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
425
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
427 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
428 mcasp->bclk_master = 1;
429 break;
430 case SND_SOC_DAIFMT_CBM_CFS:
431 /* codec is clock master and frame slave */
432 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
433 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
434
435 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
436 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
437
438 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
439 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
440 mcasp->bclk_master = 0;
441 break;
442 case SND_SOC_DAIFMT_CBM_CFM:
443 /* codec is clock and frame master */
444 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
445 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
446
447 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
449
450 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
451 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
452 mcasp->bclk_master = 0;
453 break;
454 default:
455 ret = -EINVAL;
456 goto out;
457 }
458
459 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
460 case SND_SOC_DAIFMT_IB_NF:
461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
463 fs_pol_rising = true;
464 break;
465 case SND_SOC_DAIFMT_NB_IF:
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
467 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
468 fs_pol_rising = false;
469 break;
470 case SND_SOC_DAIFMT_IB_IF:
471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
472 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
473 fs_pol_rising = false;
474 break;
475 case SND_SOC_DAIFMT_NB_NF:
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
477 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
478 fs_pol_rising = true;
479 break;
480 default:
481 ret = -EINVAL;
482 goto out;
483 }
484
485 if (inv_fs)
486 fs_pol_rising = !fs_pol_rising;
487
488 if (fs_pol_rising) {
489 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
491 } else {
492 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
494 }
495 out:
496 pm_runtime_put_sync(mcasp->dev);
497 return ret;
498 }
499
500 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
501 int div, bool explicit)
502 {
503 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
504
505 switch (div_id) {
506 case 0: /* MCLK divider */
507 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
508 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
509 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
510 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
511 break;
512
513 case 1: /* BCLK divider */
514 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
515 ACLKXDIV(div - 1), ACLKXDIV_MASK);
516 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
517 ACLKRDIV(div - 1), ACLKRDIV_MASK);
518 if (explicit)
519 mcasp->bclk_div = div;
520 break;
521
522 case 2: /* BCLK/LRCLK ratio */
523 mcasp->bclk_lrclk_ratio = div;
524 break;
525
526 default:
527 return -EINVAL;
528 }
529
530 return 0;
531 }
532
533 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
534 int div)
535 {
536 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
537 }
538
539 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
540 unsigned int freq, int dir)
541 {
542 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
543
544 if (dir == SND_SOC_CLOCK_OUT) {
545 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
546 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
547 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
548 } else {
549 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
551 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
552 }
553
554 mcasp->sysclk_freq = freq;
555
556 return 0;
557 }
558
559 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
560 int word_length)
561 {
562 u32 fmt;
563 u32 tx_rotate = (word_length / 4) & 0x7;
564 u32 mask = (1ULL << word_length) - 1;
565 /*
566 * For captured data we should not rotate, inversion and masking is
567 * enoguh to get the data to the right position:
568 * Format data from bus after reverse (XRBUF)
569 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
570 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
571 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
572 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
573 */
574 u32 rx_rotate = 0;
575
576 /*
577 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
578 * callback, take it into account here. That allows us to for example
579 * send 32 bits per channel to the codec, while only 16 of them carry
580 * audio payload.
581 * The clock ratio is given for a full period of data (for I2S format
582 * both left and right channels), so it has to be divided by number of
583 * tdm-slots (for I2S - divided by 2).
584 */
585 if (mcasp->bclk_lrclk_ratio) {
586 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
587
588 /*
589 * When we have more bclk then it is needed for the data, we
590 * need to use the rotation to move the received samples to have
591 * correct alignment.
592 */
593 rx_rotate = (slot_length - word_length) / 4;
594 word_length = slot_length;
595 }
596
597 /* mapping of the XSSZ bit-field as described in the datasheet */
598 fmt = (word_length >> 1) - 1;
599
600 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
601 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
602 RXSSZ(0x0F));
603 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
604 TXSSZ(0x0F));
605 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
606 TXROT(7));
607 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
608 RXROT(7));
609 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
610 }
611
612 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
613
614 return 0;
615 }
616
617 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
618 int period_words, int channels)
619 {
620 struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
621 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
622 int i;
623 u8 tx_ser = 0;
624 u8 rx_ser = 0;
625 u8 slots = mcasp->tdm_slots;
626 u8 max_active_serializers = (channels + slots - 1) / slots;
627 int active_serializers, numevt, n;
628 u32 reg;
629 /* Default configuration */
630 if (mcasp->version < MCASP_VERSION_3)
631 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
632
633 /* All PINS as McASP */
634 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
635
636 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
637 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
638 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
639 } else {
640 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
641 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
642 }
643
644 for (i = 0; i < mcasp->num_serializer; i++) {
645 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
646 mcasp->serial_dir[i]);
647 if (mcasp->serial_dir[i] == TX_MODE &&
648 tx_ser < max_active_serializers) {
649 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
650 tx_ser++;
651 } else if (mcasp->serial_dir[i] == RX_MODE &&
652 rx_ser < max_active_serializers) {
653 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
654 rx_ser++;
655 } else {
656 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
657 SRMOD_INACTIVE, SRMOD_MASK);
658 }
659 }
660
661 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
662 active_serializers = tx_ser;
663 numevt = mcasp->txnumevt;
664 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
665 } else {
666 active_serializers = rx_ser;
667 numevt = mcasp->rxnumevt;
668 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
669 }
670
671 if (active_serializers < max_active_serializers) {
672 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
673 "enabled in mcasp (%d)\n", channels,
674 active_serializers * slots);
675 return -EINVAL;
676 }
677
678 /* AFIFO is not in use */
679 if (!numevt) {
680 /* Configure the burst size for platform drivers */
681 if (active_serializers > 1) {
682 /*
683 * If more than one serializers are in use we have one
684 * DMA request to provide data for all serializers.
685 * For example if three serializers are enabled the DMA
686 * need to transfer three words per DMA request.
687 */
688 dma_params->fifo_level = active_serializers;
689 dma_data->maxburst = active_serializers;
690 } else {
691 dma_params->fifo_level = 0;
692 dma_data->maxburst = 0;
693 }
694 return 0;
695 }
696
697 if (period_words % active_serializers) {
698 dev_err(mcasp->dev, "Invalid combination of period words and "
699 "active serializers: %d, %d\n", period_words,
700 active_serializers);
701 return -EINVAL;
702 }
703
704 /*
705 * Calculate the optimal AFIFO depth for platform side:
706 * The number of words for numevt need to be in steps of active
707 * serializers.
708 */
709 n = numevt % active_serializers;
710 if (n)
711 numevt += (active_serializers - n);
712 while (period_words % numevt && numevt > 0)
713 numevt -= active_serializers;
714 if (numevt <= 0)
715 numevt = active_serializers;
716
717 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
718 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
719
720 /* Configure the burst size for platform drivers */
721 if (numevt == 1)
722 numevt = 0;
723 dma_params->fifo_level = numevt;
724 dma_data->maxburst = numevt;
725
726 return 0;
727 }
728
729 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
730 int channels)
731 {
732 int i, active_slots;
733 int total_slots;
734 int active_serializers;
735 u32 mask = 0;
736 u32 busel = 0;
737
738 total_slots = mcasp->tdm_slots;
739
740 /*
741 * If more than one serializer is needed, then use them with
742 * their specified tdm_slots count. Otherwise, one serializer
743 * can cope with the transaction using as many slots as channels
744 * in the stream, requires channels symmetry
745 */
746 active_serializers = (channels + total_slots - 1) / total_slots;
747 if (active_serializers == 1)
748 active_slots = channels;
749 else
750 active_slots = total_slots;
751
752 for (i = 0; i < active_slots; i++)
753 mask |= (1 << i);
754
755 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
756
757 if (!mcasp->dat_port)
758 busel = TXSEL;
759
760 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
761 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
762 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
763 FSXMOD(total_slots), FSXMOD(0x1FF));
764
765 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
766 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
767 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
768 FSRMOD(total_slots), FSRMOD(0x1FF));
769
770 return 0;
771 }
772
773 /* S/PDIF */
774 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
775 unsigned int rate)
776 {
777 u32 cs_value = 0;
778 u8 *cs_bytes = (u8*) &cs_value;
779
780 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
781 and LSB first */
782 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
783
784 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
785 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
786
787 /* Set the TX tdm : for all the slots */
788 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
789
790 /* Set the TX clock controls : div = 1 and internal */
791 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
792
793 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
794
795 /* Only 44100 and 48000 are valid, both have the same setting */
796 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
797
798 /* Enable the DIT */
799 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
800
801 /* Set S/PDIF channel status bits */
802 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
803 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
804
805 switch (rate) {
806 case 22050:
807 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
808 break;
809 case 24000:
810 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
811 break;
812 case 32000:
813 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
814 break;
815 case 44100:
816 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
817 break;
818 case 48000:
819 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
820 break;
821 case 88200:
822 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
823 break;
824 case 96000:
825 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
826 break;
827 case 176400:
828 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
829 break;
830 case 192000:
831 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
832 break;
833 default:
834 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
835 return -EINVAL;
836 }
837
838 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
839 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
840
841 return 0;
842 }
843
844 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
845 struct snd_pcm_hw_params *params,
846 struct snd_soc_dai *cpu_dai)
847 {
848 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
849 struct davinci_pcm_dma_params *dma_params =
850 &mcasp->dma_params[substream->stream];
851 int word_length;
852 int channels = params_channels(params);
853 int period_size = params_period_size(params);
854 int ret;
855
856 /*
857 * If mcasp is BCLK master, and a BCLK divider was not provided by
858 * the machine driver, we need to calculate the ratio.
859 */
860 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
861 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
862 unsigned int div = mcasp->sysclk_freq / bclk_freq;
863 if (mcasp->sysclk_freq % bclk_freq != 0) {
864 if (((mcasp->sysclk_freq / div) - bclk_freq) >
865 (bclk_freq - (mcasp->sysclk_freq / (div+1))))
866 div++;
867 dev_warn(mcasp->dev,
868 "Inaccurate BCLK: %u Hz / %u != %u Hz\n",
869 mcasp->sysclk_freq, div, bclk_freq);
870 }
871 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
872 }
873
874 ret = mcasp_common_hw_param(mcasp, substream->stream,
875 period_size * channels, channels);
876 if (ret)
877 return ret;
878
879 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
880 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
881 else
882 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
883 channels);
884
885 if (ret)
886 return ret;
887
888 switch (params_format(params)) {
889 case SNDRV_PCM_FORMAT_U8:
890 case SNDRV_PCM_FORMAT_S8:
891 dma_params->data_type = 1;
892 word_length = 8;
893 break;
894
895 case SNDRV_PCM_FORMAT_U16_LE:
896 case SNDRV_PCM_FORMAT_S16_LE:
897 dma_params->data_type = 2;
898 word_length = 16;
899 break;
900
901 case SNDRV_PCM_FORMAT_U24_3LE:
902 case SNDRV_PCM_FORMAT_S24_3LE:
903 dma_params->data_type = 3;
904 word_length = 24;
905 break;
906
907 case SNDRV_PCM_FORMAT_U24_LE:
908 case SNDRV_PCM_FORMAT_S24_LE:
909 dma_params->data_type = 4;
910 word_length = 24;
911 break;
912
913 case SNDRV_PCM_FORMAT_U32_LE:
914 case SNDRV_PCM_FORMAT_S32_LE:
915 dma_params->data_type = 4;
916 word_length = 32;
917 break;
918
919 default:
920 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
921 return -EINVAL;
922 }
923
924 if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
925 dma_params->acnt = 4;
926 else
927 dma_params->acnt = dma_params->data_type;
928
929 davinci_config_channel_size(mcasp, word_length);
930
931 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
932 mcasp->channels = channels;
933
934 return 0;
935 }
936
937 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
938 int cmd, struct snd_soc_dai *cpu_dai)
939 {
940 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
941 int ret = 0;
942
943 switch (cmd) {
944 case SNDRV_PCM_TRIGGER_RESUME:
945 case SNDRV_PCM_TRIGGER_START:
946 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
947 davinci_mcasp_start(mcasp, substream->stream);
948 break;
949 case SNDRV_PCM_TRIGGER_SUSPEND:
950 case SNDRV_PCM_TRIGGER_STOP:
951 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
952 davinci_mcasp_stop(mcasp, substream->stream);
953 break;
954
955 default:
956 ret = -EINVAL;
957 }
958
959 return ret;
960 }
961
962 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
963 struct snd_soc_dai *cpu_dai)
964 {
965 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
966 u32 max_channels = 0;
967 int i, dir;
968
969 mcasp->substreams[substream->stream] = substream;
970
971 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
972 return 0;
973
974 /*
975 * Limit the maximum allowed channels for the first stream:
976 * number of serializers for the direction * tdm slots per serializer
977 */
978 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
979 dir = TX_MODE;
980 else
981 dir = RX_MODE;
982
983 for (i = 0; i < mcasp->num_serializer; i++) {
984 if (mcasp->serial_dir[i] == dir)
985 max_channels++;
986 }
987 max_channels *= mcasp->tdm_slots;
988 /*
989 * If the already active stream has less channels than the calculated
990 * limnit based on the seirializers * tdm_slots, we need to use that as
991 * a constraint for the second stream.
992 * Otherwise (first stream or less allowed channels) we use the
993 * calculated constraint.
994 */
995 if (mcasp->channels && mcasp->channels < max_channels)
996 max_channels = mcasp->channels;
997
998 snd_pcm_hw_constraint_minmax(substream->runtime,
999 SNDRV_PCM_HW_PARAM_CHANNELS,
1000 2, max_channels);
1001 return 0;
1002 }
1003
1004 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1005 struct snd_soc_dai *cpu_dai)
1006 {
1007 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1008
1009 mcasp->substreams[substream->stream] = NULL;
1010
1011 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1012 return;
1013
1014 if (!cpu_dai->active)
1015 mcasp->channels = 0;
1016 }
1017
1018 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1019 .startup = davinci_mcasp_startup,
1020 .shutdown = davinci_mcasp_shutdown,
1021 .trigger = davinci_mcasp_trigger,
1022 .hw_params = davinci_mcasp_hw_params,
1023 .set_fmt = davinci_mcasp_set_dai_fmt,
1024 .set_clkdiv = davinci_mcasp_set_clkdiv,
1025 .set_sysclk = davinci_mcasp_set_sysclk,
1026 };
1027
1028 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1029 {
1030 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1031
1032 if (mcasp->version >= MCASP_VERSION_3) {
1033 /* Using dmaengine PCM */
1034 dai->playback_dma_data =
1035 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1036 dai->capture_dma_data =
1037 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1038 } else {
1039 /* Using davinci-pcm */
1040 dai->playback_dma_data = mcasp->dma_params;
1041 dai->capture_dma_data = mcasp->dma_params;
1042 }
1043
1044 return 0;
1045 }
1046
1047 #ifdef CONFIG_PM_SLEEP
1048 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1049 {
1050 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1051 struct davinci_mcasp_context *context = &mcasp->context;
1052 u32 reg;
1053 int i;
1054
1055 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1056 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1057
1058 if (mcasp->txnumevt) {
1059 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1060 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1061 }
1062 if (mcasp->rxnumevt) {
1063 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1064 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1065 }
1066
1067 for (i = 0; i < mcasp->num_serializer; i++)
1068 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1069 DAVINCI_MCASP_XRSRCTL_REG(i));
1070
1071 return 0;
1072 }
1073
1074 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1075 {
1076 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1077 struct davinci_mcasp_context *context = &mcasp->context;
1078 u32 reg;
1079 int i;
1080
1081 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1082 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1083
1084 if (mcasp->txnumevt) {
1085 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1086 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1087 }
1088 if (mcasp->rxnumevt) {
1089 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1090 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1091 }
1092
1093 for (i = 0; i < mcasp->num_serializer; i++)
1094 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1095 context->xrsr_regs[i]);
1096
1097 return 0;
1098 }
1099 #else
1100 #define davinci_mcasp_suspend NULL
1101 #define davinci_mcasp_resume NULL
1102 #endif
1103
1104 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1105
1106 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1107 SNDRV_PCM_FMTBIT_U8 | \
1108 SNDRV_PCM_FMTBIT_S16_LE | \
1109 SNDRV_PCM_FMTBIT_U16_LE | \
1110 SNDRV_PCM_FMTBIT_S24_LE | \
1111 SNDRV_PCM_FMTBIT_U24_LE | \
1112 SNDRV_PCM_FMTBIT_S24_3LE | \
1113 SNDRV_PCM_FMTBIT_U24_3LE | \
1114 SNDRV_PCM_FMTBIT_S32_LE | \
1115 SNDRV_PCM_FMTBIT_U32_LE)
1116
1117 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1118 {
1119 .name = "davinci-mcasp.0",
1120 .probe = davinci_mcasp_dai_probe,
1121 .suspend = davinci_mcasp_suspend,
1122 .resume = davinci_mcasp_resume,
1123 .playback = {
1124 .channels_min = 2,
1125 .channels_max = 32 * 16,
1126 .rates = DAVINCI_MCASP_RATES,
1127 .formats = DAVINCI_MCASP_PCM_FMTS,
1128 },
1129 .capture = {
1130 .channels_min = 2,
1131 .channels_max = 32 * 16,
1132 .rates = DAVINCI_MCASP_RATES,
1133 .formats = DAVINCI_MCASP_PCM_FMTS,
1134 },
1135 .ops = &davinci_mcasp_dai_ops,
1136
1137 .symmetric_samplebits = 1,
1138 },
1139 {
1140 .name = "davinci-mcasp.1",
1141 .probe = davinci_mcasp_dai_probe,
1142 .playback = {
1143 .channels_min = 1,
1144 .channels_max = 384,
1145 .rates = DAVINCI_MCASP_RATES,
1146 .formats = DAVINCI_MCASP_PCM_FMTS,
1147 },
1148 .ops = &davinci_mcasp_dai_ops,
1149 },
1150
1151 };
1152
1153 static const struct snd_soc_component_driver davinci_mcasp_component = {
1154 .name = "davinci-mcasp",
1155 };
1156
1157 /* Some HW specific values and defaults. The rest is filled in from DT. */
1158 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1159 .tx_dma_offset = 0x400,
1160 .rx_dma_offset = 0x400,
1161 .asp_chan_q = EVENTQ_0,
1162 .version = MCASP_VERSION_1,
1163 };
1164
1165 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1166 .tx_dma_offset = 0x2000,
1167 .rx_dma_offset = 0x2000,
1168 .asp_chan_q = EVENTQ_0,
1169 .version = MCASP_VERSION_2,
1170 };
1171
1172 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1173 .tx_dma_offset = 0,
1174 .rx_dma_offset = 0,
1175 .asp_chan_q = EVENTQ_0,
1176 .version = MCASP_VERSION_3,
1177 };
1178
1179 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1180 .tx_dma_offset = 0x200,
1181 .rx_dma_offset = 0x284,
1182 .asp_chan_q = EVENTQ_0,
1183 .version = MCASP_VERSION_4,
1184 };
1185
1186 static const struct of_device_id mcasp_dt_ids[] = {
1187 {
1188 .compatible = "ti,dm646x-mcasp-audio",
1189 .data = &dm646x_mcasp_pdata,
1190 },
1191 {
1192 .compatible = "ti,da830-mcasp-audio",
1193 .data = &da830_mcasp_pdata,
1194 },
1195 {
1196 .compatible = "ti,am33xx-mcasp-audio",
1197 .data = &am33xx_mcasp_pdata,
1198 },
1199 {
1200 .compatible = "ti,dra7-mcasp-audio",
1201 .data = &dra7_mcasp_pdata,
1202 },
1203 { /* sentinel */ }
1204 };
1205 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1206
1207 static int mcasp_reparent_fck(struct platform_device *pdev)
1208 {
1209 struct device_node *node = pdev->dev.of_node;
1210 struct clk *gfclk, *parent_clk;
1211 const char *parent_name;
1212 int ret;
1213
1214 if (!node)
1215 return 0;
1216
1217 parent_name = of_get_property(node, "fck_parent", NULL);
1218 if (!parent_name)
1219 return 0;
1220
1221 gfclk = clk_get(&pdev->dev, "fck");
1222 if (IS_ERR(gfclk)) {
1223 dev_err(&pdev->dev, "failed to get fck\n");
1224 return PTR_ERR(gfclk);
1225 }
1226
1227 parent_clk = clk_get(NULL, parent_name);
1228 if (IS_ERR(parent_clk)) {
1229 dev_err(&pdev->dev, "failed to get parent clock\n");
1230 ret = PTR_ERR(parent_clk);
1231 goto err1;
1232 }
1233
1234 ret = clk_set_parent(gfclk, parent_clk);
1235 if (ret) {
1236 dev_err(&pdev->dev, "failed to reparent fck\n");
1237 goto err2;
1238 }
1239
1240 err2:
1241 clk_put(parent_clk);
1242 err1:
1243 clk_put(gfclk);
1244 return ret;
1245 }
1246
1247 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1248 struct platform_device *pdev)
1249 {
1250 struct device_node *np = pdev->dev.of_node;
1251 struct davinci_mcasp_pdata *pdata = NULL;
1252 const struct of_device_id *match =
1253 of_match_device(mcasp_dt_ids, &pdev->dev);
1254 struct of_phandle_args dma_spec;
1255
1256 const u32 *of_serial_dir32;
1257 u32 val;
1258 int i, ret = 0;
1259
1260 if (pdev->dev.platform_data) {
1261 pdata = pdev->dev.platform_data;
1262 return pdata;
1263 } else if (match) {
1264 pdata = (struct davinci_mcasp_pdata*) match->data;
1265 } else {
1266 /* control shouldn't reach here. something is wrong */
1267 ret = -EINVAL;
1268 goto nodata;
1269 }
1270
1271 ret = of_property_read_u32(np, "op-mode", &val);
1272 if (ret >= 0)
1273 pdata->op_mode = val;
1274
1275 ret = of_property_read_u32(np, "tdm-slots", &val);
1276 if (ret >= 0) {
1277 if (val < 2 || val > 32) {
1278 dev_err(&pdev->dev,
1279 "tdm-slots must be in rage [2-32]\n");
1280 ret = -EINVAL;
1281 goto nodata;
1282 }
1283
1284 pdata->tdm_slots = val;
1285 }
1286
1287 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1288 val /= sizeof(u32);
1289 if (of_serial_dir32) {
1290 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1291 (sizeof(*of_serial_dir) * val),
1292 GFP_KERNEL);
1293 if (!of_serial_dir) {
1294 ret = -ENOMEM;
1295 goto nodata;
1296 }
1297
1298 for (i = 0; i < val; i++)
1299 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1300
1301 pdata->num_serializer = val;
1302 pdata->serial_dir = of_serial_dir;
1303 }
1304
1305 ret = of_property_match_string(np, "dma-names", "tx");
1306 if (ret < 0)
1307 goto nodata;
1308
1309 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1310 &dma_spec);
1311 if (ret < 0)
1312 goto nodata;
1313
1314 pdata->tx_dma_channel = dma_spec.args[0];
1315
1316 ret = of_property_match_string(np, "dma-names", "rx");
1317 if (ret < 0)
1318 goto nodata;
1319
1320 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1321 &dma_spec);
1322 if (ret < 0)
1323 goto nodata;
1324
1325 pdata->rx_dma_channel = dma_spec.args[0];
1326
1327 ret = of_property_read_u32(np, "tx-num-evt", &val);
1328 if (ret >= 0)
1329 pdata->txnumevt = val;
1330
1331 ret = of_property_read_u32(np, "rx-num-evt", &val);
1332 if (ret >= 0)
1333 pdata->rxnumevt = val;
1334
1335 ret = of_property_read_u32(np, "sram-size-playback", &val);
1336 if (ret >= 0)
1337 pdata->sram_size_playback = val;
1338
1339 ret = of_property_read_u32(np, "sram-size-capture", &val);
1340 if (ret >= 0)
1341 pdata->sram_size_capture = val;
1342
1343 return pdata;
1344
1345 nodata:
1346 if (ret < 0) {
1347 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1348 ret);
1349 pdata = NULL;
1350 }
1351 return pdata;
1352 }
1353
1354 static int davinci_mcasp_probe(struct platform_device *pdev)
1355 {
1356 struct davinci_pcm_dma_params *dma_params;
1357 struct snd_dmaengine_dai_dma_data *dma_data;
1358 struct resource *mem, *ioarea, *res, *dat;
1359 struct davinci_mcasp_pdata *pdata;
1360 struct davinci_mcasp *mcasp;
1361 char *irq_name;
1362 int irq;
1363 int ret;
1364
1365 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1366 dev_err(&pdev->dev, "No platform data supplied\n");
1367 return -EINVAL;
1368 }
1369
1370 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1371 GFP_KERNEL);
1372 if (!mcasp)
1373 return -ENOMEM;
1374
1375 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1376 if (!pdata) {
1377 dev_err(&pdev->dev, "no platform data\n");
1378 return -EINVAL;
1379 }
1380
1381 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1382 if (!mem) {
1383 dev_warn(mcasp->dev,
1384 "\"mpu\" mem resource not found, using index 0\n");
1385 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 if (!mem) {
1387 dev_err(&pdev->dev, "no mem resource?\n");
1388 return -ENODEV;
1389 }
1390 }
1391
1392 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1393 resource_size(mem), pdev->name);
1394 if (!ioarea) {
1395 dev_err(&pdev->dev, "Audio region already claimed\n");
1396 return -EBUSY;
1397 }
1398
1399 pm_runtime_enable(&pdev->dev);
1400
1401 ret = pm_runtime_get_sync(&pdev->dev);
1402 if (IS_ERR_VALUE(ret)) {
1403 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1404 pm_runtime_disable(&pdev->dev);
1405 return ret;
1406 }
1407
1408 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1409 if (!mcasp->base) {
1410 dev_err(&pdev->dev, "ioremap failed\n");
1411 ret = -ENOMEM;
1412 goto err;
1413 }
1414
1415 mcasp->op_mode = pdata->op_mode;
1416 /* sanity check for tdm slots parameter */
1417 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1418 if (pdata->tdm_slots < 2) {
1419 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1420 pdata->tdm_slots);
1421 mcasp->tdm_slots = 2;
1422 } else if (pdata->tdm_slots > 32) {
1423 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1424 pdata->tdm_slots);
1425 mcasp->tdm_slots = 32;
1426 } else {
1427 mcasp->tdm_slots = pdata->tdm_slots;
1428 }
1429 }
1430
1431 mcasp->num_serializer = pdata->num_serializer;
1432 #ifdef CONFIG_PM_SLEEP
1433 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1434 sizeof(u32) * mcasp->num_serializer,
1435 GFP_KERNEL);
1436 #endif
1437 mcasp->serial_dir = pdata->serial_dir;
1438 mcasp->version = pdata->version;
1439 mcasp->txnumevt = pdata->txnumevt;
1440 mcasp->rxnumevt = pdata->rxnumevt;
1441
1442 mcasp->dev = &pdev->dev;
1443
1444 irq = platform_get_irq_byname(pdev, "rx");
1445 if (irq >= 0) {
1446 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
1447 dev_name(&pdev->dev));
1448 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1449 davinci_mcasp_rx_irq_handler,
1450 IRQF_ONESHOT, irq_name, mcasp);
1451 if (ret) {
1452 dev_err(&pdev->dev, "RX IRQ request failed\n");
1453 goto err;
1454 }
1455
1456 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1457 }
1458
1459 irq = platform_get_irq_byname(pdev, "tx");
1460 if (irq >= 0) {
1461 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
1462 dev_name(&pdev->dev));
1463 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1464 davinci_mcasp_tx_irq_handler,
1465 IRQF_ONESHOT, irq_name, mcasp);
1466 if (ret) {
1467 dev_err(&pdev->dev, "TX IRQ request failed\n");
1468 goto err;
1469 }
1470
1471 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1472 }
1473
1474 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1475 if (dat)
1476 mcasp->dat_port = true;
1477
1478 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1479 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1480 dma_params->asp_chan_q = pdata->asp_chan_q;
1481 dma_params->ram_chan_q = pdata->ram_chan_q;
1482 dma_params->sram_pool = pdata->sram_pool;
1483 dma_params->sram_size = pdata->sram_size_playback;
1484 if (dat)
1485 dma_params->dma_addr = dat->start;
1486 else
1487 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1488
1489 /* Unconditional dmaengine stuff */
1490 dma_data->addr = dma_params->dma_addr;
1491
1492 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1493 if (res)
1494 dma_params->channel = res->start;
1495 else
1496 dma_params->channel = pdata->tx_dma_channel;
1497
1498 /* dmaengine filter data for DT and non-DT boot */
1499 if (pdev->dev.of_node)
1500 dma_data->filter_data = "tx";
1501 else
1502 dma_data->filter_data = &dma_params->channel;
1503
1504 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1505 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1506 dma_params->asp_chan_q = pdata->asp_chan_q;
1507 dma_params->ram_chan_q = pdata->ram_chan_q;
1508 dma_params->sram_pool = pdata->sram_pool;
1509 dma_params->sram_size = pdata->sram_size_capture;
1510 if (dat)
1511 dma_params->dma_addr = dat->start;
1512 else
1513 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1514
1515 /* Unconditional dmaengine stuff */
1516 dma_data->addr = dma_params->dma_addr;
1517
1518 if (mcasp->version < MCASP_VERSION_3) {
1519 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1520 /* dma_params->dma_addr is pointing to the data port address */
1521 mcasp->dat_port = true;
1522 } else {
1523 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1524 }
1525
1526 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1527 if (res)
1528 dma_params->channel = res->start;
1529 else
1530 dma_params->channel = pdata->rx_dma_channel;
1531
1532 /* dmaengine filter data for DT and non-DT boot */
1533 if (pdev->dev.of_node)
1534 dma_data->filter_data = "rx";
1535 else
1536 dma_data->filter_data = &dma_params->channel;
1537
1538 dev_set_drvdata(&pdev->dev, mcasp);
1539
1540 mcasp_reparent_fck(pdev);
1541
1542 ret = devm_snd_soc_register_component(&pdev->dev,
1543 &davinci_mcasp_component,
1544 &davinci_mcasp_dai[pdata->op_mode], 1);
1545
1546 if (ret != 0)
1547 goto err;
1548
1549 switch (mcasp->version) {
1550 #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \
1551 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1552 IS_MODULE(CONFIG_SND_DAVINCI_SOC))
1553 case MCASP_VERSION_1:
1554 case MCASP_VERSION_2:
1555 ret = davinci_soc_platform_register(&pdev->dev);
1556 break;
1557 #endif
1558 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1559 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1560 IS_MODULE(CONFIG_SND_EDMA_SOC))
1561 case MCASP_VERSION_3:
1562 ret = edma_pcm_platform_register(&pdev->dev);
1563 break;
1564 #endif
1565 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1566 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1567 IS_MODULE(CONFIG_SND_OMAP_SOC))
1568 case MCASP_VERSION_4:
1569 ret = omap_pcm_platform_register(&pdev->dev);
1570 break;
1571 #endif
1572 default:
1573 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1574 mcasp->version);
1575 ret = -EINVAL;
1576 break;
1577 }
1578
1579 if (ret) {
1580 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1581 goto err;
1582 }
1583
1584 return 0;
1585
1586 err:
1587 pm_runtime_put_sync(&pdev->dev);
1588 pm_runtime_disable(&pdev->dev);
1589 return ret;
1590 }
1591
1592 static int davinci_mcasp_remove(struct platform_device *pdev)
1593 {
1594 pm_runtime_put_sync(&pdev->dev);
1595 pm_runtime_disable(&pdev->dev);
1596
1597 return 0;
1598 }
1599
1600 static struct platform_driver davinci_mcasp_driver = {
1601 .probe = davinci_mcasp_probe,
1602 .remove = davinci_mcasp_remove,
1603 .driver = {
1604 .name = "davinci-mcasp",
1605 .of_match_table = mcasp_dt_ids,
1606 },
1607 };
1608
1609 module_platform_driver(davinci_mcasp_driver);
1610
1611 MODULE_AUTHOR("Steve Chen");
1612 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1613 MODULE_LICENSE("GPL");
Linux with added FPC-III support